Anomaly detection method and apparatus

Abstract

The present disclosure provides an anomaly detection method and device, wherein the method comprises: using a preset intercept callback function in a current compilation stage to serialize an intermediate representation of the current compilation stage to obtain an intermediate representation snapshot; executing the intermediate representation snapshot with a plurality of preset data precisions to obtain data results of the plurality of data precisions; calculating a reference deviation and a quantization deviation according to the data results of the plurality of data precisions; and in response to determining that the reference deviation satisfies a first preset condition and / or the quantization deviation satisfies a second preset condition, determining that the current compilation stage has a compilation anomaly. The method realizes full-stage reproducibility of the compilation process, reduces the fault positioning granularity to a single compilation stage, and improves the defect detection efficiency of the quantization compiler.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to an anomaly detection method, an anomaly detection device, an electronic device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] Currently, compilers for GPUs (Graphics Processing Units) and AI (Artificial Intelligence) accelerator chips employ a multi-stage progressive lowering architecture, gradually transforming high-level computational graphs into machine code executable on hardware. Each lowering stage contains multiple compiler passes (stages or steps), and any pass may introduce computational errors or functional defects. Existing technologies generally use difference testing to identify bugs (errors, defects, or faults) in the compilation process. Difference testing involves running the same input under multiple compilers or different configurations of the same compiler and comparing the differences in the output to discover bugs. Summary of the Invention

[0003] This disclosure provides an anomaly detection method, anomaly detection device, electronic device, computer-readable storage medium, and computer program product.

[0004] In a first aspect, embodiments of this disclosure propose an anomaly detection method, comprising: serializing the intermediate representation of the current compilation stage using a preset interception callback function in the current compilation stage to obtain an intermediate representation snapshot; executing the intermediate representation snapshot with preset multiple data precisions to obtain data results with multiple data precisions; calculating a reference deviation and a quantization deviation based on the data results with multiple data precisions; and determining that a compilation anomaly exists in the current compilation stage in response to determining that the reference deviation meets a first preset condition and / or the quantization deviation meets a second preset condition.

[0005] Secondly, embodiments of this disclosure propose an anomaly detection device, comprising: a serialization module, an execution module, a calculation module, and a determination module. The serialization module is configured to serialize the intermediate representation of the current compilation stage using a preset interception callback function in the current compilation stage, obtaining an intermediate representation snapshot; the execution module is configured to execute the intermediate representation snapshots at preset multiple data precisions, obtaining data results at multiple data precisions; the calculation module is configured to calculate a reference deviation and a quantization deviation based on the data results at multiple data precisions; and the determination module is configured to determine that a compilation anomaly exists in the current compilation stage in response to determining that the reference deviation meets a first preset condition and / or the quantization deviation meets a second preset condition.

[0006] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform an anomaly detection method as described in any implementation of the first aspect.

[0007] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions that, when executed by a processor, enable the anomaly detection method as described in any implementation of the first aspect.

[0008] Fifthly, embodiments of this disclosure provide a computer program product including a computer program, which, when executed by a processor, can implement the anomaly detection method described in any implementation of the first aspect.

[0009] According to the technical solution provided in the embodiments of this disclosure, the intermediate representation of the current compilation stage can be serialized using a preset interception callback function in the current compilation stage to obtain an intermediate representation snapshot; then, the intermediate representation snapshots are executed with multiple preset data precisions to obtain data results with multiple data precisions; then, the reference deviation and quantization deviation are calculated based on the data results with multiple data precisions; finally, in response to determining that the reference deviation meets the first preset condition and / or the quantization deviation meets the second preset condition, it can be determined that there is a compilation anomaly in the current compilation stage.

[0010] By pre-setting interception callback functions for each compilation stage, an intermediate representation snapshot is automatically generated after all Pass operations in each stage are completed. Then, multi-precision parallel computation is applied to the same intermediate representation snapshot to calculate reference deviation and quantization deviation in layers. Combined with a preset tolerance threshold, compilation stage anomalies are automatically identified. On the one hand, this ensures reproducibility across all stages of the compilation process, reducing fault location granularity to a single compilation stage. On the other hand, it accurately distinguishes between general compilation logic defects and quantization conversion-related defects, differentiates between inherent floating-point rounding errors, natural quantization precision loss, and code anomaly errors, reducing manual debugging workload and thus improving the compiler's defect detection, tracing, and repair efficiency.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A flowchart of an anomaly detection method provided in this embodiment of the disclosure; Figure 2 A flowchart of another anomaly detection method provided in this disclosure embodiment; Figure 3 A flowchart of yet another anomaly detection method provided in this disclosure embodiment; Figure 4 A flowchart illustrating the detection process for an anomaly phase provided in this embodiment of the disclosure; Figure 5 A flowchart of the abnormal step detection process provided in the embodiments of this disclosure; Figure 6 This is a structural block diagram of an anomaly detection device provided in an embodiment of the present disclosure; Figure 7 This is a schematic diagram of the structure of an electronic device suitable for performing an anomaly detection method, provided as an embodiment of the present disclosure. Detailed Implementation

[0013] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding; these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0014] This disclosure relates to the field of integrated circuit technology, specifically to an anomaly detection method, anomaly detection device, electronic device, computer storage medium, and program product, applicable to scenarios such as compiler testing, compiler defect localization, and difference testing of systems such as graphics card chips and AI chips.

[0015] Currently, the compilers for GPUs and AI acceleration chips adopt a Lowering architecture. Each Lowering stage contains multiple compiler passes (such as constant folding, instruction scheduling, register allocation, etc.), and any one of these passes may introduce computational errors or functional defects.

[0016] Some discrepancy detection schemes employ a three-stage framework to test the model loading, high-level optimization, and low-level optimization stages separately. This means that the GPU hardware backend is not considered, and the three stages are tested independently without inter-stage comparison. Consequently, due to the lack of inter-stage comparison, it is impossible to distinguish which compilation stage the anomaly occurred in. The entire process must be checked step by step, significantly increasing the number of checks, resulting in extremely low localization efficiency and wasting computing power and time.

[0017] Other discrepancy detection schemes employ a method of constructing multiple adversarial compilation configurations, using the SBFL (Spectrum-Based Fault Localization) method to analyze and locate the source file of the fault. This approach locates the fault only at the source file level, rather than the pass level; moreover, it targets C / C++ compilers, not GPU / AI compilers.

[0018] Moreover, existing difference testing methods can only detect "the compiler output is wrong," but they don't know which stage or which pass introduced the error, meaning they cannot pinpoint the bug to a specific compilation pass. In this case, engineers need to manually troubleshoot by disabling each pass one by one, which can take hours to days, resulting in a significant waste of computing power and time.

[0019] Therefore, existing anomaly detection solutions lack stage boundary comparison and screening, resulting in problems such as low fault location efficiency and insufficient anomaly subdivision capability. In addition, due to the lack of structured detection reports, key information such as step numbers, operator types, subdivided anomaly categories, and multi-precision results are not integrated, which is not conducive to developers quickly locating and repairing the problem.

[0020] The following description of several optional embodiments illustrates the technical solutions of this disclosure and the technical effects produced by these solutions. It should be noted that the following embodiments can be referenced, learned from, or combined with each other. Identical terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0021] Please refer to Figure 1 , Figure 1 A flowchart of an anomaly detection method provided in this disclosure embodiment, wherein process 100 includes the following steps: Step 101: Serialize the intermediate representation of the current compilation stage using the pre-defined interception callback function in the current compilation stage to obtain an intermediate representation snapshot.

[0022] In this embodiment, during the initialization phase of the compilation pipeline, intercept callback functions are pre-registered for each compilation stage. These callback functions are attached to the closing hook point after all passes in the corresponding compilation stage have been executed. Once all operator transformations, lowering, and quantization transformation passes within the current stage have been completed, the compilation process automatically triggers the callback logic when it passes this checkpoint (CP). The callback function's input parameters carry the complete intermediate representation (IR) context of the current stage, the stage identifier CP number, and the current data precision configuration information.

[0023] After the intercept callback function is triggered, the complete computation graph (IR) structure in memory during the current compilation phase is read. The entire IR structure, including operator nodes, tensor information, precision type, quantization parameters, operator dependencies, and input / output dimensions, is then traversed. Finally, all IR data is serialized according to a preset storage format (JSON / binary byte stream) to remove temporary runtime cache variables and retain the complete static IR information that can be independently reproduced.

[0024] Next, the serialized IR data is bound to a unique identifier for the current stage. This unique identifier could be CPn, where n is the sequence number of the compilation pipeline, incrementing from 0. It is used to distinguish intermediate representation snapshots at different positions in the compilation chain. For example, if the sequence number of the current compilation stage is 2, then the unique identifier CPn is CP-2. In addition, information such as timestamps, compilation branches, and precision configuration tags are also included and persistently written to local storage or a memory cache, generating a static IR snapshot for the corresponding stage. This snapshot is stored independently and can be loaded and executed separately from the original compilation process.

[0025] The anomaly detection method in this embodiment is applicable not only to AI compilers (HLO / StableHLO pipeline) but also to GPU graphics compilers. Specifically, for AI compilers, the complete compilation chain generally includes: HLO (High Level Optimizer) / StableHLO (standardized stable version of HLO), optimized HLO (i.e., a new high-level IR after graph transformation, operator splitting, quantization insertion, and fusion optimization of the original StableHLO / HLO), LLVM (Low Level Virtual Machine) IR, target ISA (Instruction Set Architecture), and machine code. Accordingly, intercept points are set at each compilation stage. Specifically, intercept point CP-0 is set at the HLO / StableHLO output location, with an IR format of HLO / StableHLO / SPIR-V and a standard serialization format. Intercept point CP-1 is set after HLO optimization (i.e., after high-level optimization), with an IR format of Optimized HLO / Lowered IR and a serialization format of optimized IR text + metadata (recording the list of executed passes). Intercept point CP-2 is set after LLVM IR generation, with an IR format of LLVM IR Bitcode and a serialization format of a bc file + Pass Pipeline record. Here, LLVM IR Bitcode is the binary serialization format of the intermediate representation (IR) in the LLVM compiler infrastructure, usually with a .bc file extension; bc is the binary serialization file of LLVM IR, storing the intermediate representation; and Pass Pipeline refers to a compilation pipeline consisting of a set of passes arranged in a preset sequence. After the target ISA code is generated, set the intercept point CP-3, whose IR format is the target ISA assembly and whose serialization method is an assembly text file; after the machine code is generated, set the intercept point CP-4, whose IR format is an executable binary and whose serialization method is ELF / CUBIN binary.

[0026] For a GPU graphics compiler, the complete compilation chain generally includes: SPIR-V (Standard Portable Intermediate Representation-V) / DXIL (DirectX Intermediate Language), vendor front-end IR, LLVM IR / vendor intermediate IR, GPU ISA assembly, and GPU machine code. Accordingly, intercept points are set at each compilation stage, namely, intercept point CP-0 is set in SPIR-V / DXIL, intercept point CP-1 is set in vendor front-end IR, intercept point CP-2 is set in LLVM IR / vendor intermediate IR, intercept point CP-3 is set in GPU ISA assembly, and intercept point CP-4 is set in GPU machine code.

[0027] The following section uses XLA (accelerated linear algebra compiler) / StableHLO compiler, LLVM-based compilers, and GPU graphics compilers as examples to illustrate the interception implementation. For the XLA / StableHLO compiler, the interception implementation can utilize XLA's HloPassInterface (standard interface for HLO transform channels) to register before_pass (triggered before a single transform is executed) and after_pass (triggered after a single transform is executed) callbacks in the Pass Pipeline. Furthermore, an Hlo Module can be serialized before and after each Pass execution.

[0028] For LLVM-based compilers, the interception implementation can be achieved by using LLVM's PassInstrumentationCallbacks to register beforePass / afterPass listeners, and serializing the module before and after each Pass.

[0029] For GPU graphics compilers, the interception implementation can be done in the IR-ISA pipeline by dumping intermediate results after each LoweringPhase.

[0030] For example, after all the Passes in Stage0 are executed, the intercept callback function is triggered at CP-0, and the final IR of Stage0 is serialized to obtain the CP-0 snapshot; then, the Lowering and quantization conversion Passes inside Stage1 are executed. After the processing of Stage1 is completed, the callback is triggered again at CP-1, and the IR of Stage1 is serialized to generate the CP-1 snapshot.

[0031] Step 102: Perform intermediate representation snapshots with multiple preset data precisions to obtain data results with multiple data precisions.

[0032] In this embodiment, the preset multiple data precisions may include: target precision, standard precision, and high precision. The target precision is a low-precision format, such as FP4 (4-bit Floating Point), FP8 (8-bit Floating Point), or INT8 (8-bit Integer), with the precision level represented as P_custom. The standard precision is a standard reference precision, such as FP32 (32-bit Floating Point), with the precision level represented as P_32. The high precision can be FP64 (64-bit Floating Point), with the precision level represented as P_64. That is, for each IR snapshot captured at a Checkpoint, the corresponding interpreter or reference backend is executed independently to obtain the computational output for that stage. Furthermore, at each Checkpoint, not only is the IR snapshot executed with the target precision, but the same IR is also executed simultaneously with both standard and high precision, thus obtaining data execution results corresponding to different data precisions. In addition, the hardware computing device will be initialized, and an independent computing context will be allocated for each precision, thereby isolating the computing caches of different precisions and avoiding mutual interference between values.

[0033] Specifically, the IR snapshot is loaded into the high-precision computation context, all low-precision quantization acceleration logic is disabled, and all operators are executed using 64-bit floating-point arithmetic rules. Simultaneously, input tensors, intermediate feature tensors, and output tensors are all stored using FP64, preserving the original high-precision values ​​completely. After computation, the high-precision output result is exported. The same IR snapshot is then reused, switching to the standard-precision computation context. Operators uniformly use 32-bit floating-point arithmetic, performing only regular floating-point calculations without introducing quantization conversion. Simultaneously, the original tensor parameters from the snapshot are read directly for computation, yielding the standard-precision output result. Then, the context switches back to low-precision computation, reading the quantization parameters bound to each tensor in the IR snapshot. During computation, the input floating-point tensor is quantized to INT8 integers, and calculations are performed based on INT8. After calculation, the floating-point output is dequantized to obtain the low-precision output result.

[0034] Finally, the three sets of results are bound to the corresponding precision labels and the current IR snapshot number CP-n, and the original input data, intermediate feature values ​​of each layer, and final output tensor are saved synchronously.

[0035] Taking the compilation pipeline of the AI ​​compiler as an example, the executor of CP-0 (original HLO / StableHLO) is XLAInterpreter Backend. XLA comes with a pure C++ operator interpreter that does not compile or generate hardware instructions. It calculates operators line by line according to the standard mathematical formulas in sequence, without being affected by the hardware characteristics of the GPU chip or instruction set optimization. The calculation results are closest to the theoretical mathematical truth.

[0036] The executor for CP-1 (optimized HLO) is the XLA Interpreter Backend. It reuses the same XLA interpreter to execute the optimized HLO snapshot after operator fusion, quantization insertion, and constant folding. The purpose is to compare the execution results of CP-0 and CP-1 to verify that the computational semantics of various HLO optimization passes have not been altered, and that the optimized numerical logic remains consistent with the original model.

[0037] The executor for CP-2 (LLVM IR) is the LLVM lli interpreter / LLVM JIT. lli is the official LLVM IR text / bytecode interpreter, which emulates LLVM instructions in pure software and is independent of the target hardware. JIT is just-in-time compilation, which compiles LLVM IR into native CPU instructions for execution in real time. Both can independently load LLVM IR snapshots for computation, used to verify whether the HLO downgrade to LLVM IR step introduces computational bias.

[0038] The executor for CP-3 (GPU ISA Assembly PTX / SASS) is the vendor's simulator / reference hardware. The chip vendor's official simulator is a pure software simulation of GPU hardware executing ISA instructions, isolating it from real hardware scheduling interference; the standard reference hardware uses a compliant benchmark GPU to run assembly code. It is used to verify the numerical errors in the IR downgrade to hardware-specific assembly instructions stage.

[0039] The executor of CP-4 (GPU machine code) is the target real hardware. The binary machine code can only run on the corresponding GPU / AIASIC (Application-Specific Integrated Circuit) acceleration chip, representing the real business deployment scenario; it is used to capture the real quantization deviation caused by the hardware underlying instruction scheduling and tensor core operation.

[0040] Different levels of checkpoint IR snapshots are matched with corresponding independent execution environments. Each level of independent executor can load the output multi-precision calculation results of the same level IR snapshot in parallel, and complete the calculation of reference deviation and quantization deviation layer by layer, thereby accurately locating the anomalies introduced by each level of compilation transformation.

[0041] Step 103: Calculate the reference deviation and quantization deviation based on the data results from multiple data precisions.

[0042] In this embodiment of the disclosure, the reference deviation refers to the calculation error generated by the FP32 standard compilation path itself. The reference deviation is based on the calculation result of FP64 high precision, and the comparison object is the calculation result of FP32 standard precision. The reference deviation is used to check for general compilation logic defects, such as lowering conversion errors, operator implementation bugs, IR structure rewriting errors, constant calculation errors, memory read and write anomalies, etc., which will directly amplify the reference deviation.

[0043] Quantization deviation refers to the additional error of the low-precision quantization format compared to the standard FP32. The benchmark for quantization deviation is the calculation result of the standard precision of FP32, and the comparison object is the calculation result of the target precision (FP8 / INT8 / FP4 low precision). Quantization deviation is used to locate defects in quantization-related processes.

[0044] In other words, after determining the output results corresponding to FP64 high precision, FP32 standard precision, and FP8 / INT8 / FP4 low precision, the FP64 high precision result is used as the truth benchmark. The error of the FP32 standard precision result relative to the truth value is calculated element by element, and the average absolute error is statistically analyzed to obtain the reference deviation. Then, using the FP32 standard precision result as the comparison benchmark, the average absolute error corresponding to each type of low precision quantization result is calculated to obtain the quantization deviation. The reference deviation is used to verify whether there are underlying logic anomalies in the standard precision compilation path, while the quantization deviation is used to distinguish between the inherent numerical loss caused by low precision quantization and the abnormal errors introduced by the quantization compilation transformation.

[0045] Step 104: In response to determining that the reference deviation meets the first preset condition and / or the quantization deviation meets the second preset condition, determine that there is a compilation error in the current compilation stage.

[0046] In this embodiment, preset conditions corresponding to the reference deviation and quantization deviation are pre-configured. These preset conditions refer to the reference deviation threshold and the quantization deviation threshold corresponding to the low-precision format. The reference deviation is compared with the reference deviation threshold, and the quantization deviation is compared with its corresponding quantization deviation threshold. If the reference deviation meets the first preset condition and / or the quantization deviation meets the second preset condition, it is determined that a compilation error exists in the current compilation stage.

[0047] On the one hand, when the reference deviation and the reference deviation threshold meet a preset relationship, or when the quantization deviation and the quantization deviation threshold meet a preset relationship, it is determined that there is a compilation anomaly in the current compilation stage. For example, when the reference deviation is greater than the reference deviation threshold, or when the quantization deviation is greater than the quantization deviation threshold, it is determined that the deviation meets the preset conditions for anomaly judgment, and it is determined that there is a compilation anomaly in the compilation stage to which the current IR snapshot belongs, and the anomaly type, the current checkpoint identifier, and all deviation data are recorded.

[0048] For example, the reference deviation threshold can be the FP32 tolerance, which is the inherently allowed error tolerance range for 32-bit floating-point numbers and is the normal upper limit threshold for the inherent rounding error of floating-point calculations. If the reference deviation is greater than the FP32 tolerance, it is determined that there is a compilation error in the current compilation stage, i.e., a Pass logic error. The quantization deviation threshold is the target precision tolerance, which can include FP8, INT8, FP4, etc., and correspondingly, the quantization deviation threshold includes FP8 tolerance, INT8 tolerance, FP4 tolerance, etc., that is, the quantization deviation threshold is determined according to the format of the target precision. If the quantization deviation is greater than the quantization deviation threshold, it is also determined that there is a compilation error in the current compilation stage.

[0049] On the other hand, when the reference deviation and the reference deviation threshold satisfy a preset relationship, and the quantization deviation and the quantization deviation threshold also satisfy a preset relationship, it can be determined that there is a compilation exception in the current compilation stage. For example, when the reference deviation is less than or equal to the reference deviation threshold and the quantization deviation is greater than the quantization deviation threshold, it is determined that there is a compilation exception in the current compilation stage, and the exception type is a low-precision path exception.

[0050] According to the anomaly detection method provided in this disclosure, by pre-setting interception callback functions for each compilation stage, an IR snapshot is automatically generated after all Pass operations in each stage are completed. Then, multi-precision parallel computation is performed on the same IR snapshot to calculate the reference deviation and quantization deviation in layers, and the compilation stage anomalies are automatically determined in combination with a preset tolerance threshold. On the one hand, the entire compilation process is reproducible, reducing the granularity of fault location to a single compilation stage; on the other hand, it can accurately distinguish between general compilation logic defects and quantization conversion-related defects, distinguish between floating-point inherent rounding errors, natural quantization precision loss, and code anomaly errors, reducing the workload of manual debugging, and thus improving the defect detection efficiency, source tracing efficiency, and repair efficiency of the quantization compiler.

[0051] Please refer to Figure 2 , Figure 2 A flowchart of another anomaly detection method provided in this disclosure embodiment, wherein process 200 includes the following steps: Step 201: In response to the interception point of the current compilation stage in the compilation process, trigger the interception callback function bound to the interception point to obtain the intermediate representation of the current compilation stage.

[0052] In this embodiment, interception callback functions are pre-registered at each stage of the compilation pipeline. When the compilation process reaches the interception point of the current compilation stage, the callback logic is automatically triggered, that is, the interception callback function bound to that interception point is triggered. If the pre-defined interception callback function is detected to be triggered, the internal execution logic of the callback is entered. That is, the callback function reads the complete IR of the current stage from the compilation context environment, that is, it fully obtains all internal data of the IR, such as operator topology, tensor dimension, constant weight, scale (scaling factor) and zero-point (zero point) quantization parameters, memory allocation information, etc.

[0053] In some optional implementations of the embodiments of this disclosure, the above-mentioned anomaly detection method may further include the following: inserting interception points at the transition boundaries of each compilation stage of the compilation pipeline, wherein the transition boundary is the dividing position between two adjacent compilation stages; and registering a preset interception callback function for each interception point.

[0054] In this implementation, intercept points are pre-inserted at the transition boundaries of each compilation stage in the compilation pipeline. The compilation pipeline, within the AI ​​compiler, is an ordered, sequential processing chain that gradually converts the original AI model into hardware-executable code. The entire chain is divided into multiple sequentially executed compilation stages. For example, the compilation pipeline may sequentially include a model import stage, a graph optimization stage, an operator lowering stage, and a hardware instruction generation stage. The boundary between two adjacent compilation stages is the transition boundary, and an intercept point is inserted at each transition boundary. Specifically, intercept points are set at the first transition boundary between the model import stage and the graph optimization stage, the second transition boundary between the graph optimization stage and the operator lowering stage, and the third transition boundary between the operator lowering stage and the hardware instruction generation stage.

[0055] For each interception point, the interception callback function is registered during the compilation initialization phase, establishing a binding relationship between each interception point and a pre-defined interception callback function. Different interception points can reuse the same set of interception callback functions, or they can register different interception callback functions according to the processing logic of the corresponding compilation phase. When the compilation process reaches an interception point at any transition boundary, the compilation pipeline will interrupt the current pipeline execution flow and call the interception callback function bound to that interception point.

[0056] By setting up interception points and registering callback functions at the transformation boundaries of each compilation stage, IR can be stably captured at the stage transition, facilitating subsequent IR snapshot collection and compilation anomaly detection.

[0057] Step 202: Serialize and encode the intermediate representation according to the standard format corresponding to the intermediate representation to obtain an intermediate representation snapshot.

[0058] In this step, after obtaining the complete IR of the current compilation stage captured by the callback function, the IR type is first identified, and serialization encoding is performed according to the corresponding official specification format. For example, if it is a StableHLO / HLO IR, all information such as operator topology, tensor size, weight constants, scale / zeropoint quantization parameters, and operation attributes are serialized into binary Proto (photo) data according to the Protobuf protocol specification defined by XLA. The Protobuf protocol specification is a serialization protocol that predefines data structures and encodes memory structured data into binary byte carriers (buffers). If it is an LLVM IR, the LLVM built-in interface is called to convert it into a standard Bitcode binary stream. If it is a SPIR-V or vendor-specific GPU IR, the corresponding graphics compilation specification is followed to complete the binary encoding. After encoding, checkpoint numbers, compilation stage identifiers, target precision configurations, timestamps, and additional metadata are embedded, written to a persistent file, and an IR snapshot that can be independently loaded and parsed and reused across execution engines is generated.

[0059] By automatically capturing complete IR at each stage through callback functions and serializing them according to the corresponding specifications to generate standardized snapshots, all information such as operators and quantization parameters can be completely preserved, facilitating multi-precision independent execution and hierarchical error verification, and accurately locating numerical anomalies at each compilation level.

[0060] Step 203: Call the execution engines corresponding to the target precision, standard precision, and high precision respectively to execute the intermediate representation snapshots in parallel to obtain the corresponding target precision data results, standard precision data results, and high precision data results.

[0061] In this embodiment of the disclosure, multiple data precisions are preset, including: target precision, standard precision, and high precision. The precision value of the standard precision is greater than the precision value of the target precision and less than the precision value of the high precision. For example, the target precision can be a low precision such as FP4, FP8, or INT8, the standard precision can be FP32, and the high precision can be FP64.

[0062] This involves pre-constructing three independent execution engines: high-precision, standard-precision, and target-precision. Each engine has an isolated computation context and a dedicated operator library. Then, the same IR snapshot is synchronously distributed to the three engines, initiating parallel computation tasks. The high-precision engine uses FP64 to perform full floating-point operations and outputs high-precision data results. The standard-precision engine uses FP32 to obtain standard-precision data results. The target-precision engine reads the scaling factor and zero-point offset parameters built into the IR snapshot, performs FP4 / FP8 / INT8 low-bit-width quantization operations, and outputs target-precision data results. After all engines have completed their parallel computations, the three output tensors are aggregated to obtain the target-precision data results. Standard precision data results and high-precision data results This allows for the generation of multi-precision result datasets. By running the same IR snapshot in parallel across multiple execution engines, it synchronously produces results of three different precision levels, eliminating the need to repeatedly load snapshots and improving snapshot generation efficiency.

[0063] Step 204: Calculate the absolute value of the difference between the high-precision data result and the standard-precision data result to obtain the reference deviation.

[0064] In this embodiment, after obtaining a multi-precision result dataset containing target precision data results, standard precision data results, and high precision data results, the absolute value of the difference between the high precision data results and the standard precision data results is calculated, and the obtained value is used as the reference deviation (reference Delta). The reference deviation is expressed as... ,but The reference Delta reflects the inherent accuracy limitations of the FP32.

[0065] Step 205: Calculate the absolute value of the difference between the standard precision data result and the target precision data result to obtain the quantization deviation.

[0066] In this embodiment, the absolute value of the difference between the standard precision data result and the target precision data result is also calculated, and the obtained value is used as the quantization deviation (quantization Delta). The quantization deviation is expressed as... ,but Quantization Delta reflects the inherent precision loss of low-precision formats.

[0067] By calculating two types of deviations in a hierarchical manner, using the high-precision result as a benchmark to verify the standard precision, and then using the standard precision to verify the low precision, it is possible to clearly distinguish between general compilation logic anomalies and quantization link anomalies, locate the compilation stage of the fault, and thus improve the efficiency of defect detection.

[0068] Step 206: In response to determining that the reference deviation is greater than the first theoretical allowable deviation corresponding to the standard precision, determine that there is a compilation error in the current compilation stage.

[0069] A first theoretical tolerance deviation corresponding to the pre-configured standard precision is defined as the FP32 tolerance threshold corresponding to the inherent rounding error of FP32 floating-point operations, expressed as follows: The reference deviation corresponding to the current checkpoint. Deviation from the first theory Perform size comparison; if Greater than If a compilation exception is detected in the current IR snapshot's compilation stage, it is determined that a compilation exception exists. The exception type is then marked as a compilation logic exception (i.e., a Pass logic error). Simultaneously, the current checkpoint number, reference deviation value, first theoretical tolerance deviation value, and compilation logic exception identifier are recorded and archived for future reference. This is to facilitate the subsequent identification of operator implementation and intermediate representation conversion defects in common compilation processes such as HLO graph transformation and LLVM IR downgrading. Generally, compilation logic exceptions can include: errors in swapping operation order, errors in deleting necessary calculations, errors in reshaping (tensor dimension reshaping errors), errors in broadcasting (broadcast mechanism exceptions), error handling boundary conditions, error fusion operators, and semantic changes caused by error instruction selection.

[0070] By comparing the reference deviation with the first theoretical allowable deviation, general compiler logic defects can be quickly identified, and it can be accurately distinguished whether the error is in the basic process such as intermediate representation conversion or operator implementation. This allows for quick identification of the abnormal stage and simplifies the problem localization process.

[0071] As an example, for CP-2, P_custom=0.6039, P_32=0.6021, P_64=0.7834, Δ_ref=0.2813. It can be seen that the FP32 path has deviated from FP64, indicating that it's not an FP8 quantization error, but rather a problem with the lowering semantics. Therefore, it is classified as a Pass logic error.

[0072] Step 207: In response to determining that the quantization deviation is greater than the second theoretical tolerance deviation corresponding to the target precision, determine that there is a compilation anomaly in the current compilation stage.

[0073] A second theoretical tolerance deviation corresponding to the target accuracy is pre-configured. This second theoretical tolerance deviation is the tolerance threshold for low-precision values ​​such as FP4, FP8, and INT8, and is expressed as follows: Then Compare with the second theoretical tolerance. That is, the deviation corresponding to the current checkpoint. and Perform size comparison; if Greater than This indicates that after processing in the current compilation stage, the model's numerical results deviate from the allowable error range of the target accuracy, and the output IR has become numerically distorted. It can be determined that there is a compilation anomaly in the current compilation stage.

[0074] By comparing the reference deviation, quantization deviation and the corresponding theoretically permissible deviation, compilation anomalies can be detected from two dimensions: standard precision and target precision. This can capture two types of problems: semantic errors and quantization distortion. Based on the compilation stages associated with the interception points, it is easy to quickly locate the location of the anomaly.

[0075] Step 208: In response to determining that the reference deviation is less than or equal to the first theoretical allowable deviation and the quantization deviation is greater than the second theoretical allowable deviation, it is determined that there is a compilation exception in the current compilation stage and the exception type is a low-precision path exception.

[0076] like Less than This will further Compared with the second theoretical tolerance, and Greater than If this is detected, a compilation error is identified in the compilation stage corresponding to the current IR snapshot, and the error type is marked as a low-precision path error. The current checkpoint identifier, reference deviation value, out-of-limit quantization deviation value, corresponding target precision type, first theoretical allowable deviation, and second theoretical allowable deviation are synchronously archived for subsequent tracing of quantization link defects such as Scale, ZeroPoint parameter calculation, quantization / dequantization Pass, and low-precision operator implementation. Not exceeding If the current compilation stage's general compilation logic and low-precision quantization path are both deemed to be without faults, meaning the current precision loss is within the expected range, the compilation pipeline continues to the next stage. Thus, assuming the basic compilation logic is correct, low-precision link faults are identified using the quantization deviation threshold, accurately distinguishing specific issues such as quantization parameters and low-precision operators, and individually marking the exception type, facilitating targeted investigation of quantization-related compilation defects.

[0077] It should be noted that Table 1 shows the correspondence between various accuracy formats and their corresponding theoretical error upper bounds.

[0078] Table 1. Comparison of various accuracy formats and their corresponding theoretical error upper bounds.

[0079] Where N is the length of the longest computation chain from input to output in the IR computation graph, which can be automatically derived from the IR computation graph through topology analysis.

[0080] In some optional implementations of the embodiments of this disclosure, the above-mentioned anomaly detection method may further include the following: calculating the absolute value of the difference between the high-precision data result and the target precision data result to obtain the total deviation; in response to determining that the total deviation is less than or equal to the second theoretical allowable deviation, determining that there is no compilation anomaly in the current compilation stage.

[0081] In this embodiment, after obtaining a multi-precision result dataset containing target precision data results, standard precision data results, and high precision data results, the difference between the high precision data results and the target precision data results is calculated, and the obtained difference is used as the total deviation (total Delta). The total deviation is expressed as... ,but The total Delta reflects the overall deviation between the low precision and the Ground Truth (theoretical true value). It also sets the value corresponding to the current checkpoint. Deviation from the second theory ( Perform a size comparison; if Less than or equal to This indicates that the general compilation logic in the current compilation stage is normal and the numerical loss of the low-precision quantization path is within the normal inherent error range. Therefore, it is determined that there are no compilation anomalies in the current IR snapshot's compilation stage, and the compilation process directly proceeds to the next compilation stage's IR snapshot interception and verification phase. If... Greater than This indicates that an exception has occurred during the current compilation phase, but the specific type of exception cannot be determined and further investigation is needed. and Make a judgment.

[0082] This allows for the direct calculation of the total deviation using high-precision true values ​​and low-precision results. Combined with the second theoretical allowable deviation, it quickly determines whether the quantization link is normal, simplifying the error verification logic, quickly distinguishing between normal quantization loss and low-precision compilation anomalies, and thus improving the verification efficiency of each compilation stage.

[0083] According to the anomaly detection method provided in this disclosure, the IR of each compilation stage is automatically obtained by intercepting the callback function and standardized serialization to generate snapshots, so that the verification can be reused without repeated compilation; the multi-precision execution engine runs the snapshots in parallel, simultaneously obtaining three sets of outputs: high precision, standard precision, and target precision, and calculates the reference deviation and quantization deviation in layers, and sets two-level thresholds to determine faults in layers. This can accurately distinguish between underlying defects such as intermediate representation conversion and operator implementation and problems such as quantization parameters and low-precision operators. Moreover, the fault stage is located in layers, which improves the automation of verification, makes the defect classification clear, and also greatly reduces the cost of troubleshooting compilation errors.

[0084] Please refer to Figure 3 , Figure 3 A flowchart of another anomaly detection method provided in this disclosure embodiment, wherein process 300 includes the following steps: Step 301: Serialize the intermediate representation of the current compilation stage using the pre-defined interception callback function in the current compilation stage to obtain an intermediate representation snapshot.

[0085] Step 302: Perform intermediate representation snapshots with multiple preset data precisions to obtain data results with multiple data precisions.

[0086] Steps 301-302 above and as follows Figure 1 The steps 101-102 shown are the same. For the same parts, please refer to the corresponding parts of the previous embodiment. They will not be repeated here.

[0087] Step 303: Calculate the absolute value of the difference between the high-precision data result and the target precision data result to obtain the total deviation.

[0088] Step 304: In response to determining that the total deviation is less than or equal to the second theoretical allowable deviation, determine that there is no compilation error in the current compilation stage.

[0089] Steps 303-304 above are the same as those in the previous embodiment. Please refer to the corresponding parts of the previous embodiment. They will not be repeated here.

[0090] Step 305: In response to determining that there is no compilation exception in the current compilation stage and there is a compilation exception in the next compilation stage adjacent to the current compilation stage, determine that the compilation exception exists in the compilation steps contained in the next compilation stage.

[0091] In this embodiment, the location of the introduced bug is determined based on the output of adjacent stages. That is, if there is no exception in stage N but there is an exception in stage N+1, the pass that introduces the bug is determined to be located in the Lowering process between stage N and stage N+1, that is, it exists in the compilation steps included in the next compilation stage.

[0092] For example, a label can be generated for each CP, such as the label NORMAL indicating that no anomaly exists, and the label ABNORMAL indicating that an anomaly exists. Assume the labels for each CP are as follows: CP-0: NORMAL; CP-1: NORMAL; CP-2:FP32_PATH_ABNORMAL; CP-3:FP32_PATH_ABNORMAL; Therefore, we can conclude that the bug first appeared in CP-2, and the responsibility phase is CP-1→CP-2.

[0093] For example, if the state of stage N is represented as Status[N] and the state of stage N+1 is represented as Status[N+1], then if Status[N] = NORMAL and Status[N+1] = ABNORMAL, then it is determined that the bug was introduced from stage N to N+1; if Status[N] = ABNORMAL and Status[N+1] maintains the same type of exception, then it is determined that the exception is inherited and no new bug was added in stage N+1; if Status[N] = ABNORMAL and the exception of Status[N+1] is significantly amplified or its type changes, then it is determined that stage N+1 may introduce a second bug or amplify an existing bug.

[0094] In some optional implementations of the embodiments of this disclosure, the above-mentioned anomaly detection method may further include the following: calculating the stage increment deviation between the current compilation stage and the next compilation stage based on the reference deviation, quantization deviation, and total deviation of the current compilation stage and the next compilation stage, wherein the stage increment deviation includes: target precision increment deviation, standard precision increment deviation, or high precision increment deviation; in response to determining that the target precision increment deviation, standard precision increment deviation, or high precision increment deviation exceeds the corresponding preset stage deviation, determining that the compilation anomaly exists in the compilation steps included in the next compilation stage.

[0095] In this implementation, the differences between the high precision, standard precision, and target precision of the two stages are calculated based on the reference deviation, quantization deviation, and total deviation of the current compilation stage (stage N) and the next compilation stage (stage N+1), respectively, resulting in three types of stage incremental deviations. For example, the stage incremental deviation is denoted as... Correspondingly, the target accuracy increment deviation, standard accuracy increment deviation, or high accuracy increment deviation are expressed as: : - ; - ; - ; Assume the preset stage deviations are as follows: (Target accuracy stage deviation) (Standard accuracy stage deviation) (High-precision stage deviation). If Exceed ,or Exceed ,or Exceed If so, it is determined that the bug was introduced by the Pass in stage N→N+1.

[0096] By calculating the multi-dimensional incremental deviation between adjacent stages and comparing it with a preset threshold to identify error mutations, the system can quickly pinpoint the anomaly in the next compilation stage, distinguish the source of error between preceding and subsequent stages, accurately narrow down the scope of fault investigation, and improve the efficiency of locating compilation defects.

[0097] Step 306: Perform a binary search in the compilation steps included in the next compilation stage, and determine the target compilation step that caused the compilation exception based on the search results.

[0098] The next compilation stage divides all compilation steps into intervals according to their execution order. A binary search strategy is used to perform segmented IR snapshot verification. That is, each time the midpoint of the interval is selected to truncate the compilation, the verification is run and the deviation is compared. Then, the abnormal interval is narrowed down according to whether the deviation exceeds the limit. The binary search is iterated repeatedly until only a single step remains in the interval. Finally, the target compilation step that caused the compilation error is determined and the step number and deviation data are recorded.

[0099] This approach first identifies the stage to which the anomaly belongs by comparing adjacent stages, and then uses binary search to quickly screen the steps within the stage to which the anomaly belongs. This significantly reduces the number of repeated checks, efficiently locates the erroneous compilation steps, narrows the scope of troubleshooting, and reduces the time required to locate compilation defects.

[0100] Step 307: Generate an anomaly detection report based on the information from the target compilation steps.

[0101] In this step, the generated anomaly detection report includes: the name and number of the target compilation step, an intermediate representation snapshot before the execution of the target compilation step, an intermediate representation snapshot after the execution of the target compilation step, data results for multiple data precisions of the target compilation step, and the anomaly type of the target compilation step. Specifically, after locating the target compilation step that caused the anomaly, the business name and globally unique number of that step are extracted as basic identifiers. The original IR snapshot before the execution of that step and the IR snapshot output after the transformation process are retrieved and bound, completely preserving the intermediate data before and after the step. Simultaneously, the execution output results of three categories—high precision, standard precision, and target precision—are organized with their corresponding deviation values, and matched against the previously determined compilation logic anomalies or low-precision path anomaly types. Finally, all information is uniformly encapsulated and formatted to generate a structured anomaly detection report, which is used by developers to trace, reproduce, and repair compilation faults.

[0102] Because the report fully preserves the abnormal step number, before and after IR snapshots, multi-precision calculation results and abnormal type information, it can completely reproduce the fault scenario, intuitively compare the IR differences before and after the step, quickly assist R&D in locating the root cause, and simplify the problem review and repair process.

[0103] According to the anomaly detection method provided in this disclosure, by comparing the verification results of two adjacent compilation stages, the scope of the fault can be quickly narrowed down to the next compilation stage, avoiding indiscriminate full-process troubleshooting. Then, a binary search is used to perform segmented verification of the compilation steps within the stage, which can quickly converge with a very small number of tests and accurately locate the single target step that triggers the anomaly, which greatly improves the location efficiency compared to traversing through the entire process. Finally, the step identifier, before and after IR snapshots, multi-precision calculation data, anomaly type and other contents are integrated to generate a complete report, which fully preserves the evidence for fault reproduction, making it easy for R&D personnel to intuitively compare IR differences and quickly locate the root cause, significantly reducing the cost of troubleshooting and repairing compilation faults.

[0104] In some optional implementations of the embodiments of this disclosure, the above-mentioned anomaly detection method may further include the following: in response to determining that the anomaly type is a low-precision path anomaly, obtaining type metadata of the target compilation step, wherein the low-precision path anomaly includes: precision conversion anomaly and quantization implementation anomaly; determining the anomaly type as a precision conversion anomaly or a quantization implementation anomaly according to the category corresponding to the type metadata.

[0105] In this implementation, if the current exception is determined to be a low-precision path exception, the built-in type metadata bound to the target compilation step will be retrieved. The metadata records information such as the step function classification, processing object, and operator identifier.

[0106] If the PassType (category) is determined based on the metadata to be: CastLowering, PrecisionConversion, PackUnpack, RoundingModeSelection, SaturationClamp, SaturationClamp, or AccumulatorDowncast, then the exception type is determined to be a precision conversion exception.

[0107] If the PassType is determined based on the metadata to be: QuantizationPropagation, ScaleFold, ZeroPointPropagation, LowPrecisionRewrite, QuantizedFusion, INT8Lowering, FP8Lowering, or FP4Lowering, then the exception type is determined to be a quantization implementation exception.

[0108] Finally, the detailed anomaly types and corresponding metadata are written into the anomaly detection report to accurately identify the root cause of the fault and to target and quantify the related compilation logic for repair.

[0109] Therefore, after identifying low-precision path anomalies, the Pass type is matched according to the compilation step metadata to quickly distinguish between precision conversion anomalies and quantization implementation anomalies, thereby accurately locating the major category of compilation logic to which the fault belongs, refining the root cause of the anomaly, making the anomaly report clearly categorized, and thus improving the efficiency of subsequent fault repair.

[0110] In some optional implementations of the embodiments of this disclosure, the binary search step in step 306 can be further implemented in the following ways: a. Take the first compilation step in the next compilation stage as the first boundary node and the last compilation step in the next compilation stage as the second boundary node, generate a retrieval sequence, and determine the intermediate nodes of the retrieval sequence based on the first boundary node and the second boundary node.

[0111] After locating the responsibility phase, perform a Pass-level binary search within that phase: assuming phase N→N+1 contains the Pass sequence [ , ... The first boundary node is the left node of the search sequence, and the second boundary node is the right node of the search sequence. At this time, left=1 and right=k. Then, the middle node mid is determined based on the left and right nodes, and mid=(left+right) / 2, which is (1+k) / 2.

[0112] b. Perform the following iterative steps: take the intermediate node as the new second boundary node, and generate a new retrieval sequence based on the first boundary node and the new second boundary node.

[0113] That is, the mid node is used as the new second boundary node right, and then a new search sequence is generated based on the first boundary node left and the new second boundary node. , ... ].

[0114] c. Determine whether there are compilation anomalies in the new retrieval sequence based on the data results of multiple data precisions of the new retrieval sequence.

[0115] Then execute [ ,..., ], serialize the IR and execute it, which will execute [ ,..., The resulting temporary Checkpoint output is denoted as CP-mid. The same precision determination process as the previous Checkpoint is performed on CP-mid: first, the standard precision data result, high precision data result, and reference deviation, quantization deviation, and total deviation are calculated. Then, the relationship between the reference deviation and the first theoretical allowable deviation, the quantization deviation and the second theoretical allowable deviation, and the total deviation and the second theoretical allowable deviation is used to determine whether Status[mid] is abnormal.

[0116] d. If it is determined that the new retrieval sequence contains at least two nodes other than the first boundary node and the new second boundary node, in response to the determination that a compilation exception exists in the new retrieval sequence, the intermediate node of the new retrieval sequence is determined based on the first boundary node and the second boundary node of the new retrieval sequence, and the iterative steps of taking the intermediate node as the new second boundary node and generating a new retrieval sequence based on the first boundary node and the new second boundary node continue to be executed.

[0117] If the new search sequence contains at least two nodes other than the first boundary node and the new second boundary node, and the new search sequence has a compilation error, it indicates that CP-mid has become abnormal or its state has deteriorated relative to the stage start point CP-1. Therefore, the bug is located in the first half of the search sequence, Pass, i.e., in the... ,..., Then, based on the two boundary nodes at this point, the intermediate node of the new retrieval sequence is determined to be (1+mid) / 2. Then, steps b and c are repeated, that is, the new retrieval sequence is determined based on the new intermediate node, the IR is serialized and executed, and the same precision determination as the previous CheckPoint is performed on CP-mid.

[0118] For example, in the current compilation phase, there are 18 passes. In the first round, the search sequence is [Pass1, Pass9]. If an error occurs, the bug is determined to be in Pass1-9. The new search sequence is then [Pass1, Pass9]. The intermediate node of this new search sequence is determined to be 5. The process continues with [Pass1, Pass5] and performs an error check. If an error occurs, the bug is determined to be in Pass1-5. The new search sequence is then [Pass1, Pass5]. The intermediate node of this new search sequence is determined to be 3. The process continues with [Pass1, Pass3] and performs an error check. If an error occurs, the bug is determined to be in Pass1-3. The new search sequence is then [Pass1, Pass3]. The intermediate node of this new search sequence is determined to be 2. The process continues with [Pass1, Pass2] and performs an error check. If an error occurs, the bug is determined to be in Pass2.

[0119] e. In response to the determination that there is no compilation error in the new retrieval sequence, the intermediate node is used as the new first boundary node, a new retrieval sequence is generated based on the new first boundary node and the second boundary node, the intermediate node of the new retrieval sequence is determined based on the first boundary node and the second boundary node of the new retrieval sequence, and the iterative steps of using the intermediate node as the new second boundary node and generating a new retrieval sequence based on the first boundary node and the new second boundary node continue to be executed.

[0120] If the new search sequence does not have any compilation errors, then the bug is located in the latter half of the search sequence, Pass, i.e., in Pass. ,..., In this process, the intermediate node will be used as the new first boundary node to generate a new retrieval sequence. ,..., At this point, left=mid, right=k, and the middle node of the new retrieval sequence is determined as (mid+k) / 2 based on the new first boundary node and the second boundary node. Then, steps b and c are repeated, that is, the new retrieval sequence is determined based on the new middle node, the IR is serialized and executed, and the same precision determination as the previous CheckPoint is performed on CP-mid.

[0121] For example, in the current compilation phase, there are 18 passes. In the first round, the search sequence is [Pass1, Pass9]. If the output is normal, the bug is determined to be in Pass10-18. The new search sequence is then [Pass10, Pass18]. The intermediate node of this new search sequence is determined to be 13. The process continues with [Pass1, Pass13] and exception handling is performed. If no exception is found, the bug is determined to be in Pass14-18. The new search sequence is then [Pass14, Pass18]. The intermediate node of this new search sequence is determined to be 15. The process continues with [Pass1, Pass15] and exception handling is performed. If an exception is found, the bug is determined to be in Pass14-15. The process continues with [Pass1, Pass14] and exception handling is performed. If no exception is found, the bug is determined to be in Pass15.

[0122] f. If it is determined that the new retrieval sequence contains only one node other than the first boundary node and the new second boundary node, the iteration step is determined to have ended, and the compilation step corresponding to the node in the new retrieval sequence other than the first boundary node and the new second boundary node is determined as the target compilation step that will generate a compilation exception.

[0123] The iteration process continues until the search sequence contains only one compilation step other than the two boundary nodes. At this point, the iteration step is considered complete, and the compilation steps corresponding to the nodes in the new search sequence other than the first boundary node and the new second boundary node are identified as the target compilation steps that will cause a compilation exception.

[0124] It should be noted that the first boundary node of the new retrieval sequence is the first compilation step contained in the new retrieval sequence, and the second boundary node of the new retrieval sequence is the last compilation step contained in the new retrieval sequence.

[0125] By employing binary iterative retrieval, multi-precision checks are performed only on interval boundaries and intermediate nodes, which can quickly narrow down abnormal intervals without requiring full-scale checks step by step. This significantly reduces the number of checks, efficiently converges to the faulty step, and significantly improves the speed of locating compilation anomalies.

[0126] Please refer to Figure 4 , Figure 4 A flowchart of the anomaly detection process provided in this embodiment of the disclosure is provided, wherein process 400 includes: Step 401: Test Input. Receive deep learning computation graph or GPU shader code as raw input for compilation.

[0127] Step 402: Stage 0: High-level IR. Generate intermediate representations of HLO / StableHLO / SPIR-V high-level operators, corresponding to AI computation and graphics compilation front-ends.

[0128] Step 403: Checkpoint 0 (CP 0). Save the current high-level IR serialization and execute it independently in the simulation.

[0129] Step 404: Three-Precision Comparison. For CP 0, perform IR at low precision, standard precision, and high precision to obtain the target precision data result FP_custom, the standard precision data result FP32, and the high precision data result FP64, and calculate the deviation for each. , and And based on the above deviations, determine whether there are compilation errors in stage 0.

[0130] Step 405: Stage 1: Mid-level IR optimization. After compiling the Pass, the Lowered HLO or LLVM IR is obtained, and optimizations such as quantization, operator fusion, and dimensionality transformation are completed.

[0131] Step 406: CP 1, serialize the intermediate IR and execute it independently.

[0132] Step 407: Three-Precision Comparison. For CP 1, perform IR at low precision, standard precision, and high precision to obtain the target precision data result FP_custom, the standard precision data result FP32, and the high precision data result FP64, and calculate the deviation for each. , and And based on the above deviations, determine whether there are compilation errors in stage 1.

[0133] Step 408: Phase 2: Target ISA. Convert to hardware-specific instruction set (PTX / SASS / ASIC instructions) to complete low-level instruction scheduling and low-precision degradation.

[0134] Step 409: CP 2, serialize instruction-level IR and execute it independently.

[0135] Step 410: Three-Precision Comparison. For CP 2, perform IR at low precision, standard precision, and high precision to obtain the target precision data result FP_custom, the standard precision data result FP32, and the high precision data result FP64, and calculate the deviation for each. , and And based on the above deviations, determine whether there are compilation anomalies in stage 2.

[0136] Step 411: Stage 3: Machine Code. Generate a hardware-executable binary program.

[0137] Step 412: CP 3, deploy to hardware and run, collect actual output results.

[0138] Step 413: Three-Precision Comparison. For CP 3, perform IR at low precision, standard precision, and high precision to obtain the target precision data result FP_custom, the standard precision data result FP32, and the high precision data result FP64, and calculate the deviation for each. , and And based on the above deviations, determine whether there are compilation errors in stage 3.

[0139] Step 414: Import all the deviation comparison results of the four checkpoints into the stage difference analysis engine so that the engine can compare the deviation changes of different compilation stages horizontally.

[0140] Step 415: Generate and output a defect location report, which can accurately locate the error compilation stage and generate minimal reproducible test cases.

[0141] Please refer to Figure 5 , Figure 5 A flowchart of the abnormal step detection process provided in this embodiment of the disclosure is provided, and the process 500 includes: Step 501: Using the test input + the multi-precision execution output of all checkpoints (CP0~CP4) as the overall input, perform difference comparison on the calculation results of adjacent checkpoints in turn.

[0142] Step 502: Determine whether the output of CP0 and the output of CP1 exceed the preset tolerance. If CP0 does not exceed the tolerance but CP1 does, proceed to step 503; otherwise, proceed to step 504.

[0143] Step 503: Determine if the defect / bug is located in stage 0 to stage 1, corresponding to the high-level optimization pass group.

[0144] Step 504: Determine whether the output of CP1 and the output of CP2 exceed the preset tolerance. If CP1 does not exceed the tolerance but CP2 does, proceed to step 505; otherwise, proceed to step 506.

[0145] Step 505: Determine if the bug is located in phase 1 to phase 2, corresponding to the IR downgrade Lowering Pass group.

[0146] Step 506: Determine whether the output of CP2 and the output of CP3 exceed the preset tolerance. If CP2 does not exceed the tolerance but CP3 does, proceed to step 507; otherwise, proceed to step 508.

[0147] Step 507: Determine if the bug is located in stage 2 to stage 3, and generate a Pass group corresponding to the ISA hardware instructions.

[0148] Step 508: Determine whether the output of CP3 and the output of CP4 exceed the preset tolerance. If CP3 does not exceed the tolerance but CP4 does, proceed to step 509; otherwise, proceed to step 510.

[0149] Step 509: Determine if the bug is located in stage 3 to stage 4, corresponding to the machine code encoding / hardware execution group.

[0150] Step 510: If none of the stages are exceeded, the test is considered passed.

[0151] Step 511: Perform fine-grained Pass binary search localization within the defect stage, that is, perform binary search convergence verification on all Passes within this stage to locate the faulty Pass.

[0152] Step 512: Generate a standardized defect report that accurately identifies the faulty pass and exports the minimum IR use case that can be used to reproduce the fault.

[0153] For reference, in a specific implementation scenario, the following scenario occurs: when the self-developed AI chip compiler is compiling a certain Batch Normalization subgraph of ResNet-50, the FP8 precision output deviates abnormally from the FP32 reference value, and the CI report indicates test failure.

[0154] Its Checkpoint configuration is as follows: CP-0: StableHLO input graph (BatchNorm subgraph, shape=[1,64,56,56]); CP-1: High-level optimized HLO (passed 12 passes including BatchNormExpander, constant folding, and algebraic simplification). CP-2: LLVM IR (through 18 passes including type lowering, vectorization, and cyclic transformations); CP-3: ASIC ISA (passes 15 passes including instruction selection, register allocation, and instruction scheduling); CP-4: Machine code (final binary).

[0155] The results of the Dual-Delta three-precision comparison are as follows: CP-0 is normal; CP-1 is normal; CP-2 is abnormal; and CP-3 is abnormal.

[0156] Stage Difference Analysis: CP-0-CP-1: Consistent output, indicating normal high-level optimization pass. CP-1-CP-2: Abnormal output offset occurs; therefore, the bug is located in the Lowering stage of HLO→LLVM IR. CP-2-CP-3: Deviation inherited, no new deviations, ISA code generation is normal.

[0157] Continue with the binary search for the Pass (in the 18 HLO→LLVM IR Passes of Phase 2): Round 1: If Pass 1-9 is executed and the output is normal, then the bug is in Pass 10-18; Round 2: If Pass 1-13 is executed and the output is normal, then the bug is in Pass 14-18; Round 3: If Pass 1-15 is executed and an exception is output, then the bug is in Pass 14-15; Round 4: If Pass 1-14 is executed and the output is normal, then the bug is in Pass 15.

[0158] Location: Lowering implementation error in Pass 15 "BatchNormToReduceAndBroadcast".

[0159] Root cause: This pass incorrectly swapped the computation order of mean and variance when decomposing BatchNorm into Reduce + Broadcast, causing a shift in the normalization result. Since the error occurred in the Lowering logic (non-precision conversion), both FP32 and FP8 paths were affected (i.e., Δ_ref anomaly).

[0160] For reference, in another specific implementation scenario, when the GPU graphics compiler is compiling a certain PixelShader, the texture blending output with FP16 mediump precision exhibits banding artifacts on a specific GPU architecture.

[0161] Checkpoint configuration is as follows: CP-0: SPIR-V input (Pixel Shader, including texture sample + mix operation); CP-1: Vendor front-end IR (passed 8 passes including inlining and dead code elimination); CP-2: LLVM IR (passed 10 passes including type legalization and vectorization); CP-3: GPU ISA (20 passes including instruction selection, scheduling, register allocation, etc.).

[0162] The results of the Dual-Delta alignment (for the operation on mix(colorA, colorB, factor)) are as follows: CP-0 is normal; CP-1 is normal, CP-2 is normal, and CP-3 is abnormal.

[0163] The phase difference analysis results show that the bug is located in the CP-2-CP-3 (LLVM IR-GPU ISA) phase.

[0164] Pass Binary Search (in the 20 ISA code generation passes of Phase 3): 5 binary searches locate the "FP16 Pack / Unpack instruction generation" pass, which uses truncation instead of round-to-nearest-even when packing the intermediate FP32 result into FP16, resulting in a greater-than-expected loss of low-order precision.

[0165] Key to the judgment: Dual-Delta shows that the FP32 path output is normal (Δ_ref<10^-7), only the FP16 path is abnormal, which is clearly separated into "low precision implementation bug" rather than "FP16 inherent precision limitation".

[0166] For reference, in another specific implementation scenario, the AI ​​compiler, when compiling a fusion subgraph containing MatMul+BiasAdd+ReLU, exhibits a step-like jump in the INT8 quantization output within a specific input range.

[0167] Checkpoint configuration is as follows: CP-0: StableHLO input (MatMul[128,128]+BiasAdd+ReLU, input scale=0.02); CP-1: Optimized HLO (after 10 passes including OpFusion and quantization parameter propagation); CP-2: LLVM IR (after 14 passes including INT8 quantization, lowering, and vectorization); CP-3: ASIC ISA.

[0168] The results of the Dual-Delta three-precision alignment are as follows: CP-0 is normal; CP-1 is abnormal and CP-2 is an abnormal inheritance.

[0169] The results of the stage difference analysis are as follows: the bug is located in CP-0-CP-1 (high-level optimization stage).

[0170] In the first phase of the Pass, a binary search is performed: the “QuantizationPropagation” Pass is located 4 times out of 10 Passes. When the quantization parameter (scale / zero_point) is propagated from MatMul to BiasAdd, the quantization range of the bias is not properly considered, which causes the bias to overflow in INT8 representation.

[0171] Further reference Figure 6 As an implementation of the methods shown in the above figures, this disclosure provides an embodiment of an anomaly detection device, which is similar to... Figure 1 The examples of anomaly detection methods shown correspond to those of the examples.

[0172] like Figure 6 As shown, the anomaly detection device 600 of this embodiment may include: a serialization module 601, an execution module 602, a calculation module 603, and a determination module 604. The serialization module 601 is configured to serialize the intermediate representation of the current compilation stage using a preset interception callback function in the current compilation stage, obtaining an intermediate representation snapshot. The execution module 602 is configured to execute the intermediate representation snapshots with preset multiple data precisions, obtaining data results with multiple data precisions. The calculation module 603 is configured to calculate a reference deviation and a quantization deviation based on the data results with multiple data precisions. The determination module 604 is configured to determine that a compilation anomaly exists in the current compilation stage in response to determining that the reference deviation meets a first preset condition or the quantization deviation meets a second preset condition.

[0173] In some optional implementations of the embodiments of this disclosure, the specific processing of the serialization module 601, the execution module 602, the calculation module 603, and the determination module 604, and the resulting technical effects, can be referred to respectively. Figure 1 The relevant descriptions of steps 101-104 in the corresponding embodiments will not be repeated here.

[0174] In some optional implementations of the embodiments of this disclosure, the above-mentioned anomaly detection device 600 may further include: an interception point setting module (not shown in the figure), configured to insert interception points at the transition boundaries of each compilation stage of the compilation pipeline, wherein the transition boundary is the dividing position between two adjacent compilation stages; and to register a preset interception callback function for each interception point.

[0175] In some optional implementations of the embodiments of this disclosure, the serialization module 601 is further configured to: in response to the interception point of the current compilation stage being executed in the compilation process, trigger the interception callback function bound to the interception point to obtain the intermediate representation of the current compilation stage; and perform serialization encoding according to the specification format corresponding to the intermediate representation to obtain an intermediate representation snapshot.

[0176] In some optional implementations of the embodiments of this disclosure, the multiple data precisions include: target precision, standard precision, and high precision, wherein the precision value of the standard precision is greater than the precision value of the target precision and less than the precision value of the high precision; and the execution module 602 is further configured to: call the execution engines corresponding to the target precision, standard precision, and high precision respectively to execute the intermediate representation snapshots in parallel to obtain the corresponding target precision data results, standard precision data results, and high precision data results.

[0177] In some optional implementations of the embodiments of this disclosure, the calculation module is further configured to: calculate the absolute value of the difference between the high-precision data result and the standard-precision data result to obtain the reference deviation; and calculate the absolute value of the difference between the standard-precision data result and the target-precision data result to obtain the quantization deviation.

[0178] In some optional implementations of the embodiments of this disclosure, the determining module includes: a first determining submodule, configured to determine that a compilation error exists in the current compilation stage in response to determining that a reference deviation is greater than a first theoretical allowable deviation corresponding to the standard precision; or to determine that a compilation error exists in the current compilation stage in response to determining that a quantization deviation is greater than a second theoretical allowable deviation corresponding to the target precision.

[0179] In some optional implementations of the embodiments of this disclosure, the determining module includes: a second determining submodule, configured to determine, in response to determining that a compilation exception exists in the current compilation stage and the exception type is a low-precision path exception, in response to determining that the reference deviation is less than or equal to the first theoretical allowable deviation and the quantization deviation is greater than the second theoretical allowable deviation.

[0180] In some optional implementations of the embodiments of this disclosure, the above-mentioned anomaly detection device 600 may further include: a non-anomaly determination module (not shown in the figure), configured to calculate the absolute value of the difference between the high-precision data result and the target precision data result to obtain the total deviation; in response to determining that the total deviation is less than or equal to the second theoretical allowable deviation, determining that there is no compilation anomaly in the current compilation stage.

[0181] In some optional implementations of the embodiments of this disclosure, the above-mentioned anomaly detection device 600 may further include: a step determination module and a binary search module (not shown in the figure). The step determination module is configured to: in response to determining that there is no compilation exception in the current compilation stage and there is a compilation exception in the next compilation stage adjacent to the current compilation stage, determine that the compilation exception exists in the compilation steps included in the next compilation stage; the binary search module is configured to: perform a binary search in the compilation steps included in the next compilation stage, and determine the target compilation step that generated the compilation exception based on the search results.

[0182] In some optional implementations of the embodiments of this disclosure, the above-mentioned anomaly detection device 600 may further include: an incremental deviation determination module (not shown in the figure), configured to calculate the stage incremental deviation between the current compilation stage and the next compilation stage based on the reference deviation, quantization deviation and total deviation of the current compilation stage and the next compilation stage, wherein the stage incremental deviation includes: target precision incremental deviation, standard precision incremental deviation or high precision incremental deviation; in response to determining that the target precision incremental deviation, standard precision incremental deviation or high precision incremental deviation exceeds the corresponding preset stage deviation, determining that the compilation anomaly exists in the compilation steps included in the next compilation stage.

[0183] In some optional implementations of the embodiments of this disclosure, the binary search module is further configured to: take the first compilation step included in the next compilation stage as the first boundary node, take the last compilation step included in the next compilation stage as the second boundary node, generate a search sequence, and determine the intermediate node of the search sequence based on the first boundary node and the second boundary node; perform the following iterative steps: take the intermediate node as the new second boundary node, generate a new search sequence based on the first boundary node and the new second boundary node; determine whether the new search sequence has a compilation error based on the data results of multiple data precisions of the new search sequence; if it is determined that the new search sequence contains at least two nodes other than the first boundary node and the new second boundary node, in response to determining that the new search sequence has a compilation error, determine the intermediate node of the new search sequence based on the first boundary node and the second boundary node of the new search sequence, and continue to take the intermediate node as the new second boundary node, and determine the intermediate node of the new search sequence based on the data results of multiple data precisions of the new search sequence; if it is determined that the new search sequence contains at least two nodes other than the first boundary node and the new second boundary node, in response to determining that the new search sequence has a compilation error, determine the intermediate node of the new search sequence based on the first boundary node and the new second boundary node, and continue to perform the iterative steps: take the intermediate node as the new second boundary node, and determine the intermediate node of the new search sequence based on the data results of multiple data precisions of the new search sequence; if it is determined that the new search sequence contains at least two nodes other than the first boundary node and the new second boundary node, generate a new search sequence based on the data results of multiple data precisions of the new search sequence. The iterative steps for generating new retrieval sequences from boundary nodes: In response to determining that the new retrieval sequence does not have a compilation exception, the intermediate node is taken as the new first boundary node, and a new retrieval sequence is generated based on the new first boundary node and the second boundary node. The intermediate node of the new retrieval sequence is determined based on the first boundary node and the second boundary node of the new retrieval sequence, and the iterative steps of taking the intermediate node as the new second boundary node and generating a new retrieval sequence based on the first boundary node and the new second boundary node continue. If it is determined that the new retrieval sequence contains only one node other than the first boundary node and the new second boundary node, the iterative steps are determined to have ended, and the compilation steps corresponding to the nodes in the new retrieval sequence other than the first boundary node and the new second boundary node are determined as the target compilation steps that cause compilation exceptions. Here, the first boundary node of the new retrieval sequence is the first compilation step contained in the new retrieval sequence, and the second boundary node of the new retrieval sequence is the last compilation step contained in the new retrieval sequence.

[0184] In some optional implementations of the embodiments of this disclosure, the above-mentioned anomaly detection device 600 may further include: a report generation module (not shown in the figure), configured to generate an anomaly detection report based on the information of the target compilation step, wherein the anomaly detection report includes: the name and number of the target compilation step, the IR snapshot before the execution of the target compilation step, the IR snapshot after the execution of the target compilation step, the data results of the target compilation step at multiple data precisions, and the anomaly type of the target compilation step.

[0185] In some optional implementations of the embodiments of this disclosure, the above-mentioned anomaly detection device 600 may further include: a path anomaly determination module (not shown in the figure), configured to obtain type metadata of the target compilation step in response to determining that the anomaly type is a low-precision path anomaly, wherein the low-precision path anomaly includes: precision conversion anomaly and quantization implementation anomaly; and determine the anomaly type as a precision conversion anomaly or a quantization implementation anomaly according to the category corresponding to the type metadata.

[0186] This embodiment exists as a device 600 embodiment corresponding to the above method embodiment. The key steps or equivalent technical means that can be implemented by each component in the anomaly detection device 600 embodiment provided in this embodiment, as well as the technical effects brought about by this device embodiment, can be referred to the relevant descriptions in the above method embodiments, and will not be repeated here.

[0187] According to embodiments of the present disclosure, the present disclosure also provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform an anomaly detection method as described in any implementation of the first aspect.

[0188] According to embodiments of this disclosure, this disclosure also provides a non-transitory computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, can implement the anomaly detection method described in any of the above embodiments.

[0189] For example, the computer instructions corresponding to an anomaly detection method in this embodiment can be stored on storage media such as optical discs, hard disks, and USB flash drives. When the computer instructions corresponding to an anomaly detection method in the storage media are read or executed by a computer, the anomaly detection method as described in any of the above embodiments can be implemented.

[0190] According to embodiments of this disclosure, this disclosure also provides a computer program product including a computer program that, when executed by a processor, can implement the anomaly detection method described in any of the above embodiments.

[0191] Figure 7 A schematic block diagram of an example electronic device 700 that can be used to implement embodiments of the present disclosure is shown. The electronic device 700 according to embodiments of the present disclosure includes a processor 701 and a memory 702 storing an executable computer program. The processor 701, when executing the executable computer program stored in the memory 702, implements the anomaly detection method provided in embodiments of the present disclosure.

[0192] In some optional implementations of the embodiments of this disclosure, the electronic device 700 may further include a communication interface 703 and a bus 704 for connecting the processor 701, the memory 702 and the communication interface 703.

[0193] In some optional implementations of the embodiments of this disclosure, bus 704 is used to connect communication interface 703, processor 701 and memory 702 to realize mutual communication between these devices.

[0194] In some optional implementations of the embodiments of this disclosure, the processor 701 may be at least one of the following: Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor. It is understood that, for different devices, the electronic device used to implement the function of the processor 701 may also be other, and the embodiments of this disclosure do not specifically limit it.

[0195] The aforementioned memory 702 is used to store executable computer programs and data. The executable computer program includes computer operation instructions. Memory 702 may include high-speed RAM and may also include non-volatile memory, such as at least two disk drives. In practical applications, the aforementioned memory 702 can be volatile memory, such as random-access memory (RAM); or non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); or a combination of the above types of memory, and provides executable computer programs and data to the processor.

[0196] Furthermore, the functional modules in this embodiment can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional module.

[0197] If the integrated units described above are implemented as software functional modules and not sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure embodiment, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the method of this disclosure embodiment. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0198] According to the technical solution of this disclosure, by pre-setting interception callback functions for each compilation stage, an intermediate representation snapshot is automatically generated after all Pass operations in each stage are completed. Then, multi-precision parallel operations are performed on the same intermediate representation snapshot to calculate the reference deviation and quantization deviation in layers, and anomalies in the compilation stage are automatically determined in combination with a preset tolerance threshold. On the one hand, the entire compilation process is reproducible, reducing the granularity of fault location to a single compilation stage; on the other hand, it can accurately distinguish between general compilation logic defects and quantization conversion-related defects, distinguish between floating-point inherent rounding errors, natural quantization precision loss and code anomaly errors, reduce the workload of manual debugging, and improve the defect detection efficiency, source tracing efficiency and repair efficiency of the quantization compiler.

[0199] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0200] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this disclosure, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0201] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0202] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An anomaly detection method, characterized in that, The method includes: Using the pre-defined interception callback function in the current compilation stage, the intermediate representation of the current compilation stage is serialized to obtain an intermediate representation snapshot; The intermediate representation snapshots are executed with multiple preset data precisions to obtain data results with the multiple data precisions; Calculate the reference deviation and quantization deviation based on the data results of the multiple data precisions; In response to determining that the reference deviation meets a first preset condition and / or the quantization deviation meets a second preset condition, it is determined that there is a compilation anomaly in the current compilation stage.

2. The method according to claim 1, characterized in that, The method further includes: Interception points are inserted at the transition boundaries of each compilation stage in the compilation pipeline, wherein the transition boundary is the dividing position between two adjacent compilation stages; Register a preset interception callback function for each interception point.

3. The method according to claim 2, characterized in that, The step of serializing the intermediate representation of the current compilation stage using a pre-defined interception callback function to obtain an intermediate representation snapshot includes: In response to the compilation process reaching the interception point of the current compilation stage, the interception callback function bound to the interception point is triggered to obtain the intermediate representation of the current compilation stage; The intermediate representation snapshot is obtained by serializing and encoding it according to the standard format corresponding to the intermediate representation.

4. The method according to claim 1, characterized in that, The multiple data precisions include: target precision, standard precision, and high precision, wherein the standard precision value is greater than the target precision value and less than the high precision value; and The step of performing intermediate representation snapshots with preset multiple data precisions to obtain data results with the multiple data precisions includes: The intermediate representation snapshots are executed in parallel by calling the execution engines corresponding to the target precision, the standard precision, and the high precision respectively, to obtain the corresponding target precision data results, standard precision data results, and high precision data results.

5. The method according to claim 4, characterized in that, The calculation of reference deviation and quantization deviation based on the data results of the multiple data precisions includes: The reference deviation is obtained by calculating the absolute value of the difference between the high-precision data result and the standard-precision data result; The quantization deviation is obtained by calculating the absolute value of the difference between the standard accuracy data result and the target accuracy data result.

6. The method according to claim 4, characterized in that, The response to determining that the reference deviation meets a first preset condition and / or the quantization deviation meets a second preset condition, and determining that there is a compilation anomaly in the current compilation stage, includes: In response to determining that the reference deviation is greater than the first theoretical allowable deviation corresponding to the standard precision, a compilation anomaly is determined to exist in the current compilation stage; or In response to determining that the quantization deviation is greater than the second theoretical allowable deviation corresponding to the target accuracy, it is determined that there is a compilation anomaly in the current compilation stage.

7. The method according to claim 6, characterized in that, The step of determining that a compilation error exists in the current compilation stage in response to determining that the reference deviation meets a first preset condition and / or the quantization deviation meets a second preset condition further includes: In response to determining that the reference deviation is less than or equal to the first theoretical allowable deviation and the quantization deviation is greater than the second theoretical allowable deviation, it is determined that there is a compilation exception in the current compilation stage and the exception type is a low-precision path exception.

8. The method according to claim 7, characterized in that, The method further includes: Calculate the absolute value of the difference between the high-precision data result and the target precision data result to obtain the total deviation; In response to determining that the total deviation is less than or equal to the second theoretical allowable deviation, it is determined that there are no compilation exceptions in the current compilation stage.

9. The method according to any one of claims 1-8, characterized in that, The method further includes: In response to determining that there is no compilation exception in the current compilation stage and there is a compilation exception in the next compilation stage adjacent to the current compilation stage, it is determined that the compilation exception exists in the compilation steps included in the next compilation stage; A binary search is performed in the compilation steps included in the next compilation stage, and the target compilation step that caused the compilation exception is determined based on the search results.

10. The method according to claim 9, characterized in that, The method further includes: Based on the reference deviation, quantization deviation, and total deviation of the current compilation stage and the next compilation stage, calculate the stage increment deviation between the current compilation stage and the next compilation stage, wherein the stage increment deviation includes: target precision increment deviation, standard precision increment deviation, or high precision increment deviation. In response to determining that the target precision increment deviation, the standard precision increment deviation, or the high precision increment deviation exceeds the corresponding preset stage deviation, it is determined that the compilation exception exists in the compilation steps included in the next compilation stage.

11. The method according to claim 9, characterized in that, The step of performing a binary search in the compilation steps included in the next compilation stage, and determining the target compilation step that caused the compilation exception based on the search results, includes: The first compilation step included in the next compilation stage is taken as the first boundary node, and the last compilation step included in the next compilation stage is taken as the second boundary node. A retrieval sequence is generated, and the intermediate node of the retrieval sequence is determined based on the first boundary node and the second boundary node. Perform the following iterative steps: use the intermediate node as the new second boundary node, and generate a new retrieval sequence based on the first boundary node and the new second boundary node; Determine whether the new retrieval sequence has compilation anomalies based on data results at multiple data precisions. If it is determined that the new retrieval sequence contains at least two nodes other than the first boundary node and the new second boundary node, in response to determining that the new retrieval sequence has a compilation error, the intermediate node of the new retrieval sequence is determined based on the first boundary node and the second boundary node of the new retrieval sequence, and the iterative steps of taking the intermediate node as the new second boundary node and generating a new retrieval sequence based on the first boundary node and the new second boundary node continue to be executed. In response to determining that the new retrieval sequence does not have a compilation error, the intermediate node is used as a new first boundary node, a new retrieval sequence is generated based on the new first boundary node and the second boundary node, the intermediate node of the new retrieval sequence is determined based on the first boundary node and the second boundary node of the new retrieval sequence, and the iterative steps of using the intermediate node as a new second boundary node and generating a new retrieval sequence based on the first boundary node and the new second boundary node are continued. If it is determined that the new retrieval sequence contains only one node other than the first boundary node and the new second boundary node, the iteration step is determined to have ended, and the compilation step corresponding to the node other than the first boundary node and the new second boundary node contained in the new retrieval sequence is determined as the target compilation step that caused the compilation exception. The first boundary node of the new retrieval sequence is the first compilation step contained in the new retrieval sequence, and the second boundary node of the new retrieval sequence is the last compilation step contained in the new retrieval sequence.

12. The method according to claim 9, characterized in that, The method further includes: An anomaly detection report is generated based on the information of the target compilation step. The anomaly detection report includes: the name and number of the target compilation step, an intermediate representation snapshot before the execution of the target compilation step, an intermediate representation snapshot after the execution of the target compilation step, data results of the target compilation step at multiple data precisions, and the anomaly type of the target compilation step.

13. The method according to claim 12, characterized in that, The method further includes: In response to determining that the exception type is a low-precision path exception, the type metadata of the target compilation step is obtained, wherein the low-precision path exception includes: precision conversion exception and quantization implementation exception; Based on the category corresponding to the type metadata, determine whether the anomaly type is the precision conversion anomaly or the quantization implementation anomaly.

14. An anomaly detection device, characterized in that, The device includes: The serialization module is configured to use a preset interception callback function in the current compilation stage to serialize the intermediate representation of the current compilation stage and obtain an intermediate representation snapshot. The execution module is configured to execute the intermediate representation snapshots with multiple preset data precisions respectively, and obtain data results with the multiple data precisions; The calculation module is configured to calculate a reference deviation and a quantization deviation based on the data results of the plurality of data precisions; The determination module is configured to determine that a compilation error exists in the current compilation stage in response to determining that the reference deviation meets a first preset condition and / or the quantization deviation meets a second preset condition.

15. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the anomaly detection method according to any one of claims 1-13.

16. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the processor to execute the anomaly detection method according to any one of claims 1-13.

17. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the anomaly detection method according to any one of claims 1-13.

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