Instruction translation method, code translation apparatus, processor and system on chip

Abstract

The application discloses an instruction translation method, a code translation device, a processor and a system on chip. The method comprises the following steps: obtaining source architecture code to be executed by a target processor, and translating the source architecture code into target architecture code; in the process of translating the source architecture code into the target architecture code, in response to a to-be-translated instruction in the source architecture code being a preset instruction, the to-be-translated instruction is parsed, and a data loading mode corresponding to the to-be-translated instruction is determined, wherein the preset instruction contains a target value with a bit width greater than a preset bit width; the target value is loaded into a preset storage unit based on the data loading mode, an instruction sequence corresponding to the target value is generated, and a target instruction corresponding to the to-be-translated instruction is constructed based on the instruction sequence. The application solves the technical problem of low efficiency in translating instructions with large immediate numbers in the related art.

Description

Technical Field

[0001] This application relates to the field of processors, and more specifically, to an instruction translation method, a code translation apparatus, a processor, and a system-on-a-chip. Background Technology

[0002] In the field of computing, binary translation technology plays a crucial role, especially in terms of architectural compatibility and portability. Through binary translation, immediate values ​​in the source architecture code can be directly mapped to the target architecture to construct the corresponding target architecture code, thus enabling the portability of the source architecture code to the target architecture. However, because some instructions may contain immediate values ​​with large bit widths, these immediate values ​​may not be suitable for the immediate value mapping methods currently used in binary translation technology. This leads to low translation efficiency when performing binary translation on instructions containing immediate values ​​with large bit widths.

[0003] There is currently no effective solution to the above problems. Summary of the Invention

[0004] This application provides an instruction translation method, a code translation apparatus, a processor, and a system-on-a-chip to at least solve the technical problem of low efficiency in translating instructions with large immediate values ​​in related technologies.

[0005] According to one aspect of the embodiments of this application, an instruction translation method is provided, comprising: obtaining source architecture code to be executed by a target processor, and translating the source architecture code into target architecture code, wherein the source architecture code is code executed under the source architecture corresponding to the source processor, and the target architecture code is code executed under the target architecture corresponding to the target processor; in the process of translating the source architecture code into target architecture code, in response to the instruction to be translated in the source architecture code being a preset instruction, parsing the instruction to be translated to determine the data loading method corresponding to the instruction to be translated, wherein the preset instruction contains a target value with a bit width greater than a preset bit width; loading the target value into a preset storage unit based on the data loading method to generate an instruction sequence corresponding to the target value; and constructing a target instruction corresponding to the instruction to be translated based on the instruction sequence.

[0006] According to one aspect of the embodiments of this application, an instruction execution method is provided, comprising: in response to receiving a data read instruction, reading a target instruction from a preset storage unit, wherein the target instruction is used to characterize an instruction constructed by exponentiation based on an instruction sequence, the instruction sequence is used to characterize an instruction sequence generated based on a target value stored in the preset storage unit, the target value is loaded into the preset storage unit by a data loading method, the data loading method is used to characterize the data loading method determined by parsing the instruction to be translated in the source architecture code during the process of translating source architecture code into target architecture code, the instruction to be translated is a preset instruction, the preset instruction contains a target value, the bit width of the target value is greater than a preset bit width, the source architecture code is code executed under the source architecture corresponding to the source processor, the target architecture code is code executed under the target architecture corresponding to the target processor, and the target instruction belongs to the target architecture code; decoding the target instruction to obtain an instruction decoding result; and executing the target instruction based on the instruction decoding result to obtain an instruction execution result.

[0007] According to another aspect of the embodiments of this application, an instruction translation apparatus is also provided, comprising: a code translation module, configured to acquire source architecture code to be executed by a target processor, and translate the source architecture code into target architecture code, wherein the source architecture code is code executed under the source architecture corresponding to the source processor, and the target architecture code is code executed under the target architecture corresponding to the target processor; an instruction parsing module, configured to, during the process of translating the source architecture code into target architecture code, parse the instruction to be translated in the source architecture code in response to the instruction to be translated being a preset instruction, and determine the data loading method corresponding to the instruction to be translated, wherein the preset instruction contains a target value with a bit width greater than a preset bit width; a sequence generation module, configured to load the target value into a preset storage unit based on the data loading method, and generate an instruction sequence corresponding to the target value; and an instruction construction module, configured to construct a target instruction corresponding to the instruction to be translated based on the instruction sequence.

[0008] According to one aspect of the embodiments of this application, an instruction execution apparatus is provided, comprising: an instruction reading module, configured to read a target instruction from a preset storage unit in response to receiving a data reading instruction, wherein the target instruction is used to characterize an instruction constructed by exponentiation based on an instruction sequence, the instruction sequence is used to characterize an instruction sequence generated based on a target value stored in the preset storage unit, the target value is loaded into the preset storage unit by a data loading method, the data loading method is used to characterize the data loading method determined by parsing the instruction to be translated in the source architecture code during the process of translating source architecture code into target architecture code, the instruction to be translated is a preset instruction, the preset instruction contains a target value, the bit width of the target value is greater than a preset bit width, the source architecture code is code executed under the source architecture corresponding to the source processor, the target architecture code is code executed under the target architecture corresponding to the target processor, and the target instruction belongs to the target architecture code; an instruction decoding module, configured to decode the target instruction to obtain an instruction decoding result; and an instruction execution module, configured to execute the target instruction based on the instruction decoding result to obtain an instruction execution result.

[0009] According to another aspect of the embodiments of this application, a code translation apparatus is also provided for performing the above-described instruction translation method.

[0010] According to another aspect of the embodiments of this application, a processor is also provided, including the above-described code translation apparatus.

[0011] According to another aspect of the embodiments of this application, a system-on-a-chip is also provided, including the above-described code translation apparatus.

[0012] According to another aspect of the embodiments of this application, a computing device is also provided, including: a memory storing an executable program; and a processor for running the program, wherein the program executes the methods in various embodiments of this application when it runs.

[0013] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored executable program, wherein the methods of various embodiments of this application are implemented when the executable program is executed by a processor.

[0014] According to another aspect of the embodiments of this application, a computer program product is also provided, including computer instructions that, when executed by a processor, implement the methods in various embodiments of this application.

[0015] According to another aspect of the embodiments of this application, a computer program product is also provided, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the methods in various embodiments of this application.

[0016] According to another aspect of the embodiments of this application, a computer program is also provided, which, when executed by a processor, implements the methods of the various embodiments of this application.

[0017] In this embodiment, the method involves acquiring the source architecture code to be executed by the target processor and translating it into target architecture code. During the translation, if the instruction to be translated in the source architecture code is a preset instruction, the instruction is parsed to determine the corresponding data loading method. Based on the data loading method, the target value is loaded into a preset storage unit, generating an instruction sequence corresponding to the target value. The method of constructing the target instruction based on the instruction sequence, by analyzing the numerical characteristics of the target value when it is determined that the instruction to be translated contains a target value with a large bit width, ensures the rationality of the determined data loading method, thereby improving the efficiency and stability of loading the target value into the preset storage unit. This solves the technical problem of low efficiency in translating instructions with large immediate values ​​in related technologies.

[0018] It is worth noting that the general description above and the detailed description that follow are merely for illustrative purposes and do not constitute a limitation on this application. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0020] Figure 1 This is a hardware structure block diagram of a RISC-V system for implementing an instruction translation method, according to an embodiment of this application.

[0021] Figure 2 This is a schematic diagram of a system-on-a-chip using a RISC-V architecture, according to an embodiment of this application.

[0022] Figure 3 This is a flowchart illustrating an instruction translation method according to an embodiment of this application;

[0023] Figure 4 This is a schematic diagram illustrating a data format splitting process according to an embodiment of this application;

[0024] Figure 5 This is a schematic diagram illustrating an instruction translation process according to an embodiment of this application;

[0025] Figure 6This is a flowchart illustrating an instruction execution method according to an embodiment of this application;

[0026] Figure 7 This is a structural block diagram of an instruction translation device according to an embodiment of this application;

[0027] Figure 8 This is a structural block diagram of an instruction execution device according to an embodiment of this application;

[0028] Figure 9 This is a structural block diagram of a computing device according to an embodiment of this application. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] According to an embodiment of this application, an instruction translation method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0032] The method embodiment provided in Embodiment 1 of this application can be executed in a mobile terminal, computer terminal, or similar computing device. The computing device can employ a multi-core processor architecture, which may be RISC (Reduced Instruction Set Computing), ARM (Advanced RISC Machine), x86, etc., but is not limited to these. The processor can integrate multiple processing cores, each with its own independent L1 cache, sharing a larger L2 cache, and a unified LLC (Last Level Cache). The multi-level cache adopts a set-associative architecture, where both the L2 cache and LLC are highly configurable to adapt to different types of applications and workloads.

[0033] For example, taking the RISC-V architecture as an example, Figure 1 This is a hardware structure block diagram of a RISC-V system for implementing an instruction translation method, according to an embodiment of this application. Figure 1 As shown, the RISC-V system can be divided into the following layers from bottom to top: Reduced Instruction Set Architecture 101 (including the basic instruction set 101-1 and extended instruction set 101-2), hardware layer 102 (including processor 102-1, peripheral hardware circuits 102-2, etc.), interface layer 103, operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), middleware and library layer 105 (including system library 105-1, API 105-2 and middleware services 105-3), and application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n). The RISC-V system also includes a toolchain 107 that runs from the underlying hardware to the application layer. This toolchain may include compilers and assemblers 107-1, linkers 107-2, debuggers 107-3, simulators and emulators 107-4, integrated development environments 107-5, hardware description language tools 107-6, performance analysis tools 107-7, and version control systems 107-8, etc.

[0034] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including the basic instruction set and the extended instruction set. The basic instruction set represents the basic integer instruction set, such as RV32I and RV64I, while the extended instruction set can be floating-point, atomic operations, compressed instructions, etc.

[0035] Interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution units, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0036] The operating system layer 104 sits above the hardware, providing a hardware abstraction layer and management mechanisms, enabling applications to interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, and more.

[0037] The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while middleware can provide complex services such as network communication and graphical user interfaces.

[0038] The application layer 106 utilizes the functions and services provided by the lower layer to implement specific application logic. These applications can be command-line tools, graphical interface applications, server-side services, etc.

[0039] Toolchain 107 is a key component connecting the underlying hardware to the upper-level software. The various tools in toolchain 107 play a role at different levels to support the entire process from hardware design to software development, ensuring the coherence and effectiveness of the entire system design.

[0040] It should be noted that the layered design of the RISC-V architecture allows for decoupling between different layers, enabling each layer to be developed and optimized independently.

[0041] In one alternative embodiment, Figure 2 This is a schematic diagram illustrating a system-on-a-chip (SoC) using a RISC-V architecture according to an embodiment of this application. The SoC can refer to System On Chip, or SOC for short. Figure 2 As shown, the SOC contains at least one RISC-V core 202 (only one is shown in the figure). The RISC-V core 202 is connected to peripheral devices via bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0042] Under the aforementioned operating environment, this application provides the following: Figure 3 The instruction translation method shown. Figure 3This is a flowchart illustrating an instruction translation method according to an embodiment of this application, such as... Figure 3 As shown, the steps of this method may include:

[0043] Step S302: Obtain the source architecture code to be executed by the target processor, and translate the source architecture code into the target architecture code.

[0044] The source architecture code is the code executed under the source architecture corresponding to the source processor, and the target architecture code is the code executed under the target architecture corresponding to the target processor.

[0045] The source architecture code mentioned above can refer to code that can be executed under the source architecture but cannot be executed under the target architecture.

[0046] In one optional solution of this embodiment, considering that processors with different architectures may have different performance and resource consumption, in order to improve the running effect of the code, such as improving the stability and efficiency of the code during runtime, the user can choose to migrate the code executed under the source architecture corresponding to the source processor, i.e., the source architecture code mentioned above, to the target architecture corresponding to the target processor, so as to obtain the target code that can run stably and with high running efficiency, thereby ensuring the running effect of the code. Considering that different processor architectures may have different instruction sets and data representation methods—for example, the instruction set of the x86 architecture differs from that of the ARM or RISC-V architecture—if it is necessary to migrate source architecture code (e.g., instructions from the x86 architecture) to the target architecture (e.g., to the RISC-V architecture), in order to improve the compatibility of the source architecture code under the target architecture, users can utilize the instruction target processor to directly translate the source architecture code (i.e., the source architecture code) into code that can be executed under the target architecture (i.e., the target architecture code). This allows the translated target architecture code to run under the target processor's target architecture, improving the code's performance while retaining the various functions that the source architecture code could achieve when executed under the source architecture. This reduces the pressure on users to rewrite or modify a large amount of source code to use the target architecture.

[0047] Based on this, in order to stably run the source architecture code in the target processor, the instruction target processor can first obtain the source architecture code that needs to be executed in the target processor, and translate the source architecture code into target architecture code, so that the translated target architecture code can be executed in the target processor, while retaining the functionality that the source architecture code can achieve when executed in the source processor.

[0048] Step S304: In the process of translating the source architecture code into the target architecture code, in response to the fact that the instruction to be translated in the source architecture code is a preset instruction, the instruction to be translated is parsed to determine the data loading method corresponding to the instruction to be translated.

[0049] The preset instruction contains a target value with a bit width greater than the preset bit width.

[0050] The target value mentioned above can refer to the "immediate value" in the instruction to be translated. The preset instruction mentioned above can be an instruction containing a "large immediate value". Generally, the instructions that need to be translated usually contain "immediate values" that can be read by the processor immediately without needing to be loaded from registers or memory. The corresponding preset instruction mentioned above can refer to an instruction containing a "large immediate value" that cannot be read by the processor immediately and needs to be loaded from registers or memory. The preset bit width mentioned above can refer to the maximum bit width corresponding to the immediate value that the instruction set usable under the target architecture can accept.

[0051] In one optional embodiment, considering the limitations of instruction format and architecture design, the size of immediate values ​​that different instruction sets can accept in most processor architectures has an upper limit, and these upper limits can vary. For example, the ADD instruction under the x86 architecture can typically accept 32-bit or 16-bit immediate values, while the ADDI instruction under the ARM and RISC-V architectures can typically accept 12-bit immediate values. Assuming the source architecture is x86 and the target architecture is RISC-V, during the translation of the source architecture code, the instructions to be translated in the source architecture code may contain 32-bit immediate values. If the value exceeds the upper limit of the immediate value that ADDI instructions under the target architecture can accept, that is, if a "large immediate value" appears in the instruction to be translated, the corresponding target processor cannot directly read and process the "large immediate value" from the instruction to be translated. Instead, it needs to parse the "large immediate value", for example, decompose the "large immediate value" into three parts: <20-bit region, 12-bit region, and 0 region>, and then load these three parts into registers respectively to generate an instruction sequence that the target processor can call. Through the generated instruction sequence, the target processor can construct a target instruction that can be executed on the target processor and matches the instruction to be translated. While directly decomposing "large immediate values" in this way can achieve binary translation, it generates multiple additional instructions. Specifically, decomposing a "large immediate value" in a single instruction to be translated results in multiple related instructions, causing the size of the constructed target instruction to exceed the size of the instruction to be translated—a phenomenon known as instruction bloat. This leads to the target processor consuming excessive processor resources and reducing the execution efficiency of the target instruction. Therefore, to avoid instruction bloat during instruction translation, the target processor needs to parse the "large immediate values" in the instruction to be translated and distribute the parsing results across various target instructions. This facilitates the generation of target instructions usable by the target processor while preventing the generated target instructions from becoming too large, which could negatively impact the stability and efficiency of the target processor's execution.

[0052] Based on this, during the translation of source architecture code into target architecture code, the target processor can first determine whether the instruction to be translated in the source architecture code is one of the aforementioned preset instructions. For example, the target processor can first determine the upper limit bit width of the immediate value corresponding to the instruction set that can be executed under the target architecture, i.e., the preset bit width, and simultaneously determine the target bit width of the target value in the instruction to be translated. Then, it compares the determined target bit width with the preset bit width. If the target bit width is greater than the preset bit width, it can be determined that the instruction to be translated is one of the aforementioned preset instructions; if the target bit width is less than or equal to the preset bit width, it can be determined that the instruction to be translated is not one of the aforementioned preset instructions. Alternatively, the target processor can use bit operations (such as bitmasking and bit shifting) to quickly determine whether the value of the immediate value field in the instruction to be translated exceeds the processing range of the target architecture, thereby quickly determining whether the instruction to be translated is a preset instruction. After detecting the target value in the instruction to be translated, if the instruction to be translated is one of the aforementioned preset instructions, the target processor can parse the instruction to be translated, thereby minimizing the occurrence of instruction bloat and affecting the efficiency of data loading and instruction execution. For example, the target processor can first extract features from the target value in the instruction to be translated to determine the data characteristics of the target value, such as the value distribution, characteristics, structure, etc., and then select an appropriate data loading method based on these characteristics, such as loading the target value through bit set or bit clear instructions, extended instructions, direct loading, split loading, constant pool loading, special instruction loading, etc.

[0053] Step S306: Load the target value into the preset storage unit based on the data loading method, and generate the instruction sequence corresponding to the target value.

[0054] The aforementioned preset storage units may include, but are not limited to, registers, memory, prefetch memory, etc.

[0055] In one optional embodiment, in order to facilitate data retrieval, after determining a reasonable data loading method, the target processor can load the target value in the instruction to be translated into the preset storage unit according to the data loading method, so as to encode and generate the instruction sequence corresponding to the target value, thereby improving the efficiency of the target processor in accessing the loaded target value.

[0056] Step S308: Construct the target instruction corresponding to the instruction to be translated based on the instruction sequence.

[0057] In one optional embodiment, after the target value is loaded into a preset storage unit to generate a corresponding instruction sequence, the target processor can construct the target instruction according to the instruction sequence so that the target processor can call and execute it.

[0058] In this embodiment, the method involves acquiring the source architecture code to be executed by the target processor and translating it into target architecture code. During the translation, if the instruction to be translated in the source architecture code is a preset instruction, the instruction is parsed to determine the corresponding data loading method. Based on the data loading method, the target value is loaded into a preset storage unit, generating an instruction sequence corresponding to the target value. The method of constructing the target instruction based on the instruction sequence, by analyzing the numerical characteristics of the target value when it is determined that the instruction to be translated contains a target value with a large bit width, ensures the rationality of the determined data loading method, thereby improving the efficiency and stability of loading the target value into the preset storage unit. This solves the technical problem of low efficiency in translating instructions with large immediate values ​​in related technologies.

[0059] In this embodiment of the application, parsing the instruction to be translated and determining the data loading method corresponding to the instruction to be translated includes: extracting features from the target value to obtain the numerical features of the target value; obtaining at least one extended instruction set that can be used under the target architecture, and the usage conditions corresponding to the at least one extended instruction set; matching the numerical features with the usage conditions to obtain a condition matching result; and in response to the condition matching result that the numerical features meet the usage conditions, constructing a data loading method based on at least one extended instruction included in the at least one extended instruction set.

[0060] The aforementioned numerical characteristics may include, but are not limited to, the specific size and bit width of the target value, and the format into which the target value can be decomposed. The aforementioned at least one extended instruction set may refer to the set of extended instructions used to load the target value into a preset memory unit. Taking a RISC-V architecture as an example, the corresponding at least one extended instruction set may include, but is not limited to, the RISC-V zbs extended instruction set, the RISC-V enhanced extended instruction set, or a user-defined enhanced extended instruction set.

[0061] In one optional embodiment, to avoid instruction bloat, an extended instruction loading method can be used to load the target value in the instruction to be translated into a preset storage unit. To determine a suitable data loading method for the target value in the instruction to be translated, the target processor can first extract features from the target value before parsing the instruction to be translated, obtaining the numerical features of the target value. Simultaneously, it can obtain at least one extended instruction set that the target processor can use under the current target architecture, as well as the usage conditions corresponding to the at least one extended instruction set. After obtaining the numerical features of the target value and the usage conditions corresponding to at least one extended instruction set, the target processor can match the numerical features with the usage conditions of different extended instruction sets to obtain the corresponding condition matching results. Based on the condition matching results, the target processor can determine the compatibility between the target value in the instruction to be translated and the extended instructions in different extended instruction sets. If the condition matching results show that the numerical characteristics of the target value do not match the usage conditions of the extended instruction set, it means that the extended instructions in the extended instruction set may not be able to accurately load the target value into the preset memory unit, and in this case, the extended instruction set can be disregarded. If the condition matching results show that the numerical characteristics of the target value match the usage conditions of the extended instruction set, it means that the extended instructions in the extended instruction set can accurately load the target value into the preset memory unit, and the corresponding target processor can use at least one extended instruction included in the extended instruction set to construct a corresponding data loading method so as to accurately load the target value into the preset memory unit using at least one extended instruction.

[0062] To facilitate understanding of the aforementioned user-defined enhanced instruction set, this application provides the following explanation. Generally, users can analyze the relevant instruction behavior of target values ​​under different architectures and define the required enhanced instruction set based on the analysis results. Taking x86 and ARM architectures as examples, the most complex part to parse in these two architectures is the immediate value logic operation instruction part in the ARM architecture. This part of the instruction typically uses a combination of IMMR+IMMS+N to encode immediate values. When translating this part of the instruction, the binary translator needs to perform further encoding to obtain the required immediate value. However, for the immediate value related instructions in the x86 architecture, they can be obtained directly from the instruction without further encoding and decoding work. Based on this, three extended instructions that directly map to ARM-related instructions can be defined, as shown in Table 1 below:

[0063] Table 1

[0064] Instruction name and content Instruction function IRANDI rd rs1 imm13 (immr imms N) Wide immediate bitwise AND instruction IREORI rd rs1 imm13 (immr imms N) Wide immediate bitwise XOR instruction IRORRI rd rs1 imm13 (immr imms N) Wide immediate bitwise OR instruction IRMOVZ rd imm16hw rd Zero-extended 16-bit immediate move

[0065] It should be noted that the functional formats of the extended instructions shown in Table 1 can be aligned with ARM (immediate versions of the AND, EOR, and ORR instructions). For example, IRANDI rd rs1 imm13(immr imms N) corresponds to the AND instruction, IREORRI rd rs1 imm13(immr imms N) corresponds to the EOR instruction, IRRORRI rd rs1 imm13(immrimms N) corresponds to the ORR instruction, and IRMODVZ rd imm16 hw rd corresponds to the MOVZ instruction. Since the extended instructions shown in Table 1 can achieve direct mapping of some large immediate values, they are also applicable to some x86 instructions with large immediate values. Zero-extended 16-bit immediate shift refers to moving a 16-bit immediate value to the destination register while clearing the other bits of the destination register to zero.

[0066] In this embodiment, at least one extended instruction set includes: a standard extended instruction set and an enhanced extended instruction set. The instructions in the standard extended instruction set are used to process the bit fields of the target value, and the instructions in the enhanced extended instruction set are used to directly map the target value from the source architecture to the target architecture. Obtaining the usage conditions corresponding to at least one extended instruction set includes: in response to at least one extended instruction set being a standard extended instruction set, determining whether the usage condition is whether the target value is the exponent of a first value; in response to at least one extended instruction set being an enhanced extended instruction set, determining whether the usage condition is whether the target value is an unsigned number with a first bit width, or whether the data format of the target value can be split into a preset format.

[0067] The aforementioned standard extended instruction set may refer to the RISC-V zbs extended instruction set mentioned earlier, which can be used to process the bit fields of a target value, such as directly setting a given specific bit to 1 or 0, or inserting a specified field into a given specific bit. The aforementioned enhanced extended instruction set may refer to the aforementioned RISC-V enhanced extended instruction set, which can be used to map a target value from the source architecture to the target architecture, for example, by directly loading a large immediate value of a specific format into a register using instructions such as IREORI and IRMOVZ.

[0068] In one optional embodiment, to accurately determine the data loading method matching the target value in the instruction to be translated, the usage conditions obtained for different extended instruction sets may include at least the usage conditions corresponding to the standard extended instruction set and the usage conditions corresponding to the enhanced extended instruction set. The usage conditions corresponding to the standard extended instruction set may be: whether the target value is the exponent of a first value; for example, if the target architecture is RISC-V, the first value may be 2. The usage conditions corresponding to the enhanced extended instruction set may be: whether the target value is an unsigned number with a first bit width, or whether the data format of the target value can be split into a preset format; for example, if the target architecture is RISC-V, the first bit width may refer to 16 bits, and the preset format may refer to the IMMR+IMMS+N format.

[0069] In this embodiment, in response to the numerical characteristics satisfying the usage conditions, a data loading method is constructed based on at least one extended instruction included in at least one extended instruction set, including: in response to the target value being the exponent of a first value, a first data loading method is constructed based on bit manipulation instructions in the standard extended instruction set, wherein the bit manipulation instructions are used to characterize setting a preset bit in a preset storage unit to a second value; in response to the target value being an unsigned number with a first bit width, a second data loading method is constructed based on zero-expansion instructions in the enhanced extended instruction set, wherein the zero-expansion instructions are used to characterize zero-expansion of the bit width of the target value based on the width of the preset storage unit; in response to the data format of the target value being decomposed into a preset format, a third data loading method is constructed based on bitwise OR instructions in the enhanced extended instruction set, wherein the bitwise OR instructions are used to characterize bitwise OR processing of the target value with the value in the preset storage unit, and the value in the preset storage unit is the third value.

[0070] In one optional embodiment, if the numerical characteristics of the target value satisfy the usage conditions corresponding to at least one instruction set, the target processor can construct a corresponding data loading method based on at least one extended instruction in the extended instruction set corresponding to the usage conditions satisfied by the numerical characteristics.

[0071] For example, if the target value is the exponent of the first value (e.g., 2), the target processor can determine that the extended instruction set that can load the target value into the preset memory unit is the standard extended instruction set. The target processor can construct the corresponding first data loading method according to the bit operation instructions in the standard extended instruction set, so as to load the target value into the preset memory unit through the first data loading method. The bit operation instructions can be used to set the value of the specified preset bit in the preset memory unit. For example, the target processor can use the BSETI instruction in the zbs extended instruction set to set the specified bit in the register to 1 in order to load the target value of the exponent of 2.

[0072] If the target value is an unsigned number with the first bit width (e.g., 16), the target processor can determine that the extended instruction set that can load the target value into the preset memory unit is the enhanced extended instruction set. The target processor can then construct a corresponding second data loading method based on the zero-extension instruction in the enhanced extended instruction set to load the target value into the preset memory unit. The zero-extension instruction can be used to zero-extension the bit width of the target value according to the width of the preset memory unit. For example, the target processor can first determine the width of the preset memory unit, such as the register width, and then use the IRMOVZ instruction in the RISC-V enhanced extended instruction set to zero-extension the target value from the first bit width to the determined register width, and then load the data into the expanded target value.

[0073] If the data format of the target value can be split into a preset format, the target processor can determine the extended instruction set that can currently load the target value into the preset memory unit. This can be the aforementioned user-defined enhanced extended instruction set. The target processor can construct a corresponding third data loading method based on the bitwise OR instruction in the enhanced extended instruction set, so as to load the target value into the preset memory unit through the third data loading method. Here, the bitwise OR instruction can refer to the instruction that performs bitwise OR processing between the target value and the value in the preset memory unit. The value in the preset memory unit can be a third value, such as 0.

[0074] In this embodiment of the application, the method further includes: in response to the target value not being a second value or a third value, splitting the target value based on the bit width of the target value to obtain a first value part and a second value part, wherein the bit width of the first value part is the same as the bit width of the second value part, and the last bit of the first value part is before the first bit of the second value part; in response to the first value part and the second value part being different, detecting the first value part to determine whether there is a continuous second value in the first value part; in response to the existence of a continuous second value, determining that the data format of the target value can be split into a preset format; in response to the absence of a continuous second value, determining that the data format of the target value cannot be split into a preset format.

[0075] In one optional embodiment, in order to accurately determine whether the target value can be split into a preset format, the target processor can first determine whether the target value is the second or third value mentioned above, that is, whether it is 1 or 0. If not, the target processor can first split the target value according to the bit width of the target value to obtain a first value part and a second value part with the same bit width. The first value part can be regarded as the low-order immediate value of IMMS, and the second value part can be regarded as the high-order immediate value of IMMR. The last bit of the first value part is before the first bit of the second value part. After splitting the target value into a first value part and a second value part, the target processor can further match the first value part with the second value part. If the first value part and the second value part are different, the target processor can further detect the first value part to determine whether there is a continuous second value in the first value part, that is, whether there is a continuous 1. If there is a continuous 1 in the first value part, it can be determined that the data format of the target value can be split into the aforementioned preset format. If the target value is 1 or 0, or the target value cannot be split into a first value part and a second value part with the same bit width, or the first value part and the second value part are exactly the same, or there is no continuous 1 in the first value part, the target processor can determine that the data format of the target value cannot be split into the preset format.

[0076] To facilitate understanding of the process of splitting the target numerical data into the aforementioned preset format, Figure 4 This is a schematic diagram illustrating a data format splitting process according to an embodiment of this application. For example... Figure 4 As shown, the process of splitting the data format of the target value may include:

[0077] Step 1, Format check:

[0078] In this step, the target processor can first check whether the target value is all 0 or all 1. If the binary representation of the target value is all 0 or all 1, it means that the target value cannot be directly parsed into the format IMMR+IMMS+N. If the binary representation of the target value is not all 0 or all 1, the subsequent process can continue.

[0079] The second step is to determine the size of the element:

[0080] After determining that the target value can be parsed into the format IMMR+IMMS+N, the target processor can first start from the high-order bits of the target value, taking an element size of 64 bits (or the original bit width of the target value) to initialize the target value. Then, the target value is divided into a first half and a second half of 64 bits (or the current element size), that is, the target value is divided into two values ​​with the same bit width. After obtaining two values ​​with the same bit width, the target processor can further compare whether the binary representations of these two values ​​are the same. If they are the same, the element size can be halved (size / =2) until it is determined that the two values ​​with the same bit width after division are different in size; if they are different, the next step can be performed.

[0081] The third step is to calculate the number of 1s and the number of shifts:

[0082] The target processor can calculate the number of consecutive 1s in the halved element: For consecutive 1s in the middle, bitwise operation functions in computer languages ​​(such as Rust's `trailing_ones` and `trailing_zeros`) can be used to calculate the number of consecutive 1s and the shift number. For consecutive 1s at both ends: the binary representation of the target value needs to be inverted, and then it needs to be checked again whether the inverted target value is in the form of consecutive 1s in the middle. If the inverted target value is in the form of consecutive 1s in the middle, it means that the original immediate value satisfies the condition of consecutive 1s at both ends. At this time, the number of leading 1s and trailing 1s, as well as the shift number of leading 1s, can be calculated.

[0083] Step 4: Calculate IMMR, IMMS, and N:

[0084] IMMR: Determine the value of IMMR (i.e., the shift number) based on the shift number obtained in step 3.

[0085] IMMS and N: The values ​​of IMMS and N depend on the number of consecutive 1s and the element size, and can be obtained through mapping calculations. The specific values ​​vary depending on the parsing result of the target value. N and the higher-order bits of IMMS jointly determine the element size. When N is 0, the relationship between the number of consecutive 1s n starting from the highest bit of IMMS and the element size s is as follows: s = 32 / 2 nFor example, if the quantity is 3, then the element size is 4; when N is 1, the element size is 64 bits; the low-order part of IMMS represents the number of consecutive 1s, specifically the relationship: number of consecutive 1s = low-order bit value + 1.

[0086] Step 5: Return IMMR, IMMS, and N.

[0087] In this embodiment of the application, the method further includes: in response to the condition matching result that the numerical feature does not meet the usage conditions, decomposing the target value according to a preset combination method; in response to the successful decomposition of the target value, constructing a fourth data loading method based on the preset loading instruction corresponding to the preset combination method.

[0088] In one optional embodiment, if the condition matching result shows that the numerical characteristics of the target value do not meet the usage conditions of the aforementioned extended instruction set, the target processor can further determine whether the target value can be decomposed according to a preset combination method, such as whether it can be decomposed according to the combination method of <20-bit region, 12-bit region, 0 region>. If so, that is, the target value is successfully decomposed according to the preset combination method, the target processor can construct a corresponding fourth data loading method according to the preset loading instruction corresponding to the preset combination method, so as to load the target value into the preset storage unit using the fourth data loading method. The preset loading instruction may include: LUI instruction for loading the 20-bit region, ADDIW instruction for loading the 12-bit region, and SLLI instruction for loading the 0 region. Correspondingly, when loading the target value according to the fourth data loading method, the target processor can first decompose the target value according to the combination method of <20-bit region, 12-bit region, 0 region>, and then use LUI instruction, ADDIW instruction, and SLLI instruction to load the 20-bit region, 12-bit region, and 0 region respectively, thereby realizing the data loading operation.

[0089] In this embodiment of the application, the method further includes: in response to determining that the data loading method has failed, matching the target value with a preset value range to obtain a value matching result; in response to the value matching result being that the target value is within the preset value range, splitting the target value to obtain a first split value and a second split value, wherein the bit width of the first split value is the same as the bit width of the second split value; parsing the first split value and the second split value respectively to determine a first loading method for the first split value and a second loading method for the second split value; loading the first split value into a preset storage unit based on the first loading method, and loading the second split value into a preset storage unit based on the second loading method; in response to successfully loading the first split value and the second split value, restoring the first split value and the second split value to the target value in the preset storage unit based on a value addition instruction.

[0090] The above preset numerical range is used to reflect the bit width of the preset memory cell.

[0091] In one optional embodiment, if it is determined that the data loading method fails, i.e., the target value cannot be quickly loaded into the preset memory unit through the aforementioned four data loading methods, then taking a 64-bit RISC-V architecture as an example, the target processor can further determine whether the target value is within the preset value range to determine whether the target value conforms to the 32-bit unsigned expression format. If it does, it means that the target value can be zero-extended to 64 bits and then decomposed into two values ​​with the same bit width. At this time, these two values ​​can be regarded as values ​​that can meet the usage conditions of at least one of the aforementioned extended instruction sets. For example, these two values ​​may be 16-bit unsigned numbers, or they may be exponents of 2, or they may be values ​​that can be decomposed into the format IMMR+IMMS+N. In this case, the target processor can load these two values ​​into the preset memory unit according to the corresponding extended instruction set, and then restore these two values ​​in the preset memory unit to obtain the target value, thereby realizing the operation of loading the target value into the preset memory unit.

[0092] Based on this, if the data loading method fails, the target processor can first match the target value with a preset value range to obtain the corresponding value matching result. If the value matching result shows that the target value is within the preset value range, the target processor can extend the bit width of the target value from zero to the bit width of the preset storage unit. Then, it can split the extended value to obtain two split values ​​with the same bit width: a first split value and a second split value. The first and second split values ​​are then parsed at different levels to determine the first loading method corresponding to the first split value and the second loading method corresponding to the second split value, following the aforementioned process of determining the data loading method. Finally, the first split value is loaded into the preset storage unit according to the first loading method, and the second split value is loaded into the preset storage unit using the second loading method. Furthermore, within the preset storage unit, the target processor can use the corresponding value addition instruction to restore the loaded first and second split values ​​to the target value, thereby realizing the operation of loading the target value into the preset storage unit.

[0093] For example, assuming the target value is 0x12345678, a 32-bit unsigned number, this means that in a RISC-V architecture, this value can be directly placed into a 32-bit register. However, if the current RISC-V architecture has a 64-bit width, the target value can first be zero-extended to obtain a 64-bit extended value, such as 0x0000000012345678. Then, this extended value can be split into two 32-bit values: a first split value of 0x00000000 and a second split value of 0x12345678. For these two split values, the corresponding data loading method can be determined according to the aforementioned usage conditions, i.e., the first loading method and the second loading method. After loading these two split values ​​into the register according to the corresponding data loading method, a value addition instruction, such as the ADDUW instruction, can be used to restore these two values ​​to the target value in the register, thus realizing the data loading operation.

[0094] In this embodiment of the application, the method further includes: generating an index value based on the target value in response to the numerical matching result being outside the preset numerical range; storing the target value in a constant pool based on the index value; and reading the target value from the constant pool based on the index value and loading the target value into a preset storage unit in response to receiving a numerical loading instruction.

[0095] In one optional embodiment, if the numerical matching result shows that the target value is outside the preset numerical range and the target value cannot be loaded into the register in the aforementioned manner, the target processor can also generate a corresponding index value for the target value and store the target value in the constant pool according to the index value. Then, upon receiving a numerical loading instruction, the target value is read from the constant pool according to the index value, and finally the target value is loaded into the preset storage unit. Although loading the target value into the preset storage unit through the constant pool is less efficient than the aforementioned data loading method, using the constant pool as the most basic data loading method to load the target value into the preset storage unit can largely guarantee the target processor's need for the target value, thereby ensuring the stability of the translation of the instructions to be translated.

[0096] To facilitate understanding of the process described above, in which the target value of the instruction to be translated is loaded into a preset storage unit to achieve instruction translation, Figure 5 This is a schematic diagram illustrating an instruction translation process according to an embodiment of this application. Binary translation involves front-end, mid-end, and back-end processes. The front-end is primarily responsible for the semantic interpretation of the instructions, while the mid-end and back-end are responsible for semantic optimization and generating the target instructions. For example... Figure 5As shown, during the instruction translation process, the front-end can first parse the instruction to be translated to determine whether it is a preset instruction. If it is a preset instruction, the target value for data loading is determined from the preset instructions, and then the target value is sent to the middleware. The front-end handles both fixed and implicit large immediate values. Implicit large immediate values ​​refer to those present in the target instruction being translated, such as the Guest architecture ADDI instruction, where the immediate value is not necessarily the same for each instruction. For fixed large immediate value handling, direct enhanced extended instruction mapping can be performed. For example, some condition bit calculations require mask bit operations on fixed bits. If the mask can be described using the IMMR+IMMS+N encoding method, then it can be directly parsed and described using enhanced extended instructions at that location. After receiving the target value sent by the front end, the middleware can determine whether the target value can be directly binary translated using at least one extended instruction set and the corresponding usage conditions. If the target value can be directly binary translated, the middleware can determine at least one extended instruction in the corresponding extended instruction set and send the extended instruction and the target value to the backend, so that the backend can directly load the target value into the preset storage unit using the corresponding extended instruction. For example, the middleware can check whether the target value is a power of 2. If so, it can use the BSETI instruction to load the data. Alternatively, it can check whether the target value is a 32-bit unsigned number. If so, it can use the IRMOVZ instruction to load the data. Or, it can check whether the target value can be parsed into the format IMMR+IMMS+N. If so, it can use the IR_ORRI instruction to load the data.

[0097] Furthermore, if the target value cannot be directly binary translated, the intermediate processor can determine whether the target value can be transformed. For example, the target processor can determine whether to zero-extend the target value according to the bit width of the preset memory unit, and then split the extended target value into two split values ​​with the same bit width. It can then determine whether to determine the corresponding extension instructions for loading data for the different split values. If the corresponding extension instructions can be determined, the target processor can send the determined extension instructions and the corresponding split values ​​to the backend, so that the backend can use the determined extension instructions to load the corresponding split values ​​into the preset memory unit and use a value addition instruction to restore them in the preset memory unit. If, after zero-expansion and splitting the target value, a suitable extension instruction for data loading still cannot be determined, the mid-end can directly send the target value to the back-end. In this case, the back-end can only receive the target value and not the corresponding extension instruction. The corresponding preset instruction group in the back-end is empty at this time. In this case, the back-end can generate a suitable index value for the target value through a constant pool and store the target value in the constant pool according to the index value. Then, when a value loading instruction is received, the corresponding target value is called from the constant pool according to the index value in the value loading instruction to load the target value into the preset storage unit.

[0098] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation portals are provided for users to choose to authorize or refuse.

[0099] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0100] According to another aspect of this application, an instruction execution method is also provided. Figure 6 This is a flowchart illustrating an instruction execution method according to an embodiment of this application, such as... Figure 6 As shown, the method may include the following steps:

[0101] Step S602: In response to receiving a data read instruction, the target instruction is read from a preset storage unit.

[0102] Here, the target instruction is used to represent the instruction constructed by the exponent based on the instruction sequence. The instruction sequence is used to represent the instruction sequence generated based on the target value stored in the preset storage unit. The target value is loaded into the preset storage unit through a data loading method. The data loading method is used to represent the data loading method determined by parsing the instructions to be translated in the source architecture code during the process of translating the source architecture code into the target architecture code. The instructions to be translated are preset instructions, which contain the target value. The bit width of the target value is greater than the preset bit width. The source architecture code is the code executed under the source architecture corresponding to the source processor. The target architecture code is the code executed under the target architecture corresponding to the target processor. The target instruction belongs to the target architecture code.

[0103] Step S604: Decode the target instruction to obtain the instruction decoding result.

[0104] Step S606: Execute the target instruction based on the instruction decoding result to obtain the instruction execution result.

[0105] In one optional embodiment, when executing the target instruction, the target processor may first read the target instruction from a preset storage unit and decode the target instruction to obtain the corresponding instruction decoding result. Finally, the target instruction is executed according to the instruction decoding result to obtain the corresponding instruction execution result.

[0106] Here, the target instruction can refer to an instruction constructed from an instruction sequence. The instruction sequence can be a sequence of instructions generated from a target value stored in a preset memory unit. The target value can be loaded into the preset memory unit via a data loading method. The data loading method refers to the data loading method determined by parsing the instructions to be translated in the source architecture code during the translation of the source architecture code into target architecture code. The instructions to be translated are preset instructions, which contain the target value, and the bit width of the target value is greater than the preset bit width. The source architecture code is the code executed under the source architecture corresponding to the source processor, and the target architecture code is the code executed under the target architecture corresponding to the target processor. The target instruction belongs to the target architecture code. The specific process of constructing the corresponding target instruction for the instructions to be translated during code translation can be found above and will not be elaborated upon here.

[0107] During the decoding phase, the target processor can first analyze the target instruction to determine information such as the instruction type, opcode, operands, and register addresses, in order to construct the corresponding instruction decoding result. Once the target instruction is decoded, the target processor can enter the execution phase. For example, the target processor can perform arithmetic operations, logical operations, data movement, conditional jumps, or other operations based on the instruction decoding result of the target instruction to obtain the corresponding instruction execution result.

[0108] According to another aspect of the embodiments of this application, the embodiments of this application also provide an instruction translation apparatus for implementing the above-described instruction translation method. Figure 7 This is a structural block diagram of an instruction translation device according to an embodiment of this application, such as... Figure 7 As shown, the device may include: a code translation module 702, an instruction parsing module 704, a sequence generation module 706, and an instruction construction module 708.

[0109] The code translation module 702 is used to obtain the source architecture code to be executed by the target processor and translate the source architecture code into the target architecture code. The source architecture code is the code executed under the source architecture corresponding to the source processor, and the target architecture code is the code executed under the target architecture corresponding to the target processor. The instruction parsing module 704 is used to parse the instruction to be translated in the source architecture code as a preset instruction if the instruction to be translated in the source architecture code is a preset instruction, and determine the data loading method corresponding to the instruction to be translated. The preset instruction contains a target value with a bit width greater than a preset bit width. The sequence generation module 706 is used to load the target value into a preset storage unit based on the data loading method and generate an instruction sequence corresponding to the target value. The instruction construction module 708 is used to construct the target instruction corresponding to the instruction to be translated based on the instruction sequence.

[0110] In this embodiment, the instruction parsing module 704 includes: a feature extraction unit, used to extract features from the target value to obtain the numerical features of the target value; a condition acquisition unit, used to acquire at least one extended instruction set that can be used under the target architecture, and the usage conditions corresponding to the at least one extended instruction set; a feature matching unit, used to match the numerical features with the usage conditions to obtain a condition matching result; and a mode construction unit, used to construct a data loading mode based on at least one extended instruction included in the at least one extended instruction set in response to the condition matching result indicating that the numerical features meet the usage conditions.

[0111] In this embodiment, at least one extended instruction set includes: a standard extended instruction set and an enhanced extended instruction set. The instructions in the standard extended instruction set are used to process the bit fields of the target value, and the instructions in the enhanced extended instruction set are used to directly map the target value from the source architecture to the target architecture. The condition acquisition unit is further configured to: in response to at least one extended instruction set being a standard extended instruction set, determine whether the usage condition is whether the target value is the exponent of a first value; in response to at least one extended instruction set being an enhanced extended instruction set, determine whether the usage condition is whether the target value is an unsigned number with a first bit width, or whether the data format of the target value can be split into a preset format.

[0112] In this embodiment, the method construction unit is further configured to: in response to the target value being the exponent of a first value, construct a first data loading method based on bit manipulation instructions in the standard extended instruction set, wherein the bit manipulation instructions are used to characterize setting a preset bit in a preset storage unit to a second value; in response to the target value being an unsigned number with a first bit width, construct a second data loading method based on zero-expansion instructions in the enhanced extended instruction set, wherein the zero-expansion instructions are used to characterize zero-expansion of the bit width of the target value based on the width of the preset storage unit; in response to the target value's data format being decomposed into a preset format, construct a third data loading method based on bitwise OR instructions in the enhanced extended instruction set, wherein the bitwise OR instructions are used to characterize bitwise OR processing of the target value with the value in the preset storage unit, and the value in the preset storage unit is the third value.

[0113] In this embodiment, the apparatus further includes: a value splitting module, configured to split the target value based on the bit width of the target value to obtain a first value part and a second value part in response to the target value not being a second value or a third value, wherein the bit width of the first value part is the same as the bit width of the second value part, and the last bit of the first value part is before the first bit of the second value part; a value detection module, configured to detect the first value part in response to the difference between the first value part and the second value part, and determine whether there is a continuous second value in the first value part; a first determination module, configured to determine that the data format of the target value can be split into a preset format in response to the existence of a continuous second value; and a second determination module, configured to determine that the data format of the target value cannot be split into a preset format in response to the absence of a continuous second value.

[0114] In this embodiment of the application, the above-mentioned device further includes: a numerical decomposition module, used to decompose the target numerical value according to a preset combination method in response to the condition matching result being that the numerical feature does not meet the usage conditions; and a method construction module, used to construct a fourth data loading method based on the preset loading instruction corresponding to the preset combination method in response to the successful decomposition of the target numerical value.

[0115] In this embodiment, the apparatus further includes: a value matching module, configured to match the target value with a preset value range in response to a failure to determine the data loading method, to obtain a value matching result; a value splitting module, configured to split the target value to obtain a first split value and a second split value in response to the value matching result indicating that the target value is within the preset value range, wherein the bit width of the first split value is the same as the bit width of the second split value; a value parsing module, configured to parse the first split value and the second split value respectively, to determine a first loading method for the first split value and a second loading method for the second split value; a value loading module, configured to load the first split value into a preset storage unit based on the first loading method, and load the second split value into a preset storage unit based on the second loading method; and a value restoration module, configured to restore the first split value and the second split value to the target value in the preset storage unit based on a value addition instruction in response to a successful loading of the first split value and the second split value.

[0116] In this embodiment of the application, the above-mentioned device further includes: an index generation module, used to generate an index value based on the target value in response to the value matching result being outside the preset value range; a value storage module, used to store the target value in a constant pool based on the index value; and a value reading module, used to read the target value from the constant pool based on the index value and load the target value into a preset storage unit in response to receiving a value loading instruction.

[0117] According to another aspect of the embodiments of this application, the embodiments of this application also provide an instruction execution apparatus for implementing the above-described instruction execution method. Figure 8 This is a structural block diagram of an instruction execution device according to an embodiment of this application, such as... Figure 8 As shown, the device may include: an instruction reading module 802, an instruction decoding module 804, and an instruction execution module 806.

[0118] The instruction reading module 802 is used to read the target instruction from the preset storage unit in response to receiving a data reading instruction. The target instruction represents the instruction constructed by exponentiation based on the instruction sequence. The instruction sequence represents the instruction sequence generated based on the target value stored in the preset storage unit. The target value is loaded into the preset storage unit through a data loading method. The data loading method represents the data loading method determined by parsing the instruction to be translated in the source architecture code during the translation of the source architecture code into the target architecture code. The instruction to be translated is a preset instruction, which contains the target value. The bit width of the target value is greater than the preset bit width. The source architecture code is the code executed under the source architecture corresponding to the source processor, and the target architecture code is the code executed under the target architecture corresponding to the target processor. The target instruction belongs to the target architecture code. The instruction decoding module 804 is used to decode the target instruction to obtain the instruction decoding result. The instruction execution module 806 is used to execute the target instruction based on the instruction decoding result to obtain the instruction execution result.

[0119] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, they can also be implemented by hardware. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a processor to execute the methods of the various embodiments of this application.

[0120] According to another aspect of the embodiments of this application, a code translation apparatus is also provided for performing the above-described instruction translation method.

[0121] According to another aspect of the embodiments of this application, a processor is also provided, including the above-described code translation apparatus.

[0122] According to another aspect of the embodiments of this application, a system-on-a-chip is also provided, including the above-described code translation apparatus.

[0123] Embodiments of this application may provide a computing device. Figure 9 This is a structural block diagram of a computing device according to an embodiment of this application. Figure 9 As shown, the computing device A may include one or more (only one is shown in the figure) processors 902, memory 904 and peripheral interfaces 906, wherein the processors 902, memory 904 and peripheral interfaces 906 are interconnected via a bus 908.

[0124] The memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the methods and apparatus in the embodiments of this application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, thereby implementing the methods in the above embodiments. The memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to terminal A via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0125] The processor can invoke information and application programs stored in the memory through a transmission device to execute the methods in the various embodiments of this application.

[0126] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0127] Embodiments of this application also provide a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store program code executed by the method provided in the above embodiments.

[0128] Optionally, in this embodiment, the storage medium can be located in any one of the computing devices in the computing device group.

[0129] Optionally, in this embodiment, the computer-readable storage medium includes a stored executable program, wherein the methods of various embodiments of the present application are implemented when the executable program is executed by a processor.

[0130] Embodiments of this application also provide a computer program product. Optionally, in this embodiment, the computer program product may include a computer program that, when executed by a processor, implements the methods provided in the embodiments described above.

[0131] Embodiments of this application also provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which can be used to store a computer program that, when executed by a processor, implements the method provided in the above embodiments.

[0132] Embodiments of this application also provide a computer program. Optionally, in this embodiment, when the computer program is executed by a processor, it implements the method provided in the above embodiments.

[0133] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0134] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of units or modules may be electrical or other forms.

[0135] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0136] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0137] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0138] The above are merely preferred embodiments of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for translating instructions, characterized in that, include: Obtain the source architecture code to be executed by the target processor, and translate the source architecture code into target architecture code, wherein the source architecture code is the code executed under the source architecture corresponding to the source processor, and the target architecture code is the code executed under the target architecture corresponding to the target processor; In the process of translating the source architecture code into the target architecture code, in response to the fact that the instruction to be translated in the source architecture code is a preset instruction, the instruction to be translated is parsed to determine the data loading method corresponding to the instruction to be translated, wherein the preset instruction contains a target value with a bit width greater than a preset bit width; Based on the data loading method, the target value is loaded into a preset storage unit, and an instruction sequence corresponding to the target value is generated; The target instruction corresponding to the instruction to be translated is constructed based on the instruction sequence.

2. The method according to claim 1, characterized in that, The step of parsing the instruction to be translated and determining the data loading method corresponding to the instruction to be translated includes: Feature extraction is performed on the target value to obtain the numerical features of the target value; Obtain at least one extended instruction set that can be used under the target architecture, and the usage conditions corresponding to the at least one extended instruction set; The numerical features are matched with the usage conditions to obtain the condition matching result; In response to the condition matching result bit indicating that the numerical feature satisfies the usage condition, the data loading method is constructed based on at least one extended instruction included in the at least one extended instruction set.

3. The method according to claim 2, characterized in that, The at least one extended instruction set includes: a standard extended instruction set and an enhanced extended instruction set. Instructions in the standard extended instruction set are used to process the bit fields of the target value, and instructions in the enhanced extended instruction set are used to directly map the target value from the source architecture to the target architecture. Obtaining the usage conditions corresponding to the at least one extended instruction set includes: In response to the fact that the at least one extended instruction set is the standard extended instruction set, the usage condition is determined to be whether the target value is the exponent of the first value; In response to the at least one extended instruction set being the enhanced extended instruction set, the usage condition is determined to be whether the target value is an unsigned number with a first-bit width, or whether the data format of the target value can be split into a preset format.

4. The method according to claim 3, characterized in that, In response to the numerical feature satisfying the usage condition, the data loading method is constructed based on at least one extended instruction included in the at least one extended instruction set, comprising: In response to the target value being an exponent of the first value, a first data loading method is constructed based on bit manipulation instructions in the standard extended instruction set, wherein the bit manipulation instructions are used to characterize setting a preset bit in the preset storage unit to a second value; In response to the target value being an unsigned number with the first bit width, a second data loading method is constructed based on the zero-expansion instruction in the enhanced extension instruction set, wherein the zero-expansion instruction is used to characterize zero-expansion of the bit width of the target value based on the width of the preset storage unit; In response to the target value's data format being split into a preset format, a third data loading method is constructed based on the bitwise OR instruction in the enhanced extended instruction set. The bitwise OR instruction is used to characterize performing a bitwise OR operation between the target value and the value in the preset storage unit, where the value in the preset storage unit is the third value.

5. The method according to claim 3, characterized in that, The method further includes: In response to the target value not being a second or third value, the target value is split based on the bit width of the target value to obtain a first value part and a second value part, wherein the bit width of the first value part is the same as the bit width of the second value part, and the last bit of the first value part is before the first bit of the second value part. In response to the difference between the first numerical portion and the second numerical portion, the first numerical portion is detected to determine whether there is a continuous second numerical value in the first numerical portion; In response to the existence of consecutive second values, it is determined that the data format of the target value can be split into the preset format; In response to the absence of consecutive second values, it is determined that the data format of the target value cannot be split into the preset format.

6. The method according to claim 2, characterized in that, The method further includes: In response to the condition matching result indicating that the numerical feature does not meet the usage conditions, the target numerical value is decomposed according to a preset combination method; In response to the successful decomposition of the target value, a fourth data loading method is constructed based on the preset loading instruction corresponding to the preset combination method.

7. The method according to claim 1, characterized in that, The method further includes: In response to determining that the data loading method has failed, the target value is matched with a preset value range to obtain a value matching result; In response to the numerical matching result that the target value is within the preset numerical range, the target value is split to obtain a first split value and a second split value, wherein the bit width of the first split value and the bit width of the second split value are the same. The first split value and the second split value are analyzed respectively to determine the first loading method of the first split value and the second loading method of the second split value; The first split value is loaded into the preset storage unit based on the first loading method, and the second split value is loaded into the preset storage unit based on the second loading method; In response to the successful loading of the first split value and the second split value, the first split value and the second split value are restored to the target value in the preset storage unit based on the value addition instruction.

8. The method according to claim 7, characterized in that, The method further includes: In response to the numerical matching result being that the target value is outside the preset numerical range, an index value is generated based on the target value; The target value is stored in the constant pool based on the index value; In response to receiving a value loading instruction, the target value is read from the constant pool based on the index value and loaded into the preset storage unit.

9. A method for executing instructions, characterized in that, include: In response to receiving a data read instruction, a target instruction is read from a preset storage unit. The target instruction represents an instruction constructed from an instruction sequence, and the instruction sequence represents an instruction sequence generated from a target value stored in the preset storage unit. The target value is loaded into the preset storage unit via a data loading method, which represents the data loading method determined by parsing the instruction to be translated in the source architecture code during the translation of the source architecture code into target architecture code. The instruction to be translated is a preset instruction, which includes the target value. The bit width of the target value is greater than a preset bit width. The source architecture code is code executed under the source architecture corresponding to the source processor, and the target architecture code is code executed under the target architecture corresponding to the target processor. The target instruction belongs to the target architecture code. The target instruction is decoded to obtain the instruction decoding result; The target instruction is executed based on the instruction decoding result to obtain the instruction execution result.

10. A code translation device, characterized in that, The code translation device is used to perform the method described in any one of claims 1 to 9.

11. A processor, characterized in that, include: The apparatus of claim 10.

12. A system-on-a-chip, characterized in that, include: The apparatus of claim 10.

13. A computing device, characterized in that, include: Memory, which stores executable programs; A processor for running the program, wherein the program, when running, performs the method according to any one of claims 1 to 9.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored executable program, wherein the executable program, when executed by a processor, implements the method according to any one of claims 1 to 9.

15. A computer program product, characterized in that, Includes computer instructions that, when executed by a processor, implement the method according to any one of claims 1 to 9.

Images