An online flash read-write method and system based on an aerial entertainment system processor board

Abstract

The present application relates to the field of aviation entertainment system development and testing, and more particularly to a flash online read-write method and system based on an aviation entertainment system processor board. The method initially configures the test device through test software on the test industrial computer to establish a network communication connection between the test device and the test industrial computer and determine a CPU configuration file loading path; a file transfer service is run on the test industrial computer to enable the test device to acquire a configuration file matching the dual-core processor and the target board via Ethernet. Unlike the prior art, the present application solves the problem of cumbersome operation and easy damage to the circuit board in the conventional hard copy mode, significantly improves the simplicity, safety and efficiency of flash online read-write, and increases the read-write speed by 95% compared to the conventional hard copy mode, which takes at least one hour or more, while the present method only takes about 3 minutes to complete.

Description

Technical Field

[0001] This invention relates to the field of aviation entertainment system development and testing. More specifically, this invention relates to a method and system for online flash reading and writing based on an aviation entertainment system processor board. Background Technology

[0002] Currently, the repair and testing of avionics components typically involves loading programs, reading data, or burning data into the memory on the board. The TPCU-t component, installed in aircraft seats, provides passengers with audio, video, and interactive entertainment services during their journey. This component is widely used in various aircraft models, including the A320, A330, A340, B747, B767, B777, and B787. Because the original manufacturer's testing equipment and repair techniques are not publicly available, the domestic capability to repair TPCU-t components and their processor boards is extremely limited.

[0003] When repairing TPCU-t components, it is often necessary to reload the flash program of the board. A common method is to use a hard copy method, which involves removing the memory chip from the circuit board, using a general-purpose programmer to read and write data or burn the program, and then resoldering the chip back onto the original circuit board after the operation is completed. Although this method can operate the flash, it has drawbacks such as being cumbersome, inefficient, and having a high risk of hardware damage during disassembly and soldering, which can easily introduce new electrical faults or even cause irreversible physical damage to the circuit board.

[0004] In summary, existing technologies generally suffer from low efficiency, easy damage to hardware, and poor stability when performing Flash read and write operations on circuit boards. Summary of the Invention

[0005] To address the aforementioned technical problems of low efficiency, easy damage to hardware, and poor stability, the present invention provides solutions in the following aspects.

[0006] In a first aspect, the present invention discloses a method for online flash reading and writing based on an aviation entertainment system processor board, applied to a test industrial control computer, a test device, and a target board. The target board includes a dual-core processor OMAP5910 integrating an ARM core and a DSP core, an SDRAM chip MT48LC32M16A2, and a Flash memory chip S29GL256N. The method includes: Step S10: Initially configure the test device through the serial port on the test industrial control computer to establish a network communication connection between the test device and the test industrial control computer and determine the CPU configuration file loading path; Step S20: Run a file transfer service on the test industrial control computer to enable the test device to obtain a configuration file that matches the dual-core processor and the target board via Ethernet. The configuration file is written according to the software configuration manual of the dual-core processor and the hardware connection relationship of the target board, and is used to configure the internal register data parameters of the dual-core processor to realize communication between the test device and the dual-core processor. Step S30: Establish a remote login connection between the test industrial computer and the test device; the test device loads register configuration parameters into the dual-core processor via the JTAG interface according to the configuration file to complete the target board initialization; Step S40: The test industrial control computer sends Flash read / write commands to the test device, and then the test device controls the dual-core processor to perform online read / write operations on the target board via the JTAG interface.

[0007] Preferably, step S10, configuring the testing device via the serial port on the industrial control computer, further includes: Configure the IP address and subnet mask of the test device, as well as the host IP address of the test industrial control computer acting as the upper computer; The configuration includes the firmware information and network parameters of the test device, in order to establish network communication between the test device and the test industrial control computer and determine the access path of the configuration file.

[0008] Preferably, before establishing a remote login connection between the test industrial computer and the test device, the following steps are also included: Power on the target board and check whether the network connection between the test industrial computer and the test device is reliable; If the network connection is reliable and the test device can read the configuration file through the file transfer service, the test industrial control computer will initiate a remote login connection request to the test device. If the remote login connection is successful, Flash read and write operations will be performed. Otherwise, return to retest the network connection.

[0009] Preferably, step S30 further includes: The configuration file is generated based on the dual-core processor's software configuration manual and the target board's hardware connection relationships; Hardware connectivity includes the peripheral connections of the Flash memory chip, SDRAM, and crystal oscillator on the target board; The configuration file sets corresponding configuration parameters for different register addresses of the dual-core processor. The configuration parameters include at least the register address, the written value, and the execution order. After the target board is powered on, the configuration parameters are loaded into the SDRAM via Ethernet and the test device to complete the target board initialization.

[0010] It should be added that after the target board is powered on, the test device obtains the configuration file via Ethernet, parses the register configuration commands contained therein, and writes them one by one into the corresponding registers of the processor through the JTAG interface, thereby completing the initialization configuration of the clock, memory interface, etc., and enabling the SDRAM and other peripherals to enter a usable state, thus completing the target board initialization.

[0011] Preferably, the configuration file includes: Configuration of the ARM core in a dual-core processor and configuration of the DSP core; The ARM core is based on the ARM9TDMI architecture and supports 32-bit and 16-bit instruction sets. The ARM core is configured to drive the peripherals and network protocol stack of the target board, while the DSP core is configured to match the dual-core working environment of the dual-core processor. When generating the configuration file, the clock division parameters of the dual-core processor and the timing parameters of the external memory interface are determined based on the target board's external clock, external memory allocation location, and peripheral connection relationships, as well as the dual-core processor's datasheet.

[0012] Preferably, the configuration file also includes clock configuration parameters: The clock configuration parameters are determined based on the target board's external clock, external memory allocation location, and peripheral connection relationships, and according to the calculation formula in the dual-core processor's datasheet. The clock division parameters and external memory interface timing parameters of the dual-core processor are then written into the register configuration parameters.

[0013] Preferably, the configuration file also includes memory mapping parameters and external memory interface configuration parameters: The memory mapping parameter is used to specify the mapping address of the internal RAM of the dual-core processor. The test device accesses the target board to define the workspace for debugging. The external memory interface configuration parameters are determined based on the external memory allocation location of the target board.

[0014] Preferably, the configuration file also includes Flash bus access parameters: Flash bus access parameters include chip type parameters for adapting to the type of Flash memory chip, capacity parameters for adapting to the capacity boundary of Flash memory chip, and bus width parameters for adapting to the bus connection method between Flash memory chip and dual-core processor.

[0015] Preferably, in step S40, the test device controls the dual-core processor via the JTAG interface to perform online read / write operations on the target board, including: Flash memory chips include boot Flash and application Flash; The configuration file selected based on the target board's board part number; Perform read operations on the boot Flash, write operations on the boot Flash, read operations on the app Flash, and write operations on the app Flash on the test industrial control computer. When a write operation is selected, the corresponding program data is written to the corresponding Flash on the target board via the test device; When a read operation is selected, the test device reads the program data in the corresponding Flash on the target board and transmits it back to the test industrial control computer. After the Flash read / write operation is complete, disconnect the test industrial computer from the test device.

[0016] This invention utilizes a collaborative communication method combining TFTP file transfer service and Telnet remote login. It generates a configuration file containing clock division, memory mapping, external memory interface timing, and Flash bus access parameters based on the target board's dual-core processor (OMAP5910) software configuration manual and hardware peripheral connection relationships. The configuration parameters are loaded into the processor via the JTAG interface, and differentiated Flash read / write execution instructions are output. After successful target board initialization, the boot Flash and app Flash programs are loaded, data is read, and programmed online. This means that this invention can achieve online flash read / write operations on an aviation entertainment system processor board without relying on desoldering the Flash chip. It possesses dual functions: proactive collaborative control of the entire process from test device configuration to target board initialization, and output of Flash read / write results. It is simple to operate, has no risk of hardware damage, and offers fast read / write speeds and high stability.

[0017] Compared with existing technologies, the method of this invention solves the problems of cumbersome operation, high risk of hardware damage, and permanent damage to circuit boards caused by the need to disassemble and solder the Flash chip in the traditional hard copy method.

[0018] In a second aspect, the present invention discloses a flash online read / write system based on an aviation entertainment system processor board, comprising: Test industrial control computers, testing equipment, and target boards; The testing equipment includes, The serial port configuration module is used to perform initial configuration of the test device through the serial port on the test industrial control computer, so as to establish a network communication connection between the test device and the test industrial control computer and determine the CPU configuration file loading path; The file transfer service module is used to run a file transfer service on the test industrial control computer, so that the test device can obtain a configuration file that matches the dual-core processor and the target board via Ethernet. The configuration file is written according to the software configuration manual of the dual-core processor and the hardware connection relationship of the target board, and is used to configure the internal register data parameters of the dual-core processor to realize communication between the test device and the dual-core processor. The remote login module is used to establish a remote login connection between the test industrial computer and the test device; The read / write command module is used to send Flash read / write commands to the test device via the test industrial control computer; The testing device is used to test the dual-core processor controlling the target board via the JTAG interface to perform online read and write operations.

[0019] The beneficial effects of this invention are as follows: By configuring the firmware information, network parameters and configuration file working directory of the test device through the serial port, and by coordinating the TFTP file transfer service and Telnet remote login on the host side, the problems of the traditional hard copy method, such as the cumbersome operation of disassembling and soldering the Flash chip, the high risk of hardware damage, and the permanent damage to the circuit board, are completely eliminated. After the test device is powered on and connected to the target board, the clock division, memory mapping, external memory interface timing and Flash bus access parameters in the configuration file are loaded via the network. The configuration values ​​are written to the ARM core and DSP core of the dual-core processor (OMAP5910) via the JTAG interface, so that the CPU can start normally and drive the peripherals. The entire initialization process is completed quickly. At the same time, the differentiated configuration file is automatically matched according to the board part number, supporting online program loading, data reading and writing of boot Flash and app Flash, and can actively disconnect after reading and writing is completed. The entire solution eliminates the need for complex chip desoldering and resoldering operations, enabling proactive collaborative control throughout the entire process from test device configuration and target board initialization to online Flash reading and writing. It is easy to operate, poses no risk of hardware damage, offers fast reading and writing speeds and high stability, and significantly improves the testing and maintenance efficiency and intelligent operation and maintenance level of avionics boards. Attached Figure Description

[0020] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein: Figure 1 This is a flowchart of the online flash read / write method based on the processor board of the aviation entertainment system in Embodiment 1; Figure 2 This is the flowchart of the host computer software design in Example 1; Figure 3 This is the overall block diagram of the flash online read / write system based on the aviation entertainment system processor board in Embodiment 2. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0023] It should be noted that, in the specific embodiments of the present invention, the OMAP5910 dual-core processor from Texas Instruments is used as an example for the description and verification of the technical solution.

[0024] However, those skilled in the art should understand that the core principles and configuration process of the Flash online read / write method and system based on the testing device provided by this invention do not depend on the specific model OMAP5910.

[0025] In practical implementation, the processor can also be other embedded processor chips with similar architecture. The Flash online read / write function of this invention can be implemented simply by configuring the corresponding register parameters and test device configuration file according to the target processor's datasheet. Therefore, the scope of protection claimed by this invention should not be limited to the specific example of the OMAP5910.

[0026] Example 1 like Figure 1 As shown, this embodiment discloses a method for online flash reading and writing based on an aviation entertainment system processor board, applied to a test industrial control computer, a test device, and a target board. The target board includes a dual-core processor integrating an ARM core and a DSP core, SDRAM, and a Flash memory chip. The method includes: Step S10: Initially configure the test device through the serial port on the test industrial control computer to establish a network communication connection between the test device and the test industrial control computer and determine the CPU configuration file loading path.

[0027] Preferably, step S10, configuring the testing device via the serial port on the industrial control computer, further includes: Configure the IP address and subnet mask of the test device, as well as the host IP address of the test industrial control computer acting as the upper computer; The configuration includes the firmware information and network parameters of the test device, in order to establish network communication between the test device and the test industrial control computer and determine the access path of the configuration file.

[0028] In this embodiment, the test industrial control computer is a host computer with integrated TFTP Server components, the test device is a self-developed device, and the target board is a board card in Thales' TPCU-t component, with a dual-core processor of OMAP5910, a Flash memory chip of S29GL256N, and an SDRAM of MT48LC32M16A2.

[0029] In this embodiment, the part number of the board is 250029-XX or 253812-XX; the OMAP5910 includes an ARM core TI925T and a DSP core TMS320C55X; two S29GL256Ns are generally used, one as boot Flash and the other as app Flash.

[0030] The specific implementation process is as follows: connect the serial port of the test industrial control computer to the serial port of the test device, and use terminal software to enter the configuration interface of the test device; Update the firmware information of the test device (on first use); Configure the IP address and subnet mask of the test device and the host IP address of the test industrial control computer (which acts as the host computer) to ensure that the test device and the test industrial control computer are on the same Ethernet segment. Set the directory name of the working directory for the configuration file (e.g., " / tftpboot").

[0031] Then, according to the OMAP5910 processor's software configuration manual, analyze the target board's hardware connections (including the S29GL256N Flash chip, MT48LC32M16A2 SDRAM, and peripheral connections to the external crystal oscillator); set the CPU's required configuration parameters for different register addresses, specifically by writing the following commands into the configuration file: use WM160xfffecf00 0x0ca0 and WM16 0xfffecf00 0x2cb0 (i.e., write to the DPLL1_CTL_REG register) to set the clock division and multiplication parameters; use the WORKSPACE 0x20000000 command to specify the internal RAM's mapped address; use the CHIPTYPEMIRRORX16 command to specify the Flash as 16 bits wide to adapt to the OMAP5910's EMIF interface timing; use the CHIPSIZE0x02000000 command to specify the external Flash capacity as 32MB; use BUSWIDTH... The 16 command specifies that the bus width of the external Flash is 16 bits; The above configuration parameters are written into the configuration file, and the compatibility of the register parameters is verified by online debugging using a self-developed testing device until all peripherals of the target board are configured correctly, and finally a complete configuration file is generated.

[0032] It should be noted that the above commands are for illustrative purposes only. The configuration file does not contain all the register operations; it only provides examples of a very small portion of the register operation methods.

[0033] Through these operations, the verified configuration file can be automatically loaded via the network when the subsequent test device is powered on, avoiding the tedious manual configuration each time and ensuring the consistency and reliability of parameters during batch testing.

[0034] Step S20: Run the file transfer service on the test industrial computer to enable the test device to obtain the configuration file that matches the dual-core processor and target board via Ethernet.

[0035] In this embodiment, the test industrial control computer runs a TFTP Server service. The test device is a self-developed device, which has been configured with an IP address on the same network segment as the test industrial control computer. After the target board is powered on, the test device sends a request to the TFTP Server of the test industrial control computer via Ethernet, and obtains a configuration file that matches the hardware of the target board according to the configuration file working directory set in step S10. This configuration file is then used by the test device to configure the CPU registers.

[0036] The TFTP Server service is TFTPD32 in Windows, tftpd-hpa in Linux, or other related services in other environments.

[0037] Preferably, before establishing a remote login connection between the test industrial control computer and the test device, the method in this embodiment further includes: Power on the target board and check whether the network connection between the test industrial computer and the test device is reliable; If the network connection is reliable and the test device can read the configuration file through the file transfer service, the test industrial control computer will initiate a remote login connection request to the test device. If the remote login connection is successful, Flash read and write operations will be performed. Otherwise, return to retest the network connection.

[0038] This detection mechanism ensures the smooth operation of the communication path before establishing remote login, avoids the invalidation of subsequent operations due to network anomalies, and improves the robustness of the process.

[0039] Step S30: Establish a remote login connection between the test industrial control computer and the test device; the test device loads register configuration parameters into the dual-core processor via the JTAG interface according to the configuration file to complete the target board initialization.

[0040] Preferably, step S30 further includes: The configuration file is generated based on the dual-core processor's software configuration manual and the target board's hardware connection relationships; Hardware connectivity includes the peripheral connections of the Flash memory chip, SDRAM, and crystal oscillator on the target board; The configuration file sets corresponding configuration parameters for different register addresses of the dual-core processor. The configuration parameters include at least the register address, the written value, and the execution order. After the target board is powered on, the configuration parameters are loaded into the SDRAM via Ethernet and the test device to complete the target board initialization.

[0041] Preferably, the configuration file includes: Configuration of the ARM core in a dual-core processor and configuration of the DSP core; The ARM core is based on the ARM9TDMI architecture and supports 32-bit and 16-bit instruction sets. The ARM core is configured to drive the peripherals and network protocol stack of the target board, while the DSP core is configured to match the dual-core working environment of the dual-core processor. When generating the configuration file, the clock division parameters of the dual-core processor and the timing parameters of the external memory interface are determined based on the target board's external clock, external memory allocation location, and peripheral connection relationships, as well as the dual-core processor's datasheet.

[0042] Preferably, the configuration file also includes clock configuration parameters: The clock configuration parameters are determined based on the target board's external clock, external memory allocation location, and peripheral connection relationships, and according to the calculation formula in the dual-core processor's datasheet. The clock division parameters and external memory interface timing parameters of the dual-core processor are then written into the register configuration parameters.

[0043] Preferably, the configuration file also includes memory mapping parameters and external memory interface configuration parameters: The memory mapping parameter is used to specify the mapping address of the internal RAM of the dual-core processor. The test device accesses the target board to define the workspace for debugging. The external memory interface configuration parameters are determined based on the external memory allocation location of the target board.

[0044] Preferably, the configuration file also includes Flash bus access parameters: Flash bus access parameters include chip type parameters for adapting to the type of Flash memory chip, capacity parameters for adapting to the capacity boundary of Flash memory chip, and bus width parameters for adapting to the bus connection method between Flash memory chip and dual-core processor.

[0045] In this embodiment, the Telnet protocol is used to establish a remote login connection between the test industrial control computer and the test device. Specifically, the test device is on the same Ethernet segment as the test industrial control computer via the IP address configured in step S10. The test industrial control computer is running the TFTP Server service, and after the target board is powered on, the test device can obtain the configuration file from the test industrial control computer via the TFTP protocol. At this time, the test industrial control computer, acting as a client, initiates a connection request to the Telnet port (default port 23) of the test device. If the connection is successful, the test industrial control computer can send debugging commands to the test device through the command-line interface; if the connection fails, it returns to re-detect the network connection until a successful connection is established before subsequent Flash read / write operations can be performed.

[0046] It should be noted that the test device requires the TFTP Server to be run before establishing a Telnet connection. This is a communication sequence specified by its firmware design to ensure that the configuration file is ready. Following this sequence can prevent failures during initialization due to missing configuration parameters, thus ensuring the successful establishment of the debug session.

[0047] The specific implementation of the test device loading register configuration parameters into the dual-core processor via the JTAG interface according to the configuration file is as follows: The test setup connects to the OMAP5910 dual-core processor on the target board via a JTAG interface. The test setup reads the configuration file, parses the register addresses, write values, and execution order parameters, and then writes the configuration data to the corresponding registers of the processor line by line using JTAG instructions. This process directly configures the processor's clock, memory mapping, and external memory interface, enabling the SDRAM controller to complete its initialization. Afterward, the test setup can download subsequent debug code or data to the available SDRAM for execution as needed. At this point, the CPU completes the basic boot process, and the target board is initialized.

[0048] This initialization method, which does not rely on the existing firmware of the target board, can successfully establish a hardware debugging environment even when the Flash is blank or the program is corrupted, providing another debugging method for online reading and writing in maintenance scenarios.

[0049] The configuration file generation is based on the OMAP5910 software configuration manual provided by Texas Instruments and the actual hardware connections of the target board. The hardware connections include: two S29GL256N Flash chips as bootFlash and application Flash respectively, one MT48LC32M16A2 SDRAM chip, and the frequency value of an external crystal oscillator. The configuration file sets corresponding configuration parameters for different register addresses of the OMAP5910, including register addresses, write values ​​(such as 0x0ca0 and 0x2cb0), and execution order (first configure the clock, then configure memory mapping, and finally configure peripheral interfaces). After the target board is powered on, these configuration parameters are transmitted via Ethernet from the test industrial computer's TFTP Server to the self-developed test device, and then loaded into the SDRAM by the test device via the JTAG interface, ultimately completing the target board initialization.

[0050] The configuration file specifically includes separate configurations for the ARM core and DSP core in the OMAP5910. The ARM core is a TI925T, based on the ARM9TDMI architecture, supporting both 32-bit ARM and 16-bit Thumb instruction sets. Its configuration is used to drive the target board's peripherals and network protocol stack, as the ARM core is responsible for general system control and communication. The DSP core is a TMS320C55X, and its configuration is used to match the dual-core operating environment, including the dual-core communication interface and the allocation of shared resources. When generating the configuration file, the processor's clock division parameters and external memory interface timing parameters are determined based on the target board's external clock (e.g., crystal oscillator frequency of 12MHz or 13MHz), the allocation location of external memory (e.g., app Flash mapping address of 0x02000000), and peripheral connections, and according to the clock calculation formula provided in the OMAP5910 datasheet.

[0051] The configuration file also includes clock configuration parameters.

[0052] Specifically, the test setup configures the OMAP5910 clock by writing to the DPLL1_CTL_REG register. This involves two write commands: WM16 0xfffecf00 0x0ca0 and WM16 0xfffecf00 0x2cb0. Here, 0xfffecf00 is the address of the DPLL1_CTL_REG register, and 0x0ca0 and 0x2cb0 are the values ​​written in the two commands. These values ​​are calculated according to the formulas in the datasheet based on the external crystal oscillator frequency and the required core clock frequency.

[0053] The configuration file also includes memory mapping parameters and external memory interface configuration parameters. The memory mapping parameters are implemented using the `WORKSPACE 0x20000000` command, which specifies the mapped address of the OMAP5910's internal RAM as 0x20000000, allocating a debugging workspace for the test device to access the target board. The external memory interface configuration parameters are determined based on the target board's external memory allocation location. The OMAP5910 has an external memory interface (EMIF) that supports SDRAM and asynchronous memories (such as Flash).

[0054] The `CHIPTYPE MIRRORX16` command specifies the Flash type as 16 bits wide to adapt to the timing of the OMAP5910's EMIF interface; the `CHIPSIZE 0x02000000` command specifies the external Flash size as 32MB; and the `BUSWIDTH 16` command specifies the external Flash bus width as 16 bits. These parameters collectively configure the EMIF access timing, such as read / write cycles, setup time, and hold time, enabling the EMIF to correctly access the S29GL256N Flash chip and the MT48LC32M16A2 SDRAM chip. All configuration parameters were verified and debugged online using a self-developed testing device, with initial register values ​​manually modified until all peripherals on the board were functioning correctly, ultimately generating a complete configuration file.

[0055] It should be noted that after the target board initialization is completed, the test device automatically enables Flash read and write operations, or the test industrial control computer sends an enable command via Telnet.

[0056] Step S40: The test industrial control computer sends Flash read / write commands to the test device, and then the test device controls the dual-core processor to perform online read / write operations on the target board via the JTAG interface.

[0057] Preferably, in step S40, the test device controls the dual-core processor via the JTAG interface to perform online read / write operations on the target board, including: Flash memory chips include boot Flash and application Flash; The configuration file selected based on the target board's board part number; Perform read operations on the boot Flash, write operations on the boot Flash, read operations on the app Flash, and write operations on the app Flash on the test industrial control computer. When a write operation is selected, the corresponding program data is written to the corresponding Flash on the target board via the test device; When a read operation is selected, the test device reads the program data in the corresponding Flash on the target board and transmits it back to the test industrial control computer. After the Flash read / write operation is complete, disconnect the test industrial computer from the test device.

[0058] In this embodiment, after the target board is initialized, the test industrial control computer sends Flash read / write commands to the test device through the established Telnet connection. The test device converts these commands into JTAG debugging instructions, controls the external memory interface (EMIF) of the OMAP5910 dual-core processor through the JTAG interface, and then performs online read / write operations on the Flash memory chip on the target board. The target board contains two S29GL256N Flash chips, one as bootFlash (stores the boot program) and the other as app Flash (stores the application program). Both Flash chips are connected to the processor through the OMAP5910's EMIF, and the data bus width is 16 bits.

[0059] The bit width of the data bus is specified by the BUSWIDTH 16 command in the configuration file.

[0060] The specific read / write process is as follows: First, select the matching configuration file based on the target board's part number. Since different part numbers may have different peripheral layouts, corresponding initialization parameters are required. On the test industrial control computer, the user or automation script can select four operation types: boot Flash read, boot Flash write, app Flash read, and app Flash write. When a write operation is selected, the test industrial control computer transmits the program data to be programmed to the test device via the TFTP protocol. The test device then uses JTAG instructions to write the data to the corresponding Flash chip address space in a page-by-page programming manner via the OMAP5910's EMIF. During the writing process, the test device must follow the S29GL256N chip's write timing sequence (including write command sequence, status query, etc.), which is achieved by controlling the OMAP5910's GPIO or direct memory access. When a read operation is selected, the test device uses JTAG instructions to control the OMAP5910 to read data from the specified Flash address and then transmits it back to the test industrial control computer via Ethernet. All read / write operations must be "enabled" beforehand (as shown in the flowchart) to ensure that the configuration parameters are correctly loaded. After the read and write operations are completed, the test industrial control computer actively disconnects the Telnet connection with the test device, ending the test session.

[0061] The entire online read and write operation does not require physical disassembly and assembly of the hardware, reducing the long maintenance work required in the traditional way to within a few minutes, improving testing and repair efficiency and reducing the risk of hardware damage.

[0062] Furthermore, the host computer software in this embodiment is used to implement test device configuration, network connection detection, configuration file transmission, remote login, and Flash read / write control. Its software execution flow is as follows: Figure 2 As shown.

[0063] After the test software starts, it first determines whether the test device is being used for the first time. If it is, it initializes and configures the test device via serial port, including setting the test device's IP address, subnet mask, and configuration file access path. Then, it starts the file transfer service and checks the network connection status between the test industrial computer and the test device. After the network connection is normal, it establishes a remote login connection and loads the corresponding configuration file according to the board part number selected by the user, completing the target board initialization. After initialization, it performs Flash read and write operations and disconnects the connection after the operation is completed.

[0064] Example 2 This invention also provides a flash online read / write system based on an aviation entertainment system processor board. For example... Figure 3 As shown, the system also includes a processor and a memory. The memory stores computer program instructions, which, when executed by the processor, implement a flash online read / write method based on an aviation entertainment system processor board according to the first aspect of the present invention.

[0065] This embodiment discloses a flash online read / write system based on an aviation entertainment system processor board. The system of this embodiment includes: Test industrial control computers, testing equipment, and target boards; The testing equipment includes, The serial port configuration module is used to perform initial configuration of the test device through the serial port on the test industrial control computer, so as to establish a network communication connection between the test device and the test industrial control computer and determine the CPU configuration file loading path; The file transfer service module is used to run a file transfer service on the test industrial control computer, so that the test device can obtain a configuration file that matches the dual-core processor and the target board via Ethernet. The configuration file is written according to the software configuration manual of the dual-core processor and the hardware connection relationship of the target board, and is used to configure the internal register data parameters of the dual-core processor to realize communication between the test device and the dual-core processor. The remote login module is used to establish a remote login connection between the test industrial computer and the test device; The read / write command module is used to send Flash read / write commands to the test device via the test industrial control computer; The testing device is used to test the dual-core processor controlling the target board via the JTAG interface to perform online read and write operations.

[0066] It should be added that the test industrial control computer is connected to the test device via serial port and Ethernet respectively, and the test device is connected to the target board via JTAG interface.

[0067] In this embodiment, the system's operating logic is as follows: The test industrial control computer (host computer) first performs initial settings for the test device through the serial port configuration module, including updating the test device firmware, assigning an IP address (on the same network segment as the test industrial control computer), and setting the configuration file working directory. This step enables the test device to have network communication capabilities and configuration file location capabilities.

[0068] Subsequently, the file transfer service module (TFTP Server) runs on the test industrial control computer. After the target board is powered on, the test device requests a configuration file matching the target board's hardware (OMAP5910 dual-core processor, S29GL256N Flash, MT48LC32M16A2 SDRAM) from the TFTP Server via Ethernet. This configuration file contains parameters such as clock division, internal RAM mapping, EMIF timing, and Flash bus width (e.g., WM16 command configuration of DPLL1_CTL_REG, WORKSPACE, CHIPTYPE, CHIPSIZE, BUSWIDTH, etc.).

[0069] Next, the remote login module (Telnet) establishes a connection between the test industrial control computer and the test device. Based on the acquired configuration file, the test device loads register configuration parameters into the OMAP5910 processor via the JTAG interface, initializes the SDRAM and EMIF interface, enabling the processor to start normally and access peripherals.

[0070] Finally, the read / write command module sends Flash read / write commands (such as boot Flash read / write, app Flash read / write). The test device converts the commands into JTAG debugging instructions, controlling the OMAP5910's EMIF to perform online data reading or programming on the two S29GL256N Flash chips on the target board. After the operation is complete, the test industrial control computer disconnects from the test device. The various modules of this system work collaboratively, achieving an automated process from configuration to read / write, reducing the possibility of human error.

[0071] The system also includes other components well known to those skilled in the art, such as communication interfaces, the settings and functions of which are known in the art and will not be described in detail here.

[0072] In this invention, the aforementioned memory can be any tangible medium containing or storing a program that can be used or combined with an instruction execution system, apparatus, or device. For example, a computer-readable storage medium can be any suitable magnetic or magneto-optical storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc., or any other medium that can be used to store desired information and can be accessed by an application, module, or both. Any such computer storage medium can be part of a device or accessible to or connected to a device. Any application or module described in this invention can be implemented using computer-readable / executable instructions that can be stored or otherwise maintained by such a computer-readable medium.

[0073] In the description of this specification, "multiple" means at least two, such as two, three or more, etc., unless otherwise expressly and specifically defined.

[0074] While this specification has shown and described numerous embodiments of the invention, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and essence of the invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in the practice of this invention.

Claims

1. A method for online flash reading and writing based on an aviation entertainment system processor board, applied to a test industrial control computer, a test device, and a target board, wherein the target board includes a dual-core processor integrating an ARM core and a DSP core, SDRAM, and a Flash memory chip, characterized in that, The method includes: Step S10: Initially configure the test device through the serial port on the test industrial control computer to establish a network communication connection between the test device and the test industrial control computer and determine the CPU configuration file loading path; Step S20: Run a file transfer service on the test industrial control computer to enable the test device to obtain a configuration file that matches the dual-core processor and the target board via Ethernet. The configuration file is written according to the software configuration manual of the dual-core processor and the hardware connection relationship of the target board, and is used to configure the internal register data parameters of the dual-core processor to realize communication between the test device and the dual-core processor. Step S30: Establish a remote login connection between the test industrial computer and the test device; the test device loads register configuration parameters into the dual-core processor via the JTAG interface according to the configuration file to complete the target board initialization; Step S40: The test industrial control computer sends a Flash read / write command to the test device, and then the test device controls the dual-core processor to perform online read / write on the target board via the JTAG interface.

2. The flash online read / write method based on the processor board of an aviation entertainment system according to claim 1, characterized in that, Step S10, configuring the testing device via the serial port on the testing industrial control computer, further includes: Configure the IP address and subnet mask of the test device, as well as the host IP address of the test industrial control computer, which serves as the host computer. The configuration includes the firmware information and network parameters of the test device, in order to establish network communication between the test device and the test industrial control computer and determine the access path of the configuration file.

3. The online flash read / write method based on an aviation entertainment system processor board according to claim 1, characterized in that, Before establishing a remote login connection between the test industrial computer and the test device, the following steps are also included: Power on the target board and check whether the network connection between the test industrial control computer and the test device is reliable; If the network connection is reliable and the test device is able to read the configuration file through the file transfer service, the test industrial control computer initiates a remote login connection request to the test device. If the remote login connection is successful, then Flash read / write operations are performed; Otherwise, return to retest the network connection.

4. The method for online flash reading and writing based on an aviation entertainment system processor board according to claim 1, characterized in that, Step S30 also includes: The configuration file is generated based on the software configuration manual of the dual-core processor and the hardware connection relationship of the target board; The hardware connection relationships include the peripheral connection methods of the Flash memory chip, SDRAM, and crystal oscillator on the target board. The configuration file sets corresponding configuration parameter information for different register addresses of the dual-core processor. The configuration parameter information includes at least the register address, the written value, and the execution order. After the target board is powered on, the configuration parameter information is loaded into the SDRAM via Ethernet and the test device to complete the target board initialization.

5. The flash online read / write method based on the processor board of an aviation entertainment system according to claim 4, characterized in that, The configuration file includes: The configuration of the ARM core and the configuration of the DSP core in the dual-core processor; The ARM core is based on the ARM9TDMI architecture and supports 32-bit and 16-bit instruction sets. The configuration of the ARM core is used to drive the peripherals and network protocol stack of the target board. The configuration of the DSP core is used to match the dual-core working environment of the dual-core processor. When generating the configuration file, the clock division parameters and external memory interface timing parameters of the dual-core processor are determined based on the target board's external clock, external memory allocation location, and peripheral connection relationships, and according to the datasheet of the dual-core processor.

6. The online flash read / write method based on an aviation entertainment system processor board according to claim 4, characterized in that, The configuration file also includes clock configuration parameters: The clock configuration parameters are determined based on the target board's external clock, external memory allocation location, and peripheral connection relationships, and according to the calculation formula in the dual-core processor's datasheet. The clock division parameters and external memory interface timing parameters of the dual-core processor are then written into the register configuration parameters.

7. The method for online flash reading and writing based on an aviation entertainment system processor board according to claim 4, characterized in that, The configuration file also includes memory mapping parameters and external memory interface configuration parameters: The memory mapping parameters are used to specify the mapping address of the RAM inside the dual-core processor, and the test device accesses the target board to define the workspace for debugging. The external memory interface configuration parameters are determined based on the external memory allocation location of the target board.

8. The online flash read / write method based on an aviation entertainment system processor board according to claim 4, characterized in that, The configuration file also includes Flash bus access parameters: The Flash bus access parameters include chip type parameters for adapting to the type of Flash memory chip, capacity parameters for adapting to the capacity boundary of the Flash memory chip, and bus width parameters for adapting to the bus connection method between the Flash memory chip and the dual-core processor.

9. The online flash read / write method based on an aviation entertainment system processor board according to claim 1, characterized in that, Step S40, in which the testing device controls the dual-core processor via the JTAG interface to perform online read / write operations on the target board, includes: The Flash storage chip includes boot Flash and app Flash; The configuration file selected based on the board part number of the target board; On the test industrial control computer, read operations on the boot Flash, write operations on the boot Flash, read operations on the app Flash, and write operations on the app Flash are performed. When a write operation is selected, the corresponding program data is written into the Flash memory on the target board via the test device. When a read operation is selected, the test device reads the program data in the corresponding Flash on the target board and transmits it back to the test industrial control computer. After the Flash read / write operation is completed, disconnect the connection between the test industrial computer and the test device.

10. A flash online read / write system based on an aviation entertainment system processor board, characterized in that, The online flash read / write method for a flight entertainment system processor board according to any one of claims 1-9 includes: Test industrial control computers, testing equipment, and target boards; The testing equipment includes, The serial port configuration module is used to perform initial configuration of the test device through the serial port on the test industrial control computer, so as to establish a network communication connection between the test device and the test industrial control computer and determine the CPU configuration file loading path; The file transfer service module is used to run a file transfer service on the test industrial control computer, so that the test device can obtain a configuration file that matches the dual-core processor and the target board via Ethernet. The configuration file is written according to the software configuration manual of the dual-core processor and the hardware connection relationship of the target board, and is used to configure the internal register data parameters of the dual-core processor to realize communication between the test device and the dual-core processor. A remote login module is used to establish a remote login connection between the test industrial control computer and the test device; The read / write command module is used to send Flash read / write commands to the test device through the test industrial control computer. The testing device is used to control the dual-core processor to perform online read and write operations on the target board via the JTAG interface.

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