A method for ensuring continuity of optical path in WSS online program updating

Abstract

The application discloses a WSS online program updating method for guaranteeing optical path continuity, relates to the technical field of optical communication and optical network device control, and comprises the following steps: dividing a flash memory into a first storage area, a second storage area and a third storage area; receiving an online updating instruction, copying a main program image in the second storage area to the third storage area, and performing data integrity check; writing an updating program image into the second storage area and performing data integrity check; after the data integrity check is passed, only a reset operation is performed on a processing system PS, and a programmable logic PL side is kept running; after the processing system PS is reset and restarted, image generation parameters are read from an external nonvolatile memory to restore image display and restore the reception of a new image frame. The method realizes safe, reliable and rollback online upgrading of software at the processing system PS end, and has high industrialization prospects and application value.

Description

Technical Field

[0001] This application relates to the field of optical communication and optical network equipment control technology, and in particular to a WSS online program update method to ensure optical path continuity. Background Technology

[0002] Wavelength Selective Switch (WSS) is a core optical device in modern optical communication networks, widely used in systems such as Dynamically Reconfigurable Optical Add-Drop Multiplexers (ROADM) and Optical Cross-Connects (OXC) to achieve flexible scheduling and routing of multi-wavelength signals. With the development of 5G, Data Center Interconnect (DCI), and computing networks, optical networks are placing higher demands on the intelligence, programmability, and reliability of WSS.

[0003] Wavelength Scanner Arrays (WSAs) are typically implemented using a System-on-Chip (SoC) architecture, such as Xilinx Zynq series or Zynq UltraScale+MPSoC series Field-Programmable Gate Arrays (FPGAs). These chips integrate a Processing System (PS) and Programmable Logic (PL). The PS runs embedded software responsible for protocol processing, communication management, LCOS (Liquid Crystal on Silicon) image generation, and the user interface. The PL handles high-speed logic control, wavelength switching, LCOS driving, and timing control. The optical output of the WSS depends on the image content displayed on the LCOS. The PS transmits the generated image data to the PL's DDR memory chip via a direct memory access channel (such as a VDMA channel). The LCOS driving logic on the PL then reads the data from the DDR memory chip and drives the LCOS display, thereby achieving optical path selection and switching for the target wavelength.

[0004] To support remote operation and maintenance, feature iteration, and vulnerability patching, WSS needs to have online software update capabilities. Traditional update methods often use single-zone Flash boot or whole-chip replacement, but these methods have the following problems during the update process: 1) PS restart during the update process can cause the management end (e.g., UART / I²C / SPI / Ethernet, etc.) to lose connection; 2) After PS restart, the values ​​of sensitive optical device registers, such as GAMMA value, are reinitialized, causing optical path output to jump or even turn off; 3) After PS restart, data needs to be retransmitted. If the input is interrupted during the data update via VDMA / AXI channel, image tearing or screen distortion may occur; 4) If the new version is damaged or incompatible, the device may fail to start and run normally; 5) When writing the program, link abnormalities / transmission errors can easily lead to incorrect data being written. In addition, although there are dual-bank Flash solutions in existing technologies for firmware redundancy, they are mostly focused on storage layer switching and cannot guarantee the continuity of the optical path during WSS online program updates. Summary of the Invention

[0005] This application addresses the aforementioned problems and technical requirements by proposing a WSS online program update method to ensure optical path continuity. The technical solution of this application is as follows: A method for online program updating of a WSS (Wireless Supersonic Switch) to ensure optical path continuity. The WSS includes a processing system PS, a programmable logic unit (PL), and a liquid crystal on silicon (LCOS). The processing system PS is connected to a flash memory and an external non-volatile memory. The WSS online program updating method includes the following steps: The Flash memory is divided into at least three storage areas: a first storage area for storing the boot program image and the recovery program image, a second storage area for storing the main program image, and a third storage area for storing the backup program image; the image generation parameters of the WSS are stored in an external non-volatile memory, and the image generation parameters are used to generate silicon-based liquid crystal LCOS display images that meet the current optical path scheduling requirements. In response to receiving an online update command, the current main program image in the second storage area is copied to the third storage area, and the data integrity of the main program image copied to the third storage area is verified. After the data integrity of the main program image copied to the third storage area passes the verification, the received updated program image is written to the second storage area, and the data integrity of the updated program image written to the second storage area is verified. In response to the data integrity verification of the update program image written to the second storage area passing, a reset operation is performed only on the processing system PS, so that the programmable logic PL side continues to run, thereby keeping the display content of the liquid crystal on silicon (LCOS) unchanged during the reset of the processing system PS. After the processing system PS is reset and restarted, it reads the image generation parameters from the external non-volatile memory, restores the image display according to the image generation parameters, and resumes the reception of new image frames on the programmable logic PL side.

[0006] A further technical solution is that the boot program image in the first storage area completes the initialization configuration of the optical sensitive register on the programmable logic PL side when the WSS is powered on; the program images in the second and third storage areas do not repeat the configuration of the optical sensitive register during the startup process; the optical sensitive register is a register used to control the optical output parameters of the silicon-based liquid crystal LCOS on the programmable logic PL side.

[0007] A further technical solution involves performing a reset operation only on the processing system PS to keep the programmable logic PL running, including: After detecting the image frame transmission status and determining that the current complete image frame transmission has ended, the programmable logic (PL) side will continuously output the currently transmitted complete image frame during the PS reset of the processing system, so as to keep the display content of the liquid crystal on silicon (LCOS) unchanged during the PS reset of the processing system.

[0008] A further technical solution involves continuously outputting the complete image frame that has been transmitted during the PS reset of the programmable logic (PL) side, including: In response to receiving a PS reset request from the processing system, the header check bit and trailer check bit of the image frame data transmitted through the AXI-Stream interface are monitored. When the check value of the header check bit indicates the start of the current complete image frame and the check value of the trailer check bit indicates the end of the current complete image frame, the transmission of the current complete image frame is determined to be over. Close the direct memory access write channel and stop receiving new image frame data.

[0009] A further technical solution involves determining the end of the transmission of the current complete image frame, including: The counter deployed at the AXI-Stream interface starts counting after detecting the header check bit of the image frame data and confirming that the check value corresponding to the header check bit is correct. When the counter count reaches the number of data corresponding to the complete image frame and confirms that the check value corresponding to the tail check bit is correct, the counter is cleared, and the transmission of the current complete image frame is considered complete.

[0010] Further technical solutions include the following: The WSS online program update method also includes: When data integrity verification of the updater image written to the second storage area fails, the backupr image is read from the third storage area and rewritten to the second storage area. The rewritten backupr image in the second storage area is then loaded to restore the system to its normal operating state before the update.

[0011] The further technical solution is that the online update command and the update program image are transmitted through an asynchronous transmission protocol, and the online update command carries the target version number and the target checksum; WSS online application update methods also include: Before transmitting the update program image, the processing system PS verifies the validity of the received target version number. Once the target version number passes the validity verification, the update program image is transmitted. After receiving the update program image, the checksum of the update program image is calculated and compared with the target checksum. If the comparison results match, the current main program image in the second storage area is copied to the third storage area.

[0012] Further technical solutions include the following: The WSS online program update method also includes: When WSS powers on, it loads the main program image from the second storage area based on the MULTI_BOOT mechanism and performs a power-on startup verification. If the main program image from the second storage area fails the power-on startup verification, it loads the backup program image from the third storage area based on the MULTI_BOOT mechanism and performs a power-on startup verification. If the backup program image from the third storage area fails the power-on startup verification, it loads the recovery program image from the first storage area.

[0013] A further technical solution involves performing a reset operation on the processing system PS, including: Call the function interface that only resets the processing system PS to perform a reset operation on the processing system PS.

[0014] A further technical solution involves performing data integrity verification on the main program image copied to the third storage area or the update program image written to the second storage area, including: The program image written to the storage area is read back using the serial peripheral interface protocol. When the checksum of the read-back program image is consistent with the checksum of the program image before writing, and the version number of the read-back program image is consistent with the version number of the program image before writing, the data integrity check is considered to have passed.

[0015] The beneficial technical effects of this application are: This application discloses a WSS online program update method to ensure optical path continuity. The method divides the Flash memory into a first storage area for storing boot program and recovery program images, a second storage area for storing the main program image, and a third storage area for storing backup program images. Upon receiving an online update command, the current main program image in the second storage area is first backed up to the third storage area. Then, the update program image is written to the second storage area. Data integrity checks are performed on both the backed-up and written program images. Only after successful checks is a reset operation performed on the processing system PS, keeping the programmable logic block (PL) running and thus maintaining the unchanged display content of the liquid crystal on silicon (LCOS) during PS reset. After PS reset and restart, image generation parameters are read from external non-volatile memory to restore image display. This method achieves safe, reliable, and rollback-enabled online updates of the processing system PS software. The LCOS display content remains unchanged during the update process, ensuring the continuity of the WSS optical path and preventing optical output jumps or shutdowns during the update. Simultaneously, the data integrity check and backup mechanism ensures the safety and reliability of the update process and provides failure recovery capabilities. This method effectively solves the problems of communication interruption, image jump, and device blanking caused by upgrade failure in traditional online program update methods. It meets the stringent requirements of optical communication equipment for high availability and high reliability, and has high industrialization prospects and application value.

[0016] The initialization configuration of the optical sensitive registers on the programmable logic (PL) side is completed by the boot program image in the first storage area when the WSS is powered on. The program images in the second and third storage areas do not reconfigure the optical sensitive registers during the startup process. This ensures that the LCOS optical sensitive registers will not be reinitialized when the PS of the subsequent processing system is reset and restarted. This avoids the optical parameter jump caused by register reconfiguration and ensures the stability of the optical path during the update process from the source.

[0017] Before the PS reset of the processing system, the image frame transmission status is detected. The display content is locked in the current complete image frame only after the transmission of the current complete image frame is confirmed to be completed. The frame boundary is accurately determined by monitoring the frame start signal and the frame end signal, avoiding image tearing or screen distortion caused by freezing in the middle of frame transmission. At the same time, by disabling the direct memory access write channel and continuously outputting the currently transmitted complete image frame on the programmable logic (PL) side during the PS reset of the processing system, true image freeze display is achieved. This ensures that the LCOS display content is complete, stable, and without jumps or black screens during the PS reset, providing solid technical support for ensuring the continuity of the optical path during the update process.

[0018] Furthermore, a comprehensive data security system is constructed by implementing multi-level checks at each stage of the update process: First, the target version number is validated before transmitting the update program image to prevent erroneous upgrades or version rollbacks due to misoperation. Second, after receiving the update program image, a checksum is calculated and compared with the target checksum to ensure data integrity during transmission and prevent the continued use of corrupted data due to link anomalies or transmission errors. Third, the backup master program image copied to the third storage area undergoes data integrity verification to ensure the backup image is reliable and usable, providing a secure foundation for subsequent rollbacks. Finally, the update program image written to the second storage area undergoes post-write readback data integrity verification to promptly detect bit flips, write errors, and other issues during Flash writing, ensuring that the data written to the storage area is completely consistent with the actual requirements. Through these multi-level checks before, after, after backup, and after writing, any data anomalies at any stage can be promptly intercepted and the update process terminated without damaging the existing program. This fundamentally prevents erroneous data from being written to the storage area, significantly improving the security, reliability, and traceability of the WSS online update process. Attached Figure Description

[0019] Figure 1 This is an architecture diagram of a WSS online application update system in an example.

[0020] Figure 2 This is a flowchart of the WSS online application update method in an example.

[0021] Figure 3 This is a flowchart of the WSS power-on startup verification method in an example.

[0022] Figure 4 This is a flowchart of the update program image verification method in an example. Detailed Implementation

[0023] The specific embodiments of this application will be further described below with reference to the accompanying drawings.

[0024] To address issues such as communication interruptions, image jumps, and device blanking due to upgrade failures in traditional online application update methods, this application discloses a WSS online application update system. Please refer to [link / reference]. Figure 1 The system includes a WSS (wavelength selective switch), Flash memory, and external non-volatile memory (Eeprom).

[0025] The WSS is connected to both the Flash memory and the external non-volatile memory. The WSS includes a processing system (PS), programmable logic unit (PL), and a liquid crystal on silicon (LCOS). Both the PS and PL contain DDR memory chips. The Flash memory comprises three storage areas: a first area for storing the boot program image and recovery program image, a second area for storing the main program image, and a third area for storing the backup program image. The external non-volatile memory stores image generation parameters, which are used to generate an LCOS display image that conforms to the current optical path scheduling requirements.

[0026] Based on the WSS online program update system, this application discloses a WSS online program update method that ensures optical path continuity. Please refer to [link / reference]. Figure 2 The flowchart shown illustrates the specific steps of this method as follows: Step 1: The Flash memory is pre-divided into at least three storage areas: a first storage area for storing the boot program image and the recovery program image, a second storage area for storing the main program image, and a third storage area for storing the backup program image; the image generation parameters of WSS are stored in an external non-volatile memory. The image generation parameters are used to generate silicon-based liquid crystal LCOS display images that meet the current optical path scheduling requirements.

[0027] The bootloader (FSBL) image follows the boot process of the WSS's internally embedded BootROM, completing the initialization of the core hardware on the PS side of the processing system, including the CPU, DDR memory, clock, interrupts, Flash, and communication peripherals, thus building the basic execution environment for subsequent program operation. The minimal recovery program image is a fallback program designed for extreme failures, stored together with the FSBL in the first storage area of ​​the Flash memory. When the main program in the second storage area and the backup program in the third storage area are damaged due to upgrade power failure, transmission errors, or other reasons, the minimal recovery program can be automatically started after the device is reset, preventing the device from becoming unusable. Moreover, since the first storage area is only accessed upon power-up, the optical sensor registers already configured in the first storage area will not be reconfigured during program updates, maintaining basic optical path stability. At the same time, basic communication functions such as asynchronous transmission and reception are retained, supporting remote rewriting of the main program partition, allowing device recovery to be completed without manual disassembly.

[0028] Image generation parameters include configuration parameters strongly related to LCOS (Liquid Crystal on Silicon) display and WSS (Wavelength Scheduling), such as LCOS optical calibration parameters (GAMMA calibration value, pixel phase compensation coefficient, optical bias parameters, etc.), which are fundamental parameters to ensure the optical power and phase accuracy of LCOS display; wavelength routing service parameters (input / output port mapping relationship of each wavelength channel, light attenuation configuration value, grating phase distribution parameters, etc.), which are the core basis for generating corresponding wavelength-scheduled images; drive timing control parameters (LCOS horizontal and vertical synchronization parameters, pixel clock configuration, direct memory access channel transmission configuration, etc.), which ensure the timing consistency of image transmission and display; and frame status verification parameters (version number, checksum, etc. corresponding to the currently effective image), used to verify image consistency when switching between old and new programs.

[0029] To avoid optical parameter jumps caused by the reinitialization of the optical sensitive register during online program updates due to power failure or reset, thus leading to optical path instability, in one embodiment, the bootloader image in the first storage area completes the initialization configuration of the optical sensitive register on the programmable logic PL side when the WSS is powered on; the program images in the second and third storage areas do not reconfigure the optical sensitive register during startup; the optical sensitive register is a register used to control the optical output parameters of the silicon-based liquid crystal LCOS on the programmable logic PL side.

[0030] During the initialization phase of the first storage area startup, the PS terminal of the processing system completes the configuration of the programmable logic PL and the optical sensitive registers related to the silicon-based liquid crystal LCOS display, and writes them into the Eeprom. After the PS is reset, the new program reads from the Eeprom and restores the image display consistency, which enables the image generation parameters to meet the persistent requirements that can be recovered after power failure / reset.

[0031] Furthermore, in extreme cases where system power outages, resets, or program crashes corrupt both the main program image in the second storage area and the backup program image in the third storage area, to prevent complete device failure and unusability, the program images in each storage area must be verified before each program update during WSS power-on. For details, please refer to... Figure 3 The WSS power-on verification method includes: When WSS powers on, it loads the main program image from the second storage area based on the MULTI_BOOT mechanism and performs a power-on startup verification. If the main program image from the second storage area fails the power-on startup verification, it loads the backup program image from the third storage area based on the MULTI_BOOT mechanism and performs a power-on startup verification. If the backup program image from the third storage area fails the power-on startup verification, it loads the recovery program image from the first storage area.

[0032] Among them, the power-on startup verification is a hardware verification (such as IDCODE / CRC / watchdog) built into the MULTI_BOOT mechanism. The specific process can be found in existing technologies, and will not be described in detail in this application.

[0033] The WSS power-on verification method implements a three-level cascaded fault tolerance for power-on startup. Even if the update program image is corrupted, it ensures that the device can boot and recover, fundamentally preventing the device from becoming a "blank board" and improving the maintainability and reliability of the device. Power-on verification is the last line of defense against device invalidity. It ensures that even if an accident occurs during the update process (power failure / crash / dual-zone damage), the device will always be able to boot on the next power-on.

[0034] Step 2: In response to receiving the online update command, the current main program image in the second storage area is copied to the third storage area, and the data integrity of the main program image copied to the third storage area is verified. After the data integrity of the main program image copied to the third storage area passes the verification, the received updated program image is written to the second storage area, and the data integrity of the updated program image written to the second storage area is verified.

[0035] When receiving an update program image, the transmitted update program image needs to be verified to ensure the accuracy of the transmitted data. In one embodiment, the online update command and the update program image are transmitted via an asynchronous transmission protocol. The online update command carries the target version number and the target checksum. The asynchronous transmission protocol is determined based on the actual chip model used; for example, Zynq series FPGAs use the UART protocol. The update program image contains the main program of the processing system's PS terminal and is stored in a bin file, and is transmitted in packets via the UART protocol. For details, please refer to [link to relevant documentation]. Figure 4 The method for updating the program image verification is as follows: Before transmitting the update program image, the processing system PS verifies the validity of the received target version number. If the target version number passes the validity verification, the update program image is transmitted. After receiving the update program image, the checksum of the update program image is calculated and compared with the target checksum. If the comparison results match, the update program image passes verification, and the current main program image in the second storage area is copied to the third storage area. The specific method for validity verification can employ existing techniques, and the checksum calculation of the update program image can also employ existing techniques, such as the CRC32 algorithm.

[0036] By validating the target version number before transmitting the update program image, erroneous upgrades or version rollbacks due to misoperation are avoided. After receiving the update program image, the checksum is calculated and compared with the target checksum, ensuring the integrity of the transmitted data and preventing corrupted data from being written to the storage area due to link anomalies or transmission errors, thus further improving the reliability of program updates.

[0037] To further ensure the integrity of data written to the storage area, a readback verification is required after each data write. In one embodiment, data integrity verification for the main program image copied to the third storage area or the update program image written to the second storage area includes: The program image written to the memory area is read back using the Serial Peripheral Interface (SPI) protocol. Data integrity verification is considered successful when the checksum of the read-back program image matches the checksum of the program image before writing, and the version number of the read-back program image matches the version number of the program image before writing. The specific protocol used to access the Flash memory via the SPI protocol can be selected based on actual application requirements, such as the QSPI protocol.

[0038] The program image written to the storage area is read back using the serial peripheral interface protocol. The checksum and version number of the read-back program image are compared with the program image before writing. This achieves dual verification after writing and read-back, which can promptly detect problems such as bit flips and write errors during the Flash writing process. It ensures that the program image written to the storage area is completely consistent with the actual required data, thus guaranteeing the reliability of program storage and the security of the update process.

[0039] To address situations where the new version of the program is corrupted or incompatible, this application also designs a rollback mechanism to ensure the high availability of optical network services. In one embodiment, the WSS online program update method further includes: When data integrity verification of the updater image written to the second storage area fails, the backupr image is read from the third storage area and rewritten to the second storage area. The rewritten backupr image in the second storage area is then loaded to restore the system to its normal operating state before the update.

[0040] Traditional program update methods require manual disassembly and recovery when the new version is unavailable, which is extremely difficult and costly to maintain remote WSS devices. The rollback mechanism in this application can quickly restore to a usable historical version in case of upgrade anomalies, avoiding optical path interruptions due to upgrade failures. This ensures the device can be restored to a working state under any abnormal scenario, making remote upgrades safer. Automatic recovery is possible without human intervention after an upgrade failure, supporting unattended remote maintenance. Furthermore, this method not only allows for backup and rollback of the previous version through a second storage area, but also provides backup recovery through the first storage area in extreme cases, completely preventing the device from becoming unbootable.

[0041] Additionally, if the online program update fails due to verification failure of the transmitted update program image or data integrity verification failure of the main program image copied to the third storage area, the original main program image in the second storage area will be loaded to function normally. The update will be repeated after further investigation to resolve the issues.

[0042] Step 3: In response to the successful data integrity verification of the update program image written to the second storage area, a reset operation is performed only on the processing system PS, so that the programmable logic PL side continues to operate, thereby maintaining the display content of the liquid crystal on silicon (LCOS) unchanged during the reset of the processing system PS.

[0043] When entering the PS reset phase of the program update, the display content of the base liquid crystal LCOS is maintained unchanged by resetting only the processing system PS while keeping the programmable logic PL side running, thereby ensuring the continuous stability of the optical path. In one embodiment, performing a reset operation only on the processing system PS to keep the programmable logic PL side running includes: After detecting the image frame transmission status and determining that the current complete image frame transmission has ended, the programmable logic (PL) side will continuously output the currently transmitted complete image frame during the PS reset of the processing system, so as to keep the display content of the liquid crystal on silicon (LCOS) unchanged during the PS reset of the processing system.

[0044] Before the processing system PS performs a restart, this application sends a control command to the programmable logic PL through the processing system PS, so that during the reset period of the processing system PS, the base liquid crystal LCOS continuously reads the currently transmitted complete image frame from the memory chip DDR on the programmable logic PL side.

[0045] Specifically, the method for continuously outputting the currently completed image frame during the PS reset of the programmable logic PL side is as follows: In response to receiving the PS reset request of the processing system, the header check bit and the tail check bit of the image frame data transmitted by the AXI-Stream interface are monitored. When the check value of the header check bit indicates that the current complete image frame has started, and the check value of the tail check bit indicates that the current complete image frame has ended, the transmission of the current complete image frame is determined to be over. Close the direct memory access write channel and stop receiving new image frame data.

[0046] In one embodiment, determining the end of the current complete image frame transmission includes: The counter deployed at the AXI-Stream interface starts counting after detecting the header check bit of the image frame data and confirming that the check value corresponding to the header check bit is correct. When the counter count reaches the number of data corresponding to the complete image frame and confirms that the check value corresponding to the tail check bit is correct, the counter is cleared, and the transmission of the current complete image frame is considered complete.

[0047] This method uses data flow integrity monitoring for soft data isolation. By adding a monitor at the interface, it not only provides soft data isolation but also detects packet loss. The header and tail check bits have customizable checksum values. When the counter reaches the number of data points corresponding to a complete image frame (e.g., 1920*1080 data points for a silicon-based liquid crystal LCOS), if the checksum value corresponding to the tail check bit is incorrect, a data anomaly warning signal is issued and the program update is stopped.

[0048] Upon receiving the counter reset signal and confirming the completion of the current complete image frame transmission, the PS instruction causes the direct memory access write channel to stop receiving new image frames to avoid half-frame / torn updates. The PL-side memory chip DDR stops refreshing and continuously outputs "the last complete image data corresponding to the freeze moment." The direct memory access channel is determined based on the specific chip type. For ZYNQ series chips, the direct memory access channel is the VDMA (Video Direct Memory Access) channel, a dedicated bus channel for high-speed transmission of streaming image data between the PS and PL ends.

[0049] This method detects the image frame transmission status before PS reset and only locks the display content in the current complete image frame after confirming that the transmission of the current complete image frame has ended. By monitoring the header and tail check bits of the image frame data transmitted through the AXI-Stream interface, it accurately determines the end of the transmission of the current complete image frame, avoiding image tearing or screen distortion caused by freezing in the middle of frame transmission. At the same time, by disabling the direct memory access write channel and keeping the LCOS display content in the current complete image frame during the PS reset of the processing system, it achieves true image freeze display, ensuring that the LCOS display content is complete, stable, without jumps, and without black screens during PS reset, providing solid technical support for ensuring the continuity of the optical path during the upgrade process.

[0050] In one embodiment, performing a reset operation on the processing system PS includes: calling a function interface that only resets the processing system PS to perform a reset operation on the processing system PS.

[0051] The PS (Reset Processor) interface is a pre-packaged, directly callable standard function interface. For the ZYNQ MPSOC series chips, the PS interface is XPfw_ResetPsOnly(). Developers only need to include the corresponding header file to call it directly, perfectly meeting the requirement of maintaining continuous operation of the PL-side LCOS driver and uninterrupted optical path during upgrades.

[0052] By calling the function interface of the PS-only reset processing system, a reset operation is performed on the PS. Only the PS is reset without affecting the running state of the programmable logic PL. This ensures that the timing control and LCOS drive logic on the PL side continue to run continuously during the PS reset, providing a key technical guarantee for uninterrupted optical path during program updates. At the same time, it avoids the management channel interruption problem caused by a full chip reset.

[0053] Step 4: After the processing system PS is reset and restarted, the image generation parameters are read from the external non-volatile memory, the image display is restored according to the image generation parameters, and the programmable logic PL side is restored to receive new image frames.

[0054] After the new version of PS starts, it first reads the image generation parameters from the external non-volatile memory to ensure consistent image generation; after confirming that the display has been restored, it then restores the VDMA write channel enable by PS command and switches back to "real-time data mode".

[0055] This application proposes an online program update method for WSS. Through innovative designs such as a three-zone Flash operation mechanism, EEPROM image generation parameter information storage, third storage area caching of the previous version, and PS exclusive reset, it effectively solves the problems of communication interruption, image jump, and device blanking caused by upgrade failure in traditional update methods. It meets the stringent requirements of optical communication equipment for high availability and high reliability, and has good industrialization prospects and promotion and application value.

[0056] The above descriptions are merely preferred embodiments of this application, and this application is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of this application should be considered to be included within the protection scope of this application.

Claims

1. A WSS online program update method to ensure optical path continuity, characterized in that, The WSS includes a processing system PS, a programmable logic PL, and a silicon-based liquid crystal LCOS. The WSS is connected to a flash memory and an external non-volatile memory, respectively. The WSS online program update method includes: The Flash memory is divided into at least three storage areas: a first storage area for storing the boot program image and the recovery program image, a second storage area for storing the main program image, and a third storage area for storing the backup program image; the image generation parameters of the WSS are stored in an external non-volatile memory, and the image generation parameters are used to generate silicon-based liquid crystal LCOS display images that meet the current optical path scheduling requirements; In response to receiving an online update command, the current main program image in the second storage area is copied to the third storage area, and the data integrity of the main program image copied to the third storage area is verified. After the data integrity of the main program image copied to the third storage area passes the verification, the received updated program image is written to the second storage area, and the data integrity of the updated program image written to the second storage area is verified. In response to the data integrity verification of the update program image written to the second storage area passing, a reset operation is performed only on the processing system PS, so that the programmable logic PL side continues to run, thereby keeping the display content of the liquid crystal on silicon (LCOS) unchanged during the reset of the processing system PS. After the processing system PS is reset and restarted, it reads the image generation parameters from the external non-volatile memory, restores the image display according to the image generation parameters, and resumes the reception of new image frames on the programmable logic PL side.

2. The WSS online program update method according to claim 1, characterized in that, The bootloader image in the first storage area completes the initialization configuration of the optical sensitive registers on the programmable logic (PL) side when the WSS is powered on; the program images in the second and third storage areas do not reconfigure the optical sensitive registers during the startup process. The optical sensitive register is a register used to control the optical output parameters of the silicon-based liquid crystal LCOS on the programmable logic PL side.

3. The WSS online program update method according to claim 1, characterized in that, The step of performing a reset operation only on the processing system PS to keep the programmable logic PL running includes: After detecting the image frame transmission status and determining that the current complete image frame transmission has ended, the programmable logic (PL) side will continuously output the currently transmitted complete image frame during the PS reset of the processing system, so as to keep the display content of the liquid crystal on silicon (LCOS) unchanged during the PS reset of the processing system.

4. The WSS online program update method according to claim 3, characterized in that, The programmable logic (PL) side will continuously output the complete image frame that has been transmitted during the processing system (PS) reset, including: In response to receiving a PS reset request from the processing system, the header check bit and trailer check bit of the image frame data transmitted through the AXI-Stream interface are monitored. When the check value of the header check bit indicates the start of the current complete image frame and the check value of the trailer check bit indicates the end of the current complete image frame, the transmission of the current complete image frame is determined to be over. Close the direct memory access write channel and stop receiving new image frame data.

5. The WSS online program update method according to claim 4, characterized in that, The step of determining the end of the transmission of the current complete image frame includes: A counter located at the AXI-Stream interface starts counting after detecting the header check bit of the image frame data and confirming that the check value corresponding to the header check bit is correct. When the counter count reaches the number of data corresponding to the complete image frame and confirms that the check value corresponding to the tail check bit is correct, the counter is cleared, and the transmission of the current complete image frame is considered complete.

6. The WSS online program update method according to claim 1, characterized in that, The WSS online program update method also includes: When data integrity verification of the updater image written to the second storage area fails, the backupr image is read from the third storage area and rewritten to the second storage area. The rewritten backupr image in the second storage area is then loaded to restore the system to its normal operating state before the update.

7. The WSS online program update method according to claim 1, characterized in that, The online update command and the update program image are transmitted via an asynchronous transmission protocol, and the online update command carries the target version number and the target checksum; The WSS online program update method also includes: Before transmitting the update program image, the processing system PS verifies the validity of the received target version number. Once the validity of the target version number is verified, the update program image is transmitted. After receiving the update program image, the checksum of the update program image is calculated and compared with the target checksum. When the comparison results match, the current main program image in the second storage area is copied to the third storage area.

8. The WSS online program update method according to claim 1, characterized in that, The WSS online program update method also includes: When WSS powers on, it loads the main program image from the second storage area based on the MULTI_BOOT mechanism and performs a power-on startup verification. If the main program image from the second storage area fails the power-on startup verification, it loads the backup program image from the third storage area based on the MULTI_BOOT mechanism and performs a power-on startup verification. If the backup program image from the third storage area fails the power-on startup verification, it loads the recovery program image from the first storage area.

9. The WSS online program update method according to claim 1, characterized in that, Performing a reset operation on the processing system PS includes: Call the function interface that only resets the processing system PS to perform a reset operation on the processing system PS.

10. The WSS online program update method according to claim 1, characterized in that, Data integrity verification for the master program image copied to the third storage area or the update program image written to the second storage area includes: The program image written to the storage area is read back using the serial peripheral interface protocol. When the checksum of the read-back program image is consistent with the checksum of the program image before writing, and the version number of the read-back program image is consistent with the version number of the program image before writing, the data integrity check is considered to have passed.

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