A signal processing module remote upgrading method based on FPGA control
Patent Information
- Application Number
- CN202611297066.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-25
- Publication Date
- 2026-10-30
AI Technical Summary
[0004]本申请的目的是，针对当前由于DSP芯片内部程序为顺序执行，在对自身以及FPGA芯片在线升级时所耗费时间较长，执行DSP芯片上电配置以及健康管理功能的ARM单片机无法远程升级，导致升级操作步骤繁琐的问题，提供一种基于FPGA控制的信号处理模块远程升级方法，在模块现有调试网口的基础上，实现对信号处理模块内部的FPGA芯片以及DSP芯片进行同时升级操作，可减小维护负担，降低模块升级失败后死机风险，实现信号处理模块一键式远程安全升级
[0023]提供一种基于FPGA控制的信号处理模块远程升级方法：
Smart Images
Figure CN123011278A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of signal processing module upgrade technology for electronic devices, and specifically relates to a remote upgrade method for a signal processing module based on FPGA control. Background Technology
[0002] Airborne radar systems require high-speed processing of large amounts of data and continuous, reliable operation. Therefore, each signal processing module contains numerous complex electronic components such as DSP chips, FPGA chips, and ARM microcontrollers. During system integration testing and flight testing before finalization, software programs and logic need continuous updates and upgrades. Thus, the signal processing module sends upgrade data to the DSP chip via a network interface. The DSP chip then completes its own upgrade and distributes the upgrade data to the FPGA chip, completing the FPGA chip upgrade operation. This process is sequential and time-consuming. Furthermore, the ARM microcontroller that controls the DSP chip's power-on and performs health management functions cannot be upgraded online. If this logic or program needs to be upgraded during integration testing and flight testing, it requires disassembling the sub-unit cover and module debugging cover, and then upgrading via JTAG, resulting in high maintenance costs and significant upgrade risks.
[0003] In view of the aforementioned technical problems, this application is hereby submitted. Summary of the Invention
[0004] The purpose of this application is to address the problems of cumbersome upgrade procedures caused by the sequential execution of internal programs in DSP chips, which results in long online upgrade times for both the chip itself and the FPGA chip, and the inability of ARM microcontrollers to remotely upgrade the DSP chip's power-on configuration and health management functions. This application provides a remote upgrade method for signal processing modules based on FPGA control. By utilizing the module's existing debugging network port, it enables simultaneous upgrades of both the FPGA and DSP chips within the signal processing module. This reduces maintenance burden, lowers the risk of system crashes after upgrade failures, and achieves one-click remote and secure upgrades of the signal processing module.
[0005] The technical solution of this application is:
[0006] A method for remotely upgrading a signal processing module based on FPGA control includes:
[0007] The configuration system includes a main control unit, an FPGA chip, a DSP chip, and an ARM microcontroller;
[0008] The main control unit is responsible for storing and transmitting version upgrade files for each FPGA chip, DSP chip, and ARM microcontroller.
[0009] The FPGA chip receives upgrade files from the FPGA chip, DSP chip, and ARM microcontroller transmitted by the host computer, caches them in DDR, erases and burns its own FLASH, and sends them to the DSP chip and ARM microcontroller.
[0010] When the system is powered on, the FPGA chip and DSP chip start working. The ARM microcontroller first works in the BOOT area. After failing to recognize the successful upgrade mark, it executes the original program area.
[0011] When the FPGA chip receives the upgrade command from the host computer, it receives the upgrade files for the FPGA chip, DSP chip, and ARM microcontroller, caches them in DDR, and then verifies them. If the verification fails, it requests the host computer to resend the files.
[0012] After the FPGA chip successfully verifies its performance, it sends an upgrade command to the DSP chip and simultaneously erases and reprograms its own FLASH memory.
[0013] After the FLASH of the FPGA chip is programmed, the programmed data is read back and verified. If the verification is successful, the programming completion flag is set to valid; otherwise, the FPGA chip will reprogram the FLASH.
[0014] After receiving the upgrade command from the FPGA chip, the DSP chip replies with a response packet to the FPGA chip. Upon receiving the response packet, the FPGA chip sends the upgrade data in packets to the DSP chip for FLASH erasure and programming. After programming is complete, the DSP chip reads back and verifies the programmed data. If the verification is successful, the DSP chip sets the programming completion flag to valid and notifies the FPGA chip to send an upgrade command to the ARM microcontroller. Otherwise, the DSP chip will re-initiate the upgrade request to the FPGA chip.
[0015] The ARM microcontroller responds to the upgrade command and jumps to the boot program area to execute. The ARM microcontroller requests, receives, caches, and verifies the ARM microcontroller upgrade file. If the verification fails, it requests the FPGA chip to resend the upgrade file.
[0016] After the system is powered on again, the FPGA chip and DSP chip jump to the program burning area. If the jump fails, it will roll back to the original program area. The ARM microcontroller first works in the BOOT area. After recognizing the successful upgrade mark, it executes the upgrade program area; otherwise, it executes the original program area.
[0017] According to at least one embodiment of this application, in the above-described remote upgrade method for a signal processing module based on FPGA control, the FPGA chip determines whether the DSP chip and FPGA chip have been successfully upgraded based on communication with the DSP chip and the ARM microcontroller, and interacts with the host computer based on the determination information.
[0018] According to at least one embodiment of this application, in the above-described remote upgrade method for a signal processing module based on FPGA control, the FPGA chip receives upgrade files for the FPGA chip, DSP chip, and ARM microcontroller transmitted by the host computer through a network interface.
[0019] According to at least one embodiment of this application, in the above-described remote upgrade method for a signal processing module based on FPGA control, the FPGA chip erases and programs its own FLASH memory via the SPI interface.
[0020] According to at least one embodiment of this application, in the above-described remote upgrade method for a signal processing module based on FPGA control, the FPGA chip transmits the required upgrade files for the ARM microcontroller via the UART interface according to the Modelbus protocol.
[0021] According to at least one embodiment of this application, in the above-described remote upgrade method for a signal processing module based on FPGA control, the FPGA chip sends an upgrade file to the DSP chip via the SRIO interface.
[0022] This application has at least the following beneficial technical effects:
[0023] A method for remotely upgrading a signal processing module based on FPGA control is provided:
[0024] This method enables one-click remote upgrades of signal processing modules, improving module flexibility and significantly reducing maintenance costs.
[0025] The design incorporates backup functionality for ARM microcontroller software, DSP chip upgrade programs, and FPGA chip programs. This reduces the cost of software upgrade failures and ensures that modules can still run the original version of the program after a failed upgrade, allowing for another software upgrade.
[0026] This method achieves the same result on existing products without incurring any additional costs. Specifically, it addresses signal processing modules with network communication capabilities, such as FPGA chips + ARM microcontrollers + multiple DSP chips, particularly those where the ARM microcontroller controls the power-on of the DSP chips and has no external interfaces. This simplifies software upgrades and ensures that the DSP chips, FPGA chips, and ARM microcontrollers continue to function normally and can be upgraded again even after a failed upgrade, requiring no hardware modifications and significantly reducing maintenance burden. Attached Figure Description
[0027] Figure 1 A principle block diagram of the remote upgrade method for a signal processing module based on FPGA control provided in this application embodiment;
[0028] Figure 2A flowchart illustrating a remote upgrade method for a signal processing module based on FPGA control, provided in an embodiment of this application.
[0029] To better illustrate this embodiment, some content in the accompanying drawings may be omitted, enlarged, or reduced. They are for illustrative purposes only and should not be construed as limiting the scope of this application. Detailed Implementation
[0030] To make the technical solution and advantages of this application clearer, the technical solution of this application will be described in a clearer and more complete manner below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only some embodiments of this application, and are only used to explain this application, not to limit this application. It should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, and other related parts can be referred to the general design.
[0031] Furthermore, unless otherwise defined, the technical or scientific terms used in this application description shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The word "comprising" as used in this application description indicates that the concept preceding the word encompasses the concepts listed following the word and their equivalents, without excluding other related concepts.
[0032] Furthermore, the terms indicating location used in the description of this application are only used to indicate relative directions or positional relationships. When the absolute position of the described object changes, its relative positional relationship may also change accordingly. It should also be noted that, unless otherwise explicitly specified and limited, terms such as "installation" and "connection" used in the description of this application should be interpreted broadly. For example, a connection can be a fixed connection or a detachable connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand its specific meaning in this application according to the specific circumstances.
[0033] A remote upgrade method for a signal processing module based on FPGA control is proposed. This method enables one-click online upgrades of the FPGA chip, ARM microcontroller, and DSP chip on the local board. It also ensures that the program automatically reverts to the original program should the upgrade fail. The principle block diagram is shown below. Figure 1 As shown, it includes a main controller, an FPGA chip, a DSP chip, and an ARM microcontroller, forming an FPGA chip + ARM microcontroller + DSP chip architecture.
[0034] The main controller is responsible for storing and transmitting version upgrade files for each FPGA chip, DSP chip, and ARM microcontroller.
[0035] The FPGA chip receives upgrade files for the FPGA chip, DSP chip, and ARM microcontroller from the host computer via the network interface, caches them in DDR, and then erases and programs its own FLASH via the SPI interface; it transmits the required upgrade files for the ARM microcontroller via the UART interface according to the Modelbus protocol; and the upgrade files for the DSP chip are sent via the SRIO interface.
[0036] The FPGA chip has the following interface circuits:
[0037] Network interface: Supports TCP / IP communication protocol, enables network communication with the host computer, and completes the reception of upgrade files for FPGA chips, DSP chips and ARM microcontrollers;
[0038] UART interface: used to send ARM microcontroller upgrade files to the ARM microcontroller;
[0039] SRIO interface: Used to send DSP chip upgrade files to the DSP chip;
[0040] SPI interface: used to erase and program the FLASH memory of the FPGA chip itself.
[0041] The DSP chip is interconnected with the FPGA chip via the SRIO interface.
[0042] The ARM microcontroller is interconnected with the FPGA chip via the UART interface.
[0043] RAM cache: such as mainstream RAM like DDR2 and DDR3, used to store ARM microcontroller / CPLD upgrade files.
[0044] The specific method for remotely upgrading a signal processing module based on FPGA control is as follows:
[0045] When the system is powered on, the FPGA chip and DSP chip start working. The ARM microcontroller first works in the BOOT area. After failing to recognize the successful upgrade flag, it executes the original program area.
[0046] The FPGA chip receives the upgrade command from the host computer through the network interface, receives the upgrade files of the FPGA chip, DSP chip and ARM microcontroller, caches them in DDR, and then verifies them. If the verification fails, it requests the host computer to resend the command.
[0047] After the FPGA chip successfully verifies its performance, it sends an upgrade command to the DSP chip. At the same time, it also erases and programs its own FLASH memory. The programming process of the DSP chip and the programming process of the FPGA chip will be executed in parallel.
[0048] After the FLASH of the FPGA chip is programmed, the programmed data is read back and verified. If the verification is successful, the programming completion flag is set to valid; otherwise, the FPGA chip will reprogram the FLASH.
[0049] After receiving the upgrade command from the FPGA chip, the DSP chip replies with a response packet. Upon receiving the response packet, the FPGA chip sends the upgrade data in packets to the DSP chip for FLASH erasure and programming. After programming is complete, the DSP chip also reads back and verifies the FLASH data. If the verification is successful, the DSP chip sets the programming completion flag to valid and notifies the FPGA chip to send an upgrade command to the ARM microcontroller. Otherwise, the DSP chip will re-initiate the upgrade request to the FPGA chip.
[0050] The ARM microcontroller responds to the upgrade command and jumps to the boot program area to execute. The ARM microcontroller requests, receives, caches, and verifies the ARM microcontroller / CPLD upgrade file. If the verification fails, it requests the FPGA chip to resend the file.
[0051] After the system is powered on again, the FPGA chip and DSP chip will jump to the program burning area. If the jump fails, they will roll back to the original program area. The ARM microcontroller first works in the BOOT area. After recognizing the successful upgrade flag, it executes the upgrade program area; otherwise, it executes the original program area to ensure that the original functions of the signal processing module are not lost.
[0052] The FPGA chip can determine whether the DSP chip and FPGA chip have been successfully upgraded based on communication with the DSP chip and ARM microcontroller, and then exchange the information with the host computer.
[0053] The remote upgrade method for a signal processing module based on FPGA control disclosed in the above embodiments employs software backup functionality to reduce the risk of upgrade failure and improve stability. It uses an FPGA chip to control the online upgrade of the FPGA chip, DSP chip, and ARM microcontroller within the signal processing module, achieving one-click online upgrade of the signal processing module. Furthermore, because the FPGA chip runs programs in parallel, it distributes upgrade data to the DSP chip while upgrading itself online, thereby shortening the online upgrade time for both the DSP chip and the FPGA chip. The key technologies involved are as follows:
[0054] TCP / IP network communication technology: The FPGA chip supports TCP / IP network communication and receives upgrade files sent by the host computer;
[0055] Dual-zone technology: The FLASH of the FPGA chip and the DSP chip are each divided into two zones. One zone is responsible for storing the original programming file, and the other zone stores the upgrade data, so that the previous program can be automatically rolled back in case of programming failure.
[0056] SRIO communication protocol: FPGA chips and DSP chips support SRIO communication. The FPGA chip distributes upgrade data to the DSP chip through this interface.
[0057] ARM microcontroller serial port loading and software backup technology: ARM microcontrollers support serial port loading and hardware support software backup capabilities;
[0058] Modlebus protocol communication technology: When the FPGA chip distributes upgrade data to the ARM microcontroller, there is a Modlebus packet handshake protocol to increase the reliability of data distribution.
[0059] The technical solution of this application has been described in conjunction with the preferred embodiments shown in the accompanying drawings. Those skilled in the art should understand that the protection scope of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of this application.
Claims
1. A method for remotely upgrading a signal processing module based on FPGA control, characterized in that, include: The configuration system includes a main control unit, an FPGA chip, a DSP chip, and an ARM microcontroller; The main control unit is responsible for storing and transmitting version upgrade files for each FPGA chip, DSP chip, and ARM microcontroller. The FPGA chip receives upgrade files from the FPGA chip, DSP chip, and ARM microcontroller transmitted by the host computer, caches them in DDR, erases and burns its own FLASH, and sends them to the DSP chip and ARM microcontroller. When the system is powered on, the FPGA chip and DSP chip start working. The ARM microcontroller first works in the BOOT area. After failing to recognize the successful upgrade mark, it executes the original program area. When the FPGA chip receives the upgrade command from the host computer, it receives the upgrade files for the FPGA chip, DSP chip, and ARM microcontroller, caches them in DDR, and then verifies them. If the verification fails, it requests the host computer to resend the files. After the FPGA chip successfully verifies its performance, it sends an upgrade command to the DSP chip and simultaneously erases and reprograms its own FLASH memory. After the FLASH of the FPGA chip is programmed, the programmed data is read back and verified. If the verification is successful, the programming completion flag is set to valid; otherwise, the FPGA chip will reprogram the FLASH. After receiving the upgrade command from the FPGA chip, the DSP chip replies with a response packet to the FPGA chip. Upon receiving the response packet, the FPGA chip sends the upgrade data in packets to the DSP chip for FLASH erasure and programming. After programming is complete, the DSP chip reads back and verifies the programmed data. If the verification is successful, the DSP chip sets the programming completion flag to valid and notifies the FPGA chip to send an upgrade command to the ARM microcontroller. Otherwise, the DSP chip will re-initiate the upgrade request to the FPGA chip. The ARM microcontroller responds to the upgrade command and jumps to the boot program area to execute. The ARM microcontroller requests, receives, caches, and verifies the ARM microcontroller upgrade file. If the verification fails, it requests the FPGA chip to resend the upgrade file. After the system is powered on again, the FPGA chip and DSP chip jump to the program burning area. If the jump fails, it will roll back to the original program area. The ARM microcontroller first works in the BOOT area. After recognizing the successful upgrade mark, it executes the upgrade program area; otherwise, it executes the original program area.
2. The remote upgrade method for a signal processing module based on FPGA control according to claim 1, characterized in that, The FPGA chip determines whether the DSP chip and FPGA chip have been successfully upgraded based on communication with the DSP chip and ARM microcontroller, and then exchanges the information with the host computer.
3. The remote upgrade method for a signal processing module based on FPGA control according to claim 2, characterized in that, The FPGA chip receives upgrade files for the FPGA chip, DSP chip, and ARM microcontroller transmitted from the host computer via a network interface.
4. The remote upgrade method for a signal processing module based on FPGA control according to claim 3, characterized in that, The FPGA chip erases and programs its own FLASH memory via the SPI interface.
5. The remote upgrade method for a signal processing module based on FPGA control according to claim 4, characterized in that, The FPGA chip transmits the necessary upgrade files to the ARM microcontroller via the UART interface according to the Modebus protocol.
6. The remote upgrade method for a signal processing module based on FPGA control according to claim 5, characterized in that, The FPGA chip sends upgrade files to the DSP chip via the SRIO interface.