Multi-core soc refresh system

Abstract

The application discloses a multi-core SOC refreshing system, an MPU core completes loading of refreshing data and writing to an eMMC chip, an MCU core completes carrying work of the refreshing data from the eMMC chip to a NorFlash chip, direct access of the eMMC and the NorFlash storage medium is adopted for data writing, the data transmission rate between the core and the storage medium is greatly improved, the flashing rate is improved, the refreshing link is shortened, and the refreshing stability and reliability are further improved; the MCU core and the MPU core support independent running, the refreshing process and the componentization of the refreshing execution task can reduce software dependence, improve software compatibility and reusability to a greater extent, are more favorable to operation maintenance and portability of software program development, and thus software development cost is reduced.

Description

Technical Field

[0001] This invention relates to intelligent connected vehicle technology, and in particular to a multi-core SOC refresh system. Background Technology

[0002] With the increasing application and adoption of automotive Ethernet in the automotive field, the automotive industry has established the ISO 13400 standard. ISO 13400, also known as DoIP (Diagnostic over Internet Protocol), is a set of standards developed by the International Organization for Standardization (ISO). It defines methods for diagnostic communication using Ethernet in vehicle networks. The ISO 13400 protocol specification comprises four parts: general information, use case definitions, transport protocols and network layer services, wired vehicle interfaces based on IEEE 802.3, and high-speed data link connectors based on Ethernet. These constitute the core elements of the DoIP standard, providing a unified diagnostic communication interface standard for vehicle manufacturers and diagnostic tool developers.

[0003] Furthermore, with the increasing complexity of the automotive electronic and electrical architecture, the number of ECU (Electronic Control Unit) controllers deployed in the vehicle has increased significantly. This means that the complexity of automotive software development is increasing. In the context of rapid and agile software development and delivery, the methods for upgrading ECU software need to be stable, reliable, and efficient.

[0004] OTA (Over-The-Air) technology for vehicle software updates refers to the process or method of remotely upgrading and updating vehicle controller software via an air interface of mobile communication. Current methods for upgrading controller nodes using OTA technology involve storing the required software upgrade package for the ECU controller on a NorFlash chip located outside the multi-core SOC (System-on-Chip) chip. Before the update, the software upgrade package is stored in the NorFlash chip external to the multi-core SOC chip. The entire flashing process involves only the MCU core or MPU core within the multi-core SOC chip, communicating with the relevant controller node via Ethernet for network communication and flashing functionality. However, this existing upgrade method places all functional logic within the MCU core or MPU core of the multi-core SOC chip. The actual flashing speed and quality are limited by the performance and hardware resources of the MCU core or MPU core. Furthermore, the diagnostic flashing link is relatively long, requiring high Ethernet network communication performance, and the flashing rate depends on the performance of the multi-core SOC chip, often limited by the performance of the MCU core. In addition, existing DOIP refresh / OTA refresh methods rely on the Ethernet application or Ethernet configuration of the two cores for the refresh links of the MCU core and MPU core inside the multi-core SOC chip, which makes it difficult to achieve software compatibility and scalability, and increases software development costs. Summary of the Invention

[0005] The technical problem to be solved by this invention is to provide a multi-core SOC refresh system with high write speed, high stability, high reliability, and high software compatibility and reusability.

[0006] To solve the above-mentioned technical problems, the present invention provides a multi-core SOC refresh system, which includes a multi-core SOC chip, an eMMC chip, a NorFlash chip, and a diagnostic device;

[0007] The multi-core SOC chip is signal-connected to the diagnostic equipment, eMMC chip, and NorFlash chip, respectively.

[0008] The multi-core SOC chip includes an MCU core and an MPU core;

[0009] The diagnostic device establishes an Ethernet communication link with the multi-core SOC chip via Ethernet Diagnostic DoIP for data access and sends data to be refreshed to the multi-core SOC chip.

[0010] The MPU core stores the data to be refreshed into the eMMC chip as a refresh image file using the eMMC direct drive method.

[0011] The MCU core reads and stores the refresh image file from the eMMC chip into the NorFlash chip using the eMMC direct drive method.

[0012] Preferably, the MPU core stores the data to be refreshed into the eMMC chip using the eMMC direct drive method, and then restarts the multi-core SOC chip.

[0013] When the multi-core SOC chip restarts, the MCU core directly reads and stores the data to be refreshed from the eMMC chip into the NorFlash chip.

[0014] Preferably, the diagnostic device is a TBOX controller or an external diagnostic instrument;

[0015] The TBOX controller is used to download and send the data to be refreshed to the multi-core SOC chip via Ethernet in OTA mode; the TBOX controller and the multi-core SOC chip establish a link for data access using Ethernet diagnostic DoIP.

[0016] The external diagnostic instrument establishes an Ethernet communication link with the multi-core SOC chip via Ethernet Diagnostic DoIP for data access and sends new data to the multi-core SOC chip.

[0017] Preferably, the components of the MPU kernel include a DoIP server, a UDS diagnostic service module, and a Self Update refresh process;

[0018] The DoIP server is used to establish a link with an external diagnostic instrument or TBOX controller, and at the same time to interact and respond with the UDS diagnostic service module to realize the transmission and refresh of Ethernet diagnostic data.

[0019] The UDS diagnostic service module is used to implement diagnostic security authentication and diagnostic refresh process and complete refresh data loading.

[0020] When the diagnostic device connects to the multi-core SOC chip, the diagnostic device, acting as a DoIP client, initiates a route activation request to determine whether the route activation is successful. If the route activation is successful, the diagnostic device establishes a diagnostic link with the multi-core SOC chip and sends a diagnostic request to the DoIP server.

[0021] The DoIP server's protocol stack processes diagnostic requests from diagnostic devices and interacts with the UDS diagnostic service module for diagnostic service data.

[0022] The UDS diagnostic service module performs diagnostic security authentication on the diagnostic request.

[0023] If the security authentication is successful, the DoIP server receives the data to be refreshed and activates the SelfUpdate refresh process.

[0024] Preferably, the multi-core SOC control system further includes a Switch chip;

[0025] The Switch chip is signal-connected to the TBOX controller, the external diagnostic instrument, and the multi-core SOC chip, respectively.

[0026] The external switch chip is a Layer 2 network communication device for Ethernet link network transmission. As a switch for Ethernet communication, it realizes Layer 2 message routing for Ethernet communication.

[0027] The external diagnostic instrument or TBOX controller establishes a link with the multi-core SOC chip through the Switch chip to access data.

[0028] When the Self Update process is executed, the Switch data to be flashed is first loaded into the NorFlash of the external Switch chip, and then the data to be flashed is written into the designated storage partition of the eMMC chip.

[0029] Preferably, the components of the MPU kernel also include an eMMC driver;

[0030] The eMMC driver is used to read and write access to external eMMC chips;

[0031] When the Self Update process is executed, the data to be refreshed is written into a designated storage partition of the eMMC chip as a refresh image file.

[0032] Preferably, when the Self Update process is executed, the data to be refreshed is written to a designated storage partition of the eMMC chip as a refresh image file, and a refresh flag is written to a first designated address of the eMMC chip. Furthermore, if the MPU kernel successfully completes writing the refresh image file to the designated storage partition of the eMMC chip, a valid image flag is written to a second designated address of the eMMC chip.

[0033] Preferably, the MCU core includes a refresh complex driver, a Flash driver, and an eMMC driver;

[0034] The refresh complexity driver is used to complete the writing, loading, and integrity verification of the refresh image file;

[0035] The refresh complex driver completes the writing of the refresh image file of the NorFlash chip through the Flash driver;

[0036] The refresh complexity driver reads the refresh image file in the eMMC chip through the eMMC driver.

[0037] After the multi-core SOC chip restarts and the MCU core successfully boots, the process of reading and storing the refresh image file from the eMMC chip to the NorFlash chip is as follows:

[0038] S1. The refresh complex driver determines whether the first specified address of the eMMC chip is a refresh flag. If it is a refresh flag, proceed to step S2; otherwise, the refresh fails and proceed to step S50.

[0039] S2. The refresh complex driver checks whether the second specified address in the eMMC is a valid image flag. If it is, proceed to step S3; otherwise, the refresh fails and proceed to step S50.

[0040] S3. The refresh complex driver calculates the CRC value of the refresh image file in the specified storage partition in the eMMC and compares it with the CRC value carried at the end of the refresh image file. If the two match, the refresh image file is complete, and proceed to step S4; otherwise, the refresh fails, and proceed to step S50.

[0041] S4. The refresh complex driver reads the refresh image file in the specified storage partition of the eMMC through the eMMC driver, and writes it into the partition to be refreshed of the NorFlash chip through the Flash driver;

[0042] S5. The refresh complex driver calculates whether the CRC value of the refresh image file written to the partition to be refreshed in the NorFlash chip is consistent with its carried CRC value. If they are consistent, proceed to step S6; otherwise, the refresh fails and proceed to step S50.

[0043] S6. The refresh complex driver clears the refresh flag in the first specified address of the eMMC chip, indicating that the MCU core data refresh was successful;

[0044] S7. The complex driver is refreshed, and the SOC chip is restarted;

[0045] S50. End.

[0046] Preferably, the eMMC chip includes partition A of MCU kernel application executable file, partition B of MCU kernel application executable file, partition A of MPU kernel uboot target file, partition B of MPU kernel uboot target file, partition A of MPU kernel image file, partition B of MPU kernel image file, partition A of MPU kernel rootfs image file, and partition B of MPU kernel rootfs image file, with partitions A and B serving as backup partitions for each other;

[0047] When the Self Update process is executed, if the currently running program is in partition B of the eMMC chip, the data to be updated is written into partition A of the eMMC chip as a refresh image file. After the data to be updated is successfully updated in partition A, the currently running program is switched to partition A of the eMMC chip. If the currently running program is in partition A of the eMMC chip, the data to be updated is written into partition B of the eMMC chip as a refresh image file. After the data to be updated is successfully updated in partition B, the currently running program is switched to partition B of the eMMC chip.

[0048] After the Self Update process is executed and the data to be updated is successfully written to both partitions B and A of the eMMC chip, the multi-core SOC chip is restarted.

[0049] Preferably, the NorFlash chip includes an MCU kernel application software A partition, an MCU kernel application software B partition, and an MCU kernel default boot partition, wherein the application software A partition and B partition are backup partitions for each other;

[0050] The default boot partition of the MCU kernel is used to record A / B partition information and the application software execution flag of the corresponding partition; the application software of the corresponding partition can only run when the application software execution flag is valid.

[0051] Preferably, in step S1, if the first specified address is a refresh flag, the refresh complex driver reads the current running partition information of the MCU kernel from the MCU kernel default boot partition of the MCU kernel, determines the partition to be flashed in the NorFlash chip, and then proceeds to step S2.

[0052] In step S5, if the CRC value of the refresh image file written to the partition to be flashed in the NorFlash chip matches the CRC value it carries, the refresh complex driver first erases the A / B partition information and application software execution flag information of the MCU kernel default boot partition; then, it writes the current A / B partition information of the MCU kernel to the MCU kernel default boot partition, sets the flag information of the application software corresponding to the currently running partition to be valid, and clears the valid flag information of the application software in the other partition, completing the A / B partition switching, and then proceeds to step S6.

[0053] Preferably, in step S6, the complex driver is refreshed, and a fixed value is written into the specified address of the eMMC chip to notify the MPU kernel that the NorFlash chip refresh is complete.

[0054] The multi-core SOC refresh system of this invention completes the software flashing of the entire SOC system or individual kernels through DoIP / OTA refresh. The data refresh is divided into two stages. In the first stage, the diagnostic device uses DoIP to connect to the MPU core in the multi-core SOC chip and writes the data to be refreshed into the storage unit of the eMMC (Embedded Multi Media Card) chip as a refresh image file. In the second stage, the MCU core reads the refresh image file from the storage unit of the eMMC chip and moves it to the NorFlash chip.

[0055] This multi-core SoC refresh system uses direct access to eMMC and NorFlash storage media for data writing. The MPU core uses DoIP refresh to download the data to be refreshed from the diagnostic device to the local cache. Then, the MPU core uses a direct eMMC driver to write and store the cached data to be refreshed to the eMMC chip. Finally, the MCU core uses a direct access to eMMC and NorFlash driver to transfer the data to be refreshed (refresh image file) from the eMMC chip to the specified address on the NorFlash chip. In this multi-core SoC refresh system, DoIP refresh directly completes the data writing interaction through the read and write of the eMMC hardware driver. The MCU core only needs to complete the data transfer work from the eMMC chip to the NorFlash chip. The data transfer rate between the core and the storage media is significantly improved, thereby increasing the refresh rate. The refresh chain is also shortened, further improving the stability and reliability of the refresh. The MCU core and MPU core run independently. The modularization of the refresh process and refresh execution tasks reduces software dependencies, greatly improves software compatibility and reusability, and is more conducive to the operation, maintenance, and portability of software programs, thereby reducing software development costs. Attached Figure Description

[0056] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a schematic diagram of an embodiment of the multi-core SOC refresh system of the present invention;

[0058] Figure 2 This is a flowchart illustrating the process of writing a refresh image file from the MPU kernel to the eMMC chip in an embodiment of the multi-core SOC refresh system of the present invention.

[0059] Figure 3 This is a flowchart illustrating the process of writing a refresh image file from the MCU core to the NorFlash chip in an embodiment of the multi-core SOC refresh system of the present invention. Detailed Implementation

[0060] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] The terms "first," "second," and similar words used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Words such as "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0062] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0063] Example 1

[0064] A multi-core SOC refresh system such as Figure 1As shown, it includes a multi-core SOC (System on Chip) chip, an eMMC (Embedded Multi Media Card) chip, a NorFlash chip, and diagnostic equipment;

[0065] The multi-core SOC chip is signal-connected to the diagnostic equipment, eMMC chip, and NorFlash chip, respectively.

[0066] The multi-core SOC chip includes an MCU (Micro Controller Unit) core and an MPU (Micro Processor Unit) core;

[0067] The diagnostic device establishes a link with the multi-core SOC chip using DoIP (Diagnostic over Internet Protocol) for data access and sends the data to be refreshed to the multi-core SOC chip.

[0068] The MPU core stores the data to be refreshed into the eMMC chip as a refresh image file using the eMMC direct drive method.

[0069] The MCU core reads and stores the refresh image file from the eMMC chip into the NorFlash chip using the eMMC direct drive method.

[0070] The MCU core is an M-core (embedded real-time processor core) under the ARM (Advanced RISC Machines, i.e., a Reduced Instruction Set Computer) architecture, which is suitable for handling real-time control tasks and implements functions based on the FreeRTOS system or the Autosar (Automotive Open System Architecture) OS.

[0071] The MPU core is the application processing core in the ARM architecture, also known as the A core. It is typically used for high-performance computing and the execution of general-purpose operating systems, and can be used to develop software functions and applications based on the Linux / QNX operating system.

[0072] The multi-core SOC refresh system in Example 1 completes the software flashing of the entire SOC system or individual kernels through DoIP / OTA refresh. The data refresh is divided into two stages. In the first stage, the diagnostic device uses DoIP to connect to the MPU core in the multi-core SOC chip and writes the data to be refreshed into the storage unit of the eMMC (Embedded Multi Media Card) chip as a refresh image file. In the second stage, the MCU core reads the refresh image file from the storage unit of the eMMC chip and moves it to the NorFlash chip.

[0073] This multi-core SoC refresh system uses direct access to eMMC and NorFlash storage media for data writing. The MPU core uses DoIP refresh to download the data to be refreshed from the diagnostic device to the local cache. Then, the MPU core uses a direct eMMC driver to write and store the cached data to be refreshed to the eMMC chip. Finally, the MCU core uses a direct access to eMMC and NorFlash driver to transfer the data to be refreshed (refresh image file) from the eMMC chip to the specified address on the NorFlash chip. In this multi-core SoC refresh system, DoIP refresh directly completes the data writing interaction through the read and write of the eMMC hardware driver. The MCU core only needs to complete the data transfer work from the eMMC chip to the NorFlash chip. The data transfer rate between the core and the storage media is significantly improved, thereby increasing the refresh rate. The refresh chain is also shortened, further improving the stability and reliability of the refresh. The MCU core and MPU core run independently. The modularization of the refresh process and refresh execution tasks reduces software dependencies, greatly improves software compatibility and reusability, and is more conducive to the operation, maintenance, and portability of software programs, thereby reducing software development costs.

[0074] Example 2

[0075] Based on the multi-core SOC refresh system of Embodiment 1, the MPU core stores the data to be refreshed into the eMMC chip using the eMMC direct drive method, and then restarts the multi-core SOC chip.

[0076] When the multi-core SOC chip restarts, the MCU core directly reads and stores the refresh image file from the eMMC chip into the NorFlash chip.

[0077] Example 3

[0078] Based on the multi-core SOC refresh system of Embodiment 2, the diagnostic device is a TBOX controller or an external diagnostic instrument (Tester);

[0079] The TBOX controller is an in-vehicle network remote communication terminal controller used to download and send data to be refreshed to the multi-core SOC chip via Ethernet in OTA (Over The Air) mode, completing secure access and download of data with the cloud and interaction; the TBOX controller and the multi-core SOC chip establish a link for data access via Ethernet diagnostic DoIP, and connect to the MPU core of the multi-core SOC chip via Ethernet for data transmission and sending of data to be refreshed;

[0080] The external diagnostic instrument (Tester) is an external diagnostic device used as the host computer for DoIP refresh. As a DoIP client, it establishes an Ethernet communication link with the multi-core SOC chip using DoIP (Diagnostic over Internet Protocol, vehicle Ethernet diagnostic protocol) to access data and send new data to be refreshed to the multi-core SOC chip.

[0081] The multi-core SOC refresh system in Example 3 supports OTA refresh and DoIP refresh. The cloud data download interaction for OTA refresh is completed by the TBOX controller. Then, the data access between the TBOX controller and the multi-core SOC chip still uses the DoIP (Diagnostic over Internet Protocol) diagnostic refresh link.

[0082] Example 4

[0083] Based on the multi-core SOC refresh system of Embodiment 3, the components of the MPU kernel include a DoIP server, a UDS diagnostic service module, and a Self Update refresh process;

[0084] The DoIP server is used to establish a connection with the external diagnostic instrument (Tester) or the OTA master in the TBOX controller, and to interact and respond with the UDS (Unified Diagnostic Services) module to realize the transmission and refresh of Ethernet diagnostic data.

[0085] The UDS module is used for diagnostic security authentication;

[0086] like Figure 2 As shown, when the diagnostic device connects to the multi-core SOC chip, the diagnostic device, acting as a DoIP client, initiates a route activation request to determine whether the route activation is successful. If the route activation is successful, the diagnostic device establishes a diagnostic link with the multi-core SOC chip and sends a diagnostic request to the DoIP server.

[0087] The DoIP server's protocol stack processes diagnostic requests from diagnostic devices and interacts with the UDS module for diagnostic service data.

[0088] The UDS diagnostic service module performs diagnostic security authentication on the diagnostic request (UDS 0x27 service);

[0089] If the security authentication is successful, the DoIP server receives the data to be refreshed and activates the SelfUpdate refresh process; otherwise, the refresh fails.

[0090] In the multi-core SOC refresh system of Example 4, the diagnostic device, acting as a DoIP client, initiates a route activation request and determines whether the route activation is successful. If the activation is successful, the diagnostic device establishes a diagnostic link with the controller; otherwise, the refresh fails. The DoIP server protocol stack deployed in the MPU kernel processes the diagnostic request from the diagnostic device and completes the response to the diagnostic request. The UDS module performs diagnostic security authentication on the diagnostic request (UDS 0x27 service). If the diagnostic security authentication passes, the DoIP server receives the data to be refreshed and activates the Self Update refresh process; otherwise, the refresh fails.

[0091] Example 5

[0092] Based on the multi-core SOC refresh system of Embodiment 4, the multi-core SOC control system further includes a Switch chip;

[0093] The Switch chip is signal-connected to the TBOX controller, the external diagnostic instrument, and the multi-core SOC chip, respectively.

[0094] The external switch chip is a Layer 2 network communication device for Ethernet link network transmission. As a switch for Ethernet communication, it realizes Layer 2 message routing for Ethernet communication.

[0095] The external diagnostic instrument or TBOX controller establishes a link with the multi-core SOC chip through the Switch chip to access data.

[0096] like Figure 2 As shown, when the Self Update process is executed, the Switch data to be flashed is first loaded into the NorFlash of the external Switch chip, and then the data to be flashed is written into the designated storage partition of the eMMC chip.

[0097] In the multi-core SOC refresh system of Example 5, the external diagnostic instrument (Tester) is used as the host computer for DoIP refresh. As a DoIP client, it establishes a connection with the DoIP server of the multi-core SOC chip through the Tx (diagnostic port) of the external switch chip, sends refresh data requests, and realizes the transmission of the data to be refreshed. It can simultaneously perform OTA / DoIP whole packet refresh or single-core independent refresh on the data under the MCU core and MPU core in the multi-core SOC chip, and can also support data refresh on the external switch chip.

[0098] Example 6

[0099] Based on the multi-core SOC refresh system of Embodiment 4, the components of the MPU kernel also include an eMMC driver;

[0100] The eMMC driver is used to read and write access to the external eMMC chip;

[0101] When the Self Update process is executed, the data to be refreshed is written into a designated storage partition of the eMMC chip as a refresh image file.

[0102] Preferably, when the Self Update process is executed, the data to be refreshed is written to a designated storage partition of the eMMC chip as a refresh image file, and a refresh flag is written to a first designated address of the eMMC chip. Furthermore, if the MPU kernel successfully completes writing the refresh image file to the designated storage partition of the eMMC chip, a valid image flag is written to a second designated address of the eMMC chip.

[0103] Example 7

[0104] Based on the multi-core SOC refresh system of Embodiment Six, the MCU core includes a refresh complex driver, a Flash driver, and an eMMC driver;

[0105] The refresh complexity driver is used to complete the writing, loading, and integrity verification of the refresh image file;

[0106] The refresh complex driver completes the writing of the refresh image file of the NorFlash chip through the Flash driver;

[0107] The refresh complexity driver reads the refresh image file from the eMMC chip through the eMMC driver.

[0108] like Figure 3 As shown, after the multi-core SOC chip restarts and the MCU core successfully boots, the process of reading and storing the refresh image file from the eMMC chip to the NorFlash chip is as follows:

[0109] S1. The refresh complex driver determines whether the first specified address of the eMMC chip is a refresh flag. If it is a refresh flag, proceed to step S2; otherwise, the refresh fails and proceed to step S50.

[0110] S2. The refresh complex driver checks whether the second specified address in the eMMC is a valid image flag (used to determine whether the MPU kernel has successfully completed writing the data to be refreshed into the specified storage partition in the eMMC chip). If so, proceed to step S3; otherwise, the refresh fails and proceed to step S50.

[0111] S3. The refresh complex driver calculates the CRC value of the refresh image file in the specified storage partition of the eMMC and compares it with the CRC (Cyclic Redundancy Check) value carried at the end of the refresh image file. If the two match, the refresh image file is complete, and proceed to step S4; otherwise, the refresh fails, and proceed to step S50.

[0112] S4. The refresh complex driver reads the refresh image file in the specified storage partition of the eMMC through the eMMC driver, and writes it to the partition to be refreshed of the NorFlash chip through the Flash driver;

[0113] S5. The refresh complex driver calculates whether the CRC value of the refresh image file written to the partition to be refreshed in the NorFlash chip is consistent with its carried CRC value. If they are consistent (indicating that the data is loaded completely), proceed to step S6; otherwise, the refresh fails and proceed to step S50.

[0114] S6. The refresh complex driver clears the refresh flag in the first specified address of the eMMC chip, indicating that the MCU core data refresh was successful;

[0115] S7. The complex driver is refreshed, the SOC chip is restarted, and the entire refresh process is completed;

[0116] S50. End.

[0117] The multi-core SOC refresh system in Example 7, combined with diagnostic equipment and a diagnostic link to a DoIP server deployed within the SOC chip, completes Ethernet communication. The MCU core only needs to handle the transfer of the refresh image file from the eMMC chip to the NorFlash chip. The MCU core and MPU core run independently, reducing software dependencies and significantly improving software compatibility and reusability. This is more conducive to the operation, maintenance, and portability of software programs, thereby reducing software development costs. In this multi-core SOC refresh system, data is written to the storage space by directly accessing the peripheral eMMC chip and NorFlash chip. Because data interaction is completed directly through the eMMC hardware driver, the eMMC interface access speed reaches up to 400MB / s, enabling rapid data interaction. The refresh image file loading time is greatly shortened, significantly reducing loading time and increasing the refresh rate, especially for refresh image files with large APP application executables.

[0118] Example 8

[0119] Based on the multi-core SOC refresh system of Embodiment 7, the eMMC chip includes partition A of MCU kernel application executable file, partition B of MCU kernel application executable file, partition A of MPU kernel uboot target file, partition B of MPU kernel uboot target file, partition A of MPU kernel image file, partition B of MPU kernel image file, partition A of MPU kernel rootfs image file, and partition B of MPU kernel rootfs image file, with partitions A and B serving as backup partitions for each other;

[0120] When the Self Update process is executed, if the currently running program is in partition B of the eMMC chip, the data to be refreshed is written into partition A of the eMMC chip as a refresh image file. After the data to be refreshed is successfully refreshed in partition A, the currently running program is switched to partition A of the eMMC chip. If the currently running program is in partition A of the eMMC chip, the data to be refreshed is written into partition B of the eMMC chip as a refresh image file. After the data to be refreshed is successfully refreshed in partition B, the currently running program is switched to partition B of the eMMC chip.

[0121] After the Self Update process is executed and the data to be updated is successfully written to both partitions B and A of the eMMC chip, the multi-core SOC chip is restarted.

[0122] In the multi-core SOC refresh system of Example 8, the Self Update refresh process writes the data to be refreshed into a designated partition of the eMMC chip as a refresh image file. After the write operation is complete, an A / B partition switch is performed. The purpose of setting up A / B partitions is to ensure that refresh can continue even if the write operation fails, thereby improving the robustness of the refresh system. For example, if the currently running program is on the A-side partition of the eMMC chip, after a successful refresh, it switches to the B-side partition of the eMMC chip. Similarly, if the currently running program is on the B-side partition of the eMMC chip, after a successful refresh, it switches to the A-side partition of the eMMC chip. The MPU kernel's data writing interaction is directly completed by the SelfUpdate refresh process through the eMMC hardware driver. The eMMC chip's interface access speed is up to 400MB / s, which can quickly complete data interaction and greatly shorten the refresh image file loading time.

[0123] Example 9

[0124] Based on the multi-core SOC refresh system of Embodiment 7, the NorFlash chip includes MCU kernel application software A partition, MCU kernel application software B partition and MCU kernel default boot partition, wherein application software A partition and B partition are backup partitions for each other;

[0125] The default boot partition of the MCU kernel is used to record A / B partition information and the application software execution flag of the corresponding partition; the application software of the corresponding partition can only run when the application software execution flag is valid.

[0126] The NorFlash chip serves as an external storage unit for loading and refreshing data into the MCU core, and also as the initial storage medium for loading programs during the boot process.

[0127] Preferably, in step S1, if the first specified address is a refresh flag, the refresh complex driver reads the current running partition information of the MCU kernel from the MCU kernel default boot partition of the MCU kernel, determines the partition to be flashed in the NorFlash chip, and then proceeds to step S2.

[0128] In step S5, if the CRC value of the refresh image file written to the partition to be flashed in the NorFlash chip matches the CRC value it carries, the refresh complex driver first erases the A / B partition information and the application software execution flag information of the default boot partition of the MCU kernel (this flag is used to identify whether the application software is valid; the application software can only run when the flag is valid); then, it writes the current A / B partition information of the MCU kernel to the default boot partition of the MCU kernel, sets the flag information of the application software corresponding to the currently running partition to be valid (the currently running partition is partition A or partition B, used to indicate the current running partition before the next refresh), and clears the valid flag information of the application software in the other partition (partition B or partition A), completing the A / B partition switching, and then proceeds to step S6;

[0129] Preferably, in step S6, the complex driver is refreshed, and a fixed value is written into the specified address of the eMMC chip to notify the MPU kernel that the NorFlash chip refresh is complete.

[0130] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-core SOC control system, characterized in that, It includes a multi-core SOC chip, an eMMC chip, a NorFlash chip, and diagnostic equipment; The multi-core SOC chip is signal-connected to the diagnostic equipment, eMMC chip, and NorFlash chip, respectively. The multi-core SOC chip includes an MCU core and an MPU core; The diagnostic device establishes an Ethernet communication link with the multi-core SOC chip via Ethernet Diagnostic DoIP for data access and sends data to be refreshed to the multi-core SOC chip. The MPU core stores the data to be refreshed into the eMMC chip as a refresh image file using the eMMC direct drive method. The MCU core reads and stores the refresh image file from the eMMC chip into the NorFlash chip using the eMMC direct drive method.

2. The multi-core SOC control system according to claim 1, characterized in that, The MPU core stores the data to be refreshed into the eMMC chip using the eMMC direct drive method and then restarts the multi-core SOC chip. When the multi-core SOC chip restarts, the MCU core directly reads and stores the data to be refreshed from the eMMC chip into the NorFlash chip.

3. The multi-core SOC control system according to claim 2, characterized in that, The diagnostic device is a TBOX controller or an external diagnostic instrument; The TBOX controller is used to download and send the data to be refreshed to the multi-core SOC chip via Ethernet in OTA mode; The TBOX controller and the multi-core SOC chip establish a link via Ethernet diagnostic DoIP for data access. The external diagnostic instrument establishes an Ethernet communication link with the multi-core SOC chip via Ethernet Diagnostic DoIP for data access and sends new data to the multi-core SOC chip.

4. The multi-core SOC control system according to claim 3, characterized in that, The components of the MPU kernel include the DoIP server, the UDS diagnostic service module, and the Self Update refresh process; The DoIP server is used to establish a link with an external diagnostic instrument or TBOX controller, and at the same time to interact and respond with the UDS diagnostic service module to realize the transmission and refresh of Ethernet diagnostic data. The UDS diagnostic service module is used to implement diagnostic security authentication and diagnostic refresh process, and to complete the refresh data loading. When the diagnostic device connects to the multi-core SOC chip, the diagnostic device, acting as a DoIP client, initiates a route activation request to determine whether the route activation is successful. If the route activation is successful, the diagnostic device establishes a diagnostic link with the multi-core SOC chip and sends a diagnostic request to the DoIP server. The DoIP server's protocol stack processes diagnostic requests from diagnostic devices and interacts with the UDS diagnostic service module for diagnostic service data. The UDS diagnostic service module performs diagnostic security authentication on the diagnostic request. If the security authentication is successful, the DoIP server receives the data to be refreshed and activates the Self Update refresh process.

5. The multi-core SOC control system according to claim 4, characterized in that, The multi-core SOC control system also includes a Switch chip; The Switch chip is signal-connected to the TBOX controller, the external diagnostic instrument, and the multi-core SOC chip, respectively. The external switch chip is a Layer 2 network communication device for Ethernet link network transmission. As a switch for Ethernet communication, it realizes Layer 2 message routing for Ethernet communication. The external diagnostic instrument or TBOX controller establishes a link with the multi-core SOC chip through the Switch chip to access data. When the Self Update process is executed, the Switch data to be updated is first loaded into the NorFlash of the external Switch chip, and then the data to be updated is written into the designated storage partition of the eMMC chip.

6. The multi-core SOC control system according to claim 4, characterized in that, The MPU kernel also includes an eMMC driver; The eMMC driver is used to read and write access to the external eMMC chip; When the Self Update process is executed, the data to be updated is written into a designated storage partition of the eMMC chip as an update image file.

7. The multi-core SOC control system according to claim 6, characterized in that, When the Self Update process is executed, the data to be updated is written to the designated storage partition of the eMMC chip as an update image file, and a refresh flag is written to the first designated address of the eMMC chip. If the MPU kernel successfully completes writing the update image file to the designated storage partition of the eMMC chip, an image validity flag is written to the second designated address of the eMMC chip.

8. The multi-core SOC control system according to claim 7, characterized in that, The MCU core includes a complex refresh driver, a Flash driver, and an eMMC driver. The refresh complexity driver is used to complete the writing, loading, and integrity verification of the refresh image file; The refresh complex driver completes the writing of the refresh image file of the NorFlash chip through the Flash driver; The refresh complexity driver reads the refresh image file in the eMMC chip through the eMMC driver. After the multi-core SOC chip restarts and the MCU core successfully boots, the process of reading and storing the refresh image file from the eMMC chip to the NorFlash chip is as follows: S1. The refresh complex driver determines whether the first specified address of the eMMC chip is a refresh flag. If it is a refresh flag, proceed to step S2; otherwise, the refresh fails and proceed to step S50. S2. The refresh complex driver checks whether the second specified address in the eMMC is a valid image flag. If it is, proceed to step S3; otherwise, the refresh fails and proceed to step S50. S3. The refresh complex driver calculates the CRC value of the refresh image file in the specified storage partition in the eMMC and compares it with the CRC value carried at the end of the refresh image file. If the two match, the refresh image file is complete, and proceed to step S4; otherwise, the refresh fails, and proceed to step S50. S4. The refresh complex driver reads the refresh image file in the specified storage partition of the eMMC through the eMMC driver, and writes it into the partition to be refreshed of the NorFlash chip through the Flash driver; S5. The refresh complex driver calculates whether the CRC value of the refresh image file written to the partition to be refreshed in the NorFlash chip is consistent with its carried CRC value. If they are consistent, proceed to step S6; otherwise, the refresh fails and proceed to step S50. S6. The refresh complex driver clears the refresh flag in the first specified address of the eMMC chip, indicating that the MCU core data refresh was successful; S7. The complex driver is refreshed, and the SOC chip is restarted; S50. End.

9. The multi-core SOC control system according to claim 7, characterized in that, The eMMC chip includes partition A of MCU kernel application executable file, partition B of MCU kernel application executable file, partition A of MPU kernel uboot target file, partition B of MPU kernel uboot target file, partition A of MPU kernel image file, partition B of MPU kernel image file, partition A of MPU kernel rootfs image file, and partition B of MPU kernel rootfs image file. Partitions A and B are backup partitions for each other. When the Self Update process is executed, if the currently running program is in partition B of the eMMC chip, the data to be updated is written into partition A of the eMMC chip as a refresh image file. After the data to be updated is successfully refreshed in partition A, the currently running program is switched to partition A of the eMMC chip. If the currently running program is in partition A of the eMMC chip, the data to be updated is written into partition B of the eMMC chip as a refresh image file. After the data to be updated is successfully refreshed in partition B, the currently running program is switched to partition B of the eMMC chip. After the Self Update process is executed and the data to be updated is successfully written to both partitions B and A of the eMMC chip, the multi-core SOC chip is restarted.

10. The multi-core SOC control system according to claim 8, characterized in that, The NorFlash chip includes MCU kernel application software A partition, MCU kernel application software B partition and MCU kernel default boot partition, wherein application software A partition and B partition are backup partitions for each other; The default boot partition of the MCU kernel is used to record A / B partition information and the application software execution flags of the corresponding partitions; The application software in the corresponding partition can only run when the application software execution flag is valid.

11. The multi-core SOC control system according to claim 10, characterized in that, In step S1, if the first specified address is a refresh flag, the refresh complex driver reads the current running partition information of the MCU kernel from the MCU kernel default boot partition of the MCU kernel, determines the partition to be flashed in the NorFlash chip, and then proceeds to step S2. In step S5, if the CRC value of the refresh image file written to the partition to be flashed in the NorFlash chip is consistent with the CRC value it carries, the refresh complex driver first erases the A / B partition information of the default boot partition of the MCU kernel and the application software execution flag information. Then, the current A / B partition information of the MCU kernel is written to the default boot partition of the MCU kernel, the flag information of the application software corresponding to the currently running partition is set to valid, and the valid flag information of the application software of the other partition is cleared to complete the A / B partition switching, and then step S6 is performed.

12. The multi-core SOC control system according to claim 10, characterized in that, In step S6, the complex driver is refreshed, and a fixed value is written into the specified address of the eMMC chip to notify the MPU kernel that the NorFlash chip refresh is complete.

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