An FPGA program upgrading method

Abstract

The application provides an FPGA program upgrading method, and belongs to the field of FPGA electronics.The method comprises the following steps: writing upgraded code into the FPGA mainboard FLASH which is not installed on a product through a JTAG interface; connecting and communicating between the FPGA mainboard and an upper computer through a serial port; reading out the upgraded data in the FPGA mainboard FLASH and storing the data in a bin file; connecting and communicating between the upper computer and another FPGA target board to be upgraded through the serial port; and writing the bin file content into the FLASH chip of the target board to complete the FPGA program upgrading.The method is a hard read and write operation on the FLASH, and can avoid two problems, i.e., the synthesis process of the elf file and the sof, and the sorting of data in the FLASH chip, so that the time for studying the two processes is saved, the research and development cycle is greatly shortened, the time cost is saved, and the FPGA program upgrading is realized.

Description

Technical Field

[0001] This invention relates to the field of FPGA system upgrades, and more particularly to an FPGA program upgrade method. Background Technology

[0002] FPGA (Field-Programmable Gate Array) is a type of chip whose internal structure can be modified by programming with a hardware description language. This gives it immense flexibility, leading to its widespread application in image processing, satellite communication, autonomous driving, and network communication. After power-on, an FPGA automatically loads its program from the FLASH chip. The FPGA automatically reads and runs the program data stored in the FLASH chip starting from address 0x00. Upgrading the FPGA program essentially involves updating the program data stored in the FLASH chip starting from address 0x00.

[0003] A common method for FPGA program upgrades involves using the JTAG interface and software to write program data into the FLASH chip. The FPGA then loads the new program data from the FLASH chip and runs it. This method is the simplest, but it's not very user-friendly for field upgrades and maintenance. It requires disassembling the product and on-site personnel to be familiar with the software and programmer; otherwise, the upgrade task cannot be completed. This method is generally used in research and development and production.

[0004] For remote serial port upgrades of Altera FPGAs, it is necessary to merge the .sof file generated by Quartus II and the .elf file generated by NIOS II into a new RPD file, which is then transferred to the FLASH chip using host computer software. This method requires the content structure of the synthesized RPD file to be written into the FLASH chip as required, making development quite difficult. To avoid spending time analyzing the RPD file content and reduce development difficulty, this invention proposes an FPGA program upgrade method. Summary of the Invention

[0005] To overcome the inconvenience caused by JTAG interface upgrades and reduce the development difficulty of serial port upgrades, this invention provides an FPGA program upgrade method.

[0006] This invention is implemented using the following method: An FPGA program upgrade method includes the following steps: S1: JTAG programming process, using the NIOS II Flash Programmer tool, merges the elf file and sof file and then programs them into the FLASH of the FPGA motherboard that is not installed on the product through the JTAG interface; S2: Data transfer, i.e. FLASH reading process. The host computer with upgrade software installed reads the new version of the program written to the FLASH memory chip of the FPGA board from address 0x00 and stores these upgrade data in a bin file. S3: Serial transmission. Using a host computer with upgrade software installed, this bin file is transmitted via serial port to the SDRAM on another FPGA target board to be upgraded for storage. S4: Target board upgrade. After verifying that the upgrade data is correct, the target board moves the upgrade data from SDRAM to its own FLASH storage chip. After the writing is completed, power off and restart the system to complete the program upgrade of the FPGA subsystem.

[0007] Furthermore, in step S2, the data transfer includes a control instruction parsing module, a handshake module, a FLASH chip reading module, a data encoding module, and a data sending module; The control instruction parsing module is used to receive control instructions sent by the host computer through the serial port, and to parse and read the initial address Addr of the FLASH chip and the upgrade data size FileSize in the FLASH chip from the control instructions; The handshake module is used for handshake between the FPGA and the host computer before communication, ensuring that upgrade data can be transmitted correctly; The FLASH chip reading module is used to read upgrade data from the initial address Addr, with a total upgrade data size of FileSize. At the same time, the upgrade data is transmitted to the data encoding module for encoding. The data encoding module is used to encode the read FLASH data, and the encoded upgrade data is then transmitted to the data sending module. The data sending module is used to communicate with the host computer via a serial port and send the encoded upgrade data to the host computer.

[0008] Furthermore, in step S3, the serial port transmission includes a control command parsing module, a handshake module, a data receiving module, a data decoding module, and an SDRAM read / write module; The control command module is used to parse the control commands sent by the host computer, enabling the FPGA to enter the data receiving and upgrade mode. The handshake module is used for handshake between the FPGA and the host computer before communication, ensuring that upgrade data can be transmitted correctly; The data receiving module is used to receive upgrade data transmitted from the host computer; The data decoding module is used to parse the upgrade data according to the protocol and verify whether the upgrade data is correct. If the upgrade data is verified to be correct, it is passed to the SDRAM write module. If the upgrade data is verified to be incorrect, it waits until the correct upgrade data is received and starts timing. If the timing exceeds the set value, it exits the upgrade mode. The read / write SDRAM module is used to allocate a space in the SDRAM and write the upgrade data into the SDRAM for storage. After all the upgrade data has been transmitted through the serial port, the upgrade data is read from the SDRAM and transmitted to the write FLASH module.

[0009] Further, in step S4, the write FLASH module is used to erase the FLASH storage space, receive the upgrade data transmitted from the read / write SDRAM module and write it into the FLASH chip, and the initial address of the FLASH chip is 0x00.

[0010] The beneficial effects of this invention are as follows: 1. This invention reduces the development difficulty of FPGA remote upgrade by combining JTAG interface upgrade and serial port upgrade. By using hard read and write to the FLASH chip, it avoids the need to merge the .sof file generated by Quartus II and the .elf file generated by NIOS II.

[0011] 2. The code is programmed onto an FPGA board not assembled on the product via the JTAG interface, saving the new program in the FLASH memory. Then, upgrade data is read from address 0x00 of the FLASH memory via serial port and saved as a BIN file. This BIN file is then written to the FLASH chip of the target FPGA board to be upgraded via serial port. When the system is powered off and restarted, the FPGA will automatically load the new program from address 0x00 of the FLASH chip and execute it. Program upgrades on the target FPGA board can be achieved without disassembling the device. Furthermore, by simply changing the read / write addresses of the FLASH memory, system data stored in the FLASH memory can be modified, enabling the copying and backup of user data, providing flexible functional expansion. Attached Figure Description

[0012] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart of the FPGA program upgrade method of the present invention.

[0014] Figure 2 System framework diagram in an embodiment of the present invention.

[0015] Figure 3 This is a flowchart illustrating the process of reading upgrade data by the PC host computer in an embodiment of the present invention.

[0016] Figure 4 This is a flowchart illustrating the FPGA data upload and upgrade process in an embodiment of the present invention.

[0017] Figure 5 This is a flowchart illustrating the data transmission process of the PC host computer in an embodiment of the present invention.

[0018] Figure 6 This is a flowchart illustrating the FPGA receiving upgrade data in an embodiment of the present invention.

[0019] Figure 7 This invention provides an upgraded data transmission protocol for embodiments of the present invention. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0021] like Figures 1 to 6 As shown, an FPGA program upgrade method includes the following steps: Step S1: JTAG programming process. Using the NIOS II Flash Programmer tool, the ELF file and the SOF file are merged and then programmed into the FLASH of the FPGA motherboard that is not installed on the product through the JTAG interface. Step S2: Data transfer, i.e., the FLASH reading process, the host computer with the upgrade software installed reads the new version of the program written from the 0x00 address of the FLASH storage chip of the FPGA motherboard that is not installed on the product, and stores the upgrade data in a bin file; Step S3: Serial transmission. Using a host computer with the upgrade software installed, this bin file is transmitted via serial port to the SDRAM on another FPGA target board to be upgraded for storage. Step S4: Target board upgrade. After verifying that the upgrade data is correct, the target board moves the upgrade data from SDRAM to its own FLASH storage chip. After the writing is completed, power off and restart the system to complete the program upgrade of the FPGA subsystem.

[0022] Specifically, step S1 includes the following sub-steps: Step S101: Before JTAG programming, the installation of NIOS II and Quartus II software is also included; Step S102: JTAG programming successful, proceed to step S2.

[0023] Specifically, step S2 includes the following sub-steps: Step S201: The FPGA receives the control command from the host computer and enters the upgrade data sending mode; Step S202: Parse two parameters from the control instructions, namely the initial address Addr for reading FLASH chip data and the size FileSize for reading FLASH data; Step S203: Perform a handshake with the host computer according to the protocol. If the handshake is successful, enter the upgrade data upload mode. Step S204: Read 32 bytes of data starting from address Addr in the FLASH chip; Step S205: Pack the frame header, frame number, FLASH data, and checksum into a 42-byte data packet according to the protocol; Step S206: Send the packaged 42-byte data packet; Step S207: The host computer receives the 42-byte data packet sent by the FPGA, parses the upgrade data according to the protocol, and writes it into the bin file; Step S208: Count the sent data packets, i.e., increment the Frm_Num variable by 1; Step S209: Receive the data frame fed back by the host computer. If the host computer successfully receives the upgrade data, proceed to step S210; otherwise, proceed to step S206. Step S210: Determine whether the upgraded data sent has reached the total data volume FileSize. If it has, exit the data sending mode; otherwise, proceed to step S211. Step S211: The address Addr of the FLASH chip data is offset by 32, proceed to step S204.

[0024] Specifically, step S207 includes the following sub-steps: Step S2071: The host computer checks whether the received upgrade data is correct based on CRC32 cyclic redundancy check. Step S2073: The host computer feeds back the verification result to the FPGA. If the upgrade data verification is correct, proceed to S211; if the upgrade data verification is incorrect, proceed to step S2074. Step S2074: The host computer determines whether the amount of received data has reached FileSize. If so, all received upgrade data is written to the bin file for storage; otherwise, proceed to step S211.

[0025] Specifically, step S3 includes the following sub-steps: Step S301: Connect the host computer to the product with the FPGA target board to be upgraded installed using an RS422 serial cable; Step S302: The host computer sends a transparent transmission command, causing the interface adapter board in the product to enter the data transparent transmission mode; Step S303: The host computer reads the bin file and stores it in the buffer, while simultaneously parsing the size of the bin file and the initial address of the FLASH chip for storing data; Step S304: The host computer sends a write data command, and the FPGA target board to be upgraded enters the receive upgrade data mode after receiving the command; Step S305: The host computer and the target FPGA board to be upgraded perform a handshake according to the protocol. If the handshake is successful, proceed to step S306; otherwise, perform the handshake again. Step S306: The host computer sends an upgrade data packet in a 42-byte data format; Step S307: The host computer receives the data fed back by the FPGA target board to be upgraded and determines whether the data has been successfully received by the FPGA target board to be upgraded. If the data is successfully received, proceed to step S308; otherwise, proceed to step S306. Step S308: The FPGA target board to be upgraded parses the data according to the protocol and caches the data in SDRAM. It counts the received data packets, i.e., increments the Frm_Num variable by 1. Step S309: The FPGA target board to be upgraded determines whether the received data is the last frame. If it is, proceed to step S4; otherwise, request the next frame of data from the host computer and proceed to step SS306. Specifically, step S4 includes the following sub-steps: Step S401: Erase a space of size FileSize from address 0x00 of FLASH to store upgrade data, and wait for the erasure to complete before proceeding to S402; Step S402: Read the upgrade data from the SDRAM and write the upgrade data of size FileSize sequentially starting from address 0x00 of the FLASH chip. After the writing is complete, power off and restart the system to complete the program upgrade of the FPGA subsystem.

[0026] In summary, this invention reduces the development difficulty of remote FPGA upgrades by combining JTAG interface upgrades and serial port upgrades. By using hard read / write to the FLASH chip, it avoids the need to merge the .sof file generated by Quartus II and the .elf file generated by NIOS II. The code is burned to an FPGA board not assembled on the product via the JTAG interface, allowing the new program to be stored in the FLASH. Then, FLASH data is read from address 0x00 via the serial port and saved as a bin file. This bin file is then written to the FLASH chip of the target FPGA board to be upgraded via the serial port. When the system is powered off and restarted, the FPGA automatically loads the new program from address 0x00 of the FLASH chip and executes it, achieving program upgrades on the target FPGA board without disassembling the device. Furthermore, only the read / write address of the FLASH needs to be changed to modify the system data stored in the FLASH, allowing for flexible functional expansion. The data transmission of this invention uses a request-based feedback mechanism, ensuring the correct transmission of the current frame before requesting the transmission of the next frame, thus improving the upgrade success rate.

[0027] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. An FPGA program upgrade method, characterized in that, Includes the following steps: S1: JTAG programming process, using the NIOS II Flash Programmer tool, merges the elf file and sof file and then programs them into the FLASH of the FPGA motherboard that is not installed on the product through the JTAG interface; S2: Data transfer, i.e., the FLASH reading process, uses a host computer with the upgrade software installed to obtain the new program data from the 0x00 address of the FLASH chip on the FPGA motherboard and save it as a bin file; S3: Serial transmission. Using the host computer with the upgrade software installed, this bin file is transmitted via serial port to the SDRAM on another FPGA target board to be upgraded. S4: Target board upgrade. After verifying that the upgrade data is correct, the target board moves the upgrade data from SDRAM to its own FLASH storage chip. After the writing is completed, power off and restart the system to complete the program upgrade of the FPGA subsystem.

2. The FPGA program upgrade method according to claim 1, characterized in that: Step S2 includes a control instruction parsing module, a handshake module, a FLASH chip reading module, a data encoding module, and a data sending module. The control instruction parsing module is used to receive control instructions sent by the host computer through the serial port, and to parse and read the initial address Addr of the FLASH chip and the upgrade data size FileSize in the FLASH chip from the control instructions; The handshake module is used for handshake between the FPGA and the host computer before communication, ensuring that upgrade data can be transmitted correctly; The FLASH chip reading module is used to read upgrade data from the initial address Addr, with a total upgrade data size of FileSize. At the same time, the upgrade data is transmitted to the data encoding module for encoding. The data encoding module is used to encode the read FLASH data, and the encoded data is then transmitted to the data sending module. The data sending module is used to communicate with the host computer via a serial port and send the encoded upgrade data to the host computer.

3. The FPGA program upgrade method according to claim 1, characterized in that: Step S3 includes a control instruction parsing module, a handshake module, a data receiving module, a data decoding module, and an SDRAM read / write module; The control command module is used to parse the control commands sent by the host computer, enabling the FPGA to enter the data receiving and upgrade mode. The handshake module is used for handshake between the FPGA and the host computer before communication, ensuring that upgrade data can be transmitted correctly; The data receiving module is used to receive upgrade data transmitted from the host computer; The data decoding module is used to parse the upgrade data according to the protocol and verify whether the data is correct. If the upgrade data is verified to be correct, it is passed to the SDRAM writing module. If the upgrade data is verified to be incorrect, it waits until the correct upgrade data is received and starts timing. If the timing exceeds the set value, it exits the upgrade mode. The read / write SDRAM module is used to allocate a space in the SDRAM and write the upgrade data into the SDRAM for storage. After all the upgrade data has been transmitted through the serial port, the upgrade data is read from the SDRAM and transmitted to the write FLASH module.

4. The FPGA program upgrade method according to claim 1, characterized in that: Step S4 includes writing the FLASH module; The write FLASH module is used to erase the FLASH storage space, receive upgrade data transmitted from the read / write SDRAM module and write it into the FLASH chip. The initial address for writing to the FLASH chip is 0x00.

Images