Graphical programming logic diagram topology generation method and apparatus for dcs

Abstract

The embodiment of the specification provides a graphical programming logic diagram topology generation method and device for a DCS, comprising: acquiring a graphical programming logic diagram containing graphical blocks and connection lines; mapping the graphical blocks into nodes of a directed acyclic graph and mapping the connection lines into directed edges, the direction of the directed edges being consistent with the direction of data flow or control flow; traversing all nodes, and counting the in-degree of each node; initializing a queue, and adding all nodes with an in-degree of zero into the queue; performing the following steps in a loop until the queue is empty: taking a node from the queue and adding it into an execution sequence, traversing all downstream nodes of the node and reducing the in-degree of each downstream node by one, and adding the downstream nodes with an in-degree of zero after the reduction into the queue; and outputting the execution sequence as the execution order of the graphical blocks. The stack memory overhead of recursive calls is avoided, the execution order calculation efficiency of a large-scale logic diagram is improved, dynamic local updating of the logic diagram can be supported, and the uniqueness and stability of the execution order are ensured.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of industrial automation control technology, and in particular to a method for generating graphical programming logic diagram topologies for DCS. Background Technology

[0002] In the field of industrial automation control, distributed control systems (DCS) widely adopt graphical programming, allowing engineers to build control logic by dragging and dropping graphical blocks and connecting them to represent data flow or control flow, without having to write complex text code. The core of graphical programming lies in accurately converting the graphical logic diagram into a linearly executable sequence of instructions, where the execution order of the graphical blocks directly affects the correctness and reliability of the control logic.

[0003] Currently, the industry commonly uses the Depth-First Search (DFS) algorithm for topological sorting to determine the execution order of graphical blocks. The specific steps are as follows: abstract the graphical logic graph into a directed graph, where nodes represent graphical blocks and directed edges represent dependencies; recursively traverse all reachable nodes starting from any node, recording the nodes that have been traversed, forming a reverse execution sequence; repeat the above process for untraversed nodes, ultimately obtaining the complete execution order. This solution can basically meet the requirements when processing simple logic graphs.

[0004] However, existing topological sorting schemes based on DFS have the following technical drawbacks: First, the DFS algorithm uses a recursive approach. When the number of graph blocks exceeds a certain scale, the computation speed will decrease significantly due to excessive stack memory usage, and the context switching cost of recursive calls will increase sharply with the scale. Second, when the graphical logic graph is dynamically modified (such as adding or deleting connections), DFS needs to traverse the entire graph again and cannot update the execution order locally, resulting in poor adaptability and slow response. Third, for logic graphs with multiple independent branches, DFS may cause the execution order to be unstable due to different traversal starting points, increasing the difficulty of debugging.

[0005] Therefore, there is an urgent need for a topology generation method that can efficiently and stably calculate the execution order of graphical blocks and adapt to dynamic adjustments of the logic graph. Summary of the Invention

[0006] In view of this, embodiments of this specification provide a method for generating graphical programming logic diagram topologies for DCS. One or more embodiments of this specification also relate to a graphical programming logic diagram topology generation apparatus for DCS, a computing device, a computer-readable storage medium, and a computer program, to address the technical deficiencies existing in the prior art.

[0007] According to a first aspect of the embodiments of this specification, a method for generating a graphical programming logic diagram topology for a DCS is provided, comprising: Obtain a graphical programming logic diagram, which includes graphical blocks and connections used to represent data flow or control flow between the graphical blocks; The logic graph is converted into a directed acyclic graph (DAG), in which graphical blocks are mapped to nodes of the DAG, and connections are mapped to directed edges of the DAG, with the direction of the directed edges consistent with the direction of the data flow or control flow. Traverse all nodes in the directed acyclic graph and count the in-degree of each node, which is the number of directed edges pointing to the node. Initialize a queue and add nodes with an in-degree of zero to the queue; Repeat the following steps until the queue is empty: Take a node from the queue and add it to the execution sequence; traverse all downstream nodes of the taken node and decrement the in-degree of each downstream node by one; add the downstream nodes whose in-degree becomes zero after decrementing by one to the queue. The output execution sequence serves as the execution order of the graphics blocks.

[0008] In one possible implementation, after calculating the in-degree of each node, the method further includes: detecting whether there is a cycle in the directed acyclic graph using a depth-first search algorithm; if a cycle exists, generating feedback information to prompt the user to modify the logical graph.

[0009] One possible implementation also includes a dynamic update step: monitoring adjustments to the graphical programming logic graph, incrementally updating the directed acyclic graph and in-degree when the logic graph is adjusted, and regenerating the execution sequence based on the updated directed acyclic graph and in-degree.

[0010] In one possible implementation, incremental updates include: recording the parts of the logical graph that have changed, including newly added nodes and edges, deleted nodes and edges, or edges whose directions have been modified; and performing addition, deletion, or modification operations on the directed acyclic graph based on the changed parts, and adjusting the in-degree of the affected nodes.

[0011] In one possible implementation, regenerating the execution sequence includes: using previously generated execution sequence information, recalculating the execution order only for the nodes affected by the adjustment.

[0012] In one possible implementation, converting a logical graph into a directed acyclic graph includes: establishing a data structure containing all nodes, all directed edges, and the mapping from nodes to graph blocks; wherein, a node contains a unique identifier of the associated graph block, and a directed edge contains a start node and an end node, with the start node corresponding to the upstream graph block and the end node corresponding to the downstream graph block.

[0013] In one possible implementation, the order of the graphic blocks in the execution sequence satisfies the following: for any directed edge, the graphic block corresponding to the starting node of the directed edge is arranged before the graphic block corresponding to the ending node of the directed edge.

[0014] According to a second aspect of the embodiments of this specification, a graphical programming logic diagram topology generation apparatus for a DCS is provided, comprising: The data acquisition module is configured to acquire a graphical programming logic diagram, which includes graphical blocks and connections used to represent data flow or control flow between the graphical blocks. The data conversion module is configured to convert the logic graph into a directed acyclic graph, wherein the graph blocks are mapped to nodes of the directed acyclic graph, and the connections are mapped to directed edges of the directed acyclic graph, with the direction of the directed edges being consistent with the direction of the data flow or control flow. The in-degree calculation module is configured to traverse all nodes in the directed acyclic graph and count the in-degree of each node, which is the number of directed edges pointing to the node. The queue generation module is configured to initialize a queue and add nodes with an in-degree of zero to the queue; The queue loop module is configured to repeatedly execute the following steps until the queue is empty: remove a node from the queue and add the removed node to the execution sequence; traverse all downstream nodes of the removed node and decrement the in-degree of each downstream node by one; add the downstream node whose in-degree becomes zero after decrementing by one to the queue. The data output module is configured to output the execution sequence as the execution order of the graphics blocks.

[0015] According to a third aspect of the embodiments of this specification, a computing device is provided, comprising: Memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, they implement the steps of the graphical programming logic diagram topology generation method for DCS described above.

[0016] According to a fourth aspect of the embodiments of this specification, a computer-readable storage medium is provided that stores computer-executable instructions, which, when executed by a processor, implement the steps of the graphical programming logic diagram topology generation method for DCS described above.

[0017] According to a fifth aspect of the embodiments of this specification, a computer program is provided, wherein when the computer program is executed in a computer, it causes the computer to perform the steps of the graphical programming logic diagram topology generation method for DCS described above.

[0018] This specification provides a method and apparatus for generating a graphical programming logic graph topology for DCS, comprising: acquiring a graphical programming logic graph containing graphical blocks and connections; mapping graphical blocks to nodes of a directed acyclic graph and connecting lines to directed edges, wherein the direction of the directed edges is consistent with the direction of data flow or control flow; traversing all nodes and counting the in-degree of each node; initializing a queue and adding all nodes with an in-degree of zero to the queue; repeatedly executing the following steps until the queue is empty: retrieving a node from the queue and adding it to the execution sequence; traversing all downstream nodes of the node and decrementing the in-degree of each downstream node by one; adding downstream nodes whose in-degree becomes zero after decrementing one to the queue; and outputting the execution sequence as the execution order of the graphical blocks. This avoids the stack memory overhead of recursive calls, improves the efficiency of execution order calculation for large-scale logic graphs, supports dynamic local updates of the logic graph, and ensures the uniqueness and stability of the execution order. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating a graphical programming logic diagram topology generation method for DCS provided in one embodiment of this specification; Figure 2 This is a schematic diagram of a graphical programming logic diagram topology generation method for DCS provided in one embodiment of this specification; Figure 3 This is a schematic diagram of the Kahn algorithm for a graphical programming logic diagram topology generation method for DCS provided in one embodiment of this specification; Figure 4 This is a schematic diagram illustrating the dynamic update mechanism of a graphical programming logic diagram topology generation method for DCS provided in one embodiment of this specification. Figure 5 This is a schematic diagram of DCS control logic provided in one embodiment of the graphical programming logic diagram topology generation method for DCS. Figure 6 This is a schematic diagram of a graphical programming logic diagram topology generation device for DCS provided in one embodiment of this specification; Figure 7 This is a structural block diagram of a computing device provided in one embodiment of this specification. Detailed Implementation

[0020] Many specific details are set forth in the following description to provide a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this specification. Therefore, this specification is not limited to the specific implementations disclosed below.

[0021] The terminology used in one or more embodiments of this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of this specification. The singular forms “a” and “the” as used in one or more embodiments of this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0022] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this specification, and similarly, second may also be referred to as first. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0023] This specification provides a graphical programming logic diagram topology generation method for DCS, and also relates to a graphical programming logic diagram topology generation apparatus for DCS, a computing device, and a computer-readable storage medium, which will be described in detail in the following embodiments.

[0024] See Figure 1 , Figure 1 A flowchart of a graphical programming logic diagram topology generation method for DCS provided according to an embodiment of this specification is shown, specifically including the following steps.

[0025] Step 101: Obtain the graphical programming logic diagram, which includes graphical blocks and connections used to represent data flow or control flow between graphical blocks; Step 102: Convert the logic graph into a directed acyclic graph, where graphical blocks are mapped to nodes of the directed acyclic graph, and connections are mapped to directed edges of the directed acyclic graph. The direction of the directed edges is consistent with the direction of the data flow or control flow. Step 103: Traverse all nodes in the directed acyclic graph and count the in-degree of each node; Step 104: Initialize a queue and add nodes with an in-degree of zero to the queue; Step 105: Repeat the following steps until the queue is empty: Take a node from the queue and add the taken node to the execution sequence; Traverse all downstream nodes of the taken node and decrement the in-degree of each downstream node by one; Add the downstream nodes whose in-degree becomes zero after decrementing by one to the queue. Step 106: Output the execution sequence as the execution order of the graphics blocks.

[0026] In this context, a graphical programming logic diagram refers to a control logic diagram created by a user in a DCS (Distributed Control System) graphical programming environment by dragging and dropping graphical blocks and drawing connections. For example, a user selects graphical elements such as addition blocks, comparison blocks, and input / output blocks from the toolbox, places them on the canvas, and then uses the mouse to connect the input and output ports of each block, thereby constructing a complete control algorithm.

[0027] Graphical blocks can refer to the basic functional units in DCS graphical programming, such as logic operation blocks, arithmetic operation blocks, timer blocks, counter blocks, input blocks, and output blocks. Each graphical block has a unique identifier (ID) and type attribute.

[0028] A connection can refer to a line segment that connects the ports of two graphics blocks, used to indicate the direction of data flow or control flow, typically connecting the output port of the upstream block to the input port of the downstream block.

[0029] A Directed Acyclic Graph (DAG) can refer to a graph structure consisting of nodes and directed edges, in which there are no directed cycles, meaning it is impossible to start from a node and return to that node by following a directed edge. In the DCS graphical programming scenario, each graphical block is mapped to a node, and each connection line is mapped to a directed edge, with the edge direction consistent with the data flow direction.

[0030] In-degree refers to the number of directed edges pointing to a given node in a directed graph. For a given node in a DAG, the in-degree is equal to the number of predecessor nodes that depend on the computation result of that node. For example, if node B has two directed edges from nodes A and C, then the in-degree of node B is 2, meaning that node B needs to wait for the computation results of nodes A and C before it can execute.

[0031] A queue can refer to a first-in, first-out (FIFO) data structure used to temporarily store nodes with an in-degree of zero that are waiting to be scheduled. In this method, the queue is initialized to store all nodes with an initial in-degree of zero, and new nodes are continuously added as processing progresses.

[0032] An execution sequence can refer to a list of graphical blocks arranged according to their dependencies, in which all upstream graphical blocks that each graphical block depends on have been executed when it is executed.

[0033] The present invention will be further described below through a detailed embodiment: This embodiment is applied to the DCS control system of a chemical plant. Engineers needed to design a temperature control logic. The logic diagram includes the following graphical blocks: a temperature sensor input block (denoted as block T), a setpoint input block (denoted as block S), a comparison operation block (denoted as block C, used to compare the temperature value with the setpoint), a proportional-integral-derivative control block (denoted as block P, dependent on the comparison result), and an actuator output block (denoted as block A, dependent on the control block output). In addition, there is an alarm judgment block (denoted as block Alarm, dependent on both the temperature sensor input block and the comparison operation block).

[0034] Follow the steps outlined above: First, the graphical programming logic diagram described above is obtained. The system reads all the graphical blocks placed by the user and their attributes, as well as all the connection relationships, through the interface of the graphical programming environment. For example, the connections include an input from block T to block C, another input from block S to block C, an output from block C to block P, an output from block P to block A, an input from block T to block Alarm, and another input from block C to block Alarm.

[0035] Next, the logical graph is converted into a directed acyclic graph (DAG). The system creates a DAG object, generating a corresponding node for each graphical block, with the node recording the ID of the graphical block it is associated with. For each connection, a directed edge is created, with the starting point of the edge being the node corresponding to the upstream graphical block and the ending point being the node corresponding to the downstream graphical block. This constructs a graph structure containing five nodes (T, S, C, P, A, Alarm) and seven directed edges.

[0036] Then, traverse all nodes in the directed acyclic graph and count the in-degree of each node. The system initializes the in-degree of all nodes to zero, and then traverses each directed edge. Whenever an edge pointing from node X to node Y is encountered, the in-degree of node Y is incremented by one. The calculated in-degrees are: node T has an in-degree of 0 (no edge points to T), node S has an in-degree of 0, node C has an in-degree of 2 (from T and S), node P has an in-degree of 1 (from C), node A has an in-degree of 1 (from P), and node Alarm has an in-degree of 2 (from T and C).

[0037] Next, initialize an empty queue. Add all nodes with an in-degree of zero to the queue, that is, add nodes T and S to the queue.

[0038] Then repeat the following steps until the queue is empty: In the first loop, node T is removed from the queue and added to the execution sequence. All downstream nodes of node T (i.e., nodes C and Alarm) are traversed, reducing the in-degree of node C from 2 to 1, and the in-degree of node Alarm from 2 to 1. At this point, the in-degrees of both nodes C and Alarm are not zero, so they are not added to the queue. The queue now contains node S.

[0039] In the second loop, node S is removed from the queue and added to the execution sequence. The downstream nodes of node S (only node C) are traversed, and the in-degree of node C is reduced from 1 to 0. At this point, the in-degree of node C becomes zero, and node C is added to the queue. The queue now contains one node C.

[0040] In the third iteration, node C is removed from the queue and added to the execution sequence. The downstream nodes of node C (node ​​P and node Alarm) are traversed, reducing the in-degree of node P from 1 to 0, and the in-degree of node Alarm from 1 to 0. Once the in-degrees of both node P and node Alarm are zero, they are added to the queue. The queue now contains node P and node Alarm.

[0041] In the fourth iteration, node P is retrieved and added to the execution sequence. Its downstream node (node ​​A) is traversed, the in-degree of node A is reduced from 1 to 0, and node A is added to the queue.

[0042] In the fifth loop, node Alarm is taken out and added to the execution sequence. It has no downstream nodes, and node A remains in the queue.

[0043] In the sixth iteration, node A is retrieved and added to the execution sequence, leaving the queue empty.

[0044] The final output execution sequence is: T → S → C → P → Alarm → A.

[0045] This execution sequence ensures that when each graphics block is executed, all upstream blocks it depends on have completed their calculations. For example, the alarm decision block Alarm will only execute after both T and C have finished, thus obtaining the correct alarm result.

[0046] The beneficial effects of this embodiment include: by converting the graphical logic graph into a directed acyclic graph and adopting a topological sorting method based on an in-degree queue, the stack memory overhead caused by recursive calls is avoided, and the computation time is significantly shortened in large-scale logic graphs (e.g., containing hundreds of graphical blocks); the method does not depend on the traversal starting point, and regardless of the enqueue order of nodes in the initial queue, the final generated execution sequence strictly satisfies the data dependency relationship, ensuring the uniqueness and stability of the execution order and reducing the difficulty of debugging.

[0047] In one possible implementation, after calculating the in-degree of each node, the method further includes: detecting whether there is a cycle in the directed acyclic graph using a depth-first search algorithm; if a cycle exists, generating feedback information to prompt the user to modify the logical graph.

[0048] Depth-first search (DFS) can refer to an algorithm used to traverse or search graph structures. Starting from a starting node, it visits nodes as deeply as possible along a path, backtracking to the previous node when it cannot proceed further, and continuing to explore other branches. In this method, DFS is used to detect whether a cycle (i.e., a loop) exists in a directed graph.

[0049] A loop in a directed graph refers to a path that starts from a node and follows a directed edge back to that node. In DCS graphical programming, a loop indicates a circular dependency, such as block A depending on the output of block B, and block B depending on the output of block A. In this case, the execution order of any block cannot be determined, which is a logical error.

[0050] Feedback information can refer to prompts displayed through the user interface, such as pop-up dialog boxes or highlighted connections and graphic blocks that form loops, informing the user of the existence of circular dependencies and suggesting modifications to the connection relationships.

[0051] The present invention will be further described below through a detailed embodiment, which follows the foregoing graph structure modeling steps: After constructing the directed acyclic graph and calculating the in-degree of all nodes, the system calls a loop closure detection function. This function uses a depth-first search algorithm to traverse the entire graph. Specifically, the system maintains three states for each node: unvisited, being visited, and visited. The algorithm recursively traverses its downstream nodes starting from any unvisited node.

[0052] Suppose that when designing the logic diagram, the user mistakenly connected an output of output block A back to operation block B. The output of operation block B then affects the input of output block A through other paths, forming a loop. When the depth-first search reaches a node in this loop, the algorithm will detect an edge pointing to a node in the "being visited" state. This indicates that a backward edge has been found, meaning a loop exists.

[0053] Once a loop is detected, the system immediately stops traversing and generates a feedback message. This feedback message is presented to the engineer through the user interface of the DCS graphical programming environment, for example, by displaying a warning dialog box that reads "Circular dependency detected. Please check the connections between the following graphical blocks." The connections and graphical blocks that constitute the loop are highlighted in red, and the words "Circular dependency" are marked next to the connections.

[0054] After seeing the feedback, engineers can modify the logic diagram, such as disconnecting erroneous backlinks or adding a delay block to break circular dependencies. Once modified, the system re-executes the graph structure modeling and detection process until no loops remain in the graph, before proceeding with subsequent topology sorting steps.

[0055] The beneficial effects of this embodiment include: by introducing a loop detection mechanism before the execution order calculation, it is possible to detect circular dependency errors in the user's design in a timely manner and guide the user to correct them with intuitive feedback information, thereby avoiding the problem that the execution order cannot be calculated or that the logic will be disordered during runtime due to the erroneous logic diagram, and improving the reliability and user experience of DCS graphical programming.

[0056] One possible implementation also includes a dynamic update step: monitoring adjustments to the graphical programming logic graph, incrementally updating the directed acyclic graph and in-degree when the logic graph is adjusted, and regenerating the execution sequence based on the updated directed acyclic graph and in-degree.

[0057] The dynamic update step refers to the function that, when a user modifies the graphical logic diagram in real time (e.g., adding or deleting connections or graphical blocks, or changing the direction of connections), the system does not need to reprocess the entire graph structure, but only updates the changed parts and recalculates the execution order.

[0058] Monitoring adjustments to the graphical programming logic diagram can refer to the system capturing user operations on the graphical programming interface through an event listening mechanism, such as connection addition events, connection deletion events, graphic block addition events, graphic block deletion events, connection direction modification events, etc.

[0059] Incremental updates refer to making local modifications to the directed acyclic graph and its in-degree data only for the parts that have changed, rather than rebuilding the entire graph structure and recalculating the in-degree of all nodes. For example, when adding a new connection, you only need to add a directed edge and increase the in-degree of the downstream nodes, without traversing all nodes.

[0060] The present invention will be further described below through a detailed embodiment, which follows the application scenario after the aforementioned execution sequence generation: Assume that a temperature control logic diagram containing ten graphical blocks already exists in the current DCS graphical programming environment, and the system has generated a complete execution sequence using the aforementioned method. At this point, the engineer discovers the need to add a filter block to smooth the temperature sensor input data. The engineer performs the following operations on the graphical interface: dragging a new filter block between the temperature sensor input block and the comparison operation block, deleting the existing connection from the temperature sensor block to the comparison operation block, and then adding connections from the temperature sensor block to the filter block, as well as connections from the filter block to the comparison operation block.

[0061] The system detected user adjustments to the logic diagram. Specifically, the system's event listener captured the following changes: a new graphic block (filter block, denoted as node F) was added, an existing connection (from node T to node C) was deleted, and two new connections (from node T to node F, and from node F to node C) were added.

[0062] The system performs incremental updates as follows: First, the directed acyclic graph (DAG) is modified by adding node F and directed edges T→F and F→C, and deleting directed edge T→C. Then, the in-degree is incrementally updated: For the deleted edge T→C, the in-degree of node C is decreased by one (assuming node C's original in-degree was 2, it is decreased to 1); for the newly added edge T→F, the in-degree of node F is increased by one (node ​​F's in-degree becomes 1); for the newly added edge F→C, the in-degree of node C is increased again (node ​​C's in-degree changes from 1 to 2). The in-degree of node T remains unchanged (still 0). Other affected nodes, such as other downstream nodes that originally depended on C, do not require additional adjustment because C's in-degree changes but its final value remains the same as before the modification.

[0063] After completing the incremental update, the system uses the previously generated execution sequence as a basis, recalculating only the execution order of the affected nodes and their downstream nodes. Since only nodes T, F, and C and their downstream nodes change, the system can re-execute the queue-based topology sorting only for these nodes, while keeping the order of other unaffected nodes unchanged. This results in a new execution sequence where the filter block F is executed after the temperature sensor block T and before the comparison operation block C.

[0064] The entire process does not require retracing all ten nodes, and the response time is significantly shorter than that of completely rebuilding the entire graph structure.

[0065] The beneficial effects of this embodiment include: through the dynamic update processing mechanism, when the graphical logic graph is partially modified, the system only performs incremental updates on the affected nodes and edges and regenerates the execution sequence, avoiding full graph reconstruction and recalculation of all nodes, thus greatly improving the response speed. It is especially suitable for interactive programming scenarios where engineers frequently debug and modify logic graphs.

[0066] In one possible implementation, incremental updates include: recording the parts of the logical graph that have changed, including newly added nodes and edges, deleted nodes and edges, or edges whose directions have been modified; and performing addition, deletion, or modification operations on the directed acyclic graph based on the changed parts, and adjusting the in-degree of the affected nodes.

[0067] The changed parts refer to all the graphic elements that have changed after the user modifies the logic diagram compared to before the modification. Specifically, this includes three types: addition (newly added graphic blocks or newly drawn lines), deletion (removed graphic blocks or lines), and modification (change of line direction, which can be regarded as deleting the original direction edge and then adding the new direction edge).

[0068] Affected nodes can refer to those nodes whose in-degree values ​​change due to the change in graph structure, as well as their downstream nodes. For example, when an edge from node A to node B is deleted, the in-degree of node B will decrease. The downstream nodes of node B are not directly affected, but if the in-degree of node B itself becomes zero, it may change its position in the execution sequence.

[0069] The present invention will be further described below through a detailed embodiment, which is a specific elaboration of the dynamic update step in claim 3: Based on the scenario of an engineer modifying the logic diagram in the embodiment of claim 3, the system first records the changed parts after detecting the adjustment of the logic diagram. The system internally maintains a change record list, which contains three sub-lists: a list of added items, a list of deleted items, and a list of modified items.

[0070] In this scenario, the engineer's actions are interpreted as: New additions: one node (filter block F); two edges (T→F, F→C).

[0071] Deleted item: an edge (T→C).

[0072] Modification: There is no independent operation to modify the side direction (if the user directly drags and drops to change the connection port, the system will recognize it as deleting the original connection and then adding a new connection).

[0073] The system performs the following operations based on the changed parts: The first step is to update the structure of the directed acyclic graph (DAG). The system calls the `add node` method of the DAG object to add node F to the node set. Then, it calls the `add edge` method to add edges T→F and F→C to the edge set. Finally, it calls the `remove edge` method to remove edge T→C from the edge set.

[0074] The second step is to adjust the in-degree. The system maintains an in-degree mapping table to record the current in-degree value of each node. The adjustment process is as follows: For the newly added edge T→F: the system finds the current in-degree value of node F (assuming it is 0), increments it by one, and updates it to 1.

[0075] For the newly added edge F→C: the system finds the current in-degree value of node C (assuming that the in-degree of node C in the original graph is 2), increments it by one, and updates it to 3.

[0076] For the deleted edge T→C: the system finds the current in-degree value of node C (which was 3 after the previous update), decrements it by one, and updates it to 2.

[0077] Simultaneously, the system checks whether any nodes have become zero or changed from zero to non-zero due to in-degree adjustments, and records these nodes for use when recalculating the execution order later. In this embodiment, the in-degree of node F becomes 1 (non-zero), the in-degree of node C changes from 2 to 2 (no net change), and the in-degree of node T remains zero. Therefore, node T is already a node with an in-degree of zero.

[0078] If the user's operation is to modify the direction of an edge, such as changing an edge from A→B to B→A, the system will break down the operation into: deleting the edge A→B, and then adding the edge B→A. Correspondingly, the in-degree of node B is decremented by one, and the in-degree of node A is incremented by one.

[0079] Through the above incremental adjustments, the system completed the update of the graph structure and in-degree data with minimal computational cost, preparing for the subsequent regeneration of the execution sequence.

[0080] The beneficial effects of this embodiment include: by clearly recording the change type (addition, deletion, modification direction) of the logic graph, and performing corresponding local adjustment operations on the directed acyclic graph and in-degree for each type, the dynamic update logic is clear and the computational load is controllable, avoiding full traversal of all nodes and edges, and further improving the response efficiency in the real-time editing scenario of graphical programming logic graph.

[0081] In one possible implementation, regenerating the execution sequence includes: using previously generated execution sequence information, recalculating the execution order only for the nodes affected by the adjustment.

[0082] The previously generated execution sequence information refers to the last execution sequence that the system had calculated and stored before the logical graph was adjusted. This sequence records the legal execution order of all graphical blocks.

[0083] Nodes affected by the adjustment can refer to those whose in-degree changes due to changes in the graph structure, as well as their downstream nodes in the topological sort. The execution order of these nodes may need to be recalculated, while other unaffected nodes can maintain their original relative order.

[0084] The present invention will be further described below through a detailed embodiment, which further defines the regeneration of the execution sequence step in claims 3 and 4: Following the embodiment of claim 4, the system has completed the incremental update of the DAG and in-degree. Now, the execution sequence needs to be regenerated based on the updated graph structure.

[0085] The system first retrieves the previously saved execution sequence. Before modification, the original execution sequence was: T → C → P → A → … (other nodes). Here, T is the temperature sensor block, C is the comparison operation block, P is the proportional-integral-derivative control block, and A is the actuator output block.

[0086] The system identifies the affected node set by analyzing change records. From the incremental update process, it's clear that node T's in-degree remains unchanged (still 0), node F is a new node, and node C's in-degree changes from 2 to 2 (net change is zero, but the source of its dependent edges changes). The in-degrees of node C's downstream nodes (including P, Alarm, etc.) do not directly change. However, because C's predecessor node set has changed (previously directly dependent on T, now dependent on F, and F dependent on T), node C and all its downstream nodes are considered nodes affected by the adjustment. The system marks node F, node C, and all of node C's downstream nodes as the "to be recalculated" set.

[0087] The system then extracts the unaffected node sequence from the original execution sequence. Unaffected nodes include those that precede the affected nodes in the original execution sequence and do not depend on the affected nodes. In this example, although node T is unaffected, to maintain the integrity of the execution order, the system decides to recalculate starting from all nodes with an in-degree of zero, but using information from the original sequence for pruning.

[0088] The specific recalculation process is as follows: The system initializes a queue, adding nodes with a current in-degree of zero to the queue. Based on the incrementally updated in-degree values, node T has an in-degree of zero, node S (the setpoint block) has an in-degree of zero, and node F has a non-zero in-degree (1). Therefore, the queue initially contains T and S. The system removes node T from the queue and adds it to the new execution sequence, processes T's downstream node (F), reduces F's in-degree from 1 to 0, and adds F to the queue. Then, node S is removed, and its downstream node (C) is processed, reducing C's in-degree from 2 to 1. C's in-degree is not yet zero, so it is not added to the queue. Next, node F is removed, and its downstream node (C) is processed, reducing C's in-degree from 1 to 0, and adding C to the queue. Subsequent steps are consistent with regular topology sorting.

[0089] The system found that, compared to calculating from scratch, this method utilizes the fact that nodes T and S, which were unaffected in the original execution sequence, already knew they should be placed first, and there was no need to re-evaluate those completely unaffected independent branches. The final generated new execution sequence is: T → S → F → C → P → Alarm → A. In this sequence, node F is correctly inserted between T and C in the original sequence, while the order of subsequent nodes remains largely unchanged.

[0090] The beneficial effects of this embodiment include: by utilizing the previous execution sequence information, only the nodes affected by the adjustment are recalculated, avoiding a full reordering, which can significantly reduce the amount of computation in large logic graphs, and is especially suitable for scenarios with multiple consecutive local modifications, further improving the efficiency of dynamic response.

[0091] In one possible implementation, converting a logical graph into a directed acyclic graph includes: establishing a data structure containing all nodes, all directed edges, and the mapping from nodes to graph blocks; wherein, a node contains a unique identifier of the associated graph block, and a directed edge contains a start node and an end node, with the start node corresponding to the upstream graph block and the end node corresponding to the downstream graph block.

[0092] The mapping from nodes to graphics blocks can refer to a data structure, such as a hash table or dictionary, that allows for quick lookup of the corresponding graphics block from a node identifier. The keys are node numbers or node objects, and the values ​​are the corresponding graphics block objects. This mapping facilitates the conversion of nodes in the sequence into actual executable graphics block instructions after the execution order is generated.

[0093] A unique identifier can refer to a non-repeating identifier assigned to each graphic block in the logical diagram, such as an integer ID or a globally unique identifier (GUID), used to distinguish different graphic blocks.

[0094] The starting node and ending node can refer to the starting node and ending node of a directed edge, respectively, indicating that the data flow or control flow is from the starting node to the ending node.

[0095] The present invention will be further described below through a detailed embodiment, which provides a detailed explanation of the data structure design in the graph structure modeling step: In the aforementioned embodiment of the temperature control logic diagram, when the system converts the graphical logic diagram into a directed acyclic graph, it creates the following data structure: First, the system defines a node class. This class contains the following member variables: an integer node identifier, used to uniquely identify the node in the graph; a string or integer associated graphic block identifier, which is consistent with the ID of the graphic block in the DCS graphical programming environment; in addition, it may contain other auxiliary information about the node, such as the node's position coordinates on the canvas.

[0096] For each graphical block in the logic diagram, the system creates a node object. For example, the temperature sensor input block (ID=1001) is mapped to node object N_T, and its associated graphical block identifier is 1001; the setpoint input block (ID=1002) is mapped to node object N_S; the comparison operation block (ID=1003) is mapped to node object N_C; and so on.

[0097] Secondly, the system defines an edge class. This class contains member variables of two node types: start node and end node. For example, the original connection from the temperature sensor block to the comparison operation block is mapped to an edge object E_TC, with its start node being N_T and its end node being N_C.

[0098] Then, the system defines a directed acyclic graph class. This class contains the following members: A set of nodes is typically stored using a hash set to ensure that nodes are not duplicated.

[0099] A set of edges, using a hash set to store all edge objects.

[0100] A mapping table, which is a hash mapping from graphic block identifiers to node objects. For example, the key is 1001 and the value is the node object N_T. This mapping table can be used when the system needs to quickly find the corresponding node based on the graphic block ID, such as when a user selects a graphic block and queries its position in the execution sequence.

[0101] After creating all nodes and edges, the system persistently stores the node set, edge set, and mapping table in memory for subsequent in-degree calculation, loop closure detection, and topology sorting steps. After the execution sequence is generated, the system uses the node-to-graphics block mapping table to sequentially convert the nodes in the execution sequence into actual graphical block IDs, and then outputs them to the DCS runtime execution engine.

[0102] The beneficial effects of this embodiment include: by establishing a clear data structure that includes a set of nodes, a set of edges, and a mapping from nodes to graph blocks, an efficient data access foundation is provided for subsequent in-degree statistics, topological sorting, and dynamic updates. In particular, the mapping from nodes to graph blocks enables the execution sequence results to be quickly converted into executable graph block instructions, thereby improving the overall operating efficiency of the system.

[0103] In one possible implementation, the order of the graphic blocks in the execution sequence satisfies the following: for any directed edge, the graphic block corresponding to the starting node of the directed edge is arranged before the graphic block corresponding to the ending node of the directed edge.

[0104] In this context, the graph block corresponding to the starting node of a directed edge can refer to the upstream graph block in the dependency relationship represented by that directed edge, i.e., the graph block that is depended upon. The graph block corresponding to the ending node of a directed edge can refer to the downstream graph block, i.e., the graph block that depends on the upstream computation result. This condition guarantees that in the final execution order, all data dependencies are satisfied: the graph block that is depended upon is always executed before the graph blocks that depend on it.

[0105] The present invention will be further described below through a detailed embodiment, which is used to verify whether the execution sequence generated by the aforementioned method correctly satisfies the dependency relationship: Taking the execution sequence T → S → C → P → Alarm → A generated in the embodiment of claim 1 as an example, verify whether the sequence satisfies the above conditions.

[0106] The system traverses each directed edge in the directed acyclic graph and checks whether the starting node of each edge is located before the ending node in the sequence.

[0107] The first directed edge: from T to C. In the sequence, T is in the first position, C is in the third position, and T comes before C, satisfying the condition.

[0108] The second directed edge: from S to C. S is in the second position, C is in the third position, and S precedes C, satisfying the condition.

[0109] The third directed edge: from C to P. C is in the third position, P is in the fourth position, and C precedes P, satisfying the condition.

[0110] The fourth directed edge: from P to A. P is in the fourth position, A is in the sixth position, and P is before A, which satisfies the condition.

[0111] The fifth directed edge: from T to Alarm. T is in the first position, Alarm is in the fifth position, and T is before Alarm, satisfying the condition.

[0112] The sixth directed edge: from C to Alarm. C is in the third position, Alarm is in the fifth position, and C precedes Alarm, satisfying the condition.

[0113] All six directed edges satisfy the condition that the starting node is placed before the ending node. Therefore, the execution sequence is a correct topological sort.

[0114] If an execution sequence violates this condition—for example, if Alarm appears before C—then when Alarm is executed, the calculation result of C, on which it depends, has not yet been generated, leading to a logical error. The method of this invention, through in-degree-based queue processing, fundamentally guarantees that such violating sequences will not occur.

[0115] In a real DCS system, this condition ensures that the input port of each graphic block has received the calculation results of all upstream graphic blocks at the time of its execution, thereby ensuring the correctness of the control logic.

[0116] The beneficial effects of this embodiment include: by using explicit constraints, the execution sequence is guaranteed to strictly follow the data dependencies between graphical blocks, avoiding logical disorder caused by incorrect execution order, providing a reliable compilation foundation for DCS graphical programming, and reducing the difficulty and risk of on-site debugging.

[0117] The following is in conjunction with the appendix Figure 2 Taking the application of the graphical programming logic diagram topology generation method for DCS provided in this specification based on the Kahn algorithm as an example, the method will be further explained. Figure 2 This specification illustrates the execution principle of a graphical programming logic diagram topology generation method for DCS provided in one embodiment, specifically including the following.

[0118] Graphical Logic Diagram Input: Receives a logic diagram containing graphical blocks and connections created by the user in the DCS graphical programming environment. Software-implemented data structure definition: The Block class corresponds to the graphical elements in DCS programming, containing attributes such as a unique block identifier (ID) and block type. The Connection class. It corresponds to the data flow / control flow between graphical blocks, including attributes such as the start block ID (upstream block) and end block ID (downstream block). Graph structure modeling: The input logic graph is processed to construct a directed acyclic graph (DAG) that accurately reflects the dependencies between graph blocks. For each graph block, it is directly converted into a node in the DAG. Connections representing data flow or control flow are converted into directed edges, with the direction of the directed edges consistent with the direction of the data flow or control flow. For example, if the output of "addition block A" is connected to the input of "multiplication block B", then there exists a directed edge from A to B in the DAG, indicating that B depends on the computation result of A.

[0119] Software-implemented data structure definition: A Directed Graph Node class. It corresponds to a node in a DAG (Directed Acyclic Graph) and maps to graphical blocks, containing attributes such as the associated graphical block ID. The Directed Graph Edge class. It represents the directed edges in a DAG (Directed Acyclic Graph), mapping the dependencies between them, and includes the starting node ID (corresponding to the upstream graph block) and the ending node ID (corresponding to the downstream graph block). Directed Acyclic Graph (DAG) class. Used to store the topology of a graphical logical graph, containing all nodes (deduplicated), all edges, and a mapping from block IDs to nodes (for fast lookup).

[0120] In-degree calculation: After completing the graph structure modeling, traverse all nodes in the DAG and count the in-degree of each node (i.e., the number of directed edges pointing to that node). For a directed edge, if there is a directed edge from node A to node B, then the in-degree of node B is incremented by 1. Nodes with an in-degree of 0 indicate that they have no prerequisite dependencies and can be executed first.

[0121] Execute a depth-first search algorithm to detect loops: After converting the graphical logic graph into a directed acyclic graph (DAG), a depth-first search (DFS) algorithm must be used to check for loops in the graph to ensure that the execution order of the graphical programming logic can be correctly calculated by the Kahn algorithm. If a loop exists, the user should be prompted to modify the graphical logic graph to eliminate the circular dependency.

[0122] See Figure 3 The execution order of Kahn's algorithm calculation is as follows: Initialize the queue by adding all nodes with an in-degree of 0 to the queue; Repeat the following operations until the queue is empty: a. Remove a node from the queue and add it to the execution sequence; b. Traverse all downstream nodes of this node (i.e., subsequent nodes connected by directed edges) and decrement the in-degree of these downstream nodes by 1; c. If the in-degree of a downstream node decreases to 0, then add it to the queue; The final execution sequence is the execution order of the graphics blocks that conforms to the data dependency relationship.

[0123] See Figure 4 The dynamic update mechanism is as follows.

[0124] The system monitors whether the user has adjusted the graphical programming logic diagram (DAG). If adjustments are made, the DAG and in-degree are incrementally updated, and the topology sequence is regenerated. If no adjustments are made, the topology sequence is directly output. When the user modifies the DAG (e.g., adding / deleting connections), only the in-degree of the affected nodes and related queues are recalculated; the entire DAG does not need to be reprocessed, achieving a localized and rapid update of the execution order. When the user adjusts the DAG (e.g., adding or deleting graphical blocks or connections, modifying connection directions, etc.), the dynamic update mechanism comes into play. The specific process includes: Record the changes in the graphical programming logic diagram, such as newly added nodes and edges, deleted nodes and edges, and the direction of modified edges.

[0125] Based on the changes, the DAG is updated incrementally: new nodes and edges are added directly to the DAG; deleted nodes and edges are removed from the DAG and the affected nodes are processed; when the direction of an edge is modified, the original edge is deleted first, and then the edge with the new direction is added.

[0126] Incremental updates are performed on the in-degree: for a newly added edge (A, B), the in-degree of node B is incremented by 1; for a deleted edge (A, B), the in-degree of node B is decremented by 1; for edges whose direction is modified, such as changing from (A, B) to (B, A), the in-degree of node B is decremented by 1, and the in-degree of node A is incremented by 1. The in-degrees of other nodes affected by changes in nodes or edges are also adjusted accordingly.

[0127] Based on the updated DAG and in-degree, the Kahn algorithm is used to regenerate the topological sequence. At this time, the previous topological sequence information can be used to reduce some of the computational cost.

[0128] Furthermore, the present solution will be described below through an overall embodiment. See [link to documentation]. Figure 5 A DCS control logic diagram contains three graphical blocks: input block A (no pre-dependent dependencies); operation block B (dependent on the output of A); and output block C (dependent on the outputs of A and B).

[0129] The above logic diagram is processed using the technical solution of the present invention: (1) Graph structure modeling: Convert each graphic block into nodes A, B, and C, and convert the connection into directed edges A→B, A→C, and B→C according to the defined rules. (2) Calculate the in-degree: Calculate the initial in-degree of each node. The in-degree of A is 0, the in-degree of B is 1 (from A), and the in-degree of C is 2 (from both A and B); (3) Detection of loop: None (4) Execute Kahn's algorithm: Initial queue: [A]; Remove A and add it to the execution sequence. At this time, the in-degree of A's neighboring nodes B and C are reduced by 1 respectively. The in-degree of B becomes 0 and the in-degree of C becomes 1. Add B to the queue [B]. Remove B and add it to the execution sequence. At this time, the in-degree of A's neighboring node C is reduced by 1 to become 0, and C is added to the queue [C]. Remove C and add it to the execution sequence. The queue is empty, and the final execution sequence is [A→B→C].

[0130] This sequence strictly adheres to the dependency relationship A→B→C, ensuring that C executes only after obtaining the results of A and B, thus avoiding logical errors.

[0131] This invention, by employing the Kahn algorithm, has the following advantages compared to existing DFS schemes: More efficient: Non-recursive queue operations avoid the stack memory overhead of recursive calls, and computation time can be reduced by more than 50% in a logic graph containing 1000 graph blocks. Highly adaptable to dynamic changes: When the graphical logic graph is partially modified, only the in-degree of the affected nodes needs to be updated, without having to retrace the entire graph, resulting in an 80% improvement in response speed; Stable execution order: Regardless of which node with an in-degree of 0 is selected in the initial queue, the final execution sequence will satisfy the dependency relationship, avoiding order fluctuations caused by different traversal starting points and reducing debugging difficulty.

[0132] These advantages directly solve the problems of low efficiency and poor dynamic adaptability in existing technologies, and improve the reliability and development efficiency of DCS graphical programming.

[0133] Corresponding to the above method embodiments, this specification also provides embodiments of a graphical programming logic diagram topology generation device for DCS. Figure 6 This specification illustrates a schematic diagram of a graphical programming logic diagram topology generation device for a DCS, according to one embodiment. Figure 6 As shown, the device includes: The data acquisition module 601 is configured to acquire a graphical programming logic diagram, which includes graphical blocks and connections used to represent data flow or control flow between the graphical blocks. The data conversion module 602 is configured to convert a logic graph into a directed acyclic graph, wherein graphical blocks are mapped to nodes of the directed acyclic graph, and connections are mapped to directed edges of the directed acyclic graph, with the direction of the directed edges being consistent with the direction of the data flow or control flow. The in-degree calculation module 603 is configured to traverse all nodes in the directed acyclic graph and count the in-degree of each node, which is the number of directed edges pointing to the node. The queue generation module 604 is configured to initialize a queue and add nodes with an in-degree of zero to the queue; The queue loop module 605 is configured to repeatedly execute the following steps until the queue is empty: take a node out of the queue and add the taken node to the execution sequence; traverse all downstream nodes of the taken node and decrement the in-degree of each downstream node by one; add the downstream node whose in-degree becomes zero after decrementing by one to the queue. The data output module 606 is configured to output the execution sequence as the execution order of the graphics blocks.

[0134] In one possible implementation, after calculating the in-degree of each node, the method further includes: detecting whether there is a cycle in the directed acyclic graph using a depth-first search algorithm; if a cycle exists, generating feedback information to prompt the user to modify the logical graph.

[0135] One possible implementation also includes a dynamic update step: monitoring adjustments to the graphical programming logic graph, incrementally updating the directed acyclic graph and in-degree when the logic graph is adjusted, and regenerating the execution sequence based on the updated directed acyclic graph and in-degree.

[0136] In one possible implementation, incremental updates include: recording the parts of the logical graph that have changed, including newly added nodes and edges, deleted nodes and edges, or edges whose directions have been modified; and performing addition, deletion, or modification operations on the directed acyclic graph based on the changed parts, and adjusting the in-degree of the affected nodes.

[0137] In one possible implementation, regenerating the execution sequence includes: using previously generated execution sequence information, recalculating the execution order only for the nodes affected by the adjustment.

[0138] In one possible implementation, converting a logical graph into a directed acyclic graph includes: establishing a data structure containing all nodes, all directed edges, and the mapping from nodes to graph blocks; wherein, a node contains a unique identifier of the associated graph block, and a directed edge contains a start node and an end node, with the start node corresponding to the upstream graph block and the end node corresponding to the downstream graph block.

[0139] In one possible implementation, the order of the graphic blocks in the execution sequence satisfies the following: for any directed edge, the graphic block corresponding to the starting node of the directed edge is arranged before the graphic block corresponding to the ending node of the directed edge.

[0140] The above is a schematic scheme of a graphical programming logic diagram topology generation device for DCS according to this embodiment. It should be noted that the technical solution of this graphical programming logic diagram topology generation device for DCS belongs to the same concept as the technical solution of the graphical programming logic diagram topology generation method for DCS described above. Details not described in detail in the technical solution of the graphical programming logic diagram topology generation device for DCS can be found in the description of the technical solution of the graphical programming logic diagram topology generation method for DCS described above.

[0141] Figure 7 A structural block diagram of a computing device 700 according to one embodiment of this specification is shown. The components of the computing device 700 include, but are not limited to, a memory 710 and a processor 720. The processor 720 is connected to the memory 710 via a bus 730, and a database 750 is used to store data.

[0142] The computing device 700 also includes an access device 740, which enables the computing device 700 to communicate via one or more networks 760. Examples of these networks include Public Switched Telephone Network (PSTN), Local Area Network (LAN), Wide Area Network (WAN), Personal Area Network (PAN), or combinations of communication networks such as the Internet. The access device 740 may include one or more of any type of wired or wireless network interface (e.g., a network interface card (NIC)), such as an IEEE 802.11 Wireless Local Area Network (WLAN) wireless interface, a Wi-MAX (Worldwide Interoperability for Microwave Access) interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth interface, or a Near Field Communication (NFC) interface.

[0143] In one embodiment of this specification, the above-described components of the computing device 700 and Figure 7 Other components, not shown, can also be connected to each other, for example, via a bus. It should be understood that... Figure 7 The block diagram of the computing device shown is for illustrative purposes only and is not intended to limit the scope of this specification. Those skilled in the art can add or replace other components as needed.

[0144] The computing device 700 can be any type of stationary or mobile computing device, including mobile computers or mobile computing devices (e.g., tablet computers, personal digital assistants, laptop computers, notebook computers, netbooks, etc.), mobile phones (e.g., smartphones), wearable computing devices (e.g., smartwatches, smart glasses, etc.) or other types of mobile devices, or stationary computing devices such as desktop computers or personal computers (PCs). The computing device 700 can also be a mobile or stationary server.

[0145] The processor 720 executes computer-executable instructions, which, when executed by the processor, implement the steps of the graphical programming logic diagram topology generation method for DCS described above. The above is an illustrative scheme of a computing device according to this embodiment. It should be noted that the technical solution of this computing device and the technical solution of the graphical programming logic diagram topology generation method for DCS described above belong to the same concept. Details not described in detail in the technical solution of the computing device can be found in the description of the technical solution of the graphical programming logic diagram topology generation method for DCS described above.

[0146] An embodiment of this specification also provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the graphical programming logic diagram topology generation method for DCS described above.

[0147] The above is an illustrative scheme of a computer-readable storage medium according to this embodiment. It should be noted that the technical solution of this storage medium belongs to the same concept as the technical solution of the graphical programming logic diagram topology generation method for DCS described above. For details not described in detail in the technical solution of the storage medium, please refer to the description of the technical solution of the graphical programming logic diagram topology generation method for DCS described above.

[0148] An embodiment of this specification also provides a computer program, wherein when the computer program is executed in a computer, it causes the computer to perform the steps of the above-described graphical programming logic diagram topology generation method for DCS.

[0149] The above is an illustrative scheme of a computer program according to this embodiment. It should be noted that the technical solution of this computer program belongs to the same concept as the technical solution of the graphical programming logic diagram topology generation method for DCS described above. For details not described in detail in the technical solution of the computer program, please refer to the description of the technical solution of the graphical programming logic diagram topology generation method for DCS described above.

[0150] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0151] The computer instructions include computer program code, which may be in the form of source code, object code, executable file, or certain intermediate forms. The computer-readable medium may include any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium may be appropriately added to or subtracted according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0152] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments in this specification are not limited to the described order of actions, because according to the embodiments in this specification, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments in this specification.

[0153] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0154] The preferred embodiments disclosed above are merely illustrative of this specification. Optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the embodiments described herein. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the embodiments, thereby enabling those skilled in the art to better understand and utilize this specification. This specification is limited only by the claims and their full scope and equivalents.

Claims

1. A graphical programming logic diagram topology generation method for DCS, characterized in that, include: Obtain a graphical programming logic diagram, the logic diagram including graphical blocks and connections used to represent data flow or control flow between the graphical blocks; The logic graph is converted into a directed acyclic graph, wherein the graphic blocks are mapped to nodes of the directed acyclic graph, the connecting lines are mapped to directed edges of the directed acyclic graph, and the direction of the directed edges is consistent with the direction of the data flow or the control flow. Traverse all nodes in the directed acyclic graph and count the in-degree of each node; Initialize a queue and add the node with an in-degree of zero to the queue; The following steps are executed repeatedly until the queue is empty: a node is taken out of the queue and added to the execution sequence; all downstream nodes of the taken-out node are traversed and the in-degree of each downstream node is decremented by one; the downstream nodes whose in-degree becomes zero after decrementing by one are added to the queue. The execution sequence is output as the execution order of the graphics blocks.

2. The method of claim 1, wherein, After calculating the in-degree of each node, the method further includes: detecting whether there is a cycle in the directed acyclic graph using a depth-first search algorithm; if a cycle exists, generating feedback information to prompt the user to modify the logical graph.

3. The method of claim 1, wherein, It also includes a dynamic update step: monitoring the adjustment of the graphical programming logic graph, and when the logic graph is adjusted, incrementally updating the directed acyclic graph and the in-degree, and regenerating the execution sequence based on the updated directed acyclic graph and the in-degree.

4. The method of claim 3, wherein, The incremental update includes: recording the parts of the logical graph that have changed, including newly added nodes and edges, deleted nodes and edges, or edges whose direction has been modified; and performing addition, deletion, or modification operations on the directed acyclic graph based on the changed parts, and adjusting the in-degree of the affected nodes.

5. The method of claim 3, wherein, The regeneration of the execution sequence includes: using the previously generated execution sequence information, recalculating the execution order only for the nodes affected by the adjustment.

6. The method of claim 1, wherein, The step of converting the logical graph into a directed acyclic graph includes: establishing a data structure containing all nodes, all directed edges, and the mapping from the nodes to the graph blocks; wherein, the nodes contain a unique identifier of the associated graph block, the directed edges contain a start node and an end node, the start node corresponds to the upstream graph block, and the end node corresponds to the downstream graph block.

7. The method of claim 1, wherein, The order of the graphic blocks in the execution sequence satisfies the following: for any directed edge, the graphic block corresponding to the starting node of the directed edge is arranged before the graphic block corresponding to the ending node of the directed edge.

8. A graphical programming logic diagram topology generation apparatus for a DCS, characterized by, include: The data acquisition module is configured to acquire a graphical programming logic diagram, which includes graphical blocks and connections for representing data flow or control flow between the graphical blocks; The data conversion module is configured to convert the logic graph into a directed acyclic graph, wherein the graphic blocks are mapped to nodes of the directed acyclic graph, the connecting lines are mapped to directed edges of the directed acyclic graph, and the direction of the directed edges is consistent with the direction of the data flow or the control flow. The in-degree calculation module is configured to traverse all nodes in the directed acyclic graph and calculate the in-degree of each node. The queue generation module is configured to initialize a queue and add the node with an in-degree of zero to the queue. The queue loop module is configured to repeatedly execute the following steps until the queue is empty: take a node out of the queue and add the taken-out node to the execution sequence; traverse all downstream nodes of the taken-out node and decrement the in-degree of each downstream node by one; add the downstream node whose in-degree becomes zero after decrementing by one to the queue. The data output module is configured to output the execution sequence as the execution order of the graphics blocks.

9. A computing device, comprising: include: Memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions, which, when executed by the processor, implement the steps of the graphical programming logic diagram topology generation method for DCS according to any one of claims 1 to 7.

10. A computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the graphical programming logic diagram topology generation method for DCS as described in any one of claims 1 to 7.

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