Instruction processing method and apparatus, electronic device, and readable medium

Abstract

Embodiments of the present application provide an instruction processing method and device, electronic equipment and readable medium, and relate to the technical field of computer. In the method, for any to-be-translated program of a specified source architecture, a specific running instruction in the to-be-translated program is identified; the specified source architecture includes at least two source architectures. From a predefined mapping relationship between intermediate instructions and source instruction groups, an intermediate instruction corresponding to a first source instruction group is found as a first intermediate instruction; the first source instruction group corresponds to the specific running instruction; each source instruction group includes instructions of at least two source architectures, and the semantics and updated flag bits in the instructions are matched with each other. The first intermediate instruction is translated into a first target instruction adapted to a target architecture, to obtain a translation result of the specific running instruction. In this way, the updated flag bits can be simulated, and the program can be ensured to run correctly.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to an instruction processing method, apparatus, electronic device, and readable medium. Background Technology

[0002] Currently, with the continuous development of computer technology, binary translation technology is being applied more and more widely. Through binary translators, programs from a source architecture can be translated into programs that can run on a target architecture, enabling cross-architecture operation and thus improving program compatibility and platform adaptability.

[0003] In related technologies, source architecture programs often contain specific computation instructions, which are instructions that perform calculations and update flag bits based on the calculation results. To ensure correct program execution, simulating these specific computation instructions to simulate flag bit updates during execution has become a critical technical problem that needs to be solved. Summary of the Invention

[0004] This invention provides an instruction processing method, apparatus, electronic device, and readable medium, which can solve the problem of how to simulate specific arithmetic instructions to ensure the correct operation of a program.

[0005] To address the above problems, this invention discloses an instruction processing method, the method comprising: For any program to be translated based on a specified source architecture, identify specific execution instructions within the program to be translated; the specified source architecture includes at least two source architectures; From the predefined mapping relationship between intermediate instructions and source instruction groups, the intermediate instruction corresponding to the first source instruction group is found as the first intermediate instruction; wherein, the first source instruction group corresponds to the specific execution instruction; each source instruction group includes instructions from at least two source architectures, and the semantics and updated flag bits in the instructions are matched respectively; The first intermediate instruction is translated into a first target instruction adapted to the target architecture to obtain the translation result of the specific execution instruction; the operation implemented in the first target instruction and the updated flag bit are respectively matched with the operation implemented in the instruction in the first source instruction group and the updated flag bit.

[0006] On the other hand, embodiments of the present invention disclose an instruction processing apparatus applied to a binary translator, the apparatus comprising: The identification module is used to identify specific execution instructions in any program to be translated for a specified source architecture; the specified source architecture includes at least two source architectures. The first lookup module is used to find the intermediate instruction corresponding to the first source instruction group from the predefined mapping relationship between intermediate instructions and source instruction groups as the first intermediate instruction; wherein, the first source instruction group is associated with the specific execution instruction; each source instruction group includes instructions of at least two source architectures, and the semantics and updated flag bits of the instructions are matched respectively; The first translation module is used to translate the first intermediate instruction into a first target instruction adapted to the target architecture, so as to obtain the translation result of the specific running instruction; the operation implemented in the first target instruction and the updated flag bit are respectively matched with the operation implemented in the instruction in the first source instruction group and the updated flag bit.

[0007] In another aspect, embodiments of the present invention disclose an electronic device, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, which cause the processor to execute the aforementioned method.

[0008] This invention also discloses a machine-readable medium storing instructions that, when executed by one or more processors, cause the processors to perform the methods described above.

[0009] The embodiments of the present invention have the following advantages: In the instruction processing method provided by the embodiments of the present invention, for any program to be translated with a specified source architecture, a specific execution instruction in the program to be translated is identified; the specified source architecture includes at least two source architectures. From a predefined mapping relationship between intermediate instructions and source instruction groups, an intermediate instruction corresponding to a first source instruction group is found as a first intermediate instruction; wherein, the first source instruction group corresponds to a specific execution instruction; each source instruction group includes instructions from at least two source architectures, and the semantics and updated flag bits in the instructions are matched. The first intermediate instruction is translated into a first target instruction adapted to the target architecture to obtain the translation result of the specific execution instruction; the operations implemented in the first target instruction and the updated flag bits are respectively matched with the operations implemented in the instructions in the first source instruction group and the updated flag bits. Thus, by converting the specific execution instruction in the program to be translated from the source architecture into a first intermediate instruction, and translating the first intermediate instruction into a first target instruction adapted to the target architecture, the semantics of the specific execution instruction can be accurately simulated by executing the first target instruction, and the updated flag bits can be simulated during execution, thereby ensuring that the program can run correctly. Furthermore, in this embodiment of the invention, instructions that match the semantics and updated flag bits in at least two source architectures are divided into a source instruction group, and an intermediate instruction is set for each source instruction group. This allows for unified simulation of at least two source architectures. Compared to designing a set of flag bit simulation instructions for a single source architecture, this eliminates some redundant flag bit simulation instructions, thereby avoiding the problem of redundant instruction coding and simplifying the control logic. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below.

[0011] Figure 1 This is a flowchart of the steps of an instruction processing method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the position of a flag bit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another flag position provided in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating a processing example of a binary translator provided in an embodiment of the present invention; Figure 5 This is a block diagram of an instruction processing device provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0013] First, an application scenario related to an embodiment of the present invention will be described. The instruction processing method provided in this embodiment can be applied to binary translation scenarios. Specifically, it can be applied to dynamic binary translation scenarios as well as static binary translation scenarios; this embodiment does not limit this application. Binary translation is a technology that enables instruction set simulation. Specifically, binary translation refers to the technology of translating the instructions in an executable file (i.e., the program to be translated from the source architecture) into instructions from another instruction set architecture (the target architecture), enabling the program to run across platforms.

[0014] In related technologies, programs often include numerous conditional branches. Architectures employing explicit flag operations (e.g., MIPS, Loongarch, RISC-V) typically do not configure flag registers, and the operation instructions do not generate and update flags based on the operation results. Instead, they directly use the operation results stored in general-purpose registers as the basis for determining conditional branches. Comparison instructions or comparison jump instructions compare the values ​​of the general-purpose registers to decide whether to execute a branch, i.e., which branch to actually execute.

[0015] In architectures employing implicit flag operations (such as x86 and ARM architectures), dedicated registers are used to store flags, and the values ​​of these flags are used as the basis for conditional branch decisions. Specifically, architectures using implicit flag operations have specific instruction sets (referred to as specific operation instructions) that update the flags, such as certain arithmetic and logical operation instructions. When these specific operation instructions are executed, the operation begins, and the flags are updated based on the result. The updated flags provide the basis for subsequent conditional branch decisions. The specific value of the flag can represent the state of the operation result, such as whether there was an overflow, the parity of the result, or whether a carry / borrow occurred. As a crucial part of program control flow, the flags are relied upon by conditional branches to determine whether to execute a branch and which branch to actually execute.

[0016] For programs that employ implicit flag operations, in order to ensure that they can be executed correctly in the target architecture after translation, binary translators often need to simulate specific operation instructions to provide a basis for conditional branch judgments and ensure that the program runs correctly.

[0017] Therefore, embodiments of the present invention provide an instruction processing method, which will be described in detail below.

[0018] Figure 1 This is a flowchart illustrating the steps of an instruction processing method provided in an embodiment of the present invention, applied to a binary translator, such as... Figure 1 As shown, the method may include: Step 101: For any program to be translated from a specified source architecture, identify specific execution instructions in the program to be translated; the specified source architecture includes at least two source architectures.

[0019] Step 102: From the predefined mapping relationship between intermediate instructions and source instruction groups, find the intermediate instruction corresponding to the first source instruction group as the first intermediate instruction; wherein, the first source instruction group corresponds to the specific execution instruction; each source instruction group includes instructions from at least two source architectures, and the semantics and updated flag bits in the instructions are matched.

[0020] Step 103: Translate the first intermediate instruction into a first target instruction adapted to the target architecture to obtain the translation result of the specific running instruction; the operation implemented and the updated flag bit in the first target instruction are respectively matched with the operation implemented and the updated flag bit in the instruction in the first source instruction group.

[0021] The instruction processing method provided in this invention can be used in electronic devices, specifically, in binary translators within electronic devices. In this invention, the specified source architecture includes at least two source architectures, both of which can be system architectures employing implicit flag bit operations. The specific architectures included in the specified source architecture can be set as needed, and this invention does not impose any limitations on this. For example, the specified source architecture may include the x86 architecture and the ARM architecture. The program to be translated can be a program conforming to any of the specified source architectures; for example, the program to be translated can be an x86 architecture program or an ARM architecture program. The program to be translated includes multiple instructions adapted to the source architecture. To run on the target architecture, the instructions in the program to be translated need to be translated into instructions adapted to the target architecture. The target architecture is a system architecture different from the specified source architecture that needs to be translated by the binary translator. For example, the target architecture can be a system architecture employing explicit flag bit operations, such as the Loongson architecture. In dynamic translation scenarios, the binary translator can run on the target architecture platform, executing the translated target instructions adapted to the target architecture through the processor of the target architecture platform.

[0022] The mapping relationship between intermediate instructions and source instruction groups (hereinafter referred to as the first mapping relationship) can be predefined and is used to characterize the correspondence between intermediate instructions designed for the binary translator and source instruction groups. Intermediate instructions are intermediate representation instructions designed for the binary translator, also known as flag bit simulation instructions. In the first mapping relationship, one intermediate instruction corresponds to one source instruction group, and one source instruction group includes multiple instructions adapted to the source architecture. It is understood that some instructions may not have semantically matching instructions in other source architectures, and the updated flag bits may also not match. Therefore, some source instruction groups may include only one instruction. For example, instructions with matching semantics and matching updated flag bits from at least two source architectures can be added to a source instruction group. Semantic matching between two instructions means that the two instructions semantically represent the same operation, and matching updated flag bits means that the flag bits updated by one instruction include the flag bits updated by the other instruction.

[0023] Taking x86 and ARM architectures as examples, the instruction semantics of the ADD instruction in x86 architecture and the ADDS instruction in ARM architecture are both: performing addition. The flags updated by the ADD instruction include: carry flag, parity flag, auxiliary flag, zero flag, sign flag, and overflow flag. The flags updated by the ADDS instruction include: sign flag, zero flag, carry flag, and overflow flag. Since the ADD instruction in x86 architecture and the ADDS instruction in ARM architecture represent the same operation, and the flags updated by the ADD instruction include those updated by the ADDS instruction, the ADD instruction in x86 architecture and the ADDS instruction in ARM architecture can be added to a source instruction group. Accordingly, in the first mapping relationship, the ADD instruction and the ADDS instruction in the source instruction group each correspond to the same intermediate instruction. For example, they can both correspond to the intermediate instruction: BT_ADD instruction.

[0024] By finding the first mapping relationship between intermediate instructions and source instruction groups, the source instruction group to which a specific execution instruction in the program to be translated belongs is obtained. This source instruction group is then designated as the first source instruction group; that is, the first source instruction group is the source instruction group to which the specific execution instruction belongs. Further, the intermediate instruction corresponding to the first source instruction group in the first mapping relationship can be designated as the first intermediate instruction. Assuming the specific execution instruction in the program to be translated is the ADDS instruction, the first intermediate instruction found according to the first mapping relationship can be the BT_ADD instruction. For any specific execution instruction in the program to be translated, by finding the first mapping relationship, a specific execution instruction is converted into a first intermediate instruction. Further, for any first intermediate instruction obtained through conversion, the binary translator can translate the first intermediate instruction into an instruction adapted to the target architecture, obtaining the first target instruction, thus obtaining the translation result of the specific execution instruction.

[0025] In summary, the instruction processing method provided in this embodiment of the invention identifies specific execution instructions in any program to be translated from a specified source architecture. The specified source architecture includes at least two source architectures. From a predefined mapping relationship between intermediate instructions and source instruction groups, the intermediate instruction corresponding to the first source instruction group is found as the first intermediate instruction. The first source instruction group corresponds to a specific execution instruction. Each source instruction group includes instructions from at least two source architectures, and the semantics and updated flag bits in the instructions match. The first intermediate instruction is translated into a first target instruction adapted to the target architecture to obtain the translation result of the specific execution instruction. The operations implemented and the updated flag bits in the first target instruction match the operations implemented and the updated flag bits in the instructions of the first source instruction group, respectively. Thus, by converting the specific execution instructions in the program to be translated from the source architecture into first intermediate instructions and translating the first intermediate instructions into first target instructions adapted to the target architecture, the semantics of the specific execution instructions can be accurately simulated by executing the first target instructions, and the updated flag bits can be simulated during execution, thereby ensuring that the program can run correctly. The semantics of simulating a specific running instruction refers to performing an operation equivalent to the operation implemented by the specific running instruction and updating the flag bit updated by the specific running instruction.

[0026] Furthermore, in this embodiment of the invention, instructions that match the semantics and updated flag bits in at least two source architectures are divided into a source instruction group, and an intermediate instruction is set for each source instruction group. This allows for unified simulation of at least two source architectures. Compared to designing a set of flag bit simulation instructions for a single source architecture, this eliminates some redundant flag bit simulation instructions, thereby avoiding the problem of redundant instruction coding and simplifying the control logic.

[0027] Optionally, embodiments of the present invention may further include the following steps: Step S21: When the first target instruction is executed, the operation defined by the first target instruction is executed, and the specific value of the flag bit defined by the first target instruction is calculated based on the operation result.

[0028] Step S23: Write the specific value into a pre-specified unified register according to the first flag bit mapping relationship to provide a basis for conditional branch judgment; the first flag bit mapping relationship is used to indicate the flag bit represented by each bit in the unified register.

[0029] In this embodiment of the invention, for any first target instruction, when the first target instruction is executed, the operation defined by the first target instruction is performed, and based on the result of the operation, the specific value of the flag bit defined by the first target instruction is calculated. The calculated specific value is then written into a pre-specified unified register according to the first flag bit mapping relationship.

[0030] The arithmetic operations defined by the first target instruction and the updated flag bits are determined by the instruction set design of the target architecture. The unified register can be a flag register provided by the target architecture platform, configured through the architecture design document. The bits stored in the unified register are the union of flag bits defined in at least two source architectures; that is, the unified register stores bits representing each flag bit defined in at least two source architectures, ensuring compatibility with at least two source architectures included in the specified source architecture. The first flag bit mapping relationship records each bit in the unified register and its corresponding flag bit. Accordingly, the flag bits recorded in the first flag bit mapping relationship respectively cover the flag bits defined in each of the at least two source architectures.

[0031] For any specific value of a flag bit defined by the first target instruction, the bit representing that flag bit is determined through the first flag bit mapping relationship, and the value of that bit is set to the calculated specific value. In this embodiment of the invention, when the first target instruction is executed, the arithmetic operation defined by the first target instruction is executed, and the specific value of the flag bit defined by the first target instruction is calculated based on the result of the arithmetic operation. According to the first flag bit mapping relationship, the specific value is written into a pre-specified unified register to provide a basis for conditional branch judgment. The first flag bit mapping relationship is used to indicate the flag bit represented by each bit in the unified register. In this way, it can be ensured that the flag bits stored in the unified register are updated normally during execution, thereby ensuring the correct execution of the program.

[0032] Optionally, the at least two source architectures include a first source architecture and a second source architecture; the flag bits defined in the first source architecture and the flag bits defined in the second source architecture overlap. A single bit in the unified register represents a flag bit that corresponds to a flag bit defined in the first source architecture and / or a flag bit defined in the second source architecture. In this way, compatibility simulation is performed for the first and second source architectures where the flag bits overlap, ensuring that identical flag bits in both architectures are represented by a single bit in the unified register, thereby saving hardware resources.

[0033] In one application scenario, the first source architecture can be the x86 architecture, and the second source architecture can be the ARM architecture. The x86 architecture is designed with carry flag (CF), parity flag (PF), auxiliary flag (AF), zero flag (ZF), sign flag (SF), and overflow flag (OF). These flag bits are distributed in the program status and control (EFLAGS) register designed in the x86 architecture.

[0034] Figure 2 This is a schematic diagram of the position of a flag bit provided in an embodiment of the present invention, such as... Figure 2 As shown, CF, PF, AF, ZF, SF, and OF are located in bits 0, 2, 4, 6, 7, and 11 of the EFLAGS register, respectively. The ARM architecture includes a sign flag (N), a zero flag (Z), a carry flag (C), and an overflow flag (V), which are located in the Floating-Point Status and Control Register (FPSCR) of the ARM architecture. Figure 3 This is a schematic diagram of another flag position provided in an embodiment of the present invention, such as... Figure 3 As shown, N, Z, C, and V are located at bits 31, 30, 29, and 28 of the FPSCR register, respectively.

[0035] In the flag bits of each of the two source architectures, SF in the x86 architecture is equivalent to N in the ARM architecture, both representing the sign flag. ZF in the x86 architecture is equivalent to Z in the ARM architecture, both representing the zero flag. CF in the x86 architecture is equivalent to C in the ARM architecture, both representing the carry flag. OF in the x86 architecture is equivalent to V in the ARM architecture, both representing the overflow flag. There is overlap between the ARM and x86 architectures; the specific flag bits for the ARM architecture are a subset of the flag bits for the x86 architecture.

[0036] Accordingly, the unified register in this embodiment of the invention can be configured with fields related to six flag bits based on the union of flag bits defined in the two source architectures. One field can represent one flag bit, and one field can correspond to one bit. Specifically, the 0th bit in the unified register can represent the carry flag (denoted as C), which corresponds to CF in the x86 architecture and C in the ARM architecture, respectively. It is used to indicate the overflow situation of the result during unsigned number operation. 1 indicates overflow, otherwise 0. The 1st bit in the unified register can represent the parity flag (denoted as P), which corresponds to PF in the x86 architecture. It is used to indicate the parity of the number of 1 bits in the operation result. 1 indicates an even number of 1s, otherwise 0. The 2nd bit in the unified register can represent the auxiliary flag (denoted as A), which corresponds to AF in the x86 architecture. It is used to indicate whether there is a carry / borrow situation in the 3rd bit of the operation result. The 3rd bit in the unified register can represent the zero flag (denoted as Z), which corresponds to ZF in the x86 architecture and Z in the ARM architecture. It is used to indicate whether the operation result is 0. The fourth bit of the unified register can represent the sign flag (denoted as S), which corresponds to SF in the x86 architecture and N in the ARM architecture, and is used to indicate the sign bit of the operation result. The fifth bit of the unified register can represent the overflow flag (denoted as V), which corresponds to OF in the x86 architecture and V in the ARM architecture, and is used to indicate the overflow status of the result in signed operation. 1 indicates overflow, and 0 otherwise.

[0037] The field definitions of the unified register can be shown in Table 1 below:

[0038] Table 1 Since the first 6 bits of the unified register are used to represent flag bits, their access permission can be set to Read-Write (RW). This ensures that the calculated flag values ​​can be correctly written to the corresponding bits in the unified register, and that the flag values ​​can be correctly read from the corresponding bits in the unified register. Because the last 26 bits of the unified register are reserved, their access permission can be set to Read-Only (RO). This prevents the values ​​of the last 26 bits from being modified, thus avoiding interference with normal processing logic.

[0039] In this embodiment of the invention, the effect of instructions on flag bits is defined according to Table 2 below:

[0040] Table 2 The effect of an instruction on a flag indicates whether the instruction modifies / uses the flag, and specifically how the instruction modifies the flag's value. For example, if the effect of an ADC instruction on the OF flag is represented by M, then the ADC instruction modifies the OF flag; specifically, it sets the OF flag to 0 or 1. If the effect of an OR instruction on the OF flag is represented by 0, then the OR instruction modifies the OF flag and sets it to 0.

[0041] The specific execution instructions in the primary architecture (x86 architecture) of this application scenario may include: arithmetic, logical, and shift operation instructions. For example, the specific execution instructions in the x86 architecture can be shown in Table 3 below:

[0042] Table 3 For any instruction, the effect is represented by the flag bits M, 0, and 1, which are the flag bits updated by the instruction (i.e., the defined flag bits). M indicates setting the flag to 0 or 1, 1 indicates setting the flag to 1, and --- indicates that the effect of the instruction on this flag bit is not defined. For example, for the ADD instruction in the x86 architecture, the flag bits updated by this instruction include: carry flag, parity flag, auxiliary flag, zero flag, sign flag, and overflow flag.

[0043] Furthermore, due to the existence of sub-register operations in the x86 architecture, there are four register types in x86: B (8-bit), H (16-bit), W (32-bit), and D (64-bit). Correspondingly, the same instruction in x86 can be divided into instructions with register lengths of 8 bits, 16 bits, 32 bits, and 64 bits. That is, any instruction in Table 3 can be specifically divided into instructions with register types B (8-bit), H (16-bit), W (32-bit), and D (64-bit). For example, the ADC instruction can be divided into ADC_B, ADC_H, ADC_W, and ADC_D. Accordingly, since each instruction needs to correspond to one of the four register types, the number of instruction types represented in Table 3 is 18 × 4 = 72.

[0044] The specific execution instructions in the second source architecture (ARM architecture) in this application scenario may include some arithmetic and logic instructions. For example, the specific execution instructions in the ARM architecture can be shown in Table 4 below:

[0045] Table 4 Furthermore, sub-register operations in the ARM architecture include two register types: W (32-bit) and D (64-bit). Correspondingly, the same instruction in the ARM architecture can be divided into instructions with 32-bit and 64-bit register lengths; that is, any instruction in Table 4 can be specifically divided into two register types: W (32-bit) and D (64-bit). For example, the ADCS instruction can be specifically divided into ADCS_W and ADCS_D. Accordingly, the number of instruction types represented in Table 4 is 8 × 2 = 16.

[0046] Therefore, if the x86 architecture and ARM architecture are simulated separately, then 72 + 16 = 88 instructions are needed.

[0047] In this example, the ADD instruction in the x86 architecture and the ADDS instruction in the ARM architecture have matching semantics and update the same flags (the flags updated by the ADD instruction include C, P, A, Z, S, and V, while the flags updated by the ADDS instruction include C, Z, S, and V). Since the flags updated by the ADD instruction include those updated by the ADDS instruction, the updated flags are considered to match. Specifically, most ARM instructions that affect flags are the same as those in x86 (i.e., semantically and in terms of updated flags).

[0048] For example, by consulting the instruction set manual for the ARM architecture, the semantics of each instruction and the updated flags in the ARM architecture can be determined. Simultaneously, by consulting the instruction set manual for the x86 architecture, the semantics of each instruction and the updated flags in the x86 architecture can be determined. This allows for finding instructions whose semantics and updated flags match in both architectures. Alternatively, one instruction in the ARM architecture can be executed in an ARM architecture test environment, and one instruction in the x86 architecture test environment can be executed. The execution results of the two instructions can be compared. If the results match, and the instruction is read from the registers, the value of the floating-point status and control register (e.g., FPSCR) used to store flags in the ARM architecture can be obtained, along with the updated flags such as N, Z, and C in the FPSCR. Similarly, by reading the instruction from the registers, the value of the program status control register (e.g., EFLAGS) used to store flags in the x86 architecture can be obtained, along with the updated flags such as CF and AF in the EFLAGS. If the execution results of the two instructions are consistent, and the updated flag in FPSCR is consistent with the updated flag in EFLAGS, then the semantics of the two instructions and the updated flags are determined to be consistent.

[0049] For example, the semantics of the EORS instruction in the ARM architecture and the XOR instruction in x86 are identical, both representing XOR calculations. Furthermore, the effects on the flag bits detected by the above method are identical, meaning they can be mapped to the same intermediate instruction. The semantics of the BICS instruction in the ARM architecture are relatively complex, but ultimately, the AND operation on the operands affects the flag bits. Therefore, the semantics of the BICS instruction in the ARM architecture and the OR instruction in x86 are identical, and the updated flag bits are identical, meaning they can be mapped to the same intermediate instruction. The semantics of the CMP instruction in the ARM architecture are identical to the SUB subtraction instruction in x86, and the updated flag bits are identical. The CMN instruction in the ARM architecture is also a subtraction instruction, but its semantics involve first inverting the subtrahend bit by bit, setting the carry to 1, and finally adding the minuend, the inverted subtrahend, and the carry to 1.

[0050] In the x86 architecture, there is no instruction whose semantics and updated flag bits match those of the CMN instruction in the ARM architecture. Therefore, an intermediate instruction can be mapped to the CMN instruction in the ARM architecture. Specifically, the mapping relationship between the predefined intermediate instruction and the source instruction set can be shown in Table 5 below:

[0051] Table 5 Instructions from different source architectures within the same source instruction set are all translated into the same intermediate instruction. Because the x86 architecture has four register types—B (8-bit), H (16-bit), W (32-bit), and D (64-bit)—while the ARM architecture only has two register types—32-bit and 64-bit—the mapping between intermediate instructions and source instruction sets is as follows: Except for BT_CMN, which only includes instructions with register types W (32-bit) and D (64-bit) for the ARM architecture, all other intermediate instructions are divided into four register types: B (8-bit), H (16-bit), W (32-bit), and D (64-bit).

[0052] Accordingly, the number of intermediate instruction types represented in Table 5 is 15×4+1×2=62. These 62 intermediate instructions independently simulate both the x86 and ARM architectures. This embodiment of the invention simulates both the first and second source architectures uniformly, reducing the number of instructions by (88-62) / 88=30%, effectively decreasing the instruction count. Consequently, technicians only need to develop for a smaller number of instructions and design the corresponding instructions in the target architecture. Therefore, development difficulty and workload can be reduced. Simultaneously, reducing instruction coding redundancy makes the instruction code more compact, thereby simplifying the control logic and reducing the processor's processing complexity. Furthermore, compared to designing a flag register and corresponding flag simulation instructions for a single source architecture, the microarchitecture design in this embodiment only requires a unified register, thus simplifying hardware design and avoiding redundancy. By using a unified register and a set of flag simulation instructions to unify matching instructions across multiple source architectures, the overhead of flag simulation in binary translation can be effectively reduced, optimizing binary translation.

[0053] For any intermediate instruction in the mapping relationship between intermediate instructions and source instruction groups, the semantics of the intermediate instruction are consistent with the semantics of the instructions in the corresponding source instruction group, and the flags updated by the intermediate instruction include the flags updated by all instructions in the corresponding source instruction group. That is, the flags updated by the intermediate instruction are the union of the flags updated by all instructions in the corresponding source instruction group. For example, taking the BT_ADD instruction, the flags updated by the ADD instruction in the x86 architecture include: C, P, A, Z, S, V, while the flags updated by the ADDS instruction in the ARM architecture include: S, Z, C, V. Accordingly, in the union of the two, the flags updated by the BT_ADD instruction include C, P, A, Z, S, V.

[0054] In this embodiment of the invention, an intermediate instruction is used as the key, and a source instruction group is used as the value, forming a first mapping relationship that is constructed and stored in key-value pairs. The first mapping relationship can be stored in a first designated storage location, which can be pre-specified by a technician; this embodiment of the invention does not impose any restrictions on this. For any instruction to be translated in the program to be translated, the instruction to be translated is compared with the instructions in each source instruction group in the first mapping relationship to determine whether the instruction to be translated is a specific execution instruction. For example, the opcode of the instruction to be translated can be compared with the opcodes of the instructions in each source instruction group. If an instruction with the same opcode as the instruction to be translated exists, then the instruction to be translated is determined as a specific execution instruction in the program to be translated. Further, the source instruction group containing the instruction with the same opcode as the instruction to be translated can be determined as the first source instruction group, and the intermediate instruction in the mapping relationship corresponding to the first source instruction group can be determined as the first intermediate instruction.

[0055] For example, assuming the program to be translated is an x86 architecture program, the instruction to be translated is the ADD instruction, and the instruction to be translated belongs to the source instruction group {ADD, ADDS}, then the source instruction group {ADD, ADDS} can be identified as the first source instruction group. The intermediate instruction BT_ADD corresponding to this first source instruction group is identified as the first intermediate instruction. Assuming the program to be translated is an ARM architecture program, and the specific execution instruction to be translated is the ADDS instruction, the opcode of the ADDS instruction can be compared with the opcodes of the instructions in each source instruction group in the first mapping relationship. If there is an instruction in the source instruction group whose opcode matches the opcode of the ADDS instruction, then that source instruction group is identified as the first source instruction group. The intermediate instruction corresponding to the first source instruction group is read from the first mapping relationship to obtain the first intermediate instruction. For example, since there is an instruction in the source instruction group {ADD, ADDS} whose opcode matches the opcode of the ADDS instruction, the source instruction group {ADD, ADDS} is identified as the first source instruction group, and the intermediate instruction BT_ADD corresponding to this first source instruction group is identified as the first intermediate instruction.

[0056] Alternatively, the opcodes of all specific execution instructions in a specified source architecture can be pre-recorded to form a preset opcode set. The opcode of the instruction to be translated is compared with the opcodes in each preset opcode set. If an instruction with a matching opcode exists, the instruction to be translated is identified as a specific execution instruction in the program to be translated. Further, the opcode of this specific execution instruction can be compared with the opcodes of instructions in each source instruction group. The source instruction group with an opcode matching the instruction to be translated is identified as the first source instruction group. Further, the intermediate instruction corresponding to the first source instruction group in this mapping relationship can be identified as the first intermediate instruction.

[0057] Optionally, embodiments of the present invention may further include: for other instructions in the program to be translated, translating them according to the conventional process of the binary translator corresponding to the program to be translated. Specifically, in the method of comparing the opcode of the instruction to be translated with the opcodes of the instructions in each source instruction group, if there is no instruction that matches the opcode of the instruction to be translated, that is, the instruction to be translated is not a specific execution instruction, then the instruction to be translated is determined to be another instruction in the program to be translated. In the method of comparing the opcode of the instruction to be translated with the opcodes in each preset opcode set, if there is no instruction that matches the opcode of the instruction to be translated, then the instruction to be translated is determined to be another instruction in the program to be translated.

[0058] Optionally, in this embodiment of the invention, the step of translating the first intermediate instruction into a first target instruction adapted to the target architecture may specifically include: Step 1031: Load the mapping relationship between intermediate instructions and target instruction groups corresponding to the target architecture; one intermediate instruction corresponds to one target instruction group.

[0059] Step 1032: From the mapping relationship between the intermediate instruction and the target instruction group, find the target instruction group corresponding to the first intermediate instruction, and take the instruction in the target instruction group as the first target instruction.

[0060] In this embodiment of the invention, a corresponding target instruction group can be defined for each intermediate instruction. The target instruction group includes one or more instructions adapted to the target architecture. The function implemented by the instructions in the target instruction group is consistent with the function implemented by the instructions in the source instruction group corresponding to the intermediate instruction after binary translation.

[0061] The instructions included in the target instruction set can be existing instructions in the instruction set of the target architecture, or they can be newly added instructions (i.e., extended instructions) to achieve multi-architecture adaptation. This embodiment of the invention does not impose any restrictions on this. The extended instructions corresponding to intermediate instructions can be applied only to the binary translator to avoid the burden of instruction set compatibility.

[0062] The mapping relationship between intermediate instructions and target instruction sets (hereinafter referred to as the second mapping relationship) can be predefined by an engineer for the target architecture. For example, the second mapping relationship can be constructed and stored in key-value pairs, using intermediate instructions as keys and target instruction sets as values. Since different architectures have different instruction set designs, second mapping relationships are pre-set for different architectures, and the architecture identifier is stored corresponding to the second mapping relationship set for that architecture. The second mapping relationship can be stored in a second designated storage location, which can be pre-specified by an engineer; this embodiment of the invention does not impose any restrictions on this. Accordingly, the binary translator can read the second mapping relationship corresponding to the architecture identifier of the target architecture from the second designated storage location. The first intermediate instruction is compared with each key name in the second mapping relationship, and all instructions included in the key values ​​corresponding to the matching key names are taken as the first target instruction.

[0063] Taking the Loongson architecture as an example, for the intermediate instruction BT_ADD_B, the target instruction group can be set to include the EXADD.B instruction; for the intermediate instruction BT_ADD_H, the target instruction group can be set to include the EXADD.H instruction; for the intermediate instruction BT_ADD_W, the target instruction group can be set to include the EXADD.W instruction; and for the intermediate instruction BT_ADD_D, the target instruction group can be set to include the EXADD.D instruction. Assuming the first intermediate instruction is BT_ADD_B, the instruction EXADD.B found in the target instruction group can be identified as the first target instruction.

[0064] The instruction formats for EXADD.B, EXADD.H, EXADD.W, and EXADD.D can be: exadd.b rj,rk, exadd.h rj,rk, exadd.w rj,rk, and exadd.d rj,rk.

[0065] When these four instructions are executed on the target architecture platform, they respectively perform addition operations of byte, half-word, word, and double-word lengths, and set the value of the unified register according to the result of the addition operation.

[0066] In this embodiment of the invention, updating the flag bit refers to determining the specific value of each flag bit based on the calculation result and the calculation method of each flag bit, and assigning the specific value to the corresponding bit in the unified register.

[0067] For example, when the designed first target instruction exadd.b rj,rk is executed on the target architecture platform, it implements the following processing logic: tmp_s[8:0] = signed(GR[rj][7:0]) + signed(GR[rk][7:0]) / / Treat the lower 8 bits of the two source registers as signed integers and perform addition.

[0068] tmp_u[8:0] = unsigned(GR[rj][7:0]) + unsigned(GR[rk][7:0]) / / Treat the lower 8 bits of the two source registers as unsigned integers and perform addition.

[0069] FLAG.C = tmp_u[8] / / Take the 8th bit (most significant bit) of the unsigned operation result tmp_u[8:0] and set it to the value of the corresponding flag bit in the unified register, that is, assign it to the 0th bit of the unified register. If tmp_u[8] is 1, it means that the addition of two 8-bit unsigned integers has produced a carry, that is, an unsigned overflow has occurred.

[0070] FLAG.S = tmp_s[7] / / Take the 7th bit of the signed operation result tmp_s[8:0] (i.e. the sign bit of the signed addition operation result), set it to the value of the corresponding flag bit in the unified register, i.e., assign it to the 4th bit of the unified register.

[0071] FLAG.V = (tmp_s[8]!=tmp_s[7]) ? 1 : 0 / / Compare the 8th bit (sign extension bit) and the 7th bit (sign bit) of the signed addition result. If the 8th bit and the 7th bit are not equal (indicating a signed addition overflow), set the value of the corresponding flag bit of the overflow flag in the unified register (i.e., the 5th bit of the unified register) to 1. Otherwise, set it to 0.

[0072] FLAG.Z = (tmp_s[7:0]==0) ? 1 : 0 / / If the lower 8 bits of the signed addition result are all 0, set the value of the flag bit corresponding to the zero flag in the unified register (i.e., the 3rd bit of the unified register) to 1; otherwise, set it to 0.

[0073] FLAG.P = (PCNT (tmp_s[7:0])%2==0) ? 1 :0 / / Calculate the number of 1s in the lower 8 bits of the addition result. If the number of 1s is even, set the value of the corresponding flag bit of the parity flag in the unified register (i.e., the first bit of the unified register) to 1. Otherwise, set it to 0.

[0074] FLAG.A = (has carry or borrow out of GR[rk][4]) ? 1 : 0 / / Check if there is a carry / borrow from bit 3 to bit 4 during addition. If so, set the value of the corresponding flag bit in the auxiliary flag register (i.e., bit 2 of the unified register) to 1. Otherwise, set it to 0.

[0075] Assuming the lower 8 bits of the two source registers are 01010000 and 01100000 respectively, the signed result of the addition operation is tmp_s[8:0]=010110000, and the unsigned result is tmp_u[8:0]=010110000. Since tmp_u[8]=0, the 0th bit (C flag) of the unified register is updated to 0, indicating that no carry was generated when adding unsigned integers. Since tmp_s[7] represents the sign bit of the signed addition result, and the 4th bit (S flag) of the unified register is used to indicate the sign bit of the result, in this example, when tmp_s[7]=1, the 4th bit (S flag) of the unified register is set to 1. Since tmp_s[8]=0 and tmp_s[7]=1, they are not equal, so the 5th bit (V flag) of the unified register is set to 1, indicating that there is an overflow when adding signed integers. Since the lower 8 bits of tmp_s[7:0] are not all 0, the 3rd bit (Z flag) of the unified register is set to 0, indicating that the result of the operation is not 0. Since the number of 1s in tmp_s[7:0] is not even, the 1st bit (P flag) of the unified register is set to 0, indicating that the result of the operation has an odd number of 1s. Since there is no carry / borrow from the 3rd bit to the 4th bit during the addition operation, the 2nd bit (A flag) of the unified register is set to 0, indicating that there is no carry / borrow in the 3rd bit.

[0076] In this way, the operation and flag update can be completed with a single target instruction, thereby reducing the processing overhead of the binary translator.

[0077] When the designed exadd.h rj,rk is executed on the target architecture platform, it implements the following processing logic: tmp_s[16:0] = signed(GR[rj][15:0]) + signed(GR[rk][15:0]) / / Treat the lower 16 bits of the two source registers as signed integers and perform addition.

[0078] tmp_u[16:0] = unsigned(GR[rj][7:0]) + unsigned(GR[rk][7:0]) / / Treat the lower 16 bits of the two source registers as unsigned integers and perform addition.

[0079] FLAG.C = tmp_u

[16] / / Take the 16th bit (most significant bit) of the unsigned operation result tmp_u[15:0] and set it to the value of the corresponding flag bit in the unified register. If tmp_u

[16] is 1, it means that the addition of two 16-bit unsigned integers has produced a carry, that is, an unsigned overflow has occurred.

[0080] FLAG.S = tmp_s

[15] / / Take the 15th bit of the signed operation result tmp_s[15:0] (i.e. the sign bit of the signed addition operation result) and set it to the value of the corresponding flag bit in the unified register.

[0081] FLAG.V = (tmp_s

[16] !=tmp_s

[15] ) ? 1 : 0 / / Compare the 16th bit (sign extension bit) and the 15th bit (sign bit) of the signed addition result. If the 16th bit and the 15th bit are not equal (indicating a signed addition overflow), set the value of the corresponding flag bit in the unified register to 1. Otherwise, set it to 0.

[0082] FLAG.Z = (tmp_s[15:0]==0) ? 1 : 0 / / If the lower 16 bits of the signed addition result are all 0, set the value of the corresponding flag bit of the zero flag in the unified register to 1; otherwise, set it to 0.

[0083] FLAG.P = (PCNT (tmp_s[7:0])%2==0) ? 1 :0 / / Calculate the number of 1s in the lower 8 bits of the addition result. If the number of 1s is even, set the value of the corresponding flag bit of the parity flag in the unified register to 1; otherwise, set it to 0.

[0084] FLAG.A = (has carry or borrow out of GR[rk][4]) ? 1 : 0 / / Check if there is a carry / borrow from bit 3 to bit 4 during addition. If so, set the value of the corresponding flag bit in the auxiliary flag in the unified register to 1; otherwise, set it to 0.

[0085] Correspondingly, when exadd.w rj,rk and exadd.d rj,rk are executed on the target architecture platform, the processing logic is similar to that described above, and will not be repeated here.

[0086] Because x86 and ARM architecture instructions correspond to the same intermediate instructions, their flag bits match. For example, the x86 architecture's ADD instruction updates the following flag bits: C, P, A, Z, S, V, while the ARM architecture's ADDS instruction updates the following flag bits: S, Z, C, V. Therefore, after the target instruction provided by the Loongson platform (e.g., exadd.w) is executed, it can ensure that the updated flag bits are the union of the two (C, P, A, Z, S, V), specifically including the flag bits (C, P, A, Z, S, V) required by the x86 architecture instruction and the flag bits (S, Z, C, V) required by the ARM architecture instruction, thus achieving compatibility.

[0087] Understandably, in another implementation, target instructions can be designed separately for each source architecture. The mapping relationship between intermediate instructions and target instruction sets corresponding to the target architecture includes the mapping relationship between intermediate instructions and target instruction sets set for each source architecture.

[0088] For example, mapping relationships between intermediate instructions and target instruction groups can be set for x86 and ARM architectures respectively. For instance, for the x86 architecture, for the intermediate instruction BT_ADD_W, the target instruction group can be set to include the X86ADD.W instruction. For the intermediate instruction BT_ADD_D, the target instruction group can be set to include the X86ADD.D instruction. The X86ADD.W and X86ADD.D instructions implement the same logic as the aforementioned EXADD.W and EXADD.D instructions. For instance, intermediate instructions can be used as keys, and the target instruction group set for those intermediate instructions can be used as keys to construct key-value pairs. These key-value pairs are stored in a second specified storage location based on the storage instruction. The key-value pairs stored in the second specified storage location constitute the mapping relationship between intermediate instructions and target instruction groups. Subsequently, the mapping relationship between intermediate instructions and target instruction groups can be loaded from the second specified storage location using a load instruction to find the first target instruction.

[0089] For the ARM architecture, the target instruction set can be set to include the ARMADD.W instruction for the intermediate instruction BT_ADD_W. Similarly, the target instruction set can be set to include the ARMADD.D instruction for the intermediate instruction BT_ADD_D. The designed ARMADD.W instruction, when executed on the target architecture platform, implements the following processing logic: res_s[32:0] = signed(GR[rj][31:0]) + signed(GR[rk][31:0]) / / Treat the lower 32 bits of the two source registers as signed integers and perform addition.

[0090] res _u[8:0] = unsigned(GR[rj][31:0]) + unsigned(GR[rk][31:0]) / / Treat the lower 31 bits of the two source registers as unsigned integers and perform addition.

[0091] FLAG.C = res_u

[32] / / Take the 32nd bit (most significant bit) of the unsigned operation result res_u[23:0] and set it to the value of the corresponding flag bit in the unified register, that is, assign it to the 0th bit of the unified register.

[0092] FLAG.S = res_s

[31] / / Take the 31st bit of the signed operation result res_s[32:0] (i.e. the sign bit of the signed addition operation result), set it to the value of the corresponding flag bit in the unified register, i.e., assign it to the 4th bit of the unified register.

[0093] FLAG.V = res_s

[32] != res_s

[31] ) ? 1 : 0 / / Compare the 32nd bit (sign extension bit) and the 31st bit (sign bit) of the signed addition result. If the 32nd bit and the 31st bit are not equal (indicating a signed addition overflow), set the value of the corresponding flag bit of the overflow flag in the unified register (i.e., the 5th bit of the unified register) to 1. Otherwise, set it to 0.

[0094] FLAG.Z = (res _s[31:0]==0) ? 1 : 0 / / If the lower 32 bits of the signed addition result are all 0, set the value of the flag bit corresponding to the zero flag in the unified register (i.e., the 3rd bit of the unified register) to 1; otherwise, set it to 0.

[0095] Accordingly, the mapping relationship between intermediate instructions and target instruction groups, which is set for the source architecture of the program to be translated, can be loaded to find and load the mapping relationship between intermediate instructions and target instruction groups corresponding to the target architecture. This mapping relationship is stored in a second specified storage location in the form of key-value pairs.

[0096] In this embodiment of the invention, by loading the mapping relationship between intermediate instructions and target instruction groups corresponding to the target architecture, the target instruction group corresponding to the first intermediate instruction is found by comparing the intermediate instructions with the instructions in the target instruction group in the mapping relationship. Thus, the translated first target instruction can be obtained. This ensures the efficiency of obtaining instructions that can be executed on the target architecture, thereby improving the overall processing efficiency.

[0097] Optionally, embodiments of the present invention may further include the following steps: Step S31: For any flag saving instruction in the program to be translated, find the intermediate instruction corresponding to the flag saving instruction from the predefined mapping relationship between flag saving instructions and intermediate instructions, and use it as the second intermediate instruction.

[0098] Step S32: Translate the second intermediate instruction into a second target instruction adapted to the target architecture; the second target instruction is used to extract the flag bit defined by the first target instruction from the unified register according to the first flag bit mapping relationship, and save the flag bit to the first storage location according to the second flag bit mapping relationship of the source architecture.

[0099] In this embodiment of the invention, the first flag bit mapping relationship is used to characterize each bit in the unified register and its corresponding flag bit, and the second flag bit mapping relationship is used to characterize the bits in the registers of the source architecture and their corresponding flag bits. The mapping method between the bits and flag bits of the unified register in the target architecture may differ from that of the registers in the source architecture. For example, the distribution of flag bits in the unified register may differ from the distribution of flag bits in x86's EFLAGS and the order of flag bits in ARM's FPSCR. Therefore, directly using the value of the unified register will lead to obtaining incorrect flag bit values.

[0100] For example, in the aforementioned example, the first flag bit mapping relationship can be: [Carry flag, bit 0], [Parity flag, bit 1], [Auxiliary flag, bit 2], [Zero flag, bit 3], [Sign flag, bit 4], [Overflow flag, bit 5], and stored in a predetermined storage location. In the first source architecture (x86 architecture), the flag bits of the carry flag, parity flag, auxiliary flag, zero flag, sign flag, and overflow flag correspond to bits 0, 2, 4, 6, 7, and 11 of the EFLAGS register, respectively. Correspondingly, the second flag bit mapping relationship in the source architecture (x86 architecture) can be: [Carry flag, bit 0], [Parity flag, bit 2], [Auxiliary flag, bit 4], [Zero flag, bit 6], [Sign flag, bit 7], [Overflow flag, bit 11]. In the second source architecture (ARM architecture), the sign flag, zero flag, carry flag, and overflow flag correspond to bits 28, 29, 30, and 31 of the FPSCR register, respectively. Correspondingly, the second flag mapping relationship in the source architecture (ARM architecture) can be: [sign flag, bit 31], [zero flag, bit 30], [carry flag, bit 29], [overflow flag, bit 28]. During the simulation process of this embodiment, the carry flag, parity flag, auxiliary flag, zero flag, sign flag, and overflow flag correspond to bits 0, 1, 2, 3, 4, and 5 of the unified register, respectively. The second flag mapping relationships corresponding to the two architectures are stored in a third designated storage location in the form of a mapping table. This third designated storage location can be pre-specified by a technician, and this embodiment does not impose any restrictions on it.

[0101] The program to be translated may contain flag saving instructions. These instructions are used to extract defined flags and save them to a first storage location. The defined flags and the first storage location can be determined by the instruction design, and this embodiment of the invention does not impose any limitations on this. For example, the flag saving instruction can be a PUSHF instruction. In the flag saving instruction of the program to be translated in the first source architecture, the defined flags can be carry flag, parity flag, auxiliary flag, zero flag, sign flag, and overflow flag. In the flag saving instruction of the program to be translated in the second source architecture, the defined flags can be sign flag, zero flag, carry flag, and overflow flag. The first storage location can be memory, stack, etc. The flag saving instruction to intermediate instruction mapping relationship (hereinafter referred to as the third mapping relationship) records the intermediate instructions corresponding to the flag saving instructions in each source architecture.

[0102] For example, in the third mapping relationship, the intermediate instruction corresponding to the flag bit saving instruction in the first source architecture can be X86_MFFLAG, and the intermediate instruction corresponding to the flag bit saving instruction in the second source architecture can be ARM_MFFLAG. The X86_MFFLAG and ARM_MFFLAG instructions can be called flag bit extraction simulation instructions, used to extract flag bits from the unified register according to the first flag bit mapping relationship, and save the flag bits to the first storage location according to the second flag bit mapping relationship of the source architecture. The flag bits in the unified register can be the flag bits defined by the first target instruction.

[0103] When the binary translator saves the simulated flag register (i.e., when it encounters a flag save instruction), it can extract the mapping relationship between the simulated instruction and the target instruction according to the flags, and find the target instruction corresponding to the second intermediate instruction as the second target instruction. For example, x86_MFFLAG corresponds to the target instruction x86mfflag, and ARM_MFFLAG corresponds to the target instruction armmfflag. Assuming the second intermediate instruction is x86_MFFLAG, the corresponding second target instruction can be found by loading the instruction and calling the third mapping relationship, i.e., translating it into the x86mfflag rd, mask instruction. The flags defined by the second target instruction match the flags defined by the flag save instruction. For example, the flags defined by the second target instruction can include all flags of the source architecture of the program to be translated.

[0104] When the x86mfflag instruction is executed, the following processing logic can be implemented, where the processing logic can be predefined and set by the technician: tmpl[5:0] = FLAG[5:0]&mask[5:0] / / Extract the lower 6 bits of the unified register and store them in a temporary variable.

[0105] GR[rd] = 0 / / Clear the first storage location (i.e., GR[rd]) to zero.

[0106] GR[rd][0] = tmpl[0] / / Write the 0th bit (i.e. the carry flag) of the temporary variable to the 0th bit of the first storage location.

[0107] GR[rd][2] = tmpl[1] / / Write the first bit (i.e. parity flag) of the temporary variable to the second bit of the first storage location.

[0108] GR[rd][4] = tmpl[2] / / Write the second bit (i.e., auxiliary flag) of the temporary variable to the fourth bit of the first storage location.

[0109] GR[rd][6] = tmpl[3] / / Write the 3rd bit (i.e. the zero flag) of the temporary variable to the 6th bit of the first storage location.

[0110] GR[rd][7] = tmpl[4] / / Write the 4th bit (i.e., the symbol flag) of the temporary variable to the 7th bit of the first storage location.

[0111] GR[rd]

[11] = tmpl[5] / / Write the 5th bit (i.e. overflow flag) of the temporary variable to the 11th bit of the first storage location.

[0112] It is understandable that for a flag saving instruction where the defined flag bits are partial flag bits, the flag bits defined by the corresponding second target instruction are also partial flag bits. Accordingly, the processing logic of the second target instruction can be set with a mask for extracting only the partial flag bits. For example, assuming the flag saving instruction is an STC instruction, the flag bits defined by the flag saving instruction only include the carry flag. Accordingly, the mask can be set to: mask[000001]. Based on this mask, the carry flag bit located at the 0th bit can be extracted. Only the carry flag represented by the STC instruction is saved through this carry flag bit.

[0113] In this embodiment of the invention, for any flag-saving instruction in the program to be translated, an intermediate instruction corresponding to that flag-saving instruction is found as a second intermediate instruction. The second intermediate instruction is translated into a second target instruction adapted to the target architecture. This second target instruction is used to extract the flags defined by the first target instruction from the unified register according to the first flag-mapped relationship, and save the flags to the first storage location according to the second flag-mapped relationship of the source architecture. This ensures that the flags placed in the first storage location conform to the rules of the source architecture, thereby ensuring that the program to be translated from the source architecture can correctly identify the flags when executed, thus avoiding execution anomalies.

[0114] Optionally, embodiments of the present invention may further include the following steps: Step S41: For any flag recovery instruction in the program to be translated, find the intermediate instruction corresponding to the flag recovery instruction from the predefined mapping relationship between flag recovery instructions and intermediate instructions, and use it as the third intermediate instruction.

[0115] Step S42: Translate the third intermediate instruction into a third target instruction adapted to the target architecture; the third target instruction is used to extract the flag bit from the second storage location according to the second flag bit mapping relationship, and restore the flag bit to the unified register according to the first flag bit mapping relationship.

[0116] In this embodiment of the invention, the program to be translated may contain a flag bit recovery instruction. This instruction is used to extract defined flag bits from a second storage location and restore them to a unified register. The defined flag bits and the second storage location can be determined by the instruction design, and this embodiment of the invention does not impose any limitations on this. The second storage location can be the same as the first storage location described above. For example, the flag bit saving instruction can be a POPF instruction. In the flag bit recovery instruction of the program to be translated in the first source architecture, the defined flag bits can be carry flag, parity flag, auxiliary flag, zero flag, sign flag, and overflow flag. In the flag bit recovery instruction of the program to be translated in the second source architecture, the defined flag bits can be sign flag, zero flag, carry flag, and overflow flag. The second storage location can be memory, stack, etc. The flag bit recovery instruction-intermediate instruction mapping relationship (hereinafter referred to as the fourth mapping relationship) records the intermediate instructions corresponding to the flag bit recovery instructions in each source architecture.

[0117] For example, in the fourth mapping relationship, the intermediate instruction corresponding to the flag bit recovery instruction in the first source architecture can be X86_MTFLAG, and the intermediate instruction corresponding to the flag bit recovery instruction in the second source architecture can be ARM_MTFLAG. The X86_MTFLAG and ARM_MTFLAG instructions can also be called flag bit update simulation instructions, which are used to extract the flag bit from the second storage location according to the second flag bit mapping relationship of the source architecture, and restore the flag bit to the unified register according to the first flag bit mapping relationship.

[0118] When the binary translator restores the simulated flag register (i.e., when it encounters a flag restore instruction), it can extract the update instruction and target instruction mapping relationship according to the flag bits, and find the target instruction corresponding to the third intermediate instruction as the third target instruction. For example, X86_MTFLAG corresponds to the target instruction x86mtflag, and ARM_MTFLAG corresponds to the target instruction armmtflag. Assuming the third intermediate instruction is X86_MTFLAG, the corresponding third target instruction can be found by calling the fourth mapping relationship through the load instruction, i.e., it can be translated into the x86mtflag rd, mask instruction. The flag bits defined by the third target instruction match the flag bits defined by the flag restore instruction. For example, the flag bits defined by the third target instruction can include all flag bits of the source architecture to which the program to be translated belongs.

[0119] When the x86mtflag instruction is executed, it can: extract the lower 6 bits of the second storage location and store them in a temporary variable; write the 0th bit (carry flag) of the temporary variable to the 0th bit of the unified register; write the 2nd bit (parity flag) of the temporary variable to the 1st bit of the unified register; write the 4th bit (auxiliary flag) of the temporary variable to the 2nd bit of the unified register; write the 6th bit (zero flag) of the temporary variable to the 3rd bit of the unified register; write the 7th bit (sign flag) of the temporary variable to the 4th bit of the unified register; and write the 11th bit (overflow flag) of the temporary variable to the 5th bit of the unified register. It can be understood that for a flag recovery instruction where the defined flag bits are partial flag bits, the corresponding third target instruction also defines partial flag bits. Accordingly, the processing logic of the third target instruction can be set with a mask for extracting only partial flag bits. For example, assuming that the flag bits defined by the flag bit recovery instruction only include the carry flag, then the mask can be set to: mask[000001]. According to this mask, the carry flag bit located at the 0th bit can be extracted, and the carry flag bit can be restored to the unified register only through this carry flag bit.

[0120] Figure 4 This is a schematic diagram illustrating a binary translator processing example provided by an embodiment of the present invention, for the SUB instruction in the x86 architecture (i.e. Figure 4 In X86_SUB, the CMP instruction in the ARM architecture (i.e., ... Figure 4 In the binary translator, since both the ARM_CMP and x86_SUB instructions belong to the same source instruction group, they both correspond to the first intermediate instruction BT_SUB. Therefore, during the binary translator's processing, when a specific execution instruction in the program to be translated is identified as an x86_SUB instruction, the first intermediate instruction found from the mapping relationship between intermediate instructions and source instruction groups is the BT_SUB instruction. Conversely, when a specific execution instruction in the program to be translated is identified as an ARM_CMP instruction, both the ARM_CMP and x86_SUB instructions are used as source instruction groups, and the first intermediate instruction found from the mapping relationship between intermediate instructions and source instruction groups is the BT_SUB instruction. That is, both types of instructions will be translated into the first intermediate instruction BT_SUB by the ARMTranslator and x86Translator respectively. The first intermediate instruction (i.e., the BT_SUB instruction) is translated into the first target instruction adapted to the target architecture. When the target instruction corresponding to the BT_SUB instruction (i.e., the first target instruction) is executed, a subtraction operation is performed based on the values ​​of the two source registers (SRC1 and SRC2), and the flag bit stored in the unified register (i.e., the FLAG register) is updated based on the result of the subtraction operation.

[0121] For the program to be translated using the x86 architecture, the intermediate instruction corresponding to the flag saving instruction in the program is found from the predefined mapping relationship between flag saving instructions and intermediate instructions: the x86_MFFLAG instruction. By executing the second target instruction corresponding to the x86_MFFLAG instruction, the flag bits are extracted from the unified register according to the first flag bit mapping relationship, and then saved to the first storage location according to the second flag bit mapping relationship of the x86 architecture. In this way, when it is necessary to save the simulated flag bit register, it is achieved by saving it through the x86_MFFLAG instruction, ensuring that the flag bits placed in the first storage location conform to the rules of the x86 architecture (i.e., follow the distribution order of the flag bits in the x86_EFLAGS register). Furthermore, the intermediate instruction corresponding to the flag bit recovery instruction in the program to be translated can be found from the predefined mapping relationship between flag bit recovery instructions and intermediate instructions: the X86_MTFLAG instruction. By executing the third target instruction corresponding to the X86_MTFLAG instruction, the flag bit is extracted from the second storage location according to the second flag bit mapping relationship of the X86 architecture, and the flag bit is restored to the unified register (i.e., the FLAG register) according to the first flag bit mapping relationship. In this way, when it is necessary to restore the simulated flag bit register, it can be restored by the X86_MTFLAG instruction to ensure that the flag bit placed in the unified register conforms to the simulation rules.

[0122] For the program to be translated using the ARM architecture, the intermediate instruction corresponding to the flag saving instruction in the program is found from the predefined mapping relationship between flag saving instructions and intermediate instructions: the ARM_MFFLAG instruction. By executing the second target instruction corresponding to the ARM_MFFLAG instruction, the flag bits are extracted from the unified register according to the first flag bit mapping relationship, and the flag bits are saved to the first storage location according to the second flag bit mapping relationship of the ARM architecture. In this way, when it is necessary to save the simulated flag bit register, it can be achieved by using the ARM_MFFLAG instruction to ensure that the flag bits placed in the first storage location conform to the rules of the ARM architecture (i.e., follow the distribution order of the flag bits in the ARM_FPSCR register). Furthermore, the intermediate instruction corresponding to the flag bit recovery instruction in the program can be found from the predefined mapping relationship between flag recovery instructions and intermediate instructions: the ARM_MTFLAG instruction. By executing the third target instruction corresponding to the ARM_MTFLAG instruction, the flag bits are extracted from the second storage location according to the second flag bit mapping relationship of the ARM architecture, and the flag bits are restored to the unified register (i.e., the FLAG register) according to the first flag bit mapping relationship. In this way, when it is necessary to restore the simulated flag register, it can be done through the ARM_MTFLAG instruction to ensure that the flags placed in the unified register conform to the simulation rules.

[0123] In this embodiment of the invention, for any flag bit recovery instruction in the program to be translated, an intermediate instruction corresponding to the flag bit update instruction is found as a third intermediate instruction. The third intermediate instruction is translated into a third target instruction adapted to the target architecture. The third target instruction is used to extract the flag bit from the second storage location according to the second flag bit mapping relationship of the source architecture, and restore the flag bit to the unified register according to the first flag bit mapping relationship. This ensures that the flag bit placed in the unified register conforms to the simulation rules, thereby ensuring that subsequent flag bit saving operations can proceed normally.

[0124] Reference Figure 5 The diagram illustrates a block diagram of an instruction processing apparatus provided in an embodiment of the present invention, such as... Figure 5 As shown, the instruction processing device may specifically include: The identification module 201 is used to identify specific execution instructions in any program to be translated for a specified source architecture; the specified source architecture includes at least two source architectures. The first lookup module 202 is used to look up the intermediate instruction corresponding to the first source instruction group from the predefined mapping relationship between intermediate instructions and source instruction groups as the first intermediate instruction; wherein, the first source instruction group is associated with the specific running instruction; each source instruction group includes instructions of at least two source architectures, and the semantics and updated flag bits of the instructions are matched respectively. The first translation module 203 is used to translate the first intermediate instruction into a first target instruction adapted to the target architecture, so as to obtain the translation result of the specific running instruction; the operation implemented in the first target instruction and the updated flag bit are respectively matched with the operation implemented in the instruction in the first source instruction group and the updated flag bit.

[0125] Optionally, the device further includes: The processing module is configured to execute the arithmetic operation defined by the first target instruction when the first target instruction is executed, and calculate the specific value of the flag bit defined by the first target instruction based on the result of the arithmetic operation; The writing module is used to write the specific value into a pre-specified unified register according to the first flag bit mapping relationship, so as to provide a basis for conditional branch judgment; the first flag bit mapping relationship is used to indicate the flag bit represented by each bit in the unified register.

[0126] Optionally, the at least two source architectures include: a first source architecture and a second source architecture; the flag bits defined in the first source architecture and the flag bits defined in the second source architecture have an intersection; The flag bit represented by a bit in the unified register corresponds to the flag bit defined in the first source architecture and / or the flag bit defined in the second source architecture.

[0127] Optionally, the first translation module 203 is specifically used for: Load the mapping relationship between intermediate instructions and target instruction groups corresponding to the target architecture; one intermediate instruction corresponds to one target instruction group. From the mapping relationship between intermediate instructions and target instruction groups, find the target instruction group corresponding to the first intermediate instruction, and use the instruction in the target instruction group as the first target instruction.

[0128] Optionally, the device further includes: The second search module is used to search for any flag-saving instruction in the program to be translated, and find the intermediate instruction corresponding to the flag-saving instruction from the predefined mapping relationship between flag-saving instructions and intermediate instructions as the second intermediate instruction. The second translation module is used to translate the second intermediate instruction into a second target instruction adapted to the target architecture; the second target instruction is used to extract the flag bit defined by the first target instruction from the unified register according to the first flag bit mapping relationship, and save the flag bit to the first storage location according to the second flag bit mapping relationship of the source architecture.

[0129] Optionally, the device further includes: The third lookup module is used to find, from the predefined mapping relationship between flag bit recovery instructions and intermediate instructions, any flag bit recovery instruction in the program to be translated, the intermediate instruction corresponding to the flag bit recovery instruction as the third intermediate instruction. The third translation module is used to translate the third intermediate instruction into a third target instruction adapted to the target architecture; the third target instruction is used to extract the flag bit from the second storage location according to the second flag bit mapping relationship, and restore the flag bit to the unified register according to the first flag bit mapping relationship.

[0130] Optionally, the device further includes: The fourth translation module is used to translate other instructions in the program to be translated according to the conventional process of the binary translator corresponding to the program to be translated.

[0131] In summary, the instruction processing apparatus provided in this embodiment of the invention identifies specific execution instructions in any program to be translated from a specified source architecture. The specified source architecture includes at least two source architectures. From a predefined mapping relationship between intermediate instructions and source instruction groups, the intermediate instruction corresponding to the first source instruction group is searched as the first intermediate instruction. The first source instruction group corresponds to a specific execution instruction. Each source instruction group includes instructions from at least two source architectures, and the semantics and updated flag bits in the instructions match. The first intermediate instruction is translated into a first target instruction adapted to the target architecture to obtain the translation result of the specific execution instruction. The operations implemented and the updated flag bits in the first target instruction match the operations implemented and the updated flag bits in the instructions of the first source instruction group, respectively. Thus, by converting the specific execution instructions in the program to be translated from the source architecture into first intermediate instructions and translating the first intermediate instructions into first target instructions adapted to the target architecture, the semantics of the specific execution instructions can be accurately simulated by executing the first target instructions, and the updated flag bits can be simulated during execution, thereby ensuring that the program can run correctly. Furthermore, in this embodiment of the invention, instructions that match the semantics and updated flag bits in at least two source architectures are divided into a source instruction group, and an intermediate instruction is set for each source instruction group. This allows for unified simulation of at least two source architectures. Compared to designing a set of flag bit simulation instructions for a single source architecture, this eliminates some redundant flag bit simulation instructions, thereby avoiding the problem of redundant instruction coding and simplifying the control logic.

[0132] Reference Figure 6 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Figure 6 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus.

[0133] The processor, the memory, and the communication interface communicate with each other via the communication bus; the memory stores executable instructions, which cause the processor to execute the instruction processing method of the aforementioned embodiments. The executable instructions can form a program.

[0134] This invention provides a machine-readable medium storing instructions that, when executed by one or more processors, enable the processors to perform the instruction processing method described in the foregoing embodiments. The machine-readable medium may be one or more processors.

[0135] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0136] The foregoing has provided a detailed description of an instruction processing method, an instruction processing device, an electronic device, and a readable medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the device and its core ideas. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An instruction processing method, characterized in that, The method includes: For any program to be translated based on a specified source architecture, identify specific execution instructions within the program to be translated; the specified source architecture includes at least two source architectures; From the predefined mapping relationship between intermediate instructions and source instruction groups, the intermediate instruction corresponding to the first source instruction group is found as the first intermediate instruction; wherein, the first source instruction group corresponds to the specific execution instruction; each source instruction group includes instructions from at least two source architectures, and the semantics and updated flag bits in the instructions are matched respectively; The first intermediate instruction is translated into a first target instruction adapted to the target architecture to obtain the translation result of the specific execution instruction; the operation implemented in the first target instruction and the updated flag bit are respectively matched with the operation implemented in the instruction in the first source instruction group and the updated flag bit.

2. The method according to claim 1, characterized in that, The method further includes: When the first target instruction is executed, the operation defined by the first target instruction is executed, and the specific value of the flag bit defined by the first target instruction is calculated based on the operation result. According to the first flag bit mapping relationship, the specific value is written into the pre-specified unified register to provide a basis for conditional branch judgment; the first flag bit mapping relationship is used to indicate the flag bit represented by each bit in the unified register.

3. The method according to claim 2, characterized in that, The at least two source architectures include: a first source architecture and a second source architecture; the flag bits defined in the first source architecture and the flag bits defined in the second source architecture have an intersection; The flag bit represented by a bit in the unified register corresponds to the flag bit defined in the first source architecture and / or the flag bit defined in the second source architecture, respectively.

4. The method according to claim 1, characterized in that, The step of translating the first intermediate instruction into a first target instruction adapted to the target architecture includes: Load the mapping relationship between intermediate instructions and target instruction groups corresponding to the target architecture; one intermediate instruction corresponds to one target instruction group. From the mapping relationship between intermediate instructions and target instruction groups, find the target instruction group corresponding to the first intermediate instruction, and use the instruction in the target instruction group as the first target instruction.

5. The method according to claim 2, characterized in that, The method further includes: For any flag saving instruction in the program to be translated, find the intermediate instruction corresponding to the flag saving instruction from the predefined mapping relationship between flag saving instructions and intermediate instructions, and use it as the second intermediate instruction; The second intermediate instruction is translated into a second target instruction adapted to the target architecture; the second target instruction is used to extract the flag bit defined by the first target instruction from the unified register according to the first flag bit mapping relationship, and save the flag bit to the first storage location according to the second flag bit mapping relationship of the source architecture.

6. The method according to claim 5, characterized in that, The method further includes: For any flag recovery instruction in the program to be translated, find the intermediate instruction corresponding to the flag recovery instruction from the predefined mapping relationship between flag recovery instructions and intermediate instructions, and use it as the third intermediate instruction; The third intermediate instruction is translated into a third target instruction adapted to the target architecture; the third target instruction is used to extract the flag bit from the second storage location according to the second flag bit mapping relationship, and restore the flag bit to the unified register according to the first flag bit mapping relationship.

7. The method according to claim 1, characterized in that, The method further includes: For other instructions in the program to be translated, the translation is performed according to the standard process of the binary translator corresponding to the program to be translated.

8. An instruction processing device, characterized in that, The device includes: The identification module is used to identify specific execution instructions in any program to be translated for a specified source architecture; the specified source architecture includes at least two source architectures. The first lookup module is used to find the intermediate instruction corresponding to the first source instruction group from the predefined mapping relationship between intermediate instructions and source instruction groups as the first intermediate instruction; wherein, the first source instruction group is associated with the specific execution instruction; each source instruction group includes instructions of at least two source architectures, and the semantics and updated flag bits of the instructions are matched respectively; The first translation module is used to translate the first intermediate instruction into a first target instruction adapted to the target architecture, so as to obtain the translation result of the specific running instruction; the operation implemented in the first target instruction and the updated flag bit are respectively matched with the operation implemented in the instruction in the first source instruction group and the updated flag bit.

9. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store executable instructions that cause the processor to perform the method as described in any one of claims 1 to 7.

10. A machine-readable medium, characterized in that, It stores instructions that, when executed by one or more processors, cause the processors to perform the method as described in any one of claims 1 to 7.

Images