An instruction cache prefetch method, device and processor based on FDIP

Abstract

The application discloses a kind of instruction cache prefetching method, device and processor based on FDIP, utilize branch prediction unit in predicting future fetch block and write FDIP queue, not only provide the address of the fetch block, but also based on current group PC, path history register PHR or global history register GHR, query dynamic prefetch depth prediction table, provide a corresponding prefetch depth for the fetch block.FDIP queue is subsequently based on current fetch pointer position, the position of target fetch block in queue and the prefetch depth carried by the target fetch block, determine whether to trigger instruction prefetch, effectively improve the timeliness, accuracy and resource utilization efficiency of FDIP prefetch.

Description

Technical Field

[0001] This invention relates to the technical field of processor microarchitecture, specifically to an instruction cache prefetching method, apparatus, and processor based on FDIP, which can be applied to instruction access optimization in processor front-end branch prediction units, instruction fetch units, L1 instruction caches, and multi-level cache systems. Background Technology

[0002] With the development of server applications, cloud computing applications, and large-scale software systems, the working set of program instructions continues to increase, making it difficult for the L1 instruction cache to hold all the hot-swappable code for extended periods. When the instruction cache line accessed by the processor front end is not in the L1 instruction cache, an instruction cache miss occurs, causing a pause in the instruction fetch pipeline, which in turn affects the continuous supply of decode, issue, and execute units. Therefore, how to reduce the front-end pause caused by instruction cache misses is a crucial issue in the design of modern high-performance processors.

[0003] In existing technologies, FDIP is a common instruction prefetching mechanism. This mechanism utilizes a branch prediction unit that runs before the instruction fetch unit to predict the address of future fetch blocks in advance and writes the predicted fetch blocks into the FDIP Queue. The instruction fetch unit subsequently accesses the instruction cache based on this queue. At the same time, the FDIP mechanism can initiate instruction prefetching in advance based on future fetch blocks in the queue, thereby hiding some instruction cache miss latency.

[0004] However, traditional FDIP schemes typically employ fixed depth, fixed window, or uniform strategies to prefetch future instruction blocks. For example, when there are several future instruction blocks in the FDIP queue, the system may initiate prefetching according to a fixed queue depth, fixed distance, or fixed number. This type of scheme has the following problems: First, the latency of missing services varies for different instruction blocks. Some instruction blocks may typically return from the L2 cache, requiring a smaller lead time; others may frequently return from the L3 cache or main memory, requiring earlier prefetching. A uniform prefetch depth cannot simultaneously meet the timeliness requirements of different target instruction blocks.

[0005] Second, different prediction paths have varying stability. For certain fetch blocks determined by specific branch history or path history, prefetching is usually effective; however, for fetch blocks with significant path changes, premature or excessively deep FDIP prefetching may fall on the wrong path, resulting in invalid prefetching and instruction cache pollution.

[0006] Third, fixed-depth FDIP struggles to simultaneously ensure both timeliness and accuracy in prefetching. When the prefetch depth is too shallow, the prefetch may not have returned by the time the request arrives, resulting in late prefetching. When the prefetch depth is too deep, the prefetched line may have been replaced before it is actually used, or it may have occupied other useful instruction cache lines, causing premature prefetching and cache pollution.

[0007] Fourth, existing FDIPs typically focus on "which future fetch blocks to predict," but lack a mechanism to dynamically determine "how far in advance to prefetch" for each predicted fetch block. Even if the branch prediction unit can predict future fetch paths, without dynamic prefetch depth control related to specific fetch blocks and path history, a large number of untimely or invalid prefetches may still occur.

[0008] Therefore, there is an urgent need for an improved instruction prefetching mechanism based on FDIP, which enables the branch prediction unit to provide a dynamic prefetch depth related to the fetch block and its path history when predicting future fetch blocks, and to continuously maintain this depth through prefetch result feedback, thereby improving the timeliness, accuracy and resource utilization efficiency of FDIP prefetching. Summary of the Invention

[0009] To address the aforementioned problems, the present invention aims to propose an instruction cache prefetching method, apparatus, and processor based on FDIP. By improving the instruction prefetching mechanism based on FDIP, the branch prediction unit can simultaneously provide a dynamic prefetch depth related to the fetch block and its path history when predicting future fetch blocks, and continuously maintain this depth through prefetch result feedback, thereby improving the timeliness, accuracy, and resource utilization efficiency of FDIP prefetching.

[0010] This was achieved through the following technical solutions: First, a method for instruction cache prefetching based on FDIP is proposed, including the following steps: S1. The branch prediction unit calculates the PDT index based on the current fetch block group PC and path history information, and queries the dynamic prefetch depth prediction table PDT to obtain the prefetch depth and confidence of the predicted fetch block. S2. Write the predicted fetch block address, prefetch depth, confidence level, and PDT index as entries into the FDIP queue; S3. The prefetch condition detection unit scans the FDIP queue. When the prefetch depth of the target instruction block is greater than or equal to its queue distance from the current instruction fetch pointer, the confidence level reaches a preset threshold, prefetching has not yet been initiated, the corresponding instruction cache line is not in the first-level instruction cache / prefetch queue / MSHR, and the resource is available, the trigger condition is determined to be met. S4. Write the instruction cache line corresponding to the target fetch block that meets the conditions into the prefetch queue, initiate a prefetch request when MSHR is idle, and mark the corresponding FDIP table entry as initiated prefetching; S5. After the prefetch returns, write the instruction cache line to the first-level instruction cache, set the prefetch flag, and save the PDT index. S6. When fetching instructions in the future, if the target instruction fetch block is already in the L1 instruction cache and the prefetch flag is valid, the PDT entry is located according to the saved PDT index and the corresponding confidence level is increased. If the target instruction fetch block is not in the L1 instruction cache but there is already a corresponding prefetch request in the MSHR or prefetch queue, the PDT entry is located based on the PDT index stored therein, and the corresponding confidence and prefetch depth are increased. If the target fetch block that has been prefetched is determined to be in an incorrect prediction path, the PDT entry is located based on the PDT index in the FDIP entry and the corresponding confidence level is reduced.

[0011] Optionally, when calculating the PDT index in step S1, the PDT index is obtained by hashing the current fetch block group PC and the path history information: pdt_index=hash(group_pc,PHR / GHR); the PDT tag is obtained by performing operations on a portion of the current fetch block group PC and the folded path history information: pdt_tag=partial(group_pc,folded PHR); where group_pc is the current fetch block group PC, PHR is the path history register, and GHR is the global history register.

[0012] Optionally, each entry in the FDIP queue stores at least: the target fetch block address, prefetch depth, confidence level, prefetch initiation status flag, PDT index, and PDT tag.

[0013] Optionally, in step S3, when determining whether the instruction cache line corresponding to the target fetch block already has a corresponding prefetch request in the prefetch queue or MSHR, confirmation is made by comparing the prefetch source information stored in the prefetch queue and MSHR with the address and PDT index of the target fetch block; the prefetch source information includes at least the address and PDT index of the target fetch block.

[0014] Optionally, when a prefetch request is initiated in step S4, the PDT index and PDT tag corresponding to the prefetch request are saved in the prefetch queue and MSHR; after the prefetch returns, the corresponding PDT entry is located according to the PDT index and PDT tag, and the PDT index is saved in the instruction cache line for subsequent prefetch validity judgment to locate the corresponding PDT entry for update and maintenance.

[0015] Optionally, when increasing the confidence level of the corresponding PDT entry in step S6, the prefetch depth remains unchanged.

[0016] Optionally, when increasing the confidence level of the corresponding PDT entry and increasing its prefetch depth in step S6, an increment operation is performed on the confidence level and the prefetch depth.

[0017] Optionally, when reducing the confidence level of the corresponding entry in PDT in step S6, a self-decrease operation is performed on the confidence level.

[0018] Secondly, an instruction cache prefetching device based on FDIP is proposed, which operates using the aforementioned instruction cache prefetching method, including: The path history register is used to record branch direction information, path information, or instruction fetch path information; The branch prediction unit, connected to the path history register, is used to predict future fetch blocks based on the path history information provided by the current fetch block group PC and the path history register. The Dynamic Prefetch Depth Prediction Table (PDT) connects the branch prediction unit and the path history register. It is used to index the corresponding prediction fetch block based on the group PC and path history information, and output the prefetch depth and confidence of the corresponding prediction fetch block. The FDIP queue connects the branch prediction unit and the PDT, and is used to store the address of each prediction fetch block and its corresponding prefetch depth, confidence level and PDT index; The prefetch condition detection unit is connected to the FDIP queue, the L1 instruction cache, the prefetch queue, and the MSHR, respectively. It is used to scan the FDIP queue and determine whether to trigger prefetching based on the prefetch depth, confidence, queue distance, and cache occupancy status. The prefetch queue, connected to the prefetch condition detection unit, is used to receive prefetch requests and temporarily store the address of the instruction cache line to be prefetched and its corresponding PDT index. MSHR, the connection prefetch queue, is used to track incomplete prefetch requests and their corresponding PDT indexes; The update maintenance unit is connected to the FDIP queue, prefetch queue, MSHR and level 1 instruction cache respectively, and is used to update the confidence and prefetch depth of each entry in the PDT according to the prefetch return status and subsequent fetch hit status.

[0019] In addition, a processor is proposed for running computer programs, which execute the instruction cache prefetching method described above during program execution. The advantages of this invention compared to the traditional FDIP mechanism are: First, this invention can provide different dynamic prefetch depths for different predicted finger-fetching blocks. Traditional FDIP typically uses a fixed depth or fixed window for prefetching, while this invention, through a dynamic prefetch depth prediction table, enables each finger-fetching block to have an independent prefetch depth under a specific group PC and path history context, thereby better adapting to the missing latency and path behavior of different target blocks.

[0020] Second, this invention can improve prefetch timeliness. For fetch blocks that frequently experience late prefetching, the system gradually increases their depth through late_score and feedback update mechanisms, enabling the fetch block to trigger prefetching earlier in the FDIP Queue, thereby increasing the probability that it returns to the L1 instruction cache before being accessed.

[0021] Third, this invention can reduce premature prefetching and cache pollution. For instruction cache lines that have been prefetched but replaced before use, the system uses an premature prefetch feedback mechanism (e.g., reducing the prefetch depth and confidence of the fetch block) to make subsequent prefetches closer to the actual usage point, thus avoiding premature occupation of the L1 instruction cache space.

[0022] Fourth, this invention can suppress erroneous path prefetching. Since the dynamic prefetch depth prediction table is indexed by both group PC and PHR / GHR, it can distinguish prefetching behavior under different path historical contexts; at the same time, erroneous path prefetching will reduce the useful_conf of the corresponding table entries, thereby reducing invalid FDIP prefetching on unstable paths.

[0023] Fifth, the implementation overhead of this invention is low. This scheme does not require establishing complex historical access backtracking relationships, nor does it require searching the historical buffer to find the trigger source after a missing return. Its main new structures are a dynamic prefetch depth prediction table, several additional fields in the FDIP Queue entry, and prefetch feedback update logic, making it suitable for integration with existing BPU, FTB, FDIPQueue, and I-cache front-end structures.

[0024] Sixth, this invention retains the engineering advantages of FDIP. FDIP was originally able to use the branch prediction unit to generate future fetch flow in advance. This invention adds dynamic prefetch depth prediction on this basis, so that FDIP not only knows "which blocks to fetch in the future", but also knows "how far in advance each block should be prefetched", thereby achieving a better balance between coverage, timeliness, accuracy and hardware overhead. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the main components of the device; Figure 2 The process is triggered by prefetching the predicted path; Figure 3 The process of updating the target index block advance distance and confidence is described. Detailed Implementation

[0026] The technical solutions in the embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0027] See Figure 1The schematic diagram shows that this invention adds a Dynamic Prefetch Depth Prediction Table (PDT) to the traditional FDIP prefetch architecture and expands the data structures of the FDIP queue, instruction cache, prefetch queue, and MSHR. The core workflow of the entire device is as follows: When the Branch Prediction Unit (BPU) predicts a future fetch block, it queries the PDT based on the path history information provided by the current fetch block group PC and the path history register to obtain the dynamic prefetch depth and confidence level corresponding to the predicted fetch block; then, it writes the predicted fetch block address and its corresponding prefetch depth, confidence level, and PDT index into the FDIP queue; the prefetch condition detection unit scans the FDIP queue and determines whether to trigger prefetching based on the prefetch depth, confidence level, and cache system status carried by each fetch block; after prefetching returns, the update and maintenance unit updates the corresponding entries in the PDT based on the validity and timeliness of the prefetch, thereby achieving adaptive adjustment of the prefetch depth.

[0028] In this embodiment, the Branch Prediction Unit (BPU) is used to predict future fetch blocks based on the current fetch block group PC, branch history, BTB / FTB, direction predictor, indirect branch predictor, and return address stack (RAS). In this invention, the BPU is responsible for generating the predicted fetch flow to the FDIP queue. Each time the BPU predicts a future fetch block, it triggers a query operation on the PDT to obtain the dynamic prefetch depth and confidence level corresponding to that fetch block. The BPU can be implemented using various existing branch predictors; its internal direction prediction, target prediction, and indirect branch prediction logic do not need to be modified for this invention. It only needs to provide the currently used group PC and path history information to the PDT as index input while outputting the predicted fetch block address.

[0029] The Path History Register (PHR) or Global History Register (GHR) is used to record the most recent branch direction, path information, or instruction fetch path information. Conventional BPUs already use this historical information for direction prediction, target prediction, or FTB indexing. This invention reuses this historical information as one of the index inputs for the Prefetch Depth Table (PDT), eliminating the need for an additional historical record structure and thus controlling hardware overhead. In specific implementations, the PHR can record the jump direction (take / don't take) of the most recent N branches, the GHR can record the global branch history pattern, and the folded PHR is the path history information after folding and compressing the PHR. This historical information, together with the groupPC, is used to generate the PDT index and labels to distinguish the prefetch behavior of the same instruction fetch block under different path history contexts. The PDT index is generated jointly by the groupPC, the Global History Register (PHR) / Path History Register (GHR), and the currently executing thread ID. In a multi-threaded processor environment, introducing the thread ID as an index input can isolate the prefetch behavior of different threads, avoiding mutual interference caused by multiple threads sharing the same PDT entry, and effectively improving the accuracy of prefetch depth prediction.

[0030] In this embodiment, the specific implementation of the Dynamic Prefetch Depth Prediction Table (PDT) mainly includes the following three aspects: 1) Hardware Structure: The Dynamic Prefetch Depth Prediction Table (PDT) is a new core structure in this invention, located inside the BPU or on the front-end path near the BPU / FDIP queue. The PDT can be implemented using a content-addressable storage structure, such as associative memory or a hash table. The PDT contains multiple entries, each storing at least: an index (or tag), a prefetch depth value (depth), and a confidence value (useful_conf). In specific implementations, the PDT can be implemented using an SRAM array, and the number of entries can be determined according to the design requirements of the processor front-end, for example, 128, 256, or 512 entries. The size of the PDT determines the number of contexts (group PCs, path history) it can track; a larger size allows for more granular differentiation of instruction block prefetching behavior, but also increases hardware overhead.

[0031] 2) Index Generation Logic: When the BPU predicts a fetch block, this invention calculates the PDT index based on the current fetch block group PC and path history information. Specifically, the PDT index is obtained by hashing the group PC and PHR / GHR: pdt_index = hash(group_pc, PHR / GHR). This hash operation can be implemented using conventional hash operations such as XOR, shift, and folding, with the aim of mapping the group PC and path history information to the PDT index space. The PDT tag is obtained by operating on a partial bit of the group PC and the folded path history information: pdt_tag = partial(group_pc, foldedPHR). This tag is used to distinguish different input contexts when hash collisions occur, ensuring that entries under the same index in different contexts can be correctly identified. Through the above index and tag generation methods, this invention can distinguish the prefetching behavior of the same fetch block under different path history contexts, allowing the same fetch block address to have different dynamic prefetch depths under different program execution paths.

[0032] 3) PDT Output: PDT performs a query based on the input index and label, outputting the prefetch depth (depth) and confidence (useful_conf) stored in the hit table entry. The prefetch depth indicates how far in advance the fetch block should be prefetched, and the confidence indicates the reliability of the prefetch depth value. If PDT misses, preset initial values ​​can be used as the prefetch depth and confidence for the fetch block. For example, the prefetch depth can be set to a default value (e.g., 4 or 8 fetch block distances), and the confidence can be set to an initial threshold level. These initial values ​​can be determined through simulation or actual testing based on the specific processor's cache latency characteristics.

[0033] The FDIP queue (also known as the Fetch Target Queue) is used to store the future fetch block sequence predicted in advance by the BPU. Unlike traditional FDIP queues, each entry in the FDIP queue of this invention needs to additionally store the prefetch depth (predicted_depth), confidence level (useful_conf), and a status flag indicating whether a prefetch has been issued for each fetch block. Furthermore, to support subsequent maintenance and updates of the PDT (Programming Target Depth), each entry also needs to store the PDT index and PDT tag. Specifically, each entry in the FDIP queue contains at least the following fields: target fetch block address, prefetch depth, confidence level, prefetch initiation status flag, PDT index, and PDT tag. The prefetch depth is used by the prefetch condition detection unit to determine when to trigger a prefetch for the fetch block; the confidence level is used to assist in determining whether it is worthwhile to initiate a prefetch for the fetch block; the prefetch initiation status flag is used to prevent the same fetch block from being repeatedly requested for prefetching; the PDT index and PDT tag are used to locate the corresponding PDT entry for feedback updates after the prefetch returns. The depth of the FDIP queue can be determined according to the actual needs of the processor front end, such as setting it to 32 items, 64 items or more. A deeper queue can accommodate longer prediction paths, which is beneficial for discovering far-away prefetching opportunities in advance.

[0034] The prefetch condition detection unit is a key module connecting the FDIP queue and the actual prefetch initiation logic. Its function is to truly translate the prefetch depth predicted by the PDT into an execution decision of "whether to initiate prefetching". The prefetch condition detection unit continuously scans or selects each entry in the FDIP queue and performs condition judgments on each fetch block that has not yet initiated prefetching.

[0035] Specific judgment conditions include: distance condition, confidence condition, initiation state condition, cache existence condition, and resource availability condition.

[0036] The distance condition stipulates that the distance (distance_to_head) between the target fetch block's position in the FDIP queue and the current fetch pointer's queue distance should be less than or equal to the predicted depth (predicted_depth) carried by the target fetch block. This condition ensures that the interval between the prefetch timing and the actual access timing of the target fetch block is sufficient to hide cache miss latency. If the prefetch depth is greater than the queue distance, it means that the fetch block is still far from being actually accessed, and initiating a prefetch too early may cause the prefetched line to be replaced from the cache before it is actually used, resulting in cache pollution. If the prefetch depth is less than the queue distance, the prefetch request may return before it is needed, which means that initiating a prefetch too late may lead to a late prefetch.

[0037] The confidence threshold requires that the confidence level (useful_conf) carried by the target fetch block must reach a preset threshold. This threshold can be flexibly configured according to processor design requirements, for example, set to a value of 2, 4, or 8. A higher threshold means that the system has stricter requirements for prefetch validity; only fetch blocks that have been verified to be valid multiple times will trigger prefetching, which helps to suppress invalid prefetching on faulty paths. A lower threshold, on the other hand, makes the system more proactive in initiating prefetching, which is beneficial for covering more potential cache misses, but may introduce more invalid prefetching.

[0038] The initiation status condition is that the target fetch block has not yet been prefetched. This condition is achieved by checking the prefetch initiation status flag in the FDIP table entry, which is used to avoid the same fetch block being repeatedly prefetched, thereby saving prefetch queue and MSHR resources.

[0039] The cache existence condition is that the instruction cache line corresponding to the target fetch block is not currently in the Level 1 Instruction Cache (L1I), nor in the Prefetch Queue (PQ) or MSHR. If the instruction cache line is already in the L1I, no prefetching is required; if a corresponding prefetch request is already being processed or waiting to be processed in the prefetch queue or MSHR, no further prefetching request is required. This condition is achieved by querying the tags in the L1I, the prefetch queue, and the prefetch address information stored in the MSHR.

[0040] The resource availability condition is that the system has available prefetch resources (resource_available), including free entries in the prefetch queue, free entries in MSHR, and the memory system being able to accept new prefetch requests. This condition ensures that prefetch requests are not blocked due to insufficient resources, avoiding resource contention and interference caused by prefetch requests to normal instruction fetch missing processing.

[0041] When all the above conditions are met, the prefetch condition detection unit determines that the prefetch trigger condition is met, outputs the prefetch trigger signal, and transmits the corresponding target fetch block information to the prefetch queue.

[0042] See Figure 2 The diagram shown illustrates the prefetching triggering process for the predicted path. The specific implementation of the prefetching triggering process is as follows: S1. The Branch Prediction Unit (BPU) predicts the address of the next fetch block based on the current fetch pointer and path history information, and simultaneously calculates the PDT index and queries the PDT. The PDT returns the prefetch depth and confidence level corresponding to the predicted fetch block to the BPU.

[0043] S2, BPU will write the predicted address of the fetch block, the prefetch depth and confidence returned by PDT, as well as the PDT index and label, as a new entry to the tail of the FDIP queue.

[0044] S3. The prefetch condition detection unit scans each entry in the FDIP queue and makes judgments based on the distance condition, confidence condition, initiation status condition, cache existence condition, and resource availability condition described above. If a target instruction fetch block meets all the triggering conditions, the prefetch condition detection unit writes the instruction cache line address corresponding to the target instruction fetch block into the prefetch queue.

[0045] S4. After receiving a prefetch request, the prefetch queue initiates a prefetch request to the memory system if there are idle resources in the MSHR, and simultaneously marks the FDIP entry as initiated. The prefetch queue and MSHR need to store the PDT index and PDT tag corresponding to the prefetch request so that the corresponding PDT entry can be located and updated after the prefetch returns. In addition, the prefetch queue and MSHR also need to store the address of the target fetch block, used to match the corresponding prefetch request upon prefetch return and to determine whether a prefetch request is being processed during subsequent fetches.

[0046] S5. If the target fetch block does not meet the distance condition or confidence condition, the prefetch condition detection unit will not initiate prefetching. The FDIP entry will remain in the queue. As the current fetch pointer moves forward, the queue distance will decrease. The entry may meet the distance condition in subsequent scans and trigger prefetching.

[0047] See Figure 3 The diagram illustrates the target fetch block advance distance and confidence update process. The PDT update and maintenance rely on FDIP entries, the prefetch queue, MSHR, and source information stored in the L1 instruction cache. This invention dynamically adjusts the confidence and prefetch depth of corresponding entries in the PDT based on the actual effect after the prefetch return, specifically including the following scenarios: Firstly, the update method when prefetching is timely and effective: After the prefetch request returns, the target instruction cache line is written to the first-level instruction cache, and a prefetch flag (isPrefetched=1) is set in the cache line. The PDT index and PDT tag corresponding to the prefetch request are also saved in the cache line's metadata. Subsequently, when the instruction fetching unit accesses the target instruction block normally, if it finds that the instruction block is already in the first-level instruction cache and its prefetch flag is valid, it indicates that the prefetch was timely and effective—the prefetch request has already filled the first-level instruction cache with data before the actual instruction fetch requirement arrives, successfully hiding the cache miss latency.

[0048] At this point, the update maintenance unit locates the corresponding entry in the PDT based on the PDT index and PDT tag stored in the instruction cache line, and performs a confidence increment operation on that entry, while maintaining the prefetch depth. The increased confidence indicates that the prefetch behavior of this instruction block in the current path's historical context has been validated as effective. When encountering the same context subsequently, the system's trust in this prefetch depth value increases. This positive feedback mechanism allows repeatedly validated prefetch configurations to achieve higher confidence, thus triggering prefetches more stably.

[0049] Secondly, the update method when the prefetch target is valid but the depth is insufficient: When the target fetch block is accessed during subsequent normal instruction fetching, if it is found that the fetch block is not in the first-level instruction cache, but the prefetch request corresponding to the fetch block already exists in the MSHR or prefetch queue (i.e., the prefetch has been issued but has not yet returned), it means that the target of this prefetch is valid (the fetch block will indeed be accessed), but the prefetch depth is set too shallow - the time of prefetch initiation is too close to the actual instruction fetch demand, so that the demand access has arrived before the prefetch is completed.

[0050] At this point, the update maintenance unit locates the corresponding entry in the PDT based on the PDT index and PDT tag stored in the MSHR or prefetch queue. It then performs a confidence++ operation on this entry and a depth++ operation on its prefetch depth. Increasing the prefetch depth means that when this fetch block encounters the same path history context again, it will trigger a prefetch at an earlier position in the FDIP queue (i.e., a queue position farther from the current fetch pointer), thus allowing a more sufficient time window for prefetch return and improving the timeliness of the next prefetch. Increasing the confidence indicates that although the current prefetch depth is set too shallow, the prefetch direction of this fetch block is correct, making it worthwhile to continue prefetching this fetch block after increasing the depth.

[0051] Third, the update method during erroneous path prefetching: If a prefetch has been issued, but the subsequent path is determined to be an incorrectly predicted path (i.e., the direction predicted by the branch prediction unit is inconsistent with the actual execution direction, causing the previously predicted fetch flow to be discarded), then the fetch block corresponding to the relevant prefetch request in the FDIP is not actually on the real program execution path. At this time, the update maintenance unit locates the corresponding entry in the PDT based on the PDT index and PDT tag stored in the FDIP entry that has initiated the prefetch, and performs a confidence reduction operation (i.e., decrement operation) on that entry. The decrease in confidence indicates that the prefetch behavior in the current path historical context of the fetch block has been verified as invalid, and the system's trust in the prefetch depth value decreases when encountering the same context later. When the confidence continues to decrease and falls below a preset threshold, the prefetch condition detection unit will no longer initiate a prefetch for that fetch block, thereby suppressing invalid prefetches on fetch blocks with unstable paths and reducing instruction cache pollution.

[0052] Through the aforementioned multiple feedback update mechanisms, each entry in the PDT can continuously learn and adapt to the optimal prefetch depth of the fetch block under different path history contexts during program execution, thereby achieving adaptive adjustment of the prefetch depth.

[0053] Furthermore, this also includes scenarios where prefetching is replaced before use (early prefetching). When a cache line replacement occurs in the Level 1 Instruction Cache (I-Cache), it checks whether the replaced cache line contains a fetch block that has been prefetched but never actually accessed. If so, it is determined that the fetch block has been prefetched prematurely. In this case, the system triggers feedback update logic, reducing the predicted depth of the fetch block in the corresponding PDT entry, for example, by decrementing the current depth value by 1 (depth--) or scaling it down proportionally (e.g., multiplying by 0.5), so that its subsequent prefetch initiation time is closer to the actual usage time. At the same time, it reduces the confidence of the entry or increments the early_score counter to record the history of over-prefetching of the fetch block. When the confidence is lower than a preset eviction threshold, the PDT entry can be marked as invalid or preferentially overwritten by a new entry. The above mechanism ensures that the system can adaptively adjust the prefetch lead, avoiding premature filling of the Level 1 cache and replacement with invalid entries, thereby improving cache utilization.

[0054] In the FDIP-based instruction cache prefetching device provided by this invention, the connections and signal transmission relationships between the various parts are as follows: The path history register is connected to both the branch prediction unit and the PDT, providing them with path history information. The branch prediction unit is connected to the PDT and provides the group PC to the PDT when predicting future instruction fetch blocks. The PDT is connected to the branch prediction unit and the FDIP queue, passing the queried prefetch depth and confidence level to the branch prediction unit and writing it to the FDIP queue along with the predicted instruction fetch block address.

[0055] The FDIP queue is connected to the prefetch condition detection unit, providing it with the fetch block address, prefetch depth, confidence level, and initiation status stored in each entry. The prefetch condition detection unit is connected to the FDIP queue, the L1 instruction cache, the prefetch queue, and the MSHR, respectively. It comprehensively determines whether the triggering condition is met by querying the status of these storage structures, and outputs the fetch block address that is determined to meet the condition to the prefetch queue.

[0056] The prefetch queue is connected to the MSHR, passing prefetch requests and their corresponding PDT indexes to the MSHR for tracking. The MSHR is connected to the memory system and is responsible for managing the filling and return of incomplete prefetch requests. The update and maintenance unit is connected to the FDIP queue, prefetch queue, MSHR, and L1 instruction cache, respectively. It reads prefetch source information (including PDT index, PDT tag, target address, etc.) from these structures, locates the PDT entries accordingly, and performs confidence and prefetch depth update operations.

[0057] Through the above connections, the entire device forms a complete closed loop of prediction-writing-judgment-prefetching-feedback-update, realizing the adaptive advance distance instruction prefetching function based on the branch jump history path.

[0058] In summary, this invention provides each predicted fetch block with an independent prefetch depth related to its path history context through a Dynamic Prefetch Depth Prediction Table (PDT). The prefetch depth is then transformed into an actual prefetch triggering decision through a prefetch condition detection unit. Furthermore, three feedback update mechanisms are used to continuously maintain and adjust the confidence level and prefetch depth of each entry in the PDT. This allows the prefetch depth to adaptively adapt to the cache miss latency characteristics and path stability characteristics of different fetch blocks under different execution paths, thereby achieving a better balance between prefetch timeliness, accuracy, and cache resource utilization efficiency, demonstrating significant progress.

[0059] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solutions based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. A method for instruction cache prefetching based on FDIP, characterized in that, Includes the following steps: S1. The branch prediction unit calculates the PDT index based on the current fetch block group PC and path history information, and queries the dynamic prefetch depth prediction table PDT to obtain the prefetch depth and confidence of the predicted fetch block. S2. Write the predicted fetch block address, prefetch depth, confidence level, and PDT index as entries into the FDIP queue; S3. The prefetch condition detection unit scans the FDIP queue. When the prefetch depth of the target instruction block is greater than or equal to its queue distance from the current instruction fetch pointer, the confidence level reaches a preset threshold, prefetching has not yet been initiated, the corresponding instruction cache line is not in the first-level instruction cache / prefetch queue / MSHR, and the resources are available, the trigger condition is determined to be met. S4. Write the instruction cache line corresponding to the target fetch block that meets the conditions into the prefetch queue, initiate a prefetch request when MSHR is idle, and mark the corresponding FDIP table entry as initiated prefetching; S5. After the prefetch returns, write the instruction cache line to the first-level instruction cache, set the prefetch flag, and save the PDT index. S6. When fetching instructions in the future, if the target instruction fetch block is already in the L1 instruction cache and the prefetch flag is valid, the PDT entry is located according to the saved PDT index and the corresponding confidence level is increased. If the target instruction fetch block is not in the L1 instruction cache but there is already a corresponding prefetch request in the MSHR or prefetch queue, the PDT entry is located based on the PDT index stored therein, and the corresponding confidence and prefetch depth are increased. If the target fetch block that has been prefetched is determined to be in an incorrect prediction path, the PDT entry is located based on the PDT index in the FDIP entry and the corresponding confidence level is reduced.

2. The instruction cache prefetching method based on FDIP according to claim 1, characterized in that, In step S1, when calculating the PDT index, the PDT index is obtained by hashing the current fetch block group PC and the path history information: pdt_index=hash(group_pc,PHR / GHR); the PDT tag is obtained by performing operations on a portion of the current fetch block group PC and the folded path history information: pdt_tag=partial(group_pc,folded PHR); where group_pc is the current fetch block group PC, PHR is the path history register, and GHR is the global history register.

3. The instruction cache prefetching method based on FDIP according to claim 1, characterized in that, Each entry in the FDIP queue stores at least: the target fetch block address, prefetch depth, confidence level, prefetch initiation status flag, PDT index, and PDT tag.

4. The instruction cache prefetching method based on FDIP according to claim 1, characterized in that, In step S3, when determining whether the instruction cache line corresponding to the target fetch block already has a corresponding prefetch request in the prefetch queue or MSHR, confirmation is made by comparing the prefetch source information stored in the prefetch queue and MSHR with the address and PDT index of the target fetch block; the prefetch source information includes at least the address and PDT index of the target fetch block.

5. The instruction cache prefetching method based on FDIP according to claim 1, characterized in that, When a prefetch request is initiated in step S4, the PDT index and PDT tag corresponding to the prefetch request are saved in the prefetch queue and MSHR. After the prefetch returns, the corresponding PDT entry is located based on the PDT index and PDT tag, and the PDT index is saved in the instruction cache line for subsequent prefetch validity judgment to locate the corresponding PDT entry for update and maintenance.

6. The instruction cache prefetching method based on FDIP according to claim 1, characterized in that, When increasing the confidence level of the corresponding PDT entry in step S6, the prefetch depth remains unchanged.

7. The instruction cache prefetching method based on FDIP according to claim 1, characterized in that, In step S6, when increasing the confidence level of the corresponding PDT entry and increasing its prefetch depth, an increment operation is performed on the confidence level and the prefetch depth.

8. The instruction cache prefetching method based on FDIP according to claim 1, characterized in that, In step S6, when reducing the confidence level of the corresponding entry in the PDT table, a self-decrease operation is performed on the confidence level.

9. An instruction cache prefetching apparatus based on FDIP, operating using the instruction cache prefetching method as described in any one of claims 1 to 8, characterized in that, include: The path history register is used to record branch direction information, path information, or instruction fetch path information; The branch prediction unit, connected to the path history register, is used to predict future fetch blocks based on the path history information provided by the current fetch block group PC and the path history register. The Dynamic Prefetch Depth Prediction Table (PDT) connects the branch prediction unit and the path history register. It is used to index the corresponding prediction fetch block based on the group PC and path history information, and output the prefetch depth and confidence of the corresponding prediction fetch block. The FDIP queue connects the branch prediction unit and the PDT, and is used to store the address of each prediction fetch block and its corresponding prefetch depth, confidence level and PDT index; The prefetch condition detection unit is connected to the FDIP queue, the L1 instruction cache, the prefetch queue, and the MSHR, respectively. It is used to scan the FDIP queue and determine whether to trigger prefetching based on the prefetch depth, confidence, queue distance, and cache occupancy status. The prefetch queue, connected to the prefetch condition detection unit, is used to receive prefetch requests and temporarily store the address of the instruction cache line to be prefetched and its corresponding PDT index. MSHR, the connection prefetch queue, is used to track incomplete prefetch requests and their corresponding PDT indexes; The update maintenance unit is connected to the FDIP queue, prefetch queue, MSHR and level 1 instruction cache respectively, and is used to update the confidence and prefetch depth of each entry in the PDT according to the prefetch return status and subsequent fetch hit status.

10. A processor, characterized in that, The processor is used to run a computer program, and the computer program executes the instruction cache prefetching method as described in any one of claims 1 to 8.

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