A high-precision ammeter low-power scheduling method and system

Abstract

The application relates to a high-precision electric meter low-power scheduling method and system, and relates to the technical field of smart grid metering. The method comprises the following steps: obtaining an operation parameter reflecting the operation state of an electric meter, performing task granularity segmentation on a service when a calculation-intensive service trigger condition is met, separating a numerical calculation task queue and a service scheduling task; dynamically mapping the numerical calculation task queue to an independent coprocessor for execution, mapping the service scheduling task to a main control chip for execution, and establishing a separated parallel processing architecture; monitoring the real-time load state of the main control chip, controlling the main control chip to enter deep sleep and maintaining the operation of the coprocessor when a sleep condition is met; and when the coprocessor calculation result meets a wake-up condition, sending a wake-up signal by the coprocessor to control the main control chip to resume work. The application can realize dynamic cooperation and deep sleep switching of the main control chip and the coprocessor, significantly reduce the overall power consumption, and guarantee the calculation real-time performance.

Description

Technical Field

[0001] This application belongs to the field of smart grid metering technology, specifically a high-precision electricity meter low-power scheduling method and system. Background Technology

[0002] With the deepening of smart grid construction, electricity metering equipment, as a key node connecting users and the power grid in the power system, directly affects the stability of grid operation and the accuracy of metering. High-precision electricity meters not only need to collect basic electrical quantities such as voltage and current in real time, but also need to perform high-frequency, high-precision complex calculations on multi-dimensional parameters such as instantaneous power, active and reactive power, and harmonic content. In the existing technical architecture, electricity meters typically use a single main control chip to coordinate all data acquisition, signal analysis, communication protocol parsing, and human-machine interaction. This centralized processing mode has become the mainstream implementation solution in the industry when facing the increasing requirements for metering accuracy and the complex power grid environment. It uses high-performance processors to continuously run various algorithms to ensure real-time data output and complete execution of business logic.

[0003] However, balancing the high computing power demands of high-precision calculations with the overall goal of low-power operation remains a significant technical challenge in this field. Especially in scenarios with drastic grid load fluctuations or complex power quality, intensive numerical computation tasks often cause the main control chip to operate under high load for extended periods, making it difficult to enter deep energy-saving modes. This continuous full-load operation not only results in high standby power consumption, limiting its lifespan in battery-powered or low-power-budget scenarios, but also may affect the system's response speed to other sudden service requests due to excessive resource consumption, creating bottlenecks in overall energy efficiency and operational stability. Therefore, a solution that can effectively reduce system power consumption while ensuring metering accuracy is urgently needed. Summary of the Invention

[0004] To address the above issues, this application provides a high-precision electricity meter low-power scheduling method and system to solve the contradiction between the high computing power requirements brought about by high-precision calculations and the overall low-power operation goal of the equipment during long-term operation, especially the technical problem that intensive numerical calculation tasks cause the main control chip to be in a high-load state for a long time and make it difficult to enter a deep energy-saving mode.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: The first aspect of this application provides a low-power scheduling method for high-precision electricity meters. The method includes: acquiring operating parameters reflecting the operating status of the electricity meter; determining whether a computationally intensive service triggering condition is met based on the operating parameters; in response to meeting the computationally intensive service triggering condition, performing task granular segmentation on the current service to separate a numerical computation task queue and a service scheduling task, and generating corresponding scheduling priority information; and dynamically mapping the numerical computation task queue to an independent coprocessor for execution and the service scheduling task to a main control chip for execution, based on the task granularity segmentation result and the scheduling priority information, thereby establishing a connection between the independent coprocessor and the main control chip. The system employs a separate parallel processing architecture. During the operation of this architecture, the real-time load status of the main control chip is continuously monitored. When the real-time load status meets the deep sleep trigger condition, the main control chip is controlled to enter a deep sleep state, while the independent coprocessor continues to execute numerical calculation tasks. During the execution of the numerical calculation tasks by the independent coprocessor, the operating status parameters are determined based on the calculation results of the numerical calculation tasks. When the operating status parameters meet the wake-up condition, the independent coprocessor sends a wake-up signal to the main control chip to control the main control chip to exit the deep sleep state and resume the execution of the corresponding business scheduling tasks.

[0006] A second aspect of this application provides a high-precision, low-power scheduling system for electricity meters. The system includes: a triggering and task segmentation module, used to acquire operating parameters reflecting the meter's operating status, and determine whether computationally intensive service triggering conditions are met based on the operating parameters; in response to meeting the computationally intensive service triggering conditions, performing task granular segmentation on the current service to separate a numerical computation task queue and a service scheduling task, and generating corresponding scheduling priority information; and a task mapping and parallel processing module, used to dynamically map the numerical computation task queue to an independent coprocessor for execution, and map the service scheduling task to a main control chip for execution, based on the task granularity segmentation result and the scheduling priority information, to establish a connection between the independent coprocessor and the main control chip. A discrete parallel processing architecture between chips; a sleep control module, used to continuously monitor the real-time load status of the main control chip during the operation of the discrete parallel processing architecture, and when the real-time load status meets the deep sleep trigger condition, control the main control chip to enter a deep sleep state and maintain the independent coprocessor to continue executing numerical calculation tasks; a wake-up and recovery module, used to determine the running status parameters according to the calculation result of the numerical calculation task during the execution of the numerical calculation task by the independent coprocessor, and when the running status parameters meet the wake-up condition, the independent coprocessor sends a wake-up signal to the main control chip to control the main control chip to exit the deep sleep state and resume the execution of the corresponding business scheduling tasks.

[0007] This application provides a high-precision, low-power scheduling method and system for electricity meters. The scheme acquires operating parameters reflecting the meter's operating status and determines whether the triggering conditions for computationally intensive services are met. It then performs task granularity segmentation of the current service to separate numerical computation task queues and service scheduling tasks, generating scheduling priority information. Based on the segmentation results and priority information, the numerical computation task queues are dynamically mapped to independent coprocessors for execution, while the service scheduling tasks are mapped to the main control chip for execution, thus establishing a separate parallel processing architecture between the independent coprocessor and the main control chip. During the operation of this architecture, the real-time load status of the main control chip is continuously monitored. Once the deep sleep triggering condition is met, the main control chip is controlled to enter a deep sleep state while the independent coprocessor continues to execute numerical computation tasks. Subsequently, during coprocessor execution, operating status parameters are determined based on the calculation results. When the wake-up condition is met, the coprocessor sends a wake-up signal to control the main control chip to exit sleep and resume service scheduling. This series of steps decouples the high-density numerical computation load from the main control chip and assigns it to a dedicated coprocessor. The main control chip only intervenes in the scheduling logic when necessary, thereby significantly reducing the average workload and idle waiting power consumption of the main control chip. This effectively solves the contradiction between the high computing power requirements brought by high-precision calculations and the overall low power consumption target of the equipment during long-term operation, especially the technical problem that intensive numerical computation tasks cause the main control chip to be in a high-load state for a long time and it is difficult to enter a deep energy-saving mode. Therefore, it avoids the phenomenon of excessive power consumption and response delay caused by a single chip operating at full load, and improves the energy efficiency ratio, operational stability and real-time performance and reliability of data processing of the meter system under complex operating conditions. Attached Figure Description

[0008] Figure 1 A flowchart of a high-precision, low-power scheduling method for electricity meters is provided in this application; Figure 2 The flowchart of the high-precision electricity meter low-power scheduling method provided in this application for determining whether the triggering conditions of computationally intensive services are met based on the operating parameters; Figure 3 The flowchart illustrates the process of extracting numerical calculation task queues and generating scheduling priority information based on computational attributes and real-time requirements in the high-precision electricity meter low-power scheduling method provided in this application. Figure 4 The flowchart shows how the high-precision meter low-power scheduling method provided in this application divides the numerical calculation task queue into fundamental and non-fundamental component calculation tasks and updates the sorting relationship according to the scheduling level. Figure 5 The flowchart illustrates the process of establishing a task mapping table and allocating numerical computation task queues to independent coprocessors for resource execution in the high-precision electricity meter low-power scheduling method provided in this application. Figure 6 The flowchart illustrates the process of constructing comprehensive load status parameters based on bus bandwidth utilization and heartbeat frequency and controlling the main control chip to enter a deep sleep state in the high-precision low-power scheduling method for electricity meters provided in this application. Figure 7 The flowchart illustrates the process of maintaining an independent coprocessor to perform numerical calculation tasks and dynamically adjusting the sampling and calculation frequencies to reduce energy consumption in the high-precision electricity meter low-power scheduling method provided in this application. Figure 8 The flowchart shows the process of obtaining the fundamental value sequence, extracting slope features, and separating the phase offset compensation value as the operating state parameter in the high-precision electricity meter low-power scheduling method provided in this application. Figure 9 The flowchart shows the process of generating an interrupt activation instruction and triggering the main control chip to exit the deep sleep state when the phase offset compensation value exceeds the wake-up threshold in the high-precision meter low-power scheduling method provided in this application. Figure 10 A block diagram of a high-precision electricity meter low-power scheduling system provided in this application. Detailed Implementation

[0009] To enable those skilled in the art to better understand the technical solution, the present application will be described in detail below with reference to the embodiments. The description in this section is only exemplary and explanatory, and should not be used to limit the scope of protection of the present application in any way.

[0010] like Figure 1 The diagram shown is a flowchart of a high-precision electricity meter low-power scheduling method provided in an embodiment of this application. The method includes: Step S101: Obtain the operating parameters reflecting the operating status of the electricity meter, and determine whether the triggering conditions for computationally intensive services are met based on the operating parameters; in response to meeting the triggering conditions for computationally intensive services, perform task granularity segmentation on the current service to separate the numerical calculation task queue and the service scheduling task, and generate the corresponding scheduling priority information.

[0011] In practical applications, operating parameters characterize the current workload of the electricity meter and the characteristics of the power grid environment. Data sources include the metering chip, sensor modules, and historical operating databases within the meter, specifically covering voltage and current sampling sequences, calculated power values, or harmonic analysis data. The trigger condition for computationally intensive services is a preset rule that determines whether the current service requires hardware acceleration or parallel processing. This rule defines the logical relationship between operating parameters and specific thresholds. When the operating parameters fall within the range defined by this rule, the system determines that the current service is computationally intensive, thereby triggering subsequent task scheduling processes. For example, this condition can be constructed by comparing the ratio of real-time power to rated power, analyzing the statistical distribution of harmonic distortion rate, or monitoring the execution time of a specific algorithm; alternatively, a comprehensive scoring model can be constructed by combining multi-dimensional parameters, and the determination condition is met when the score exceeds a set threshold.

[0012] In one alternative implementation, operating parameters may include instantaneous peak power and harmonic distortion rate, based on which, such as Figure 2 The diagram shown is a flowchart illustrating a method for determining whether the triggering conditions for computationally intensive services are met based on operating parameters, according to an embodiment of this application. The method includes: Step S201: Determine whether the instantaneous power peak exceeds the corresponding power threshold, and determine whether the harmonic distortion rate exceeds the corresponding harmonic threshold.

[0013] By employing a dual-condition judgment, it accurately identifies whether the current grid load state has reached the critical point requiring the activation of high-energy-consuming computing resources. The instantaneous power peak is not simply an instantaneous power reading, but a structured data sequence characterizing the intensity of the energy transmission impact per unit time. It reflects the short-term stress caused by the startup and sudden changes of inductive loads in the power system. This instantaneous power peak is typically obtained by the metering chip inside a high-precision meter based on the product of voltage and current sampling points. The data source is the meter's high-speed cache register, and the reading method follows industry-standard communication protocols (such as Modbus or DL / T645), with the data format being floating-point numbers.

[0014] After obtaining this value, it is compared with the corresponding power threshold. This power threshold is a judgment threshold determined comprehensively based on the rated capacity design of the target power grid, the thermal stability limit of the line, and the historical load statistical distribution. For example, it can be determined by collecting the maximum load data within a preset historical time period, selecting the 95th percentile value as a benchmark, and setting it by 5%-10% above the line's allowable safety margin. For typical residential electricity consumption scenarios, this threshold can be set to 4000 watts or 5000 watts, etc. This is only an example.

[0015] Meanwhile, harmonic distortion rate, as another key indicator, is used to quantify the degree of nonlinear distortion in the power grid waveform. Its physical essence reflects the ratio of the effective value of each harmonic component to the effective value of the fundamental component in the current or voltage waveform. This harmonic distortion rate is calculated by performing spectral analysis (such as Fast Fourier Transform, FFT) on the time-domain voltage or current signal collected by the meter. The harmonic distortion rate is then compared with the corresponding harmonic threshold. This harmonic threshold is set based on national power quality standards and the computational sensitivity of the equipment itself, and is used to distinguish between normal fluctuations and severe distortions requiring intensive computational processing. For example, in ordinary low-voltage distribution networks, the limit for total harmonic distortion rate is usually 5%, while for high-precision metering scenarios, in order to capture subtle changes in power quality, this harmonic threshold can be set to, for example, 3% or 8%, depending on the requirements for metering accuracy; this is only an example. Introducing harmonic distortion rate as a co-judgment condition can effectively filter out power peaks caused by a sudden increase in purely resistive load (such as the turn-on of a purely resistive heater). Although the power is high in this type of operation, the waveform distortion is small, and the calculation pressure does not increase significantly, thus avoiding false triggering.

[0016] Step S202: When the instantaneous power peak exceeds the power threshold and the harmonic distortion rate exceeds the harmonic threshold, determine that the current service meets the triggering conditions for computationally intensive services, and start task granularity segmentation.

[0017] A Boolean logic rule is established to determine the triggering conditions for computationally intensive services. Specifically, the current service is confirmed to enter computationally intensive mode only when both peak power and harmonic distortion rate exceed limits simultaneously. This logic mechanism differs from the conventional approach of triggering with a single threshold. Instead, it enhances the robustness of system state identification through a composite criterion with closer physical connections. When both of the above judgments are true, it is confirmed that the current power grid condition has reached a level requiring the activation of high-computing resources for accurate metering, and a confirmation signal that meets the triggering conditions for computationally intensive services is generated. This signal serves as a control token for subsequent processes, directly driving the system to initiate the task granularity segmentation process. This dual confirmation mechanism compresses the activation time of high-energy-consuming computing units such as coprocessors to within the truly necessary time window, avoiding frequent task refactoring and resource switching caused by random fluctuations in a single parameter. This maximizes the extension of the low-power sleep time of the main control chip while ensuring metering accuracy, thereby reducing overall system energy consumption.

[0018] Task granularity partitioning aims to decompose the currently executing business logic according to computational attributes and real-time requirements. In this process, business subtasks involving complex mathematical operations and high main control chip usage are extracted and formed into a numerical computation task queue, while lightweight business subtasks responsible for logic control, communication interaction, and data storage are classified as business scheduling tasks. The numerical computation task queue consists of a series of computational units to be executed, such as Fast Fourier Transform (FFT) operations, digital filtering, or energy parameter integration calculations; business scheduling tasks are sets of logical instructions that maintain the normal operation of the meter, such as event reporting, human-machine interaction responses, and protocol stack maintenance. Scheduling priority information is used to define the order and importance of each task in the execution queue. Its generation process can assign priority identifiers according to the timeliness requirements of the tasks, or construct a Directed Acyclic Graph (DAG) based on the dependencies between tasks to determine the execution topology. Task granularity partitioning effectively decouples tasks of different natures, laying the foundation for subsequent hardware resource mapping.

[0019] Specifically, such as Figure 3 The diagram illustrates a flowchart illustrating a method for granularly segmenting current business processes to separate numerical computation task queues and business scheduling tasks, and generating corresponding scheduling priority information, as provided in this application embodiment. The method includes: Step S301: Based on the calculation attributes and real-time requirements of each business subtask in the current business, extract the business subtasks involving numerical calculation and analysis into a numerical calculation task queue, and treat the remaining business subtasks as business scheduling tasks.

[0020] This step aims to accurately isolate and classify heterogeneous tasks in the current business flow, thereby providing a structured task queue foundation for subsequent hardware resource mapping. The core of this process lies in performing automated classification decisions based on the inherent characteristics of the business subtasks—computational attributes and real-time requirements. Computational attributes refer to the computational power requirements and data throughput characteristics exhibited by the business subtasks during execution, specifically including algorithm complexity (e.g., complex operations like the Fast Fourier Transform have higher computational complexity than simple logical judgments), floating-point operation density, and data processing scale. Real-time requirements reflect the task's sensitivity to response time. For example, in a power quality event monitoring scenario, fault recording tasks are hard real-time tasks, requiring processing within an extremely short time window, while regular data logging tasks are soft real-time tasks, allowing for millisecond-level delays.

[0021] The system iterates through all business subtasks in the current business flow and performs feature identification on each subtask. This identification process may involve parsing task metadata to obtain parameters such as the algorithm type identifier, estimated execution cycle, and maximum allowable delay time. Based on this, it determines whether the business subtask involves numerical computation and analysis. This determination process specifically includes: detecting whether the business subtask contains high-density matrix operations, integral and differential operations, or spectral transformation algorithms, and whether its data throughput exceeds a preset computationally intensive threshold (e.g., more than 10,000 data points processed per second). This preset computationally intensive threshold can be pre-calibrated based on the processing capacity of the meter's main control chip and the statistical distribution of historical load data. For example, the 95th percentile can be selected as this threshold based on the throughput distribution of numerical computation tasks under typical operating conditions.

[0022] If a business subtask simultaneously meets the characteristics of high computational consumption and high data throughput, it is identified as a business subtask involving numerical computation and analysis. These subtasks identified as involving numerical computation and analysis are then aggregated to form a numerical computation task queue, which consists of a sequence of pointers to underlying algorithm functions and their corresponding input data block indices. Other business subtasks that do not meet the above numerical computation and analysis conditions, such as logic control tasks like human-computer interaction command response, communication protocol parsing, or data storage management, are classified as business scheduling tasks and form another independent task queue. This two-dimensional feature extraction based on computational attributes and real-time requirements effectively distinguishes between high-load computational tasks and light-load logic tasks, avoiding the incorrect allocation of simple scheduling tasks to expensive computing resources.

[0023] Step S302: Determine the scheduling level corresponding to the numerical calculation task queue and the business scheduling task, and generate scheduling priority information according to the scheduling level.

[0024] After separating the task queues as described above, clear hierarchical definitions and priority identifiers are further assigned to the two types of tasks to construct an orderly scheduling system. The scheduling level is the macro-level positioning of a task queue within the overall system scheduling strategy, defining the relative importance of tasks in resource competition. The scheduling level is determined based on the physical characteristics and business value of the task type. For numerical calculation task queues, because they undertake core metering functions such as electricity metering and harmonic analysis, the accuracy and timeliness of their calculation results directly affect the fairness of billing and the safety of the power grid; therefore, they are usually assigned a higher scheduling level, such as being defined as the critical calculation level. For business scheduling tasks, which are mainly responsible for the maintenance of the system's peripheral logic and state management, although indispensable, they can make appropriate concessions in resource conflicts; therefore, they are usually assigned a lower scheduling level, such as being defined as the routine maintenance level.

[0025] Based on the determined scheduling levels, scheduling priority information is generated. This generation process includes: First, assigning a base priority value to each scheduling level, for example, 100 for the critical computing level and 10 for the routine maintenance level. Then, within the same scheduling level, fine-tuning is performed based on real-time requirements. For example, for business subtasks belonging to the critical computing level, if a task's real-time requirement is completion within 1 millisecond, its priority value is increased by 20 units from the base value; if completion within 10 milliseconds is allowed, the base value remains unchanged. Finally, the generated scheduling priority information contains a complete priority list, where each entry uniquely corresponds to a business subtask or task queue, recording its final priority value after weighted calculation. This scheduling priority information is stored in a structured data table (such as a linked list or array) for subsequent dynamic mapping steps. Through differentiated configuration based on scheduling levels, not only is it ensured that numerical computing tasks receive priority access to independent coprocessor computing resources, but also that high-value business subtasks are executed first when system resources are scarce, thus achieving dynamic matching of computing resource allocation with business objectives.

[0026] In the aforementioned technical process, a quantitative classification mechanism built based on the computational attributes and real-time requirements of business sub-tasks, along with a priority generation strategy based on scheduling levels, provides an objective engineering basis for the abstract task segmentation process. This feature-based automated classification and grading replaces the traditional static task allocation method that relies on manual experience, enabling the meter system to flexibly adapt to the resource requirements of different metering scenarios according to the actual operational business load. The clear division between numerical calculation task queues and business scheduling tasks provides the necessary data structure and logical premise for offloading computationally intensive tasks to independent coprocessors, while accurate scheduling priority information ensures that when the main control chip and independent coprocessors work in parallel, the system can respond to various business requests in an orderly manner according to predetermined strategies, thereby improving the real-time processing capability and operational stability of high-precision meters in complex metering scenarios.

[0027] Furthermore, based on the above embodiments, such as Figure 4 The diagram shows a flowchart illustrating how to divide a numerical computation task queue into fundamental and non-fundamental component computation tasks and update the sorting relationship according to the scheduling level, as provided in an embodiment of this application. The method includes: Step S401: Based on the spectral components corresponding to the numerical calculation analysis, divide the numerical calculation task queue into fundamental component calculation tasks and non-fundamental component calculation tasks.

[0028] The extracted numerical computation task queue is subjected to spectral feature analysis, and the physical attributes of the originally aggregated numerical computation tasks are deconstructed based on their corresponding spectral components. Spectral components characterize the distribution of electrical signals in the frequency domain. In the context of electricity metering, voltage or current signals are composed of superimposed sine waves of different frequencies. Components with frequencies equal to the fundamental frequency of the power grid (e.g., 50 Hz or 60 Hz) are called fundamental components, while components with frequencies that are integer multiples of the fundamental frequency are called harmonic components (i.e., non-fundamental components). Based on signal processing theory, time-domain sampled data is mapped to the frequency domain to identify the physical frequency objects targeted by each business sub-task.

[0029] For example, the calculation of the effective value of instantaneous power typically relies on the fundamental component, while harmonic distortion assessment in power quality analysis focuses on non-fundamental components. By using frequency domain analysis techniques such as Fast Fourier Transform, the frequency characteristics of interest for each task are extracted from the numerical calculation task queue. Tasks targeting fundamental parameters (such as fundamental amplitude and phase) are grouped into fundamental component calculation tasks, while tasks targeting harmonic parameters (such as harmonic content and phase) are grouped into non-fundamental component calculation tasks. This division allows the task queue to be precisely mapped to different digital signal processing units within the meter; for example, fundamental component calculation tasks can be assigned to filter banks dedicated to power frequency processing, while non-fundamental component calculation tasks can be assigned to general-purpose processing cores with high-order computing capabilities.

[0030] Step S402: Determine the subtask scheduling level within the numerical computation task queue based on the computation timeliness and computational complexity of the fundamental component computation task and the non-fundamental component computation task.

[0031] In this embodiment, after completing the physical partitioning based on spectrum classification, the performance attributes of the two types of tasks are evaluated from the perspective of computational resource consumption to determine their corresponding subtask scheduling levels. Computational timeliness refers to the maximum allowable time delay from the start of task execution to the output result, reflecting the task's sensitivity to real-time performance; computational complexity refers to the amount of central processing unit computing power, memory access bandwidth, and storage space required to complete the task, reflecting the computational scale of the task. Fundamental component calculation tasks are directly related to core businesses such as electricity metering and usually have extremely high computational timeliness requirements (e.g., needing to be completed within milliseconds), but the algorithms are relatively fixed (e.g., zero-crossing detection, moving average), and the computational complexity is relatively low; non-fundamental component calculation tasks, especially higher harmonic analysis, involve complex matrix operations and iterative algorithms. Although the real-time requirements are slightly lower than those of fundamental components, the computational complexity is extremely high.

[0032] The system reads the preset configuration attributes of each task, quantifies and evaluates its computational timeliness indicators (such as deadlines) and computational complexity indicators (such as the number of floating-point operations), and maps the tasks to different subtask scheduling levels accordingly. A subtask scheduling level is essentially a priority code used to distinguish the scheduling order of different subtasks within the numerical computation task queue; a higher value generally indicates higher priority or stronger preemption capability. For example, a fundamental component computation task with high timeliness and low complexity is designated as the highest subtask scheduling level, allowing it to be prioritized for scheduling in the numerical computation task queue; a non-fundamental component computation task with low timeliness and high complexity is designated as the second highest or ordinary subtask scheduling level, allowing it to be executed during idle periods. The process of determining the subtask scheduling level establishes a quantitative task value evaluation system, enabling subsequent scheduling decisions to be flexibly adjusted based on real-time system load status and task urgency.

[0033] Step S403: Sort the fundamental component calculation tasks and non-fundamental component calculation tasks according to the subtask scheduling level to update the sorting relationship within the numerical calculation task queue in the scheduling priority information.

[0034] The static attributes (spectral components, scheduling level) determined in the preceding steps are transformed into a dynamic execution sequence. The sorting relationship within the numerical computation task queue in the scheduling priority information is reconstructed through sorting operations, thereby guiding the actual task distribution. The sorting relationship in the scheduling priority information defines the order of each subtask in the numerical task queue, determining the order in which independent coprocessors grab tasks. Based on the determined subtask scheduling level, sorting algorithms such as priority preemption, time-slice round-robin, or earliest-to-last-deadline are used to completely rearrange the mixed fundamental component computation tasks and non-fundamental component computation tasks. During the rearrangement process, tasks belonging to higher subtask scheduling levels (e.g., fundamental component computation tasks) are placed at the head of the queue, ensuring that they can be read and executed by the coprocessor immediately upon generation; tasks belonging to lower subtask scheduling levels (e.g., some non-fundamental component computation tasks) are deferred to the tail of the queue. This update process can be executed periodically during operation or triggered by specific events, such as when a new computationally intensive service is detected, triggering a sorting update. Through this dynamic sorting mechanism, the sorting relationship in the scheduling priority information can reflect the current business urgency in real time, so that the execution flow of the coprocessor always focuses on the most critical computing tasks, avoiding the blocking of the real-time output of fundamental frequency measurement by a large number of low-priority harmonic calculations. Thus, while ensuring high-precision measurement, the parallel computing capabilities of the coprocessor are maximized.

[0035] This application's embodiments achieve refined offloading management of heterogeneous numerical computation tasks through the synergistic effect of spectrum partitioning and subtask scheduling level ordering. Spectral components, serving as physical criteria, restore tasks to their corresponding signal processing levels, providing a physical basis for differentiated resource allocation. Computational timeliness and complexity, serving as engineering criteria, further quantify the resource requirements and constraints of tasks, ensuring the rationality of the subtask scheduling level settings. Finally, based on the updated ordering relationships of the subtask scheduling level, physical and engineering attributes are transformed into execution sequences, directly driving the coprocessor's runtime sequence. This process transforms the originally straightforward computational task queue into a hierarchical and prioritized intelligent scheduling sequence, enabling high-precision fundamental frequency metering tasks to penetrate the heavy harmonic calculation background and obtain deterministic execution guarantees, thereby effectively improving the response speed and metering accuracy of electricity meters in complex power grid environments.

[0036] Step S102: Based on the task granularity segmentation results and scheduling priority information, dynamically map the numerical computation task queue to the independent coprocessor for execution, and map the business scheduling task to the main control chip for execution, so as to establish a separate parallel processing architecture between the independent coprocessor and the main control chip.

[0037] A dedicated coprocessor is an auxiliary processing unit specifically designed for handling specific types of numerical calculations. Its architecture emphasizes high-throughput mathematical computation capabilities; examples include digital signal processors (DSPs), field-programmable gate arrays (FPGAs), or dedicated metrology acceleration chips. In one alternative implementation, the dedicated coprocessor interfaces with a micro-electro-mechanical systems (MEMS) sensor to directly process voltage, current, or electric field signal data acquired by the MEMS sensor. The main control chip is the core processor responsible for overall system control, operating system operation, and peripheral device management; examples include microcontroller units (MCUs) or central processing units (CPUs). Dynamic mapping can refer to the process of allocating specific task instances to the most suitable hardware resources for execution based on task granularity partitioning results. For example, by parsing the task tag table, the address pointer of the numerical calculation task queue can be written into the command register of the independent coprocessor, and the entry address of the business scheduling task can be loaded into the task scheduler of the main control chip. Alternatively, a shared memory queue mechanism can be used, in which the main control chip writes the data to be calculated into a shared buffer and notifies the independent coprocessor to read and process it. After the independent coprocessor completes the calculation, it writes the result back into the buffer and triggers an interrupt to notify the main control chip.

[0038] In one alternative implementation, such as Figure 5 As shown, this application embodiment provides an implementation method for dynamic mapping, specifically including: Step S501: Establish a task mapping table based on the task granularity segmentation results. The task mapping table is used to represent the correspondence between each task in the numerical computation task queue and the processing resources of the independent coprocessor.

[0039] After completing the task granularity segmentation, a defined binding relationship needs to be established between the generated task entities and the underlying hardware resources. This process is achieved by constructing a task mapping table. The task mapping table, as a structured configuration file representing the mapping rules between task logical attributes and physical hardware resources, typically uses task identifiers as primary keys and resource identifiers as secondary keys, forming a many-to-one or many-to-many key-value pair mapping relationship. Based on the task granularity segmentation results generated in the preceding steps, the computation type, data throughput, and real-time constraints of each numerical computation task are analyzed, while simultaneously scanning the current available processing resource status of independent coprocessors. Subsequently, an allocation algorithm is used to logically bind specific tasks (such as Fast Fourier Transform tasks, digital filtering tasks, etc.) to specific processing resources (such as digital signal processor core numbers, dedicated hardware accelerator identifiers, shared memory segment addresses, or direct memory access channel numbers). These binding relationships are compiled or serialized into a task mapping table and stored in a storage area that can be quickly accessed by the system. The purpose of establishing this mapping table is to translate high-level business scheduling intentions into hardware-executable configuration instructions, so that the subsequent task distribution process can be carried out according to predefined rules, avoiding resource conflicts or scheduling chaos, thereby ensuring the operational stability of the parallel processing architecture.

[0040] It should be noted that the above allocation algorithms can be, for example, greedy allocation algorithms based on task priority, round-robin allocation algorithms based on resource load balancing, or heuristic allocation algorithms based on historical execution data.

[0041] Step S502: According to the task mapping table, assign each task in the numerical calculation task queue to the processing resources corresponding to the independent coprocessor for execution.

[0042] Based on the established task mapping table, specific task allocation and scheduling actions are executed, translating logical mapping into actual physical execution. When numerical computation begins, the task mapping table is parsed to query the resource identifiers corresponding to each task in the currently pending numerical computation task queue. Based on the query results, task instructions, input data pointers, and configuration parameters are written to the control registers or memory buffers corresponding to the independent coprocessor processing resources specified in the task mapping table. For example, if the task mapping table indicates that a fundamental wave computation task should be allocated to coprocessor core 0, the corresponding computation instructions are loaded into the instruction queue of core 0, and the corresponding direct memory access channel is configured for data transmission. Upon receiving the allocated task, each processing resource of the independent coprocessor begins to execute the corresponding numerical computation operations in parallel. This table-based allocation method provides task scheduling with extremely high configurability and traceability. It not only allows for dynamic adjustment of mapping strategies based on system load but also facilitates fault isolation and task migration in the event of abnormal resource usage, thereby maximizing the computational potential of the coprocessor while ensuring the metering accuracy of high-precision electricity meters.

[0043] By establishing a task mapping table and allocating resources accordingly, precise delivery of numerical computation tasks to independent coprocessor processing resources is achieved. This structured mapping mechanism ensures clear task boundaries between the main control chip and the coprocessor, eliminates uncertainties in the task distribution process, provides basic data support for the stable operation of the discrete parallel processing architecture, and also lays the hardware scheduling foundation for subsequent power management and collaborative wake-up mechanisms.

[0044] Furthermore, a discrete parallel processing architecture refers to a system operation state where the main control chip and independent coprocessors execute different types of tasks within the same clock cycle. In this architecture, the main control chip focuses on handling business scheduling tasks, such as responding to external interrupts, managing communication connections, and updating the display interface; while the independent coprocessors focus on performing numerical calculation tasks, such as calculating power parameters and harmonic analysis based on real-time sampled data. The two exchange data via a data bus or shared memory, but their logical execution is independent and does not block each other. This architecture ensures that computationally intensive loads no longer consume the main control chip's processing resources, thereby significantly reducing the main control chip's operating load.

[0045] Step S103: During the operation of the split parallel processing architecture, continuously monitor the real-time load status of the main control chip. When the real-time load status meets the deep sleep trigger condition, control the main control chip to enter the deep sleep state and maintain the independent coprocessor to continue to execute numerical calculation tasks.

[0046] In this embodiment, the real-time load status reflects the current busy level and resource usage of the main control chip, ensuring that the hibernation decision comprehensively reflects the system's operating pressure. Monitoring indicators may include, for example, CPU utilization, bus bandwidth utilization, number of interrupts processed per unit time, or task queue backlog length. The system collects the above indicator data at a fixed sampling period (e.g., every 100 milliseconds) through a kernel-level performance monitoring module or hardware performance counter, forming a continuous load status curve. This aims to capture the idle window of the main control chip and provide data support for entering low-power mode.

[0047] The deep sleep trigger condition is the criterion for determining whether the main control chip can safely shut down most modules and enter an extremely low-power state. Its setting balances system response speed requirements and energy-saving needs. For example, a load threshold can be set based on the tolerance for response latency in the business scenario. When the real-time load is below this threshold and the duration exceeds a preset safe time (e.g., 5 seconds), the trigger condition is considered met. Alternatively, a predictive model can be built based on historical data statistics of business idle patterns. When the prediction results indicate that no high-priority tasks will arrive in the near future, the sleep process is triggered in advance. Deep sleep state can refer to the main control chip shutting down the CPU core, most clock sources, and power domains, retaining only the circuitry used for wake-up detection (such as external interrupt pins or real-time clocks). In this state, the main control chip's power consumption drops to the microamplitude level.

[0048] In one alternative implementation, such as Figure 6 The diagram shown is a flowchart illustrating a method for constructing comprehensive load status parameters based on bus bandwidth utilization and heartbeat frequency, and controlling the main control chip to enter a deep sleep state, according to an embodiment of this application. The method includes: Step S601: Obtain the bus bandwidth utilization and heartbeat frequency of the main control chip.

[0049] In this embodiment, the real-time load status, serving as the data foundation for energy consumption management decisions, can also include monitoring indicators in two dimensions: bus bandwidth utilization and heartbeat frequency. Bus bandwidth utilization reflects the congestion level of the data transmission path within the main control chip and is a physical indicator of data throughput pressure; heartbeat frequency reflects the stability of the main control chip's task scheduling and system response, and its fluctuation range reflects the smoothness of system operation. By combining information from these two dimensions, load misjudgments caused by relying on only a single indicator can be avoided, thus providing accurate data support for subsequent hibernation decisions.

[0050] In practical implementation, a load sampling interval counter can be used to sample the bus bandwidth occupancy monitor and heartbeat frequency of the main control chip at preset intervals. This counter is implemented through a hardware timer. When the counter reaches the preset overflow period, it automatically triggers a low-level interrupt, reading the cumulative number of transmitted bytes in the bus bandwidth occupancy monitor register of the main control chip and the number of heartbeat clock pulses output by the phase-locked loop. The system performs smoothing processing on the collected raw data (for example, using a sliding window algorithm to calculate a weighted average of the data in the current period and the data in the previous N periods) to remove noise interference caused by instantaneous fluctuations, thus obtaining the current bus bandwidth occupancy rate and the current heartbeat frequency fluctuation amplitude.

[0051] Step S602: Construct comprehensive load status parameters based on bus bandwidth utilization and heartbeat frequency.

[0052] By fusing bus bandwidth utilization and heartbeat frequency, a comprehensive load status parameter is obtained, which fully reflects the current load level of the main control chip. This parameter is based on the orthogonal relationship between data flow and computing speed, constructing a multi-dimensional feature vector or weighted scalar, rather than a simple numerical summation. First, bus bandwidth utilization and heartbeat frequency are normalized to eliminate the difference in their dimensions. Then, weight coefficients are assigned according to the system's sensitivity to data throughput and computing power, and the comprehensive load status parameter is obtained through weighted summation or Euclidean distance calculation. This parameter can effectively avoid the distortion problem of single indicators in specific scenarios. For example, in direct memory access intensive scenarios, although the CPU utilization may be low, the bus bandwidth utilization is high. In this case, a single CPU indicator cannot reflect the true load, while the comprehensive load status parameter can accurately capture the high load state through bus utilization.

[0053] Step S603: Compare the comprehensive load status parameters with the preset hibernation determination threshold.

[0054] The preset hibernation threshold is a threshold parameter used to determine whether the system meets the conditions for deep hibernation. Its setting is directly related to the system's real-time requirements and wake-up latency tolerance. This threshold is not a fixed value, but is determined comprehensively based on the target meter's business characteristics (such as maximum event reporting latency and data acquisition cycle) and hardware performance parameters (such as cold start time and cache recovery time). During system initialization or calibration, the comprehensive load status parameter sequence from historical operating data is collected, and the statistical distribution pattern of the system entering idle state is analyzed. Combined with business requirements, a quantile value that covers more than 90% of idle scenarios and has a safety margin is selected as the benchmark threshold; or multiple threshold strategies are configured according to different working modes (such as nighttime rate periods and daytime peak periods). A logical judgment algorithm is used to calculate the difference or relative relationship between the comprehensive load status parameters and the hibernation threshold in real time, providing a Boolean decision basis for hibernation control.

[0055] Step S604: When the comprehensive load status parameter is lower than the preset sleep determination threshold, control the main control chip to enter deep sleep state.

[0056] Specifically, when the value of the comprehensive load status parameter is lower than the preset sleep determination threshold, or meets the preset sleep logic expression (e.g., all values ​​are below the threshold for N consecutive sampling periods), the main control chip is determined to be in a low-load state, allowing deep sleep operation to be performed. Control commands are sent through the power management unit to sequentially cut off the core voltage domain of the main control chip, turn off the high-frequency clock source, and suspend the currently running task context, causing the main control chip to enter a deep sleep state with extremely low power consumption. During this process, the continuous monitoring mechanism of bus bandwidth utilization and heartbeat frequency ensures the robustness of the sleep decision, avoiding false triggers caused by instantaneous data fluctuations, thereby ensuring the stability of the system's sleep / wake-up switching and providing a reliable state control foundation for the subsequent independent execution of numerical calculation tasks by the coprocessor and timely wake-up of the main control chip.

[0057] In other words, when the real-time load condition meets the deep sleep trigger condition, the main control chip performs actions such as saving the context and cutting off the power, entering a deep sleep state, suspending all service scheduling tasks and freezing its internal state. Because the independent coprocessor is equipped with an independent power management unit and clock source, its operation is not affected by the main control chip's sleep state. Through the independence of its hardware design, the system enables the independent coprocessor to continue operating during the main control chip's sleep state.

[0058] Maintaining the independent coprocessor to continue executing numerical calculations means that numerical calculations do not cease while the main control chip is in sleep mode. The independent coprocessor continues to independently complete calculations such as energy metering and harmonic analysis according to a predetermined task queue and priority. For example, during off-peak electricity consumption at night, the main control chip enters deep sleep mode due to the lack of communication and display tasks, but the independent coprocessor continues to sample voltage and current and calculate power, temporarily storing the results in local cache or non-volatile memory. This mechanism ensures the continuity and integrity of metering data, avoids data blind spots caused by the main control chip's sleep mode, and utilizes the high-efficiency computing capabilities of the coprocessor to complete necessary calculation tasks with minimal power consumption.

[0059] Specifically, such as Figure 7 The diagram shown is a flowchart of a method for maintaining an independent coprocessor to perform numerical computation tasks and dynamically adjusting sampling and computation frequencies to reduce energy consumption, according to an embodiment of this application. The method includes: Step S701: Maintain the task mapping relationship between the numerical computation task queue and the independent coprocessor.

[0060] This task mapping defines the binding rules between each task unit in the numerical computation task queue and specific processing resources (such as computing cores, hardware accelerators, or specific register addresses) within the independent coprocessor. Before the main control chip enters sleep mode, this task mapping is locked and persistently stored in non-volatile memory or a dedicated static random access memory area to prevent task allocation logic failure due to power failure or context loss of the main control chip. By maintaining this mapping, the independent coprocessor can accurately distribute the data packets to be processed to the corresponding computing units according to the established routing rules during the main control chip's sleep period, thereby maintaining the continuity and integrity of the task flow and ensuring that the independent coprocessor can uninterruptedly accept and continue executing unfinished numerical computation tasks without main control intervention.

[0061] Step S702: Control the independent coprocessor to continue executing numerical calculation tasks and cache the calculation results while the main control chip is in a deep sleep state.

[0062] After the main control chip enters deep sleep mode, the independent coprocessor takes over all numerical computation loads and autonomously schedules internal computing resources to process tasks in the queue according to the maintained task mapping relationship. Since the main control chip cannot respond to external interrupts or perform data interaction at this time, the independent coprocessor uses its on-chip integrated cache controller or externally mounted low-power storage chip to cache intermediate data generated during the computation process and the final computation results. This caching mechanism uses a circular buffer or linked list data structure to store computation results in order according to timestamps or task identifiers until the main control chip is awakened. This design not only ensures the consistency and integrity of data during the main control chip's sleep period, avoiding data loss, but also eliminates the coprocessor's dependence on the main control chip's real-time response, enabling the coprocessor to run continuously and stably in an unattended state, providing a complete data foundation for the main control chip to quickly resume operations.

[0063] Step S703: Dynamically adjust the sampling frequency and computing frequency according to the operating load of the independent coprocessor to reduce the energy consumption of the independent coprocessor during independent operation.

[0064] An adaptive frequency adjustment mechanism based on load feedback is introduced to further optimize energy consumption while ensuring computational accuracy. The operating load of the independent coprocessor reflects the current workload of the computational tasks, and its value can be obtained by statistically analyzing parameters such as the length of the task queue to be processed per unit time, CPU utilization, or hardware interrupt triggering frequency. This operating load is continuously monitored during operation. When a decrease in the operating load is detected, it indicates that the current power grid condition is stable or the computational demand is low. At this time, the sampling frequency and computation frequency of the independent coprocessor are reduced by configuring the internal clock management unit or frequency divider.

[0065] For example, reducing the sampling frequency from a conventional high frequency (e.g., 10kHz) to a low frequency (e.g., 1kHz) and simultaneously reducing the clock frequency of the computing core significantly reduces dynamic power consumption. Conversely, when the operating load increases and exceeds a preset high load threshold, the sampling frequency and computing frequency are automatically increased to ensure the real-time performance and accuracy of numerical calculations. Through this dynamic adjustment strategy, the independent coprocessor can balance performance and power consumption in real time according to actual business needs, avoiding resource redundancy or ineffective power consumption due to oversampling under low load conditions, and achieving refined energy efficiency management of the independent coprocessor during the main control chip's sleep period.

[0066] By maintaining task mapping relationships to ensure task execution continuity, coordinating with a calculation result caching mechanism to guarantee data integrity, and dynamically adjusting sampling and calculation frequencies based on the operating load, this embodiment of the application achieves autonomous, efficient, and low-power operation of the independent coprocessor during the main control chip's sleep period. The synergistic effect of these technical features enables the independent coprocessor to intelligently adapt to different computing load scenarios, reducing overall system energy consumption while maintaining the accuracy and real-time performance of high-precision meter calculations. This effectively solves the problem of coprocessor energy consumption rebound during the main control chip's sleep period, further optimizing the overall system's energy efficiency ratio.

[0067] Step S104: During the execution of numerical calculation tasks by the independent coprocessor, the running status parameters are determined based on the calculation results of the numerical calculation tasks. When the running status parameters meet the wake-up conditions, the independent coprocessor sends a wake-up signal to the main control chip to control the main control chip to exit the deep sleep state and resume the execution of the corresponding business scheduling tasks.

[0068] Operating status parameters are key indicators that reflect the operating characteristics of the power grid or abnormal states of the system, extracted or derived by an independent coprocessor during the execution of numerical calculation tasks. For example, statistical analysis can be performed on the calculated voltage and current sequences to extract features such as RMS values, peak values, or phase differences; further transformations can be performed on the calculation results, such as performing spectral analysis to obtain harmonic content, or calculating the waveform slope to obtain the dynamic rate of change.

[0069] In one alternative implementation, such as Figure 8 The flowchart shown is a process for obtaining a fundamental wave value sequence, extracting slope features, and separating phase offset compensation values ​​as operating state parameters, according to an embodiment of this application. Specifically, it includes: Step S801: Obtain the fundamental frequency value sequence obtained by the independent coprocessor performing the numerical calculation task.

[0070] The fundamental frequency value sequence is structured time-series data extracted from the raw sampled data through spectral analysis. It characterizes the core energy transmission features of the power grid, rather than simply recording instantaneous voltage or current values. When the independent coprocessor performs numerical calculations, it first acquires the power grid voltage or current signal at a preset sampling frequency using a high-precision analog-to-digital converter. Then, it processes the sampled data window using Discrete Fourier Transform (DFT) or Fast Fourier Transform (FFT) algorithms. This process converts the mixed waveform signal in the time domain into frequency domain components, precisely selecting the complex components with the power grid fundamental frequency (e.g., 50Hz or 60Hz). These complex components contain amplitude and phase information. The fundamental frequency components within the continuous time window are then arranged sequentially to form the fundamental frequency value sequence. After generating this sequence, the independent coprocessor stores it in its internal dual-port RAM for real-time reading and analysis in subsequent steps.

[0071] Step S802: Extract slope features from the fundamental wave value sequence to obtain a set of slope values.

[0072] Slope feature extraction aims to capture transient distortion information of waveforms within small time scales, and is a key mathematical transformation process that converts steady-state amplitude sequences into dynamic rate-of-change indices. This step uses difference-based algorithms or polynomial fitting algorithms to process the fundamental wave value sequence. For example, a first-order difference algorithm can be used to calculate the ratio of the numerical difference between two adjacent sampling points in the sequence to the time interval, thereby obtaining the instantaneous slope at the current time point. This process can be formally represented by the following mathematical expression:

[0073] In the formula, Indicates the first The slope value corresponding to each sampling point and They represent the first The and the first The fundamental amplitude or phase value at each sampling point This represents the sampling period. By performing the above calculation on all sampling points in the entire fundamental value sequence, a set of slope values ​​containing multiple slope values ​​is obtained. This set intuitively reflects the current steepness and smoothness of the power grid's fundamental waveform. When the power grid experiences disturbances or sudden load changes, the values ​​in the slope value set will exhibit significant nonlinear fluctuations.

[0074] Step S803: Separate the phase offset compensation value from the slope value set and use the phase offset compensation value as the running status parameter.

[0075] Extracting the phase offset compensation value from the slope value set is a process of in-depth physical semantic interpretation of the waveform's dynamic characteristics. Since there is a specific mathematical mapping relationship between the zero-crossing slope of voltage and current waveforms and their phase difference, the slope value set contains crucial information about phase offset. The system performs statistical analysis or pattern matching on the slope value set to identify specific slope distribution patterns caused by phase lead or lag. Through inversion calculation or by searching a pre-established slope-phase mapping table, the corresponding phase offset compensation value is calculated. This phase offset compensation value quantifies the degree of phase deviation of the current power grid waveform relative to the standard reference waveform and is a sensitive indicator for determining whether the power grid is experiencing resonance, frequency drift, or abnormal power factor. The system directly assigns the calculated phase offset compensation value to the operating status parameter variable, making it the core decision-making basis for subsequent judgments on whether preset wake-up conditions are met, thereby ensuring that the main control chip's wake-up action has a clear physical event triggering logic.

[0076] The wake-up condition is a preset criterion used to determine whether the main control chip needs to intervene in the processing logic. Specifically, when the independent coprocessor detects that the running status parameters meet the wake-up condition, such as... Figure 9 The diagram shown illustrates a flowchart of generating an interrupt activation instruction and triggering the main control chip to exit deep sleep mode, according to an embodiment of this application. The method involves an independent coprocessor sending a wake-up signal to the main control chip to control it to exit deep sleep mode and resume execution of corresponding service scheduling tasks. The method further includes: Step S901: When the phase offset compensation value exceeds the preset wake-up threshold, an interrupt activation command is generated, and a wake-up signal is generated according to the interrupt activation command.

[0077] During the continuous execution of numerical calculation tasks by the independent coprocessor, it monitors in real time whether the calculated phase offset compensation value meets the wake-up conditions. The preset wake-up threshold is used to define the tolerance limit of the power grid phase deviation. The determination of this threshold may include, for example, collecting the statistical relationship between phase deviation and power grid fault rate from historical operating data and setting it in combination with safety margin, such as setting it to a value of 3 degrees, 5 degrees, etc., the specific value depending on the stability requirements of the power system.

[0078] When the currently extracted phase offset compensation value is detected to be greater than the preset wake-up threshold, it is determined that the current phase deviation has exceeded the normal fluctuation range, indicating a potential power quality anomaly or fault risk, and thus an interrupt activation instruction is generated. This interrupt activation instruction is a hardware control signal generated by the internal logic of the independent coprocessor, used to trigger the subsequent wake-up signal generation circuit. Subsequently, according to the interrupt activation instruction, a physical wake-up signal is generated through the coprocessor's wake-up signal trigger. This wake-up signal can be, for example, a level change signal (such as a transition from low to high) or a pulse signal with a specific timing, and its waveform characteristics must match the electrical characteristics of the external wake-up pin of the main control chip. Through this process, the software-level anomaly determination is transformed into a hardware-level electrical trigger signal.

[0079] Step S902: Send a wake-up signal to the main control chip to trigger the main control chip to exit the deep sleep state.

[0080] The independent coprocessor sends the generated wake-up signal to the main control chip via a dedicated hardware interconnect. This interconnect can be, for example, a general-purpose input / output (GPIO) pin configured for wake-up or a dedicated interrupt line for inter-chip interconnection. During transmission, the validity and stability of the signal are ensured, for example, by maintaining a valid level for a specific duration to ensure reliable capture by the main control chip. When the main control chip is in deep sleep mode, most of its internal modules are powered down or suspended, but the wake-up detection circuit is typically in a low-power standby monitoring mode. When the main control chip's wake-up detection pin receives a wake-up signal from the independent coprocessor, its internal power management module is triggered. The main control chip then begins executing a power-on sequence, including restoring the core power supply voltage, restarting the system clock oscillator, and initializing critical registers, thereby exiting deep sleep mode and transitioning to normal operation or standby mode, preparing for subsequent execution of business logic.

[0081] Step S903: The main control chip responds to the wake-up signal and resumes the execution of service scheduling tasks, and executes the service scheduling tasks with higher priority according to the scheduling priority information.

[0082] After the main control chip completes the switch from deep sleep mode to normal operation mode, it immediately responds to the wake-up signal and resumes execution of service scheduling tasks. To ensure the real-time response of the system and the processing efficiency of critical services, the previously generated scheduling priority information is invoked upon resumption of execution. This scheduling priority information records the priority level or weight order of each service scheduling task. The operating system kernel or task scheduler first scans the queue of currently suspended or ready service scheduling tasks and sorts the tasks according to the scheduling priority information.

[0083] During task allocation and execution, processor resources are prioritized for higher-priority business scheduling tasks, such as critical tasks involving power grid fault alarms and emergency protection control. Lower-priority tasks, such as log recording and non-real-time data uploading, are scheduled for later execution or temporarily suspended. This priority-based differentiated recovery strategy ensures that the main control chip processes the most urgent business logic immediately upon being woken up, maximizing the use of limited computing resources to guarantee the safety and reliability of power grid operation.

[0084] The aforementioned technical solution achieves precise on-demand wake-up of the main control chip by using an independent coprocessor to monitor the phase offset compensation value in real time and trigger a hardware interrupt wake-up mechanism. Compared to traditional timed wake-up or software polling methods, this mechanism has lower latency and higher energy efficiency, avoiding meaningless frequent wake-ups of the main control chip. Simultaneously, a task recovery strategy incorporating scheduling priority information ensures the priority processing of critical services, enabling the entire high-precision meter system to maintain rapid response and precise scheduling capabilities to abnormal grid conditions while achieving deep sleep energy saving.

[0085] In summary, the technical solution provided in this application separates numerical computation tasks from business scheduling tasks by triggering task granularity partitioning based on runtime parameters. An independent coprocessor handles the high-density numerical computation load, freeing the main control chip from heavy computational burdens. Under this split parallel processing architecture, the load on the main control chip is significantly reduced, enabling it to meet the triggering conditions for deep sleep and enter a low-power state. The independent coprocessor maintains independent operation during the main control chip's sleep period, ensuring the continuity of data acquisition and computation. When the runtime parameters extracted from the computation results meet the wake-up conditions, the independent coprocessor actively wakes up the main control chip, ensuring the timely recovery of business scheduling logic. This dynamic collaborative working mode of the main and coprocessors effectively solves the problem of excessive energy consumption in computationally intensive scenarios for high-precision meters, significantly reducing overall power consumption while ensuring metering accuracy.

[0086] Furthermore, an exemplary embodiment of this application also provides a high-precision electricity meter low-power scheduling system.

[0087] Figure 10 A block diagram illustrating an exemplary embodiment of a high-precision electricity meter low-power scheduling system of this application is shown. (Reference) Figure 10 The high-precision electricity meter low-power scheduling system 1000 according to an exemplary embodiment of this application may include: a triggering and task splitting module 1001, a task mapping and parallel processing module 1002, a sleep control module 1003, and a wake-up and recovery module 1004.

[0088] Specifically, the triggering and task segmentation module 1001 can be used to acquire operating parameters reflecting the operating status of the electricity meter, and determine whether the triggering conditions for computationally intensive services are met based on the operating parameters; in response to meeting the triggering conditions for computationally intensive services, the current service is segmented at the task granularity to separate the numerical computation task queue and the service scheduling task, and corresponding scheduling priority information is generated; the task mapping and parallel processing module 1002 can be used to dynamically map the numerical computation task queue to an independent coprocessor for execution, and map the service scheduling task to the main control chip for execution, based on the task granularity segmentation results and scheduling priority information, so as to establish a separate parallel processing mechanism between the independent coprocessor and the main control chip. The parallel processing architecture includes a sleep control module 1003, which continuously monitors the real-time load status of the main control chip during the operation of the split parallel processing architecture. When the real-time load status meets the deep sleep trigger condition, the main control chip is controlled to enter a deep sleep state, while the independent coprocessor continues to execute numerical calculation tasks. The wake-up and recovery module 1004 is used to determine the running status parameters based on the calculation results of the numerical calculation task during the execution of numerical calculation tasks by the independent coprocessor. When the running status parameters meet the wake-up condition, the independent coprocessor sends a wake-up signal to the main control chip to control the main control chip to exit the deep sleep state and resume the execution of the corresponding business scheduling tasks.

[0089] Since the functional modules of the high-precision meter low-power scheduling system in this application are the same as those in the above method implementation, they will not be described again here.

[0090] It should be noted that, in this document, the terms "comprising," "including," and any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Specific examples have been used in this document to illustrate the principles and implementation methods of the technical solutions of this application. The above examples are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are merely preferred embodiments of this application. It should be pointed out that, due to the limitations of written expression and the objective existence of infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this application, and can also combine the above technical features in an appropriate manner; these improvements, modifications, changes, or combinations, or the direct application of the concept and technical solutions of this application to other situations without modification, should all be considered within the scope of protection of this application.

Claims

1. A low-power scheduling method for high-precision electricity meters, characterized in that, The method includes: Obtain operating parameters reflecting the operating status of the electricity meter, and determine whether the triggering conditions for computationally intensive services are met based on the operating parameters; in response to meeting the triggering conditions for computationally intensive services, perform task granularity segmentation on the current service to separate the numerical calculation task queue and the service scheduling task, and generate corresponding scheduling priority information; Based on the task granularity segmentation results and the scheduling priority information, the numerical computation task queue is dynamically mapped to an independent coprocessor for execution, and the business scheduling task is mapped to the main control chip for execution, so as to establish a separate parallel processing architecture between the independent coprocessor and the main control chip. During the operation of the split parallel processing architecture, the real-time load status of the main control chip is continuously monitored. When the real-time load status meets the deep sleep trigger condition, the main control chip is controlled to enter a deep sleep state, while the independent coprocessor continues to execute numerical calculation tasks. During the execution of the numerical calculation task by the independent coprocessor, the running status parameters are determined based on the calculation results of the numerical calculation task. When the running status parameters meet the wake-up conditions, the independent coprocessor sends a wake-up signal to the main control chip to control the main control chip to exit the deep sleep state and resume the execution of the corresponding business scheduling task.

2. The method according to claim 1, characterized in that, The operating parameters include instantaneous power peak and harmonic distortion rate; The step of determining whether the triggering conditions for computationally intensive services are met based on the operating parameters includes: Determine whether the instantaneous power peak exceeds the corresponding power threshold, and determine whether the harmonic distortion rate exceeds the corresponding harmonic threshold; When the instantaneous power peak exceeds the power threshold and the harmonic distortion rate exceeds the harmonic threshold, it is determined that the current service meets the triggering condition of the computationally intensive service, and task granularity segmentation is initiated.

3. The method according to claim 1, characterized in that, The step of dividing the current business into task-granular segments to separate numerical computation task queues and business scheduling tasks, and generating corresponding scheduling priority information, includes: Based on the computational attributes and real-time requirements of each business subtask in the current business, the business subtasks involving numerical computation and analysis are extracted into the numerical computation task queue, and the remaining business subtasks are used as the business scheduling tasks. The scheduling levels corresponding to the numerical computation task queue and the business scheduling task are determined, and the scheduling priority information is generated according to the scheduling levels.

4. The method according to claim 3, characterized in that, The method further includes: Based on the spectral components corresponding to the numerical calculation analysis, the numerical calculation task queue is divided into fundamental component calculation tasks and non-fundamental component calculation tasks. Based on the computational timeliness and computational complexity of the fundamental component calculation task and the non-fundamental component calculation task, the subtask scheduling level within the numerical calculation task queue is determined respectively. The fundamental component calculation task and the non-fundamental component calculation task are sorted according to the subtask scheduling level to update the sorting relationship within the numerical calculation task queue in the scheduling priority information.

5. The method according to claim 1, characterized in that, The step of dynamically mapping the numerical computation task queue to an independent coprocessor for execution includes: A task mapping table is established based on the task granularity segmentation results. The task mapping table is used to characterize the correspondence between each task in the numerical computation task queue and the processing resources of the independent coprocessor. According to the task mapping table, each task in the numerical computation task queue is assigned to the processing resources corresponding to the independent coprocessor for execution.

6. The method according to claim 1, characterized in that, When the real-time load state meets the deep sleep trigger condition, controlling the main control chip to enter a deep sleep state includes: Obtain the bus bandwidth utilization and heartbeat frequency of the main control chip; A comprehensive load status parameter is constructed based on the bus bandwidth utilization rate and the heartbeat frequency; The comprehensive load status parameters are compared with a preset sleep determination threshold; When the overall load status parameter is lower than the preset sleep determination threshold, the main control chip is controlled to enter the deep sleep state.

7. The method according to claim 1, characterized in that, Maintaining the independent coprocessor to continue executing the numerical computation task includes: Maintain the task mapping relationship between the numerical computation task queue and the independent coprocessor; The independent coprocessor is controlled to continue executing the numerical calculation task while the main control chip is in a deep sleep state, and the calculation results are cached. The sampling frequency and computing frequency are dynamically adjusted according to the operating load of the independent coprocessor to reduce the energy consumption of the independent coprocessor during independent operation.

8. The method according to claim 1, characterized in that, Determining the operating status parameters based on the calculation results of the numerical calculation task includes: Obtain the fundamental frequency value sequence obtained by the independent coprocessor executing the numerical calculation task; The slope feature is extracted from the fundamental wave value sequence to obtain a set of slope values; The phase offset compensation value is separated from the slope value set and used as the operating state parameter.

9. The method according to claim 8, characterized in that, The step of sending a wake-up signal from the independent coprocessor to the main control chip to control the main control chip to exit the deep sleep state and resume execution of the corresponding service scheduling tasks includes: When the phase offset compensation value exceeds a preset wake-up threshold, an interrupt activation command is generated, and a wake-up signal is generated based on the interrupt activation command. The wake-up signal is sent to the main control chip to trigger the main control chip to exit the deep sleep state; The main control chip responds to the wake-up signal and resumes execution of the service scheduling task, and executes the service scheduling task with higher priority according to the scheduling priority information.

10. A high-precision, low-power scheduling system for electricity meters, characterized in that, The system includes: The triggering and task segmentation module is used to acquire operating parameters reflecting the operating status of the electricity meter, determine whether the triggering conditions for computationally intensive services are met based on the operating parameters, and in response to meeting the triggering conditions for computationally intensive services, perform task granular segmentation on the current service to separate the numerical calculation task queue and the service scheduling task, and generate corresponding scheduling priority information. The task mapping and parallel processing module is used to dynamically map the numerical calculation task queue to an independent coprocessor for execution and to map the business scheduling task to the main control chip for execution, based on the task granularity segmentation result and the scheduling priority information, so as to establish a separate parallel processing architecture between the independent coprocessor and the main control chip. The hibernation control module is used to continuously monitor the real-time load status of the main control chip during the operation of the split parallel processing architecture. When the real-time load status meets the deep hibernation trigger condition, the module controls the main control chip to enter a deep hibernation state and keeps the independent coprocessor running numerical calculation tasks. The wake-up and recovery module is used to determine the running status parameters based on the calculation results of the numerical calculation task during the execution of the numerical calculation task by the independent coprocessor. When the running status parameters meet the wake-up conditions, the independent coprocessor sends a wake-up signal to the main control chip to control the main control chip to exit the deep sleep state and resume the execution of the corresponding business scheduling task.

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