Low power sleep method, device and storage medium for car-grade chip

Abstract

The application relates to the technical field of automotive-grade chip, and discloses a low-power sleep method and device for an automotive-grade chip and a storage medium. The method comprises the following steps: capturing a sleep enabling signal through a hardware sleep control unit, latching a gate timing parameter and establishing a power supply network topology state table; fusing a multi-dimensional environment simulation signal and an impedance monitoring value to generate a transient voltage feature vector; constructing a discrete voltage matrix and performing behavior intention identification to distinguish between active sleep and passive disturbance; when the passive disturbance is identified and the trigger condition is met, performing feature dimension reduction to generate a reduced dimension feature vector; inputting the reduced dimension feature vector into a voltage prediction model to obtain a predicted amplitude, and updating the gate timing parameter when the predicted amplitude exceeds a safety window; determining a final shutdown execution sequence according to the updated parameter and driving a functional module to perform physical power-off sleep. The application improves the prediction accuracy of transient voltage fluctuation and avoids sleep execution distortion caused by misjudgment of external disturbance.

Description

Technical Field

[0001] This application relates to the field of automotive-grade chip technology, and in particular to a low-power sleep method, apparatus and storage medium for automotive-grade chips. Background Technology

[0002] As a core component of intelligent connected vehicle electronic systems, automotive-grade chips' low-power sleep management directly impacts vehicle energy efficiency and system reliability. During the chip's entry into low-power sleep mode, the state transitions of the internal power supply network and clock tree trigger complex transient electrical characteristic changes. As each functional module shuts down sequentially according to the clock shutdown sequence, the load current in the power supply network decreases in a stepwise manner. The combined effects of parasitic resistance and capacitance can generate voltage spikes exceeding the chip's tolerance range. If these voltage spikes are not effectively suppressed, they may lead to chip malfunction or even permanent damage.

[0003] Existing chip sleep control methods suffer from the following shortcomings. First, voltage fluctuation prediction during sleep largely relies on measured data from physical samples or parameter settings based on static worst-case principles. This is not only costly and time-consuming, but also makes it difficult to capture the chip's true performance under extreme automotive environments in the early design stages. Second, temperature fluctuations and electromagnetic interference in the vehicle environment continuously affect the chip's internal resistance and capacitance parameters, causing the same sleep phase to exhibit drastically different voltage response characteristics under different environmental conditions. Traditional methods fail to incorporate the dynamic changes of environmental factors into the sleep control decision-making system. Third, existing sleep control schemes are typically executed in software by the chip's main processor. When the chip is in a low-power sleep state, the main processor may have been partially or completely powered off, making it difficult to sense the voltage status and make adjustments in real time during sleep.

[0004] Therefore, how to build a control system at the hardware level that can sense environmental changes in real time, accurately predict voltage fluctuations, and adaptively optimize sleep timing has become a technical problem that urgently needs to be solved in the field of low-power sleep mode for automotive-grade chips. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a low-power sleep method, apparatus, and storage medium for automotive-grade chips, which addresses the issues of sleep execution distortion and chip function failure caused by transient voltage fluctuations and misjudgments of disturbances during the sleep process of automotive-grade chips.

[0006] Firstly, this application provides a low-power sleep mode method for automotive-grade chips, the method comprising: Step S1: Capture the sleep enable signal through the hardware sleep control unit, latch the gate timing parameters of the current physical clock tree, and establish the topology state table of the chip's internal power supply network; Step S2: Fuse the acquired multi-dimensional environmental simulation signal with the impedance monitoring value in the topology state table to generate the first transient voltage feature vector; Step S3: Construct a discrete voltage matrix based on the first transient voltage feature vector, and perform behavioral intent recognition based on the discrete voltage matrix to distinguish between active sleep switching and passive power transient disturbances; Step S4: If the transient disturbance is identified as a passive power supply disturbance and the disturbance triggering condition is met, then feature dimensionality reduction processing is performed on the discrete voltage matrix to generate a second transient voltage feature vector; Step S5: Input the second transient voltage feature vector and the obtained parasitic capacitance value into the preset voltage prediction model, output the voltage fluctuation prediction amplitude, and update the gating timing parameters when the voltage fluctuation prediction amplitude exceeds the preset safety window; Step S6: Determine the final shutdown execution sequence based on the updated gating timing parameters and the topology state table, and drive the corresponding functional modules step by step through the gating drive array to perform physical power-off hibernation operations according to the final shutdown execution sequence.

[0007] Secondly, this application provides a low-power sleep device for automotive-grade chips, the device comprising: The topology modeling unit captures the sleep enable signal through the hardware sleep control unit, latches the gate timing parameters of the current physical clock tree, and establishes the topology state table of the chip's internal power supply network. The environmental analysis unit integrates the collected multi-dimensional environmental simulation signals with the impedance monitoring values ​​in the topology state table to generate a first transient voltage feature vector; The intent recognition unit constructs a discrete voltage matrix based on the first transient voltage feature vector, and performs behavioral intent recognition based on the discrete voltage matrix to distinguish between active sleep switching and passive power transient disturbances. If the disturbance processing unit identifies a passive power supply transient disturbance and meets the disturbance triggering condition, it performs feature dimensionality reduction processing on the discrete voltage matrix to generate a second transient voltage feature vector. The compensation update unit inputs the second transient voltage feature vector and the acquired parasitic capacitance value into a preset voltage prediction model, outputs the voltage fluctuation prediction amplitude, and updates the gating timing parameters when the voltage fluctuation prediction amplitude exceeds a preset safety window. The hibernation drive unit determines the final shutdown execution sequence based on the updated gating timing parameters and the topology state table, and drives the corresponding functional modules to perform physical power-off hibernation operations step by step through the gating drive array according to the final shutdown execution sequence.

[0008] A third aspect of this application provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the aforementioned low-power sleep method for automotive-grade chips.

[0009] Compared with the prior art, the beneficial effects of the present invention are at least as follows: This application independently completes the entire hibernation control process, from signal acquisition to physical power-off, through a hardware hibernation control unit, without relying on the main processor. This reduces power management overhead while improving the real-time performance and reliability of hibernation execution. By constructing a discrete voltage matrix and performing behavioral intent recognition, it accurately distinguishes between active hibernation switching and passive power transient disturbances, avoiding hibernation execution distortion caused by misjudgment of external disturbances and improving the accuracy of voltage fluctuation prediction. By fusing multi-dimensional environmental simulation signals and impedance monitoring values ​​for dynamic coupling feature extraction, and updating the gating timing parameters when the voltage prediction amplitude exceeds the safety window, the hibernation timing has adaptive adjustment capabilities, ensuring the low-power hibernation safety and reliability of automotive-grade chips in complex automotive environments. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart of a low-power sleep method for automotive-grade chips in an embodiment of this application; Figure 2 This is a schematic diagram of the underlying physical architecture of an automotive-grade chip according to an embodiment of this application; Figure 3 This is a schematic diagram of a low-power sleep device for automotive-grade chips according to an embodiment of this application. Detailed Implementation

[0012] This application provides a low-power sleep method, apparatus, and storage medium for automotive-grade chips. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" or "having" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0013] For ease of understanding, the specific process of the embodiments of this application is described below. Please refer to [link / reference]. Figure 1 This application provides a low-power sleep method for automotive-grade chips, applied to a hardware sleep control unit built into the automotive-grade chip, comprising: Step S1: Capture the sleep enable signal through the hardware sleep control unit, latch the gate timing parameters of the current physical clock tree, and establish the topology state table of the chip's internal power supply network.

[0014] The step S1 of establishing the topology state table of the chip's internal power supply network includes: parsing the sleep enable signal to extract the clock shutdown sequence and latching it as a gating timing parameter; traversing the physical interconnection structure of the power supply network based on the gating timing parameter, extracting power supply nodes and generating a node connectivity graph; removing redundant power supply paths in the node connectivity graph to obtain a simplified path set; calculating the node voltage drop distribution based on the impedance parameters of the simplified path set and selecting high-power nodes that are greater than a preset power consumption threshold; dividing the high-power nodes into a sleep state set according to the hierarchical relationship and mapping them to the node connectivity graph to establish the topology state table.

[0015] Specifically, such as Figure 2The diagram shows the underlying physical architecture of an automotive-grade chip. The chip integrates a power supply network, a physical clock tree, multiple functional modules, and a hardware sleep control unit. The power supply network consists of a top-level power distribution node and multiple power supply paths. Switches on each power supply path are connected to the power supply ports of each functional module to distribute power. The physical clock tree consists of multiple clock paths, each connected to the clock input of each functional module to provide its operating clock. The hardware sleep control unit is integrated into the automotive-grade chip and operates independently of the main processor. It includes an analog signal sampling front-end, a hardware comparator, a hardware timer, and a gating drive array. The input of the analog signal sampling front-end is connected to the output of a temperature sensor on the chip substrate and the output of an electromagnetic interference sensor inside the chip. It collects environmental physical analog signals and performs analog-to-digital conversion. Its output is connected to the data bus inside the hardware sleep control unit. The input of the hardware comparator is connected to the data bus inside the hardware sleep control unit. It receives voltage elements from a discrete voltage matrix and compares them with a preset hardware voltage threshold.

[0016] The output of the hardware timer is connected to the timing control register inside the hardware sleep control unit, providing the time base and counting function required for discretization slicing. The input of the gated drive array is connected to the timing control register inside the hardware sleep control unit to receive updated gating timing parameters. Its outputs are connected to the control terminals of the switching devices on each power supply path, outputting drive signals to control the switching devices on each functional module's power supply path to perform physical power-off operations. The hardware sleep control unit is also connected to the gating unit of the physical clock tree via an internal control bus, used to latch the gating timing parameters on the current physical clock tree path, and to reconfigure the shutdown nodes of the physical clock tree after updating the gating timing parameters through timing compensation.

[0017] In the above architecture, the hardware sleep control unit, triggered by the sleep enable signal, latches gating timing parameters, acquires environmental physical simulation signals, performs voltage comparison and timing slicing, updates timing parameters, and finally drives the switching devices to perform power-off operations through the gating drive array, independently completing the entire sleep control from signal acquisition to physical execution.

[0018] In the specific execution of step S1, the sleep enable signal is first captured by the hardware sleep control unit. As an ultra-low-power coprocessor with independent power supply within the automotive-grade chip, the hardware sleep control unit can monitor the entire chip's operating status in real time. The sleep enable signal is the power reduction instruction issued by the vehicle's main control system when the vehicle is off or in low-power standby mode. The system parses this sleep enable signal to extract the clock shutdown sequence. This clock shutdown sequence precisely defines the expected power-down order of each logic module within the chip. The system latches this sequence into a safety register as the initial gating timing parameters. This operation is performed to prevent the loss of timing configuration data due to transient fluctuations in the main power supply network or environmental electromagnetic interference, ensuring that subsequent physical power-down operations are predictable.

[0019] Subsequently, the physical interconnect structure of the power supply network is traversed based on the gated timing parameters. The physical interconnect structure refers to the specific metal wiring distribution network inside the chip from the top-level power grid to each underlying logic macrocell. By tracing the functional modules pointed to by the clock shutdown sequence level by level, all relevant power supply nodes are extracted, and a node connectivity graph is generated using graph theory algorithms. This connectivity graph fully reflects the topological mapping relationship of the intersection points of each power supply branch. To reduce the chip's computing power overhead and improve the real-time performance of sleep response, the system adopts a depth-first search strategy to identify and eliminate redundant power supply paths such as bypass capacitor branches in the node connectivity graph, thereby obtaining a simplified path set.

[0020] After obtaining the simplified path set, the hardware sleep control unit reads the parasitic resistance and parasitic capacitance values ​​corresponding to each power supply path in the set. These parameters reflect the parasitic effects generated in the physical implementation of the power supply network due to the resistance of the metal interconnects themselves and the inter-line coupling capacitance. Among them, the parasitic resistance value is used for subsequent steady-state voltage drop analysis and high-power node screening; the parasitic capacitance value is stored in the internal register of the hardware sleep control unit. This value is independent of the generation process of the transient voltage feature vector and will be used as an independent input dimension. After being concatenated with the second transient voltage feature vector in the voltage prediction model inference stage of step S5, it will be input into the model to calculate the transient voltage spike amplitude generated by the release of charge by the parasitic capacitance at the moment of shutdown of each functional module.

[0021] For the voltage drop distribution under steady-state operating conditions, the hardware sleep control unit calculates the steady-state voltage drop of each power supply node under preset steady-state load conditions by multiplying the load current flowing through the power supply path by the parasitic resistance value, based on Ohm's law. This yields the steady-state voltage drop distribution of each node, generating an initial voltage drop distribution map. This initial voltage drop distribution map reflects the electrical state of each power supply node during steady-state operation before sleep mode activation, serving as the data basis for subsequent power consumption value extraction and high-power node screening. For each power supply node, the actual voltage value and load current value in the initial voltage drop distribution map are read, and the two are multiplied to obtain the instantaneous power value of the node, which is then used as the power consumption value of the node. Nodes exceeding a preset power consumption threshold are marked and screened as high-power nodes. These high-power nodes store a large amount of electric field energy at the moment of sleep mode shutdown, and their release process generates large-amplitude transient voltage fluctuations, which are the main source of voltage disturbances during sleep mode.

[0022] Subsequently, the hardware sleep control unit groups and plans the selected high-power nodes according to the electrical hierarchy reflected in the node connectivity graph. Here, the electrical hierarchy refers to the hierarchical power distribution structure of the power supply network from the top-level power distribution node to the power supply ports of each functional module. Nodes within the same level have similar electrical characteristics, while different levels have clear voltage and clock domain affiliations. Specifically, the hardware sleep control unit uses a hierarchical clustering algorithm to cluster the high-power nodes. This algorithm initially treats each high-power node as an independent cluster, using the electrical distance and impedance similarity between nodes as metrics for merging two clusters. Through a bottom-up agglomerative merging strategy, in each round of merging, the two clusters with the highest similarity are selected for merging until all nodes are merged into one large cluster. During this process, the silhouette coefficient is used to evaluate the clustering effect at different merging stages. For any clustered high-power node, the average distance between the node and other nodes in its group, and the average distance between the node and its nearest neighbor nodes in other groups are calculated. The silhouette coefficient of the node is obtained by subtracting the former from the latter and dividing by the larger of the two values. The overall profile coefficient of the current clustering result is obtained by averaging the profile coefficients of all nodes. The closer the value is to positive one, the better the grouping effect. In this application, the hardware sleep control unit calculates the overall profile coefficient after each round of merging. When the coefficient reaches its maximum value, merging stops, and the current group is identified as a high-power cluster. Through this clustering, high-power nodes that are electrically adjacent and have similar impedance characteristics are grouped into the same sleep group, avoiding the superimposed voltage spikes caused by the simultaneous shutdown of multiple electrically close high-power nodes.

[0023] Finally, the hardware sleep control unit generates corresponding sleep state configuration parameters based on the electrical characteristics of each high-power cluster. These configuration parameters specify the order in which nodes within the same cluster are turned off during sleep execution and the time interval between adjacent turn-off actions. The sleep state configuration parameters are then mapped to the corresponding power supply nodes in the node connectivity graph, thereby completing the establishment of the topology state table.

[0024] When generating the corresponding sleep state configuration parameters, for multiple nodes within the same cluster, nodes with higher impedance values ​​and closer to the top-level power supply port are set as priority shutdown targets to reduce the current extraction effect on adjacent branches before shutdown. The time interval between two adjacent shutdown actions is determined based on the time constant corresponding to the maximum value of the product of parasitic resistance and parasitic capacitance in all power supply paths within the cluster, ensuring that the voltage oscillation amplitude caused by the shutdown of the previous node decays to a preset stable ratio before starting the shutdown operation of the next node. If there are mutually coupled power supply paths between different clusters, the shutdown actions of different clusters to which the coupled paths belong are alternately arranged in time according to the path intersection relationship reflected in the node connectivity diagram to avoid multiple high-power paths superimposing to generate instantaneous current spikes at the same time.

[0025] Step S2: Fuse the acquired multi-dimensional environmental simulation signal with the impedance monitoring value in the topology state table to generate the first transient voltage feature vector.

[0026] Step S2 includes: performing discretization sampling on the temperature simulation signal and the environmental electromagnetic interference simulation signal, and aligning them with the impedance monitoring values ​​in the topology state table in time sequence to construct and clean a standard environmental dataset; extracting the impedance sequence and temperature sequence from the standard environmental dataset and performing differential operations to generate an environmental change rate sequence; if the maximum value of the environmental change rate sequence exceeds a preset fluctuation threshold, then performing coupling calculations on the standard environmental dataset through a machine learning model to obtain a first coupling feature vector; extracting the time sequence features of the first coupling feature vector to generate a second coupling feature vector, and performing transient value mapping processing to generate a first transient voltage feature vector.

[0027] Specifically, temperature changes alter the resistance of the metal interconnects in the power supply network; higher temperatures result in greater resistance, leading to a larger voltage drop under the same load current. Electromagnetic interference (EMI) signals couple to power supply nodes via parasitic capacitance between the metal interconnects, superimposing high-frequency noise components into the node voltage. Impedance monitoring values ​​reflect the electrical state of the power supply network itself, including the parasitic resistance of each power supply path. These three factors do not independently affect voltage but exhibit a nonlinear coupling relationship. For example, increased temperature alters resistivity, increasing the parasitic resistance component in the impedance monitoring value. This increased parasitic resistance generates a larger voltage coupling component under the same EMI intensity, and this coupling has a cumulative effect over time; a temperature change at a certain moment will continuously affect the impedance characteristics and voltage response at subsequent moments. Therefore, step S2 quantifies the combined effects as voltage amplitude by fusing the acquired multidimensional environmental simulation signals with the impedance monitoring values ​​in the topology state table, generating a first transient voltage feature vector.

[0028] In the specific execution of step S2, the hardware sleep control unit first acquires the analog temperature signal of the chip substrate and the analog electromagnetic interference signal of the chip's environment in real time through the analog signal sampling front end. The analog temperature signal reflects the current thermal state of the chip and is output by a temperature sensor arranged on the chip substrate; its voltage amplitude changes linearly with temperature. The analog electromagnetic interference signal reflects the intensity of external radiated or conducted interference and is output by an electromagnetic interference sensor inside the chip; its voltage amplitude changes with interference intensity. Both of these signals are analog quantities that change continuously with time. To facilitate subsequent digital domain processing, the analog-to-digital converter inside the hardware sleep control unit performs discretization sampling on the two analog signals, reading the instantaneous voltage amplitude of each signal at a fixed sampling frequency and converting them into digital sequences arranged in chronological order, thus obtaining the temperature digital sequence and the electromagnetic interference digital sequence, respectively.

[0029] Meanwhile, the hardware sleep control unit reads the impedance monitoring values ​​corresponding to each power supply node from the established topology status table. These impedance monitoring values ​​include the parasitic resistance values ​​of each power supply path. Since the temperature digital sequence, electromagnetic interference digital sequence, and impedance monitoring values ​​come from different sampling channels, and their sampling times and frequencies are different, to ensure that the data from different sources have a consistent time reference in subsequent analysis, the hardware sleep control unit uses a unified sampling clock as a reference standard and aligns the three to the same time coordinate system through interpolation and resampling operations. This ensures that at each point in time, the corresponding temperature value, electromagnetic interference intensity value, and impedance monitoring value exist simultaneously.

[0030] After timing alignment is completed, the hardware sleep control unit performs outlier detection and removal on the three sets of data. That is, it identifies and deletes isolated value points that deviate significantly from the normal range due to occasional sensor failures or sudden external interference. The gaps left after removal are filled by linear interpolation of values ​​from adjacent time points, thereby constructing a standard environmental dataset. This dataset contains time-aligned and cleaned temperature, electromagnetic interference, and impedance sequences.

[0031] After constructing the standard environmental dataset, the hardware sleep control unit extracts the impedance and temperature sequences and performs differential operations on them. For the impedance sequence, the impedance values ​​at adjacent time points are subtracted sequentially, i.e., the impedance value at the later time point is subtracted from the impedance value at the previous time point, to obtain the impedance change sequence. For the temperature sequence, the temperature values ​​at adjacent time points are subtracted sequentially in the same way, to obtain the temperature change sequence. Each difference in the impedance change sequence is divided by the corresponding sampling time interval to obtain the impedance change rate sequence; each difference in the temperature change sequence is divided by the corresponding sampling time interval to obtain the temperature change rate sequence. The impedance change rate sequence and the temperature change rate sequence together constitute the environmental change rate sequence. Each value in this sequence represents the rate of change of the impedance or temperature value within the corresponding time interval, with the sign indicating the direction of change and the absolute value indicating the degree of change.

[0032] The hardware sleep control unit further calculates the maximum value in the environmental change rate sequence and compares it with a preset fluctuation threshold. The preset fluctuation threshold is an empirical value stored in the hardware sleep control unit register. Its value is determined based on the statistical range of temperature and impedance fluctuations of automotive-grade chips under normal stable operating conditions. When the maximum value of the environmental change rate does not exceed the threshold, it means that the external environment of the chip is in a relatively stable state, and its impact on the transient voltage of the power supply network is within the safety tolerance. There is no need to start subsequent machine learning calculations to save hardware resources and power consumption. Conversely, if the maximum value exceeds the threshold, it indicates that the environment has changed significantly. This change will have a non-negligible impact on the transient voltage of the power supply network, and its coupling effect needs to be further analyzed.

[0033] If the maximum value of the environmental change rate sequence exceeds a preset fluctuation threshold, the hardware sleep control unit initiates a machine learning model to perform coupled calculations on a standard environmental dataset. This machine learning model employs a long short-term memory network structure, and the training process is completed offline during the chip design phase. Specifically, it involves: pre-collecting measured transient voltage waveforms and corresponding environmental parameter sequences under various temperature conditions and electromagnetic interference intensity combinations; using the temperature value, electromagnetic interference intensity value, and impedance monitoring value from the environmental parameter sequence as model input; and using the coupled feature components obtained from signal separation processing in the measured transient voltage waveform as training labels. The signal separation processing employs a digital bandpass filtering method, specifically: based on the chip... The clock frequency range of each functional module inside the chip is set with low-pass cutoff frequency and high-pass cutoff frequency to construct a bandpass filter. The measured transient voltage waveform is input into the bandpass filter to filter out high-frequency digital switching noise generated by high-speed logic switching inside the chip and extremely low-frequency components caused by DC power supply offset, and to extract voltage fluctuation components whose frequency band is located in the temperature change and electromagnetic interference response band. The extracted voltage fluctuation components are further subjected to time-domain segment truncation based on short-time energy threshold to remove the thermal noise base segment of the measurement channel itself, and the remaining effective fluctuation segments are used as the coupling feature components corresponding to the current input environment parameter sequence in time, and are used as training labels.

[0034] Using mean squared error as the loss function, the input gate weight matrix, forget gate weight matrix, output gate weight matrix, and corresponding bias terms within the network are iteratively updated through the backpropagation algorithm. During training, an adaptive moment estimation algorithm is used to optimize the values ​​of each weight matrix and bias term. Training stops when the loss function value drops below the preset convergence threshold. At this point, the weight matrices and bias terms within the model have been adjusted to accurately describe the mapping relationship between environmental parameters and coupling features. This set of weight matrices and bias terms is permanently stored in the non-volatile storage medium inside the hardware sleep control unit for use in the actual inference stage.

[0035] During the actual inference phase, the hardware sleep control unit sequentially inputs the temperature sequence, electromagnetic interference sequence, and impedance sequence from the standard environmental dataset into the trained stacked long short-term memory network in time steps. This stacked long short-term memory network consists of a first-layer LSTM and a second-layer LSTM stacked vertically. The two layers are jointly optimized during the training phase, and their weight matrices and bias terms are iteratively updated and stored through the backpropagation algorithm.

[0036] For each time step input, the first-layer LSTM first fuses the current 3D environmental input (temperature value, electromagnetic interference intensity value, impedance monitoring value, impedance monitoring value) with the hidden state of the previous time step through the synergistic action of three gating mechanisms: forget gate, input gate, and output gate, outputting the first-layer hidden state vector. This first-layer hidden state vector integrates the environmental information of the current time step with the accumulated information of historical time steps, initially extracting the dynamic coupling relationship between temperature, electromagnetic interference, and impedance over time. Subsequently, the first-layer hidden state vector output by the first-layer LSTM at the current time step is used as the input of the second-layer LSTM at the current time step. The second-layer LSTM uses the same gating mechanism as the first layer to further extract the temporal features of the first-layer hidden state vector, outputting the second-layer hidden state vector. The second-layer LSTM, through its own cell state, transmits the high-level temporal features of the previous time step to the current time step, enabling the second-layer output at the current time step to integrate the temporal evolution patterns over a longer time scale. The stacked Long Short-Term Memory (LSTM) network sequentially performs the above two-layer computation at each time step. The hidden state vectors output by the second-layer LSTM at each time step constitute a set of feature sequences describing the dynamic coupling relationship and temporal evolution trend between temperature, electromagnetic interference, and impedance. This feature sequence is the second coupling feature vector. Based on the integration of environmental factor coupling relationships, this second coupling feature vector further explicitly strengthens the trend information of the coupling effect over time, making the feature vector contain the law of how each influencing factor gradually changes over time. Furthermore, its vector dimension is fixed to the number of neurons in the second-layer LSTM hidden layer and does not change with the length of the input sequence.

[0037] After generating the second coupling feature vector, the hardware sleep control unit performs transient value mapping on the vector, converting it into a voltage domain feature description. Before transient value mapping, the hardware sleep control unit first performs normalization processing on each element in the second coupling feature vector, that is, mapping the temperature change value, electromagnetic interference intensity value, and impedance change value in the vector to dimensionless values ​​between zero and one according to their respective ranges. After the normalization processing is completed, the hardware sleep control unit performs transient value mapping. Specifically, the hardware sleep control unit internally stores a pre-calibrated mapping function, which uses the temperature-to-voltage conversion coefficient, interference-to-voltage coupling coefficient, and impedance-to-voltage conversion coefficient as core parameters. Multiplying the normalized temperature change value by the preset temperature-to-voltage conversion coefficient yields the voltage offset caused by the temperature change. This temperature-to-voltage conversion coefficient is calculated based on the resistance-temperature curve in the chip datasheet. For example, since the resistance-temperature curve can be approximately considered a linear relationship within the operating temperature range of automotive-grade chips, this coefficient remains constant within this temperature range. The specific calibration method is as follows: During the chip design phase, the parasitic resistance of the power supply path is measured at different temperature points using simulation tools. The slope of the resistance change with temperature is fitted, and this slope is multiplied by a preset load current value to obtain the temperature-voltage conversion coefficient. Similarly, the normalized electromagnetic interference intensity value is multiplied by a preset interference-voltage coupling coefficient to obtain the voltage fluctuation component caused by the interference. This interference-voltage coupling coefficient is calculated based on the power supply rejection ratio parameter in the chip datasheet. The normalized impedance change value is multiplied by a preset impedance-voltage conversion coefficient to obtain the voltage drop caused by the impedance change. This impedance-voltage conversion coefficient is calculated based on Ohm's law from the preset load current value and the impedance monitoring value, and the unit is volt. Since the original physical dimensions of the above three coefficients have been converted to volts during the calibration process, the results of the three components are dimensionally unified.

[0038] The voltage offset caused by temperature changes, the voltage fluctuation component caused by interference, and the voltage drop caused by impedance changes are added sequentially at their corresponding time points to obtain a set of voltage amplitude sequences arranged in chronological order. This sequence is the first transient voltage feature vector obtained through transient value mapping. By mapping the dynamic coupling relationship of environmental factors into specific voltage values, the originally abstract changes in environmental parameters are quantitatively described in the form of voltage amplitudes, providing numerical inputs with clear physical meaning for subsequent discretization matrix construction and behavioral intent recognition.

[0039] Step S3: Construct a discrete voltage matrix based on the first transient voltage feature vector, and perform behavioral intent recognition based on the discrete voltage matrix to distinguish between active sleep switching and passive power supply transient disturbances.

[0040] In step S3, constructing a discrete voltage matrix based on the first transient voltage feature vector includes: slicing the first transient voltage feature vector in the time dimension, extracting time nodes and corresponding voltage amplitudes, and constructing an initial discrete voltage matrix; comparing the voltage elements of the initial discrete voltage matrix with a preset abnormal threshold to identify abnormal transient segments; and removing abnormal data based on the abnormal transient segments to obtain the final discrete voltage matrix.

[0041] In step S3, distinguishing between active sleep switching and passive power supply transient disturbances includes: calculating the voltage slope and acceleration of change at adjacent time nodes based on the discrete voltage matrix, and separating the fundamental falling fundamental component and the high-frequency oscillation component; calculating the dynamic time warping distance between the fundamental falling fundamental component and the pre-stored standard lower voltage waveform template, and calculating the energy density value of the high-frequency oscillation component; if the dynamic time warping distance is less than a preset threshold, the voltage slope is monotonically decreasing, the acceleration of change is continuously negative and the absolute value is less than a preset acceleration threshold, and the energy density value is lower than the noise baseline, then it is determined to be an active sleep switching; if the warping distance is not less than a preset threshold, the voltage slope polarity is reversed, or the energy density value is not lower than the noise baseline, then it is determined to be a passive power supply transient disturbance.

[0042] Specifically, after obtaining the first transient voltage feature vector, this vector describes the transient voltage state of the chip's power supply network under the current environmental conditions in the form of a voltage amplitude sequence. This vector contains effective voltage change information reflecting sleep behavior, but may also include abnormal data points caused by occasional sensor noise or sudden external interference. Furthermore, its data format is not yet suitable for behavior pattern discrimination. Therefore, step S3 first converts the vector into a well-structured discrete voltage matrix and removes abnormal data. Then, based on this matrix, behavior intent recognition is performed to distinguish whether the current voltage change is a normal sleep activity initiated by the chip or a passive disturbance caused by external interference, thus avoiding timing adjustments errors or sleep execution distortion in subsequent steps due to misjudgment.

[0043] In the specific execution process of constructing the discrete voltage matrix, the hardware sleep control unit first performs time-dimension slicing processing on the first transient voltage feature vector. The first transient voltage feature vector is a sequence of voltage amplitudes arranged in chronological order, and the time interval between adjacent data points is determined by the fixed sampling frequency of the analog-to-digital converter in step S2. The hardware sleep control unit takes each data point in this sequence as a sampling point, extracts the time node corresponding to each sampling point and the voltage amplitude at that time node, and arranges these voltage amplitudes in chronological order into a two-dimensional matrix. The row index of the matrix corresponds to different time nodes, and the column index corresponds to the voltage amplitude at that time node, thereby constructing the initial discrete voltage matrix, which completely retains all the information in the original voltage sequence.

[0044] After obtaining the initial discrete voltage matrix, this matrix may contain abnormal voltage values ​​caused by occasional spikes from sensors or sudden electromagnetic pulses. These abnormal values ​​do not accurately reflect the chip's own voltage fluctuations, and if not removed, they will interfere with the accuracy of subsequent behavior judgments. The hardware sleep control unit compares each voltage element in the initial discrete voltage matrix with a preset abnormal threshold. The preset abnormal threshold is a physical limit set based on the maximum voltage amplitude range that may occur at each power supply node in the automotive-grade chip's power supply network under normal operating conditions. Its value comes from the upper and lower limits of the supply voltage specified in the chip's datasheet, and the unit is volts. When a voltage amplitude exceeds this threshold, it is determined to be a physically impossible abnormal value. The hardware sleep control unit compares each voltage amplitude in the initial discrete voltage matrix with the preset abnormal threshold. When a voltage amplitude exceeds the preset abnormal threshold, the element is marked as an abnormal point, and the time interval in which consecutive abnormal points occur is marked as an abnormal transient segment. The hardware sleep control unit records the start and end times of all abnormal transient segments, removes all voltage data within these intervals from the initial discrete voltage matrix, and fills the removed positions with the linear interpolation results of adjacent normal voltage values ​​to maintain the complete data structure of the matrix. The matrix after abnormal removal and filling is used as the final discrete voltage matrix.

[0045] After constructing the discrete voltage matrix and removing abnormal data, the hardware sleep control unit performs behavioral intent recognition based on this matrix, distinguishing whether the current voltage change is a normal sleep cycle initiated by the chip or a passive transient disturbance caused by external power fluctuations or load changes. The hardware sleep control unit first calculates the voltage changes between adjacent time points based on the discrete voltage matrix. The voltage slope is the ratio of the change in voltage amplitude between two adjacent time points to the time interval, reflecting the rate of voltage decrease or increase; the acceleration is the ratio of the change in voltage slope between two adjacent time points to the time interval, reflecting the acceleration or deceleration characteristics of the voltage change trend. Through these calculations, the hardware sleep control unit obtains a voltage slope sequence and an acceleration sequence, which describe the dynamic behavior characteristics of voltage changes over time. Based on this, the hardware sleep control unit performs component separation processing on the voltage signal, specifically using digital filtering to decompose the voltage sequence in the discrete voltage matrix into a fundamental decreasing component and a high-frequency oscillation component. The fundamental decreasing component reflects the slow-changing trend of voltage, manifested as a monotonically decreasing or increasing voltage over time; the high-frequency oscillation component reflects the rapid fluctuation of voltage over a short period, manifested as high-frequency jitter superimposed on the fundamental trend.

[0046] The hardware sleep control unit calculates the dynamic time warping distance between the separated fundamental falling frequency component and the pre-stored standard voltage drop waveform template within the hardware sleep control unit. The standard voltage drop waveform template is a set of reference voltage sequences pre-stored in the non-volatile memory of the hardware sleep control unit. This template records the typical voltage drop waveforms at each time point when the chip performs a normal active sleep cycle under standard environmental conditions. It is obtained by averaging multiple measurements under calibration conditions before the chip leaves the factory and then storing the averaged values. The sampling frequency of the standard voltage drop waveform template is consistent with the fixed sampling frequency of the analog-to-digital converter in step S2. Dynamic time warping is an algorithm used to measure the similarity between two time series. Its core idea is to find an optimal matching path by non-linearly aligning the time points in the two sequences, allowing for moderate compression or stretching on the time axis while still achieving the best match. The sum of the distances between corresponding points in the two sequences under the optimal matching path is the dynamic time warping distance.

[0047] The hardware sleep control unit sequentially compares each voltage value in the fundamental falling component with each voltage value in the standard waveform template. Under the constraint of allowing time axis scaling, it searches for the matching path that minimizes the cumulative distance. The cumulative distance along this path is the dynamic time warping distance; the smaller the distance, the more similar the fundamental falling component is to the standard waveform template. Simultaneously, the hardware sleep control unit calculates the energy density value of the high-frequency oscillation component. The energy density value is calculated by summing the squares of the voltage amplitudes at each time point in the high-frequency oscillation component and then dividing by the duration of the high-frequency oscillation component to obtain the oscillation energy metric per unit time.

[0048] After completing the above calculations, the hardware sleep control unit comprehensively judges the behavior category based on four criteria. Specifically, when the dynamic time-warped distance between the fundamental falling fundamental component and the standard electrical waveform template is less than the preset similarity threshold, it indicates that the waveforms of the two still have a high degree of matching after nonlinear alignment of the time axis. The basic trend of the current voltage change is highly consistent with the standard active sleep waveform, satisfying the waveform similarity condition for active sleep judgment. The preset similarity threshold is set based on multiple sets of measured active sleep waveform data collected under calibration conditions before the chip leaves the factory. Specifically, the dynamic time-warped distance between each set of measured active sleep waveforms and the standard electrical waveform template is calculated, resulting in multiple distance values. The maximum value among these values ​​is taken and multiplied by a leniency coefficient greater than one (usually between 1.2 and 1.5). The result is the preset similarity threshold. This threshold ensures that normal active sleep waveforms under no abnormal conditions are less than this threshold, while non-sleep waveforms cannot meet this condition.

[0049] The second criterion is a monotonically decreasing voltage slope. Its physical meaning is that during active sleep mode, each functional module is shut down step by step according to a preset timing sequence. The load current on the power supply network decreases in a stepwise manner, and the voltage gradually decreases, maintaining a downward trend throughout the entire process without any voltage rebound. A monotonically decreasing voltage slope requires that the voltage slope values ​​between all adjacent time points within the observation window are negative, indicating that the voltage continuously decreases over time, with no voltage rise interval.

[0050] The third criterion is that the variable acceleration is consistently negative and its absolute value is less than the preset acceleration threshold. Variable acceleration reflects the rate of voltage drop; a negative variable acceleration indicates that the voltage drop rate is gradually slowing down. In active sleep scenarios, as more and more functional modules are shut down, the remaining load gradually decreases, and the voltage drop rate also gradually slows down. Therefore, the variable acceleration exhibits a consistently negative value, and its absolute value remains within a small range. The preset acceleration threshold is an upper limit set based on statistically measured variable acceleration data of the chip during standard active sleep. When the absolute value of the variable acceleration is less than this threshold, it indicates that the voltage drop process exhibits controlled deceleration characteristics, conforming to the physical law of gradual shutdown in active sleep. Specifically, the value of the preset acceleration threshold is determined by taking the absolute value of the measured variable acceleration data of the chip during standard active sleep, and using the 95th percentile of this absolute value sequence as the upper limit. This ensures that the vast majority of variable acceleration values ​​in normal active sleep fall below this threshold, while acceleration jumps caused by non-active sleep will not meet this condition.

[0051] The fourth criterion is that the energy density value is lower than the noise baseline. The noise baseline is a reference value pre-stored in the hardware sleep control unit. It is set based on the statistical average value of the high-frequency oscillation components of the voltage under stable operating conditions, representing the normal noise level of the chip when there are no external disturbances. When the energy density value of the high-frequency oscillation components is lower than the noise baseline, it indicates that there are no severe high-frequency fluctuations outside the normal range in the current voltage signal.

[0052] The hardware sleep control unit determines that the current voltage change is an active sleep switch when all four indicators mentioned above are met; otherwise, it is determined to be a passive power supply transient disturbance. The reason for requiring all four indicators to be met simultaneously is that they comprehensively characterize voltage change behavior from four dimensions: waveform similarity, consistency of voltage change direction, degree of control over voltage drop, and high-frequency noise level. Meeting a single indicator is insufficient to eliminate interference from other types of voltage change behavior; only when all four indicators are met simultaneously can the reliability of the determination result be ensured. Through this multi-dimensional comprehensive determination, the system effectively avoids misjudging passive disturbances such as external power supply fluctuations or load changes as active sleep behavior, ensuring that subsequent voltage fluctuation prediction and timing adjustment decisions are executed only for actual active sleep scenarios.

[0053] Suppose that while the vehicle is in motion, a high-power load device suddenly starts up. This device shares the same onboard power network as an automotive-grade chip. The startup of this device generates a large inrush current, causing a rapid drop in the power supply network voltage within a very short time. The pattern of this voltage drop may be very similar in value to the voltage drop during active sleep mode, and the drop process also exhibits a certain degree of monotonicity. If judged solely by the monotonic decrease in voltage slope, this passive disturbance scenario perfectly meets the condition of a continuously negative voltage slope, and could easily be mistakenly identified as active sleep mode.

[0054] However, voltage drops caused by surge currents typically exhibit a certain degree of voltage rebound and strong high-frequency oscillations at the end of the drop, while active sleep mode shows a controlled, step-like drop without voltage rebound. Through comprehensive evaluation using four indicators, although passive disturbances may satisfy the condition of a monotonically decreasing voltage slope, their voltage change waveform deviates significantly from the dynamic time warping of the standard electrical waveform template, failing to meet the waveform similarity condition; their voltage drop rate is characterized by acceleration abruptly changing between positive and negative rather than being continuously negative, failing the condition of changing acceleration; and their high-frequency oscillation component has a large amplitude, with energy density values ​​often exceeding the noise baseline, failing the noise condition. It is through this multi-dimensional joint evaluation that the misclassification of such passive disturbances as active sleep mode is effectively avoided, ensuring that subsequent timing adjustment decisions are only executed for genuine sleep scenarios.

[0055] Step S4: If the transient disturbance is identified as a passive power supply disturbance and the disturbance triggering condition is met, then feature dimensionality reduction processing is performed on the discrete voltage matrix to generate the second transient voltage feature vector.

[0056] Step S4 includes: extracting voltage elements in the discrete voltage matrix whose absolute amplitude is greater than a preset threshold as disturbance extrema points to confirm that the disturbance triggering condition is met; constructing a local disturbance sub-matrix by extracting data centered on the disturbance extrema points and performing normalization processing; calculating the covariance matrix of the local disturbance sub-matrix and performing eigenvalue decomposition, and selecting the main eigenvectors to form a feature projection matrix; using the feature projection matrix to perform spatial mapping on the local disturbance sub-matrix to obtain a dimension-reduced disturbance sequence; and splicing the waveform envelope features and peak attenuation coefficient of the dimension-reduced disturbance sequence to generate a second transient voltage feature vector.

[0057] Specifically, after determining that the current voltage change is a transient disturbance of the passive power supply, the hardware sleep control unit further determines whether the disturbance meets the triggering conditions. The purpose of setting the triggering conditions is that only disturbances with sufficiently significant amplitude that may pose a threat to chip safety are worth starting the subsequent dimensionality reduction and prediction processing. For disturbances with small amplitude that are within the chip power supply tolerance range, there is no need to intervene, so as to save hardware computing resources.

[0058] Specifically, the hardware sleep control unit traverses all voltage elements in the discrete voltage matrix, extracting the absolute amplitude of each element. The absolute amplitude refers to the absolute value of the voltage element, reflecting the actual magnitude of the voltage deviation from zero at that point in time, regardless of positive or negative direction. When a voltage element has an absolute amplitude greater than a preset threshold, it is marked as a disturbance extreme point, confirming that the current disturbance meets the trigger condition and initiating the subsequent processing flow. Conversely, if the absolute amplitude of all voltage elements does not exceed the preset threshold, it indicates that the disturbance amplitude is within the chip's power supply tolerance range, requiring no further processing, and the current process terminates directly. The preset threshold is a voltage limit pre-stored in the hardware sleep control unit's register. Its value is set based on the maximum voltage fluctuation range allowed by the automotive-grade chip's power supply network under normal operating conditions. Voltage fluctuations exceeding this limit are considered potentially detrimental to the chip's internal circuitry.

[0059] After confirming that the disturbance triggering condition is met, the hardware sleep control unit extracts data from the discrete voltage matrix to construct a local disturbance sub-matrix, centered on the marked disturbance extreme point. Specifically, taking the time node where the disturbance extreme point is located as the center, a preset number of adjacent time nodes and their corresponding voltage amplitudes are taken to the left and right respectively. These data are arranged in chronological order to form a local data block. The value of this preset number is determined by simulation based on the parasitic parameters of the power supply network and the load characteristics during the chip design stage. In the simulation, the voltage response waveform of the chip under the transient disturbance of the passive power supply is simulated, and the time length required for the waveform to recover to 90% of the steady-state value from the start of the disturbance is measured. This time length is divided by the sampling period of the analog-to-digital converter in step S2 to obtain the preset number of values.

[0060] The constructed local perturbation submatrix contains all voltage change information in the core perturbation region, including the steep changes in the rising and falling edges of the perturbation, the magnitude of the perturbation peak, and the waveform shape during the decay phase. After constructing the local perturbation submatrix, the hardware sleep control unit performs normalization processing on the matrix. The purpose of normalization processing is to eliminate the bias caused by the different dimensions and numerical ranges of the data in each dimension of the local perturbation submatrix in subsequent feature extraction. Specifically, for each voltage amplitude in the local perturbation submatrix, the minimum value of all voltage amplitudes in the matrix is ​​subtracted, and then divided by the difference between the maximum and minimum values, so that all values ​​are mapped to the range between zero and one. This unifies the numerical scale of each element while preserving the relative changes in the original waveform shape.

[0061] After normalization, the hardware sleep control unit calculates the covariance matrix of the local perturbation submatrix. The covariance matrix is ​​a square matrix, and the element in the i-th row and j-th column reflects the degree of linear correlation between the i-th and j-th dimensions of the local perturbation submatrix. A larger absolute value of the covariance indicates a more consistent trend between the two dimensions, while a covariance close to zero indicates almost no linear correlation between the two dimensions. By performing eigenvalue decomposition on this covariance matrix, a set of eigenvalues ​​and their corresponding eigenvectors are obtained. The magnitude of the eigenvalue represents the variance of the data along that eigenvector direction; a larger eigenvalue indicates more information contained in that direction.

[0062] The hardware sleep control unit arranges all feature values ​​in descending order, calculates the contribution rate of each feature value (i.e., the feature value divided by the sum of all feature values), and accumulates them sequentially from high to low contribution rates. It selects the feature vectors corresponding to the top few feature values ​​whose cumulative contribution rates reach a preset percentage threshold. These selected feature vectors form a feature projection matrix, which projects the original high-dimensional data into a low-dimensional space while retaining most of the variance information in the original data. The principal component analysis in this step is a secondary dimensionality reduction operation performed on the local perturbation submatrix, which differs from the principal component analysis performed on the initial discrete voltage matrix in step S3. The dimensionality reduction in step S3 applies to the initial discrete voltage matrix containing full-time series voltage data, aiming to compress the overall data volume and filter out noise across the entire time range. The dimensionality reduction in this step applies to the truncated local perturbation submatrix, aiming to further reduce the data dimension while retaining the key local features of the perturbation, providing a more compact data representation for subsequent waveform envelope and attenuation coefficient extraction. The two dimensionality reduction processes are independent and serve different data processing stages. The local perturbation submatrix is ​​spatially mapped using the feature projection matrix. Specifically, the local perturbation submatrix is ​​multiplied by the feature projection matrix to obtain a new matrix with the same number of rows but a reduced number of columns. This matrix is ​​the dimensionality-reduced perturbation sequence. The dimensionality-reduced perturbation sequence effectively reduces the data dimensionality while retaining the core feature information of the perturbation, thus reducing the complexity of subsequent calculations.

[0063] After obtaining the dimension-reduced perturbation sequence, the hardware sleep control unit further extracts waveform envelope features and peak attenuation coefficients from the original time-domain data of the local perturbation submatrix. It should be noted that the waveform envelope features and peak attenuation coefficients in this step are extracted directly from the original time-domain signal with a clear voltage dimension in the local perturbation submatrix before PCA dimension reduction processing, to ensure that the extracted features have clear physical meaning.

[0064] The waveform envelope feature refers to the contour line formed by connecting the peak points of each oscillation period in the original time-domain signal of the local perturbation submatrix, reflecting the overall trend of the perturbation voltage amplitude over time. The specific extraction method is as follows: traverse the voltage amplitude sequence arranged in chronological order within the local perturbation submatrix, identify the local maxima of each oscillation period, which is the time point where the voltage amplitude reaches its maximum within that period and its corresponding voltage amplitude; use cubic spline interpolation to connect these local maxima points into a smooth curve, and the values ​​at each time point on this curve are the waveform envelope feature values, forming the waveform envelope feature sequence.

[0065] The peak attenuation coefficient reflects the rate of attenuation between peak values ​​of adjacent oscillation periods during the attenuation process of the disturbance voltage. The specific calculation method is as follows: For two adjacent oscillation periods in the original time-domain signal of the local disturbance submatrix, extract the peak voltage amplitude of the previous period and the peak voltage amplitude of the next period. Divide the peak amplitude of the next period by the peak amplitude of the previous period to obtain the ratio of adjacent peak amplitudes. Calculate the above ratio for each pair of adjacent oscillation periods within the local disturbance submatrix to obtain a set of peak attenuation coefficient sequences. The value of each coefficient in this sequence ranges from 0 to 1. The closer the coefficient is to 1, the slower the attenuation; the closer the coefficient is to 0, the faster the attenuation. Concatenate the waveform envelope feature sequence and the peak attenuation coefficient sequence end-to-end according to their corresponding time nodes to form a comprehensive feature vector.

[0066] Meanwhile, to ensure the fixedness of the input dimension of the multilayer perceptron model in subsequent step S5, the time window length truncated when constructing the local perturbation sub-matrix in this step is a fixed value. This fixed value is determined by simulation based on the parasitic parameters and load characteristics of the power supply network during the chip design phase. Specifically, the voltage response waveform of the chip under passive power supply transient perturbation is simulated in the simulation environment. The time length required for this waveform to recover to 90% of the steady-state value from the start of the perturbation is measured. 1.2 times this time length is used as the total window length, so that the local perturbation sub-matrices truncated from different perturbation events have the same number of rows, thereby keeping the dimension of the final generated second transient voltage feature vector fixed. The above-mentioned concatenated comprehensive feature vector is used as the second transient voltage feature vector. This feature vector comprehensively describes the original time-domain amplitude profile change and energy decay law of the passive perturbation with a compact and dimensionally fixed data structure, providing a physically meaningful and dimensionally matched feature input for subsequent voltage fluctuation prediction. The second transient voltage feature vector generated by the above processing comprehensively describes the amplitude profile changes and energy decay laws of passive disturbances with a compact data structure, providing accurate and low-redundancy feature inputs for subsequent voltage fluctuation prediction. By initiating dimensionality reduction processing only for significant disturbances that meet the triggering conditions, the ineffective consumption of hardware computing resources on minor disturbances is avoided.

[0067] Step S5: Input the second transient voltage feature vector and the obtained parasitic capacitance value into the preset voltage prediction model, output the voltage fluctuation prediction amplitude, and update the gating timing parameters when the voltage fluctuation prediction amplitude exceeds the preset safety window.

[0068] Step S5 includes: extracting the second transient voltage feature vector to construct a voltage feature sequence, mapping it through a multilayer perceptron algorithm and filtering it through an activation function, then weighting, summing, and smoothing it to obtain the predicted voltage fluctuation amplitude; if the predicted voltage fluctuation amplitude is greater than the upper limit of a preset safety window, calculating the deviation and inputting it into a random forest model to determine the corresponding timing compensation parameters; parsing the initial clock shutdown node in the gating timing parameters, calculating the phase offset of the initial clock shutdown node based on the timing compensation parameters to obtain the target clock shutdown node; replacing the corresponding initial node with the target clock shutdown node to complete the update of the gating timing parameters.

[0069] Specifically, the second transient voltage feature vector and the obtained parasitic capacitance value are first input into a preset voltage prediction model. This model is used to map the dimensionality-reduced transient voltage features to specific voltage fluctuation prediction amplitudes. After dimensionality reduction and feature concatenation processing in step S4, the data structure of the second transient voltage feature vector has been transformed from the original high-dimensional voltage matrix into a compact feature sequence containing waveform envelope features and peak attenuation coefficients. However, the relationship between this feature sequence and the final voltage fluctuation amplitude is not a simple linear proportional relationship. It needs to be processed by a model with nonlinear mapping capabilities to obtain accurate prediction results.

[0070] Because a fixed time window length was used when constructing the local perturbation submatrix in step S4, the dimension of the second transient voltage feature vector is a fixed value D. The hardware sleep control unit extracts each element from the second transient voltage feature vector and arranges them in chronological order to construct a voltage feature sequence, the length of which is fixed at D. This sequence is input into the voltage prediction model, which is implemented using a multilayer perceptron algorithm. A multilayer perceptron is a feedforward artificial neural network structure consisting of an input layer, one or more hidden layers, and an output layer. Each layer contains several neuron nodes, and neurons in adjacent layers are fully connected through weight values. Each neuron contains a bias term and an activation function. The number of neurons in the input layer is set to D, which matches the fixed dimension of the second transient voltage feature vector.

[0071] The multilayer perceptron model is trained offline during the chip design phase. The training process is as follows: Measured voltage fluctuation amplitudes and corresponding second transient voltage feature vectors are pre-collected under various sleep scenarios. During the acquisition process, the same fixed time window length as in step S4 is used to extract local perturbation data and generate second transient voltage feature vectors of the same dimension D. The feature vectors of fixed dimension D are used as model input, and the measured voltage fluctuation amplitudes are used as training labels. Mean squared error is used as the loss function, and the weights between layers and the bias terms of each neuron are iteratively updated using the backpropagation algorithm. Training is complete when the loss function converges to below a preset threshold. After training, the weights between layers and the bias terms of each neuron are permanently stored in the non-volatile memory of the hardware sleep control unit. During the inference phase, the hardware sleep control unit inputs the voltage feature sequence of fixed dimension D into the model to obtain the predicted voltage fluctuation amplitude.

[0072] During the actual inference phase, the hardware sleep control unit first extracts the elements from the second transient voltage feature vector, arranges them in chronological order to construct a voltage feature sequence, and simultaneously reads the parasitic capacitance values ​​of each power supply path stored in step S1. These parasitic capacitance values ​​are then appended as an independent dimension to the end of the voltage feature sequence to form a comprehensive feature vector. Normalization is then performed on the comprehensive feature vector, mapping each element to a value between zero and one according to its numerical range. This ensures that the data across all dimensions are uniform in scale, preventing some dimensions from dominating others during subsequent weighted summation due to excessively large differences in the numerical magnitudes of different dimensions.

[0073] The normalized comprehensive feature vector is input into the input layer of the multilayer perceptron model. The input layer passes the data to the first hidden layer. Each neuron in the hidden layer performs a weighted summation operation on the received data, that is, multiplies the input data by the weight value corresponding to the neuron, sums the results, adds the bias term of the neuron, and then inputs the weighted sum into the activation function for nonlinear transformation to obtain the output value of the neuron. The activation function uses a linear rectified unit, which is mathematically expressed as outputting the input value itself when the input value is greater than zero, and outputting zero when the input value is less than or equal to zero. The above process is passed layer by layer until the output layer generates a preliminary voltage fluctuation prediction value. The preliminary prediction value output by the output layer is smoothed by moving average to remove the small jitter caused by random initialization of neurons or numerical fluctuations, to obtain the final voltage fluctuation prediction amplitude.

[0074] After obtaining the predicted voltage fluctuation amplitude, the hardware sleep control unit compares it with the upper threshold of a preset safety window. The upper threshold corresponds to the maximum transient voltage fluctuation amplitude that sensitive nodes within the chip can tolerate. When the predicted voltage fluctuation amplitude is less than or equal to this threshold, it indicates that the voltage fluctuation generated by the sleep operation under the current timing arrangement is within the chip's safe tolerance range. Conversely, if the predicted voltage fluctuation amplitude is greater than the upper threshold of the preset safety window, it indicates that the current timing arrangement will generate voltage spikes exceeding the chip's tolerance capacity, potentially damaging the internal circuitry or causing functional abnormalities, requiring updates and optimizations to the gating timing parameters. At this point, the hardware sleep control unit calculates the difference between the predicted voltage fluctuation amplitude and the upper threshold of the safety window; this difference is the deviation, reflecting the specific degree of voltage overshoot under the current timing parameters.

[0075] The calculated bias is input into the random forest model, which maps the bias to specific time-series compensation parameters. Random forest is an ensemble learning algorithm consisting of multiple decision trees. Each decision tree independently learns and regresses on the input data during training, and the final output is the average of the outputs of all decision trees. This random forest model is trained offline during the chip design phase, and its training process is divided into a data generation phase and a model training phase.

[0076] During the data generation phase, the optimal timing compensation amount under various deviation conditions is simulated in advance in the simulation environment. Specifically, for each deviation condition, all possible time offset values ​​are traversed with a preset search step size. A complete sleep shutdown timing simulation is performed for each time offset value, and the corresponding voltage fluctuation amplitude is recorded. The time offset that makes the voltage fluctuation amplitude fall within a preset safety window and has the smallest absolute value is selected as the optimal timing compensation amount under that deviation condition. The above deviation amounts are paired with their corresponding optimal timing compensation amounts to form a training dataset, where the deviation amounts serve as model input features, and the optimal timing compensation amounts serve as training labels.

[0077] During the model training phase, the Bootstrap sampling method is used to extract multiple different training subsets with replacement from the training dataset. Each training subset is used to train a decision tree. When splitting a node in each decision tree, a feature subset is randomly selected from all features for optimal splitting. A regression decision tree is constructed through recursive binary splitting until a preset stopping condition is reached. This process constructs a random forest model containing multiple decision trees. After training, the random forest model is permanently stored in the hardware sleep control unit. This model learns the mapping relationship from the bias to the optimal time-series compensation, rather than performing a simulation search during the inference phase. Therefore, only one forward computation is needed to obtain the time-series compensation parameters during inference, eliminating the need for real-time simulation traversal.

[0078] During the actual inference phase, the hardware sleep control unit inputs the deviation into the random forest model. Each decision tree in the model performs independent regression prediction on the input and outputs a compensation prediction value. The output values ​​of all decision trees are averaged to obtain the final time-series compensation parameter. This time-series compensation parameter represents the adjustment direction and adjustment magnitude of the turn-off time in the gating time-series parameter in the form of a time offset. A positive value indicates that the turn-off time is delayed, and a negative value indicates that the turn-off time is advanced.

[0079] After obtaining the timing compensation parameters, the hardware sleep control unit parses the initial clock shutdown node in the current gating timing parameters. The clock shutdown node refers to the specific time point specified in the gating timing parameters when each clock domain performs a shutdown action; each shutdown node corresponds to a clock domain and its preset shutdown time. The hardware sleep control unit performs phase offset calculations on the initial clock shutdown nodes based on the timing compensation parameters. Phase offset refers to shifting the initial shutdown time forward or backward by a specified amount of time on the time axis. Specifically, it adds the value of the initial shutdown time to the time offset indicated by the timing compensation parameters to obtain the offset shutdown time, which is the target clock shutdown node. For all clock shutdown nodes in the gating timing parameters that require offset adjustment, the hardware sleep control unit performs the above phase offset calculation one by one, replacing the corresponding initial clock shutdown node with the calculated target clock shutdown node, thereby completing the update of the gating timing parameters.

[0080] By mapping the deviation input to the random forest model as timing compensation parameters and performing phase offset calculations on the initial clock shutdown node, the shutdown time of each clock domain is shifted forward or backward on the time axis, thereby staggering the original simultaneous shutdown times of multiple high-power nodes, avoiding the superposition of voltage spikes at the same time point, controlling the voltage fluctuation amplitude within a preset safety window, effectively eliminating the risk of voltage spikes during sleep process, and ensuring the electrical safety of the chip during low-power sleep process.

[0081] Step S6: Determine the final shutdown execution sequence based on the updated gating timing parameters and topology state table, and drive the corresponding functional modules to perform physical power-off hibernation operations step by step through the gating drive array according to the final shutdown execution sequence.

[0082] Step S6 includes: reading the power supply node information in the topology state table, allocating the shutdown time in the updated gating timing parameters to each power supply node, and generating an initial shutdown execution sequence; performing a safety condition check on the initial shutdown execution sequence; if the check passes, the initial shutdown execution sequence is determined as the final shutdown execution sequence; if the check fails, the shutdown time of nodes with timing conflicts is adjusted until the safety conditions are met, and the final shutdown execution sequence is generated; and the final shutdown execution sequence is sent to the gating drive array, which then drives the corresponding functional modules to perform physical power-off hibernation operations according to the sequence.

[0083] Specifically, after updating the gating timing parameters, the hardware sleep control unit first reads the topology status table established in step S1. This topology status table records the node identifiers of each power supply node in the chip's internal power supply network, the electrical hierarchy of each node, and the high-power cluster affiliation information of each node. Simultaneously, the hardware sleep control unit reads the gating timing parameters updated in step S5. These gating timing parameters include the target clock shutdown nodes corresponding to each clock domain, and each target clock shutdown node records the shutdown time value of the corresponding clock domain.

[0084] The hardware sleep control unit matches each power supply node in the topology state table with each clock domain in the gating timing parameters. Based on the node identifier of each power supply node, it finds the corresponding target clock shutdown node in the gating timing parameters and assigns the shutdown time value of that target clock shutdown node to the corresponding power supply node, ensuring that each power supply node carries a corresponding shutdown time value. After all power supply nodes have completed their shutdown time assignments, the hardware sleep control unit sorts all power supply nodes according to the order of their shutdown times, generating an initial shutdown execution sequence.

[0085] After generating the initial shutdown execution sequence, the hardware sleep control unit performs a safety condition check on the sequence. This check includes: traversing the shutdown times of any two adjacent power supply nodes in the initial shutdown execution sequence, calculating the time interval between them, and determining whether the time interval is greater than or equal to the preset minimum safety interval; at the same time, traversing all power supply nodes belonging to the same high-power cluster and determining whether their arrangement order in the sequence is consistent with the preset shutdown order in the topology state table.

[0086] If all the above safety condition checks pass, the hardware sleep control unit determines the current initial shutdown execution sequence as the final shutdown execution sequence. If any of the above safety condition checks are not met, the hardware sleep control unit identifies power supply nodes with timing conflicts, specifically power supply nodes that cause adjacent shutdown time intervals to be less than the preset minimum safety interval, and power supply nodes whose arrangement order is inconsistent with the preset order. The shutdown times of these nodes are adjusted according to a preset fine-tuning step size, so that the shutdown times of conflicting nodes are advanced or delayed by a predetermined amount of time. After adjustment, the safety condition checks are re-executed until all safety conditions are met, and then the final shutdown execution sequence is generated.

[0087] After determining the final shutdown execution sequence, the hardware sleep control unit sends the final shutdown execution sequence to the gating drive array. After receiving the sequence, the gating drive array outputs drive signals sequentially at the corresponding time points according to the shutdown time and shutdown order of each power supply node recorded in the sequence, driving the switching devices on the power supply path of each functional module to perform physical power-off sleep operations step by step, until all functional modules to be shut down inside the chip have completed power-off.

[0088] The above describes a low-power sleep method for automotive-grade chips in an embodiment of this application. The following describes a low-power sleep device for automotive-grade chips in an embodiment of this application. Please refer to [link to relevant documentation]. Figure 3 A low-power sleep device for automotive-grade chips, as described in this application embodiment, includes: Topology modeling unit 1 captures the sleep enable signal through the hardware sleep control unit, latches the gate timing parameters of the current physical clock tree, and establishes the topology state table of the chip's internal power supply network. Environmental analysis unit 2 integrates the collected multi-dimensional environmental simulation signals with the impedance monitoring values ​​in the topology state table to generate the first transient voltage feature vector; The intent recognition unit 3 constructs a discrete voltage matrix based on the first transient voltage feature vector, and performs behavioral intent recognition based on the discrete voltage matrix to distinguish between active sleep switching and passive power transient disturbances. If the disturbance processing unit 4 identifies a passive power supply transient disturbance and meets the disturbance triggering condition, it performs feature dimensionality reduction processing on the discrete voltage matrix to generate a second transient voltage feature vector. The compensation update unit 5 inputs the second transient voltage feature vector and the acquired parasitic capacitance value into the preset voltage prediction model, outputs the voltage fluctuation prediction amplitude, and updates the gating timing parameters when the voltage fluctuation prediction amplitude exceeds the preset safety window. The hibernation drive unit 6 determines the final shutdown execution sequence based on the updated gating timing parameters and topology state table, and drives the corresponding functional modules to perform physical power-off hibernation operations step by step through the gating drive array according to the final shutdown execution sequence.

[0089] This application also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when executed on a computer, cause the computer to perform the steps of the low-power sleep method for automotive-grade chips.

[0090] It should be noted that the preset thresholds, algorithm parameters, and specific values ​​of normalization processing involved in the embodiments of the present invention are merely illustrative examples and are not intended to limit the present invention. Those skilled in the art can determine appropriate parameter values ​​through limited experimental testing and statistical analysis based on the historical data distribution, equipment characteristics, and management needs of actual sites; this process requires no creative effort.

[0091] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0092] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0093] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A low-power sleep mode method for automotive-grade chips, applied to a hardware sleep control unit built into the automotive-grade chip, the method comprising: Step S1: Capture the sleep enable signal through the hardware sleep control unit, latch the gate timing parameters of the current physical clock tree, and establish the topology state table of the chip's internal power supply network; Step S2: Fuse the acquired multi-dimensional environmental simulation signal with the impedance monitoring value in the topology state table to generate the first transient voltage feature vector; Step S3: Construct a discrete voltage matrix based on the first transient voltage feature vector, and perform behavioral intent recognition based on the discrete voltage matrix to distinguish between active sleep switching and passive power transient disturbances; Step S4: If the transient disturbance is identified as a passive power supply disturbance and the disturbance triggering condition is met, then feature dimensionality reduction processing is performed on the discrete voltage matrix to generate a second transient voltage feature vector; Step S5: Input the second transient voltage feature vector and the obtained parasitic capacitance value into the preset voltage prediction model, output the voltage fluctuation prediction amplitude, and update the gating timing parameters when the voltage fluctuation prediction amplitude exceeds the preset safety window; Step S6: Determine the final shutdown execution sequence based on the updated gating timing parameters and the topology state table, and drive the corresponding functional modules step by step through the gating drive array to perform physical power-off hibernation operations according to the final shutdown execution sequence.

2. The low-power sleep method for automotive-grade chips according to claim 1, characterized in that, Step S1 involves establishing the topology state table of the chip's internal power supply network, including: The sleep enable signal is parsed to extract the clock shutdown sequence and latched as a gating timing parameter. Based on the gating timing parameter, the physical interconnection structure of the power supply network is traversed to extract power supply nodes and generate a node connectivity graph. Redundant power supply paths in the node connectivity graph are removed to obtain a simplified path set. The node voltage drop distribution is calculated based on the impedance parameters of the simplified path set, and high-power nodes with power consumption greater than a preset power consumption threshold are selected. The high-power nodes are divided into sleep state sets according to the hierarchical relationship and mapped to the node connectivity graph to establish the topology state table.

3. The low-power sleep method for automotive-grade chips according to claim 1, characterized in that, Step S2 includes: Discretized sampling is performed on the temperature simulation signal and the environmental electromagnetic interference simulation signal, and the time sequence is aligned with the impedance monitoring values ​​in the topology state table to construct and clean a standard environmental dataset. The impedance sequence and temperature sequence in the standard environmental dataset are extracted and differential operations are performed to generate an environmental change rate sequence. If the maximum value of the environmental change rate sequence exceeds a preset fluctuation threshold, the standard environmental dataset is coupled using a machine learning model to obtain a first coupling feature vector. The time sequence features of the first coupling feature vector are extracted to generate a second coupling feature vector, and transient value mapping processing is performed to generate a first transient voltage feature vector.

4. The low-power sleep method for automotive-grade chips according to claim 1, characterized in that, Step S3, which involves constructing a discrete voltage matrix based on the first transient voltage eigenvector, includes: The first transient voltage feature vector is sliced ​​in the time dimension to extract time nodes and corresponding voltage amplitudes, and an initial discrete voltage matrix is ​​constructed. The voltage elements of the initial discrete voltage matrix are compared with the preset abnormal threshold to identify abnormal transient segments. Abnormal data are removed based on the abnormal transient segments to obtain the final discrete voltage matrix.

5. The low-power sleep method for automotive-grade chips according to claim 1, characterized in that, Step S3 distinguishes between active sleep switching and passive power transient disturbances, including: Based on the discrete voltage matrix, the voltage slope and acceleration at adjacent time nodes are calculated, and the fundamental falling fundamental component and the high-frequency oscillation component are separated. The dynamic time warping distance between the fundamental falling fundamental component and the pre-stored standard lower voltage waveform template is calculated, and the energy density value of the high-frequency oscillation component is calculated. If the dynamic time warping distance is less than a preset threshold, the voltage slope is monotonically decreasing, the acceleration is continuously negative and the absolute value is less than a preset acceleration threshold, and the energy density value is lower than the noise baseline, then it is determined to be an active sleep switch. If the dynamic time warping distance is not less than the preset threshold, the voltage slope polarity is reversed, or the energy density value is not lower than the noise baseline, then it is determined to be a passive power supply transient disturbance.

6. The low-power sleep method for automotive-grade chips according to claim 1, characterized in that, Step S4 includes: Voltage elements with absolute amplitudes greater than a preset threshold in the discrete voltage matrix are extracted as perturbation extrema to confirm that the perturbation triggering condition is met. A local perturbation sub-matrix is ​​constructed by extracting data centered on the perturbation extrema and normalizing it. The covariance matrix of the local perturbation sub-matrix is ​​calculated and eigenvalue decomposition is performed. The principal eigenvectors are selected to form a feature projection matrix. The local perturbation sub-matrix is ​​spatially mapped using the feature projection matrix to obtain a dimension-reduced perturbation sequence. The waveform envelope features and peak attenuation coefficient of the dimension-reduced perturbation sequence are concatenated to generate a second transient voltage feature vector.

7. The low-power sleep method for automotive-grade chips according to claim 1, characterized in that, Step S5 includes: The second transient voltage feature vector is extracted to construct a voltage feature sequence. The parasitic capacitance value is read and concatenated with the voltage feature sequence to form a comprehensive feature vector. The comprehensive feature vector is input into a preset voltage prediction model, mapped by a multilayer perceptron algorithm, filtered by an activation function, weighted summed, and smoothed to obtain the voltage fluctuation prediction amplitude. If the voltage fluctuation prediction amplitude is greater than the upper limit of a preset safety window, the deviation is calculated and input into a random forest model to determine the corresponding timing compensation parameters. The initial clock shutdown node in the gating timing parameters is parsed, and the phase offset of the initial clock shutdown node is calculated according to the timing compensation parameters to obtain the target clock shutdown node. The target clock shutdown node is used to replace the corresponding initial node to complete the update of the gating timing parameters.

8. The low-power sleep method for automotive-grade chips according to claim 1, characterized in that, Step S6 includes: The power supply node information in the topology state table is read, and the shutdown time in the updated gating timing parameters is allocated to each power supply node to generate an initial shutdown execution sequence. The initial shutdown execution sequence is checked for safety conditions. If the check passes, the initial shutdown execution sequence is determined as the final shutdown execution sequence. If the check fails, the shutdown time of nodes with timing conflicts is adjusted until the safety conditions are met, and the final shutdown execution sequence is generated. The final shutdown execution sequence is sent to the gating drive array, which drives the corresponding functional modules to perform physical power-off and sleep operations step by step according to the sequence.

9. A low-power sleep device for automotive-grade chips, used to implement the low-power sleep method for automotive-grade chips as described in any one of claims 1-8, characterized in that, The device includes: The topology modeling unit captures the sleep enable signal through the hardware sleep control unit, latches the gated timing parameters of the current physical clock tree, and establishes the topology state table of the chip's internal power supply network. The environmental analysis unit integrates the collected multi-dimensional environmental simulation signals with the impedance monitoring values ​​in the topology state table to generate a first transient voltage feature vector; The intent recognition unit constructs a discrete voltage matrix based on the first transient voltage feature vector, and performs behavioral intent recognition based on the discrete voltage matrix to distinguish between active sleep switching and passive power transient disturbances. If the disturbance processing unit identifies a passive power supply transient disturbance and meets the disturbance triggering condition, it performs feature dimensionality reduction processing on the discrete voltage matrix to generate a second transient voltage feature vector. The compensation update unit inputs the second transient voltage feature vector and the acquired parasitic capacitance value into a preset voltage prediction model, outputs the voltage fluctuation prediction amplitude, and updates the gating timing parameters when the voltage fluctuation prediction amplitude exceeds a preset safety window. The hibernation drive unit determines the final shutdown execution sequence based on the updated gating timing parameters and the topology state table, and drives the corresponding functional modules to perform physical power-off hibernation operations step by step through the gating drive array according to the final shutdown execution sequence.

10. A computer-readable storage medium storing instructions thereon, characterized in that, When the instruction is executed by the processor, it implements the low-power sleep method for automotive-grade chips as described in any one of claims 1-8.

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