Server and method for associating server and device information

Abstract

The application discloses a server and a device information association method thereof, and relates to the technical field of servers. A first processing module is used to obtain a first correspondence relationship for representing the correspondence relationship between a first connector and an extension port of a second processing module. The identification information of the second processing module and the identification information of the extension port are encoded based on the correspondence relationship to generate device information. The encoded device information is transmitted to a first storage module of a device expansion card through the first connector. Thus, the technical problems of the related art, such as the increase of the cost of the connector, the deterioration of the high-speed signal integrity and the insufficient system scalability caused by the physical pin coding transmission of the device information, are solved. The hardware complexity and the material cost are reduced, and the out-of-band management reliability and flexibility are improved.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a method for associating server and device information. Background Technology

[0002] In server systems, device expansion cards (such as riser cards and hard drive backplanes) are used to connect multiple external devices. The BIOS (Basic Input Output System) or BMC (Baseboard Management Controller) on the motherboard can obtain device information corresponding to the physical slots on each expansion card through PCIe (Peripheral Component Interconnect express) bus enumeration. This determines which PCIe or CXL (Compute Express Link) port of which CPU (Central Processing Unit) each physical slot is connected to, enabling device initialization, resource allocation, and out-of-band management. However, obtaining device information through PCIe bus enumeration cannot be effectively transmitted to and stored on the expansion card. The BMC struggles to independently obtain this information during system operation, limiting out-of-band management capabilities and making it impossible to accurately determine device ownership when the operating system is not running or malfunctioning.

[0003] Related technologies typically transmit and store the mapping between the physical slots on the expansion card and the CPU and its PCIe / CXL ports on the motherboard to the expansion card. Multiple dedicated pins representing CPU and port addresses are added to the high-speed connector on the motherboard. This pin information is then transmitted via cables to the GPIO (General-Purpose Input / Output) expansion chip on the expansion card and latched into each slot according to a preset mapping. However, this method requires a large number of additional pins, forcing the motherboard and expansion card to use connectors with more pins and larger packages. The cables also require additional wires, significantly increasing material costs. Furthermore, the fixed pin count encoding method is difficult to adapt to changes in the number of CPUs and ports. When the encoding range needs to be expanded, the pin functions must be redefined, lacking scalability. The limited pin resources also prevent the system from flexibly expanding to meet more management information transmission needs, hindering platform design and unified planning across multiple models. Summary of the Invention

[0004] This application provides a method for associating server and its device information, which at least solves the problems of increased connector cost and poor scalability caused by the need to add additional dedicated pins in related technologies.

[0005] This application provides a method for associating device information in a server. The server includes a motherboard, which includes a first processing module, a second processing module, and a first connector. The first and second processing modules are respectively connected to a device expansion card via the first connector. The method includes: in response to an initialization command from the motherboard, obtaining a first correspondence through the first processing module, wherein the first correspondence is used to characterize the correspondence between the first connector and the expansion ports of the second processing module; based on the first correspondence, determining the identification information of the second processing module corresponding to the device expansion card and the identification information of the expansion port of the second processing module; encoding the identification information and the expansion port identification information respectively to obtain device information of the second processing module; and sending the device information to the first storage module of the corresponding device expansion card through the first processing module.

[0006] This application also provides a server, including a memory, a processor, and a server device information association program stored in the memory and capable of running on the processor. When the processor executes the server device information association program, it implements the aforementioned server device information association method.

[0007] This application obtains a first correspondence relationship, characterized by the correspondence between the first connector and the expansion port of the second processing module, through a first processing module. Based on this correspondence, it encodes the identification information of the second processing module and the identification information of its expansion port to generate device information. The encoded device information is then sent to the first storage module of the device expansion card via the first connector. This solves the technical problems of increased connector costs, deterioration of high-speed signal integrity, and insufficient system scalability caused by transmitting device information through physical pin encoding in related technologies. It also reduces hardware complexity and material costs, and improves out-of-band management reliability and flexibility. Attached Figure Description

[0008] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of the structure of a server according to some embodiments of this application; Figure 2 This is a flowchart of a method for associating server device information according to some embodiments of this application; Figure 3 This is a schematic diagram of the structure of a server according to other embodiments of this application; Figure 4This is a schematic diagram of the structure of a server according to some embodiments of this application; Figure 5 This is a schematic diagram of the structure of a server according to some embodiments of the present application; Figure 6 This is a schematic diagram of the structure of a server according to some embodiments of this application; Figure 7 This is a schematic diagram of the structure of a server according to some embodiments of this application; Figure 8 This is a flowchart of a method for associating device information of a server according to other embodiments of this application; Figure 9 This is a flowchart of a method for associating server device information according to some embodiments of this application; Figure 10 This is a block diagram of a server according to some embodiments of this application. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0011] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0012] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0013] The specific application environment architecture or specific hardware architecture on which the method of associating server device information depends is described here.

[0014] The embodiments of this application provide a method for associating server and its device information. The method is described in detail below in conjunction with the execution flow of the server device information association method.

[0015] In some embodiments, refer to Figure 1The server includes a motherboard 1, which includes a first processing module 11, a second processing module 12, and a first connector 13. The first processing module 11 and the second processing module 12 are respectively connected to the device expansion card 2 through the first connector 13.

[0016] Specifically, the server includes a motherboard 1 and a device expansion card 2. The device expansion card 2 is plugged into the first connector 13 on the motherboard 1, thereby achieving physical connection and signal communication with the motherboard 1. The motherboard 1 integrates a first processing module 11 and a second processing module 12, both of which are connected to the device expansion card 2 through the first connector 13.

[0017] The first processing module 11 establishes a management connection with the device expansion card 2 through the first connector 13. This connection is used to manage the external devices on the device expansion card 2 and its various physical slots, including obtaining the programming information of the device expansion card 2, the presence status of the physical slots, and device address information. This management connection is typically implemented based on the I2C bus. The first processing module 11 uses this connection to read information stored in the storage module on the device expansion card 2 to identify device ownership. The first processing module 11 can be a BIOS or a BMC.

[0018] The second processing module 12 establishes a data connection with the device expansion card 2 through the first connector 13, for high-speed data interaction with external devices (such as GPUs, NVMe SSDs, network cards, etc.) connected to the physical slots on the device expansion card 2. For example, when the CPU needs to read data from the NVMe SSD, the data is transmitted between the second processing module 12 and the device expansion card 2 through the first connector 13. The second processing module 12 can be an MCU.

[0019] The first connector 13 is used to realize the signal connection between the motherboard 1 and the device expansion card 2. It carries both high-speed data signals (PCIe / CXL) between the second processing module 12 and external devices, and low-speed management signals (I2C) between the first processing module 11 and the storage module on the device expansion card 2. The first connector 13 can be an MCIO (Mini Cool EdgeIO) connector.

[0020] Based on the background technology, the first connector 13 includes a first pin group, the level state of the first pin group is used to generate the device information of the corresponding second processing module 12; the second connector 22 (the connector of the device expansion card) includes a second pin group, wherein the second pin group corresponds one-to-one with the first pin group, and the second pin group is connected to the first storage module 21; the first pin group includes N address pins of the second processing module 12 and M address pins of the expansion ports, wherein N and M are positive integers; the level states corresponding to the N address pins of the second processing module 12 are used to generate the identification information of the second processing module 12; the level states corresponding to the M address pins of the expansion ports are used to generate the expansion port identification information of the second processing module 12. In response to the initialization command of the motherboard 1, the level states of the second pin group are latched by the first storage module 21 to store the device information of the corresponding second processing module 12.

[0021] Specifically, the first connector 13 on the motherboard 1 is provided with a first pin group, which includes multiple signal lines. Each signal line is set to a high level or a low level, and these combinations of high and low levels are used to represent device information of the second processing module 12. The second connector 22 on the device expansion card 2 is provided with a second set of pins, which are connected one-to-one with the first pin group of the first connector 13 via cables, and the second set of pins is further connected to the first storage module 21 on the device expansion card 2.

[0022] The address pins of the N second processing modules 12 are used to carry the identification information of the second processing modules 12. Specifically, each address pin is set to a high level or a low level, and the level states of the N pins are combined to form an N-bit binary code. This code is used to uniquely identify a second processing module 12, and can represent 2^N different second processing modules 12.

[0023] The address pins of the M expansion ports are used to carry the expansion port identification information of the second processing module 12. Specifically, each address pin is set to a high level or a low level. The level states of the M pins are combined to form an M-bit binary code. This code is used to uniquely identify one expansion port of the second processing module 12 and can represent 2 to the power of M different expansion ports.

[0024] For example, assuming N=3 and M=4, the first pin group includes three address pins of the second processing module 12 (CPU_ADDR0, CPU_ADDR1, CPU_ADDR2) and four address pins of the expansion port (PE0, PE1, PE2, PE3). Each pin is set to a fixed level state through pull-up or pull-down resistors on the motherboard 1. If the level states of CPU_ADDR0, CPU_ADDR1, and CPU_ADDR2 are 0, 0, and 1 respectively, the 3-bit binary code is "001", corresponding to the second processing module 12 CPU1; if the level states of PE0, PE1, PE2, and PE3 are 0, 0, 0, and 1 respectively, the 4-bit binary code is "0001", corresponding to the expansion port Port1. Combined, they form a 7-bit binary code "0010001", indicating that the current device expansion card 2 belongs to Port1 of CPU1. This level state is transmitted to the first storage module 21 at the device expansion card 2 via a cable, where it is latched and stored, realizing the hardware encoding and transmission of device ownership information.

[0025] Based on the above hardware connection, when the motherboard 1 is powered on and initialized, the level state of the first pin group is transmitted to the second pin group via the cable. The first storage module 21 directly latches the level state on the second pin group, thereby obtaining and storing the device information of the second processing module 12. However, the additional (N+M) dedicated pins on the high-speed connector (e.g., N=3, M=4 in the previous example, i.e., 7 pins are required) increase the number of pins on the motherboard and expansion card connectors, as well as the number of cable cores, directly raising material costs. On the other hand, since the number of pins is fixed, the maximum number of second processing modules that this encoding scheme can represent is 2 to the power of N, and the maximum number of expansion ports is 2 to the power of M. When the system configuration exceeds this encoding range (e.g., the number of CPUs in a server exceeds 2 to the power of N, or the number of PCIe / CXL ports supported by a single CPU exceeds 2 to the power of M), the pin definitions and hardware circuits need to be redesigned, lacking flexible scalability and making it difficult to adapt to the diverse configuration requirements of different server models. In addition, the voltage level of each pin is fixedly set by pull-up or pull-down resistors, and cannot be changed once the hardware design is completed. When the device expansion card needs to be migrated to a server with a different configuration, its stored device information cannot be updated adaptively, resulting in poor versatility.

[0026] This application obtains a first correspondence relationship, characterized by the correspondence between the first connector and the expansion port of the second processing module, through a first processing module. Based on this correspondence, it encodes the identification information of the second processing module and the identification information of its expansion port to generate device information. The encoded device information is then sent to the first storage module of the device expansion card via the first connector. This solves the technical problems of increased connector costs, degraded high-speed signal integrity, and insufficient system scalability caused by transmitting device information through physical GPIO pin encoding in related technologies. It reduces hardware complexity and material costs, and improves out-of-band management reliability and flexibility.

[0027] Figure 2 This is a flowchart illustrating a method for associating server device information according to some embodiments of this application. (Refer to...) Figure 2 The server device information association method in this application embodiment may include the following steps: S110, in response to the initialization command of the motherboard 1, the first correspondence is obtained through the first processing module 11, wherein the first correspondence is used to characterize the correspondence between the first connector 13 and the expansion port of the second processing module 12.

[0028] Specifically, the first correspondence is pre-fixed by the hardware design. Each first connector 13 is connected to the corresponding expansion port of the second processing module 12 via PCB traces on the motherboard 1. The first processing module 11 obtains the mapping relationship between the second processing module 12 and its expansion port corresponding to the current first connector 13 by reading hardware configuration information or preset system topology information. For example, the first connector 13 is connected to the expansion port Port0 of the second processing module 12 (e.g., CPU0) via PCB traces on the motherboard 1. The first processing module 11 (e.g., BIOS) reads this mapping relationship during the power-on initialization phase and learns that the first connector 130 corresponds to Port0 of CPU0.

[0029] S120, based on the first correspondence, determine the identification information of the second processing module 12 corresponding to the device expansion card 2 and the identification information of the expansion port of the second processing module 12.

[0030] Specifically, the first processing module 11 identifies the second processing module 12 and its expansion port connected to the current device expansion card 2 based on the obtained first correspondence, and extracts the identification information of the second processing module 12 and the identification information of the expansion port as the basic data for subsequent encoding.

[0031] For example, suppose motherboard 1 is configured with two second processing modules 12 (CPU0 and CPU1), each CPU having four PCIe / CXL expansion ports (Port0 to Port3), and the first connector 13 is fixedly associated with Port2 of CPU0. When motherboard 1 is initialized, the first processing module 11 obtains the first correspondence, which records the mapping information of "first connector 13 → Port2 of CPU0". Based on the first connector 13 to which the current device expansion card 2 is connected, the first processing module 11 can determine that its corresponding second processing module 12 is CPU0 and its expansion port is Port2, thereby extracting the identification information of CPU0 (such as ID code "0") and the identification information of the expansion port (such as port number "2") as the raw data for subsequent encoding to generate device information.

[0032] S130, the identification information and the extended port identification information are encoded respectively to obtain the device information of the second processing module 12.

[0033] Specifically, the first processing module 11 encodes the identification information and the expansion port identification information according to a preset encoding rule to obtain the device information of the second processing module 12. This device information of the second processing module 12 uniquely identifies the second processing module 12 to which the current device expansion card 2 belongs, as well as its expansion port. For example, the first processing module 11 encodes the second processing module 12 identifier "0" as a 3-bit binary address code "000", and encodes the expansion port identifier "2" as a 4-bit binary address code "0010", combining them to obtain the 7-bit device information "0000010".

[0034] S140, the device information is sent to the first storage module 21 of the corresponding device expansion card 2 through the first processing module 11.

[0035] Specifically, the first processing module 11 transmits the encoded device information to the first storage module 21 on the device expansion card 2 via the corresponding first connector 13 and connecting cable through a low-speed communication protocol (such as the I2C protocol). This first storage module 21 stores the device information for independent reading by subsequent management modules (such as the BMC) during system operation. For example, the first processing module 11 sends the device information "0000010" to the first storage module 21 on the device expansion card 2 via the I2C bus. The BMC can then read this storage module via the I2C bus to determine that the current device expansion card 2 belongs to Port 2 of CPU0.

[0036] In some embodiments, refer to Figure 3The motherboard 1 also includes a hub 14, the channels of the hub 14 (not shown) correspond one-to-one with the first connector 13, the first connector 13 corresponds one-to-one with the expansion port of the second processing module 12, and the first processing module 11 is connected to the device expansion card 2 through the channels and the corresponding first connectors 13; wherein, obtaining the first correspondence through the first processing module includes: the first processing module 11 determines the first correspondence based on the first connector 13 corresponding to the channel of the hub 14 and the expansion port of the second processing module 12 connected to the first connector 13.

[0037] Specifically, the server motherboard 1 also includes a hub 14, such as an I2C hub, which has multiple channels. Each channel corresponds one-to-one with a first connector 13 on the motherboard 1, and each first connector 13 corresponds one-to-one with an expansion port of the second processing module 12. The first processing module 11 establishes a connection with the device expansion card 2 through a certain channel of the hub 14 and its corresponding first connector 13.

[0038] Therefore, in the hardware design of motherboard 1, each channel of hub 14 is fixedly connected to a first connector 13 via PCB traces. Simultaneously, each first connector 13 is also fixedly connected to an expansion port (such as a PCIe / CXL Root Port) of the second processing module 12 (such as a CPU). This channel-first connector-expansion port correspondence is determined during the hardware design phase and is embedded in the motherboard's circuit connections, requiring no software configuration or dynamic negotiation.

[0039] Based on this fixed hardware topology, when executing the initialization process, the first processing module 11 first identifies the current channel number (e.g., channel 0, channel 1, etc.) used for communication between itself and the hub 14. Since there is a unique and fixed correspondence between the channels of the hub 14 and the first connector 13, the first processing module 11 can uniquely determine the first connector 13 connected to the channel based on the currently used channel number (e.g., channel 0 corresponds to first connector A). Furthermore, since there is also a unique and fixed correspondence between the first connector 13 and the expansion port of the second processing module 12, the first processing module 11 can uniquely determine the second processing module 12 connected to the first connector 13 and its specific expansion port (e.g., first connector A is connected to Port 2 of CPU0) based on the identifier of the first connector 13 (e.g., connector number).

[0040] Through the step-by-step derivation of the above mapping relationship, the first processing module 11 does not need to use additional hardware pins to transmit encoded information, nor does it need to enumerate through the PCIe bus or query through software. It can indirectly obtain the identification information (such as CPU number) of the second processing module 12 corresponding to the device expansion card 2 and its expansion port identification information (such as port number) based solely on the hub channel information currently in use, thereby obtaining the first correspondence.

[0041] In some embodiments, refer to Figure 4 The device expansion card 2 includes a second connector 22, which is connected to the first connector 13 and the first storage module 21. The device information is sent to the first storage module 21 of the corresponding device expansion card 2 through the channel of the hub 14, the first connector 13 and the second connector 22 via the first processing module 11.

[0042] Specifically, the device expansion card 2 includes a second connector 22 and a first storage module 21. The second connector 22 is connected to the first connector 13 on the motherboard 1 via a cable, and the second connector 22 is also connected to the first storage module 21 on the device expansion card 2. Thus, the first processing module 11 communicates with the first storage module 21 of the device expansion card 2 through the transmission path formed by the hub 14 channel, the first connector 13, the cable, and the second connector 22.

[0043] Based on the aforementioned transmission path, after generating device information, the first processing module 11 sends out a data packet carrying the device information through the current channel of the hub 14. This data packet sequentially passes through the first connector 13 corresponding to the current channel, the cable connecting the motherboard 1 and the device expansion card 2, and the second connector 22 on the device expansion card 2, finally reaching the first storage module 21. The first storage module 21 receives the data packet and latches the device information within it, thereby permanently storing the association between the second processing module 12 to which the device expansion card 2 belongs and its expansion ports locally on the device expansion card 2.

[0044] Thus, this application relies solely on the fixed connection of the hardware design, and the device ownership relationship can be directly determined during motherboard initialization. It has the advantages of strong determinism, no need for additional configuration, and no occupation of additional pin resources of high-speed connectors.

[0045] In some embodiments, the first storage module 21 is a programmable logic chip or a storage chip.

[0046] In some embodiments, the programmable logic chip is a complex programmable logic device or a microcontroller unit.

[0047] In some embodiments, the memory chip is a non-volatile memory chip.

[0048] In some embodiments, the programmable logic chip includes registers, wherein each register corresponds to a physical slot of the device expansion card 2 and is used to store device information of the second processing module 12 corresponding to the device expansion card 2.

[0049] In some embodiments, the storage chip corresponds to the device expansion card, or corresponds one-to-one with the physical slots on the device expansion card 2, and is used to store device information of the second processing module 12 corresponding to the device expansion card 2.

[0050] Specifically, the first storage module 21 on the device expansion card 2 is used to receive and store device information sent by the first processing module 11. Its specific implementation can be flexibly adapted to different types of chips, including programmable logic chips or memory chips, depending on the actual application scenario. In the following description, the motherboard 1 including two first connectors 13 is used as an example, but this is not intended to limit the scope of this application.

[0051] When the first storage module 21 is a programmable logic chip, the programmable logic chip has multiple registers internally. Each register corresponds one-to-one with a physical slot on the device expansion card 2. Each physical slot corresponds to an independent register storage area, and each register is used to store the device information of the corresponding physical slot. The programmable logic chip can be a complex programmable logic device or a microcontroller unit. The chip itself has a moderate cost and requires corresponding firmware or logic development, resulting in a certain development cost. However, its programmable nature allows it to flexibly adapt to different functional requirements, reducing the hardware modification costs caused by changes in requirements.

[0052] When the first storage module 21 is a storage chip, the storage chip can be configured correspondingly to the device expansion card 2, that is, one storage chip is configured for each device expansion card 2. The storage chip is internally divided into multiple storage areas, each corresponding to a physical slot, and is used to store the device information of the corresponding physical slot. Alternatively, the storage chip can be configured correspondingly to each physical slot on the device expansion card 2, that is, each physical slot is configured with an independent storage chip, and each storage chip is used to store the device information of the corresponding physical slot. The storage chip can be a non-volatile storage chip, specifically an electrically erasable programmable read-only memory or flash memory. The chip itself has the lowest cost and does not require program development, but it needs to cooperate with other logic circuits (such as the I2C switching chip 23 or the first processing module 11) to complete the writing and management of address information. Therefore, it may incur additional costs in terms of system integration and external circuit support. It is suitable for scenarios that require long-term storage of configuration information and have a low change frequency.

[0053] In some embodiments, the first storage module can also be a non-programmable logic chip. When the first storage module 21 is a non-programmable logic chip, the non-programmable logic chip is configured one-to-one with each physical slot on the device expansion card 2, with each physical slot configured with an independent non-programmable logic chip, and each non-programmable logic chip is used to store the device information of the corresponding physical slot. The non-programmable logic chip can be a general-purpose input / output expansion chip, which has a simple structure, does not require a built-in processor core and program storage unit, has the lowest chip cost, and does not require firmware development, thus reducing development and testing costs. It is suitable for large-scale deployments and cost-sensitive scenarios.

[0054] Thus, the three chip implementation methods described above are suitable for different application scenarios, allowing this application to flexibly select the chip type based on requirements such as cost, functionality, and reliability. Regardless of the chip implementation method used, the first storage module is used to store the device information of the second processing module corresponding to the device expansion card, enabling the management module to independently read this information from the device expansion card via a low-speed communication protocol, thereby establishing the association between the device ownership information on the motherboard and the physical location of the device expansion card.

[0055] In some embodiments, the server device information association method further includes: in response to the power-on command of the motherboard 1, reading the device information stored in the first storage module 21 through the first processing module 11; and managing the external devices connected to the device expansion card 2 based on the device information through the first processing module 11.

[0056] Specifically, after the motherboard 1 is powered on, the first processing module 11 (such as the BIOS) actively reads the device information stored in the first storage module 21 of the device expansion card 2. This device information was encoded by the first processing module 11 and written into the first storage module 21 during the previous motherboard 1 initialization phase, and includes the identification information of the second processing module 12 (such as the CPU number) and its expansion port identification information (such as the port number). The first processing module 11 accesses the first storage module 21 through a low-speed communication protocol (such as the I2C protocol), via the corresponding channel of the hub 14, the first connector 13, the cable, and the second connector 22, to obtain the device information stored therein.

[0057] Based on the read device information, the first processing module 11 determines the second processing module 12 to which the current device expansion card 2 belongs and its specific expansion port. During the motherboard startup process, it allocates appropriate PCIe / CXL bus resources to the external devices (such as GPUs, NVMe SSDs, network cards, etc.) connected to the device expansion card 2, including bus number, device number, function number, and memory and I / O address space. This ensures that the external device is accurately mounted to the corresponding PCIe / CXL root port, avoiding resource allocation conflicts to a certain extent and ensuring that the device is correctly enumerated and identified. At the same time, when the operating system is not started or the system fails, the baseboard management controller, as the first processing module 11, can directly access the first storage module 21 through the out-of-band management channel to read the device information stored therein and obtain the device ownership relationship. This enables remote fault location, device status monitoring, and hot-swap management without the involvement of the operating system, improving the maintainability and out-of-band management capabilities of the server system.

[0058] As described in the background, devices conforming to PCIe, CXL, and UCIe (Universal Chiplet Interconnect Express) protocols typically have multiple access paths in their hardware design, including PCIe / UCIe / CXL bus paths and lower-speed management paths such as I2C (Inter-Integrated Circuit) / I3C (Improved Inter-Integrated Circuit) / USB (Universal Serial Bus). Therefore, the server's BMC and BIOS must be able to bind the PCIe / UCIe / CXL addresses, I2C / I3C / USB addresses of PCIe / UCIe / CXL devices, as well as the physical silkscreen address of the server where the device resides, to meet functional requirements such as asset management, fault diagnosis and location, heat dissipation strategies, and temperature information collection. Failure to accurately obtain the address mapping relationship of PCIe / UCIe / CXL devices will directly affect the operational efficiency of data center servers, and in severe cases, may even lead to server downtime due to improper management of PCIe / UCIe / CXL devices.

[0059] Reference Figure 5To achieve the binding of PCIe / UCIe / CXL addresses, I2C / I3C / USB addresses, and physical silkscreens for PCIe / UCIe / CXL devices, related technologies encode the CPU address and the CPU's PCIe port address, and store the encoded content through a GPIO Expander (General Purpose Input / Output Expansion Chip). The BIOS / BMC then reads and parses the PCIe device address to achieve PCIe address allocation. Simultaneously, the BIOS / BMC pre-writes the mapping relationship between the silkscreen address and the PCIe address in the server system configuration into the BIOS / BMC code through hard encoding, thereby binding the PCIe address allocation of PCIe devices to the server's silkscreen address.

[0060] However, the relevant technologies can only bind PCIe addresses to silkscreen addresses, not I2C addresses. This prevents the BIOS / BMC from simultaneously managing the same PCIe device via both PCIe and I2C paths, resulting in a single device management path and reducing the flexibility and reliability of server device management. Furthermore, because the I2C address is not bound to the device management system, the BMC cannot independently obtain device ownership information and health status (such as sensor data like temperature and voltage) via the I2C path, limiting the full utilization of the server's out-of-band management capabilities.

[0061] Based on this, this application obtains a first correspondence relationship through a first processing module, representing the correspondence between the first connector and the expansion port of the second processing module. Based on this correspondence, it encodes the identification information of the second processing module and its expansion port identification information to generate device information. Then, it sends the encoded device information to the first storage module of the device expansion card via the first connector, achieving effective transmission and storage of device ownership information between the motherboard and the device expansion card. Simultaneously, by storing the device information on the device expansion card, the BMC can independently obtain device ownership information via the I2C path, without relying on PCIe enumeration or real-time transmission by the BIOS. This achieves unified binding and management of PCIe / CXL addresses and I2C addresses, thus solving the technical problem in related technologies where the same device cannot be managed simultaneously via PCIe and I2C paths. Furthermore, by associating physical silkscreen markings with device ownership information, this application enables servers to directly report device location information using physical silkscreen markings readable by maintenance personnel, significantly improving the efficiency and accuracy of data center server maintenance.

[0062] In some embodiments, refer to Figure 6The motherboard 1 also includes: an arbitration chip 15, which is connected to the first processing module 11 and the hub 14 respectively, and is used to switch the channels of the hub 14; the device expansion card 2 includes a switching chip 23 and a second storage module 24. The first processing module 11 is connected to the switching chip 23 in sequence through the arbitration chip 15, the channel of the hub 14, the first connector 13, and the second connector 22. The switching chip 23 connects the second storage module 24 and the physical slot on the device expansion card 2 through different switching channels. The second storage module 24 is used to store the burning information, and the physical slot is used to connect external devices.

[0063] Specifically, the motherboard 1 is also equipped with an arbitration chip 15, which is connected to the first processing module 11 and the hub 14 respectively. The arbitration chip 15 is used to perform bus arbitration when multiple first processing modules 11 (such as BIOS and BMC) initiate access requests at the same time, so as to determine which first processing module 11 currently obtains the right to use the hub 14 channel and switches the selected channel to the corresponding first connector 13.

[0064] When the first processing module 11 (such as BIOS) needs to access the device expansion card 2, it sends an access request to the arbitration chip 15. The arbitration chip 15 makes a ruling according to the preset arbitration strategy (such as priority-based or first-come-first-served). If the ruling is successful, the first processing module 11 is allowed to obtain control of the hub 14 channel and switch the channel to the corresponding first connector 13, thereby establishing a communication path between the first processing module 11 and the device expansion card 2.

[0065] The device expansion card 2 is equipped with a switching chip 23 (such as an I2C switch) and a second storage module 24. The input of the switching chip 23 is connected to the first connector 13 on the motherboard 1 via the second connector 22 and a cable, and its output has multiple switching channels. The first processing module 11 establishes a communication connection with the switching chip 23 on the device expansion card 2 in sequence via the arbitration chip 15, the target channel of the hub 14, the first connector 13, the cable, and the second connector 22, and controls the switching chip 23 to switch between different switching channels to access target devices connected to different switching channels.

[0066] The switching chip 23 connects to the second storage module 24 and each physical slot on the device expansion card 2 through different switching channels. The second storage module 24 (e.g., FRU EEPROM) is used to pre-store the programming information of the device expansion card 2. This programming information includes, but is not limited to, hardware characteristics of the device expansion card 2, such as card type, number of slots, slot order, slot identifier, the mapping relationship between the switching chip 23's channels and physical slots, and the I2C address of the storage module corresponding to each slot. Each physical slot is used to connect external devices, such as GPUs, NVMe SSDs, or network cards. After the first processing module 11 switches to the corresponding channel via the switching chip 23, it can access the second storage module 24 to read the programming information, thereby obtaining the basic configuration and topology of the device expansion card 2. It can also access the storage modules corresponding to each physical slot (e.g., GPIO expansion chips, CPLDs, MCUs, or EEPROMs) to obtain the device address information of each slot or perform device management.

[0067] In response to the power-on command of the motherboard 1, the first processing module 11 accesses the second storage module 24 and the first storage module 21 of the device expansion card 2 to obtain the burning information of the device expansion card 2 and the device information of the second processing module 12 corresponding to the device expansion card 2. It also scans the physical slots of the device expansion card 2 to obtain the presence signal of the physical slots. The first processing module 11 determines the physical slots in place based on the presence signal, and determines the association information of the physical slots in place based on the burning information and the device information of the second processing module 12, and establishes a binding relationship between the physical slots in place and the corresponding association information. The first processing module 11 manages the external devices connected to the physical slots based on the binding relationship.

[0068] Specifically, in response to the power-on command from the motherboard 1, the first processing module 11 (e.g., BIOS) sequentially accesses the second storage module 24 and the first storage module 21 of the device expansion card 2 via the switching chip 23 to obtain the programming information of the device expansion card 2 and the device information of the second processing module 12 corresponding to the device expansion card 2, respectively. The programming information is pre-stored in the second storage module 24 (e.g., FRU EEPROM), including the hardware characteristics of the device expansion card 2, such as card type, number of slots, slot order, the mapping relationship between the channel of the switching chip 23 and the physical slots, and the I2C address of the storage module corresponding to each slot. The device information is stored in the first storage module 21, containing the identification information of the second processing module 12 to which the device expansion card 2 belongs and its expansion port identification information. Simultaneously, the first processing module 11 sequentially selects the channel corresponding to each physical slot via the switching chip 23, scans each physical slot, detects whether an external device is inserted in each slot, and thus obtains the presence signal of each physical slot.

[0069] Subsequently, the first processing module 11 determines the physical slot currently in the present state (i.e., the in-situ physical slot) based on the present signal, and determines the associated information of the in-situ physical slot based on the programming information and device information. This associated information includes the slot number, physical silkscreen location, PCIe address (BDF), and I2C address corresponding to the in-situ physical slot. The first processing module 11 establishes a binding relationship between the in-situ physical slot and the aforementioned associated information, that is, it associates and binds the physical slot with its ownership information, physical location information, and management address information. For example, it binds the in-situ physical slot 0 with information such as "belonging to Port0 of CPU0, located in Slot1, BDF is 00:01.0, and I2C address is 0x20".

[0070] Finally, the first processing module 11 manages the external devices connected to the physical slots based on the established binding relationships. This management includes, but is not limited to: allocating PCIe bus resources (such as BDF) to identified external devices, configuring device address spaces, generating device trees, reporting device information to the BMC, and dynamically identifying and configuring devices in response to hot-plug events.

[0071] This enables automated identification, binding, and management of the device expansion card and the external devices connected to its various physical slots, simplifying the configuration process and improving the efficiency and accuracy of server device management.

[0072] In some embodiments, the associated information includes the physical silkscreen of the external device connected to the in-slot physical slot. The method further includes: parsing the programming information to obtain the slot information of the in-slot physical slot, wherein the slot information includes the physical slot order and the relative position of the physical slot on the device expansion card 2; obtaining the insertion position of the device expansion card 2 on the server; and determining the physical silkscreen of the external device connected to the in-slot physical slot based on the physical slot order, the relative position of the physical slot on the device expansion card 2, and the insertion position.

[0073] Specifically, connection information includes the physical silkscreen markings of external devices connected to the physical slots in the server. Physical silkscreen markings refer to the physical location identifiers (such as Slot1, Slot2, etc.) marked on the server chassis or panel, used by maintenance personnel to identify and locate the devices on-site.

[0074] To determine the physical silkscreen, the first processing module 11 first parses the burning information (pre-stored in the second storage module 24) to obtain the slot information of the physical slots in place. This slot information includes the physical slot order (e.g., slot 0, slot 1, slot 2, etc.) and the relative position of each physical slot on the device expansion card 2 (e.g., top-down arrangement or left-to-right arrangement). Simultaneously, the first processing module 11 obtains the insertion position of the device expansion card 2 in the server chassis, for example, position 1 (near CPU0) or position 2 (near CPU1) of the device expansion card 2 inserted on the motherboard 1. This insertion position can be obtained through slot markings or insertion position detection circuits in the motherboard 1 hardware design.

[0075] The first processing module 11 determines the physical silkscreen of the external device connected to the physical slot based on the physical slot order, the relative position of the physical slot on the device expansion card 2, and the insertion position of the device expansion card 2 on the server. For example, when the device expansion card 2 is inserted into position 1 of the motherboard 1, its slot 0 corresponds to the chassis silkscreen Slot 1, and slot 1 corresponds to Slot 2; when the same device expansion card 2 is inserted into position 2 of the motherboard 1, its slot 0 corresponds to the chassis silkscreen Slot 4, and slot 1 corresponds to Slot 5.

[0076] After determining the physical silkscreen, the first processing module 11 establishes a binding relationship between the in-situ physical slots and the physical silkscreen. Specifically, the first processing module 11 associates the physical slot order, the relative position of the physical slots on the device expansion card 2, the insertion position of the device expansion card 2 on the server, and the physical silkscreen to form a mapping relationship between physical slots and physical silkscreen. For example, when the device expansion card 2 is inserted into slot 1 of the motherboard 1, and its slot 0 corresponds to the chassis silkscreen Slot 1, the first processing module 11 binds "slot 0" and "slot 1". After the binding is completed, the server can directly report the device location information with physical silkscreen identifiers that are readable by maintenance personnel. When events such as device failure, abnormal temperature, or disconnection are detected, alarms containing physical silkscreen information can be directly output. Maintenance personnel do not need to consult any documents or drawings; they can quickly locate the target physical slot and its connected external devices based on the silkscreen identifiers printed on the chassis panel, thereby significantly shortening the fault location time, reducing the risk of misoperation, and improving the efficiency and accuracy of server maintenance.

[0077] In some embodiments, the associated information includes the address information of the expansion port of the second processing module 12 corresponding to the in-situ physical slot. The method further includes: parsing the device information to obtain the expansion port identification information of the second processing module 12 corresponding to the in-situ physical slot; querying a preset expansion port identification information-address information mapping table based on the expansion port identification information of the second processing module 12 to obtain the address information of the expansion port of the second processing module 12 corresponding to the in-situ physical slot; wherein the preset expansion port identification information-address information mapping table includes multiple expansion port identification information and the address information of the expansion port corresponding to each expansion port identification information.

[0078] Specifically, the associated information includes the address information of the extended port of the second processing module 12 corresponding to the physical slot in place, which is used to uniquely identify the extended port in the server system.

[0079] To obtain the address information, the first processing module 11 first parses the device information stored in the first storage module 21 and extracts the extended port identification information of the second processing module 12 corresponding to the physical slot in place. This identification information is used to uniquely identify an extended port of the second processing module 12 (such as Port0, Port1, etc.).

[0080] After obtaining the identification information, the first processing module 11 queries a preset extended port identification information-address information mapping table to obtain the address information of the extended port of the second processing module 12 corresponding to the physical slot in place. The preset mapping table is stored in advance in the server system and contains multiple extended port identification information and the address information of the extended port corresponding to each extended port identification information. The mapping relationship is predetermined by the hardware design or system configuration.

[0081] After obtaining the address information of the aforementioned extended port, the first processing module 11 establishes a binding relationship between the in-situ physical slot and the address information of the extended port. Specifically, the first processing module 11 associates the physical slot identifier with the parsed extended port address information to form a mapping between physical slot and extended port address information. For example, when the in-situ physical slot is slot 0, its corresponding extended port identifier is Port0, and the address information corresponding to Port0 obtained by querying the mapping table is "00", the first processing module 11 binds "slot 0" with the address information "00". After the binding is completed, the server can perform PCIe bus enumeration, resource allocation, and device addressing based on the address information, or locate the logical position of the device in the system through the address information, thereby achieving accurate management and rapid location of device information.

[0082] In some embodiments, the associated information includes the I2C address of the first storage module 21 in the physical slot. The method further includes: parsing the programming information to obtain a second correspondence between the switching channel and the physical slot; and controlling the switching channel to open sequentially based on the second correspondence to obtain the I2C address of the first storage module 21 in the physical slot.

[0083] Specifically, the associated information includes the I2C address of the first storage module 21 of the physical slot in which it is located. This I2C address is used by the first processing module 11 to access the first storage module 21 of the corresponding physical slot via the I2C bus to read the device information of that slot.

[0084] To obtain the I2C address, the first processing module 11 first parses the programming information (pre-stored in the second storage module 24) to obtain a second correspondence between the switching channels of the switching chip 23 and the physical slots. This second correspondence is predetermined by the hardware design and records which switching channel of the switching chip 23 each physical slot on the device expansion card 2 is connected to. After obtaining the second correspondence, the first processing module 11 controls each switching channel of the switching chip 23 to open sequentially based on the correspondence, that is, selects each switching channel one by one on the I2C bus. When a certain switching channel is selected, the first processing module 11 reads the I2C address of the first storage module 21 of the corresponding physical slot through the channel and stores the I2C address as one of the associated information of the physical slot, thereby establishing a binding relationship between the physical slot and the I2C address.

[0085] In this way, the first processing module can directly access the first storage module of the corresponding physical slot through the I2C address to obtain the device information of the slot, thereby achieving accurate reading and management of the device information.

[0086] In some embodiments, the associated information includes the device identifier of the external device, and the method further includes: parsing the programming information to obtain a second correspondence between the switching channel and the physical slot; controlling the switching channel to open sequentially based on the second correspondence, and assigning a device identifier to the external device connected to the physical slot based on the extended port identification information of the second processing module 12.

[0087] Specifically, the first processing module 11 first parses the burning information (stored in the second storage module 24) to obtain the second correspondence between the switching channel of the switching chip 23 and the physical slot. The second correspondence records which switching channel of the switching chip 23 each physical slot on the device expansion card 2 is connected to.

[0088] Based on the second correspondence, the first processing module 11 controls the switching channels of the switching chip 23 to open sequentially, selecting each physical slot in turn. Each time a channel is selected, the first processing module 11 accesses the storage module of the corresponding physical slot through the channel, reads the device information stored therein, and obtains the expansion port identification information (such as CPU0 / Port0) of the second processing module 12 corresponding to the physical slot. Since the expansion port identification information indicates which CPU and which PCIe / CXL port the physical slot belongs to, the BIOS determines the bus range that the external device connected to the physical slot should be allocated to, that is, under which expansion port bus number the device should belong, and assigns the corresponding PCIe bus number, device number, and function number to the external device, that is, the BDF (Bus-Device-Function) identifier (such as 00:01.0, 00:02.0, etc.).

[0089] Taking Port0 of CPU0 as an example, if its corresponding bus number is "00", then the external devices connected to each physical slot under this port are all assigned bus numbers of "00", and the device numbers are different from each other (such as 01, 02, 03), so as to distinguish the devices in different slots under the same expansion port.

[0090] The first processing module 11 associates physical slots with the parsed external device BDF identifiers, forming a mapping between physical slots and device identifiers. For example, when the in-slot physical slot is slot 0 and the device identifier assigned to its corresponding external device is 00:01.0, the first processing module 11 binds "slot 0" to "00:01.0"; similarly, it binds slot 1 to 00:02.0 and slot 2 to 00:03.0. After binding, the server can query the corresponding device identifier through the physical slot and also locate the physical slot through the device identifier, thus realizing a bidirectional association between physical slots and device identifiers. In this way, the first processing module associates and binds physical slots with device identifiers, providing a basis for subsequent PCIe bus enumeration, device access, and resource allocation.

[0091] In some embodiments, the first processing module 11 includes a baseboard management controller, a basic input / output system, or a programmable logic device.

[0092] In some embodiments, the method further includes: establishing a third correspondence between a device identifier and a physical slot through a basic input / output system; and sending the third correspondence to a baseboard management controller through a preset communication interface.

[0093] Specifically, a third correspondence between device identifiers and physical slots is established through the basic input / output system. This third correspondence records the mapping relationship between the device identifiers (such as BDF numbers) assigned to the external devices connected to each physical slot and the physical slots.

[0094] After assigning device identifiers to the external devices connected to each physical slot, the Basic Input / Output System (BIOS) generates this mapping. Subsequently, the BIOS sends this third mapping to the board management controller via a preset communication interface, such as IPMI or Redfish interface.

[0095] After receiving the third correspondence, the baseboard management controller can locate the corresponding physical slot based on the device identifier during system operation, or query the corresponding device identifier based on the physical slot. This eliminates the need to rely on real-time transmission from the basic input / output system, thus accurately determining the correspondence between the device identifier and the physical slot even when the operating system is not running or the system is malfunctioning. This provides a basis for device management and fault location in out-of-band scenarios.

[0096] As a concrete example, refer to Figure 7 The motherboard side includes the BMC, BIOS, CPLD, I2C arbitration chip, I2C hub chip, I2C connector, PCIe / UCIe / CXL high-speed connectors; connectors for device expansion cards, I2C connectors, Mux chips, memory chips, logic chips, physical slots, and cables connecting the motherboard and device expansion cards.

[0097] As a first embodiment, refer to Figure 7On the motherboard side, a pin representing the CPU address, i.e., CPU_ADDR0 / 1 / 2, is added to the MCIO of the high-speed connector. These pins represent CPU0, CPU1, ..., CPU7, respectively, using CPU encoding. Simultaneously, pins representing the PCIe / UCIe / CXL port (expansion port) addresses, i.e., PE0 / 1 / 2 / 3, are added to the MCIO of the high-speed connector, each representing a different PCIe / UCIe / CXL port descriptor. This high-speed connector connects to the PCIe / UCIe / CXL expansion card (device expansion card) via a cable. The CPU_ADDR0 / 1 / 2 pin information and the PE0 / 1 / 2 / 3 information are stored through a GPIO expansion chip or the expansion card (a non-programmable logic chip). The GPIO expansion chip and the PCIe / UCIe / CXL slot number (the physical slot number of the device expansion card) have a predefined mapping relationship. For example, GPIO expansion chip 0 corresponds to PCIe / UCIe / CXL slot 0, and GPIO expansion chip 1 corresponds to PCIe / UCIe / CXL slot 1. This design stores the CPU address information and PCIe / UCIe / CXL port address information corresponding to the PCIe / UCIe / CXL slots into the GPIO expansion chip corresponding to the slot. The motherboard BIOS and BMC read and decode the information in the GPIO expansion chip corresponding to each slot through the I2C connector.

[0098] As a second embodiment, refer to Figure 7 The device expansion card uses a connector (first connector) to bind low-speed communication protocols such as PCIe, UCIe, CXL, I2C, PESTI, and USB. The low-speed communication protocols are connected to the logic chip (e.g., CPLD, MCU, etc.) of the device expansion card via a low-speed hub (e.g., an I2C / PESTI / USB hub, I2C preferred in this embodiment). For example, if the device expansion card is a hard drive backplane expansion card, a CPLD is selected as the logic chip because hard drive backplanes already require CPLD processing; if the device expansion card is a riser expansion card, an MCU is selected as the logic chip because MCUs are low-cost and simple to design and develop.

[0099] The motherboard-side BIOS and CPLD encode CPU_ADDR[0:2] and Port[0:3] according to the first correspondence (the correspondence between the first connector and the expansion ports of the second processing module), and transmit the encoded information to the logic chip of the expansion card via a low-speed communication protocol. The expansion card logic chip decodes and transmits the encoded information. This achieves the transmission of virtual encoded information for CPU_ADDR[0:2] and Port[0:3] in each slot. Furthermore, the motherboard-side BMC and BIOS connect to the logic chip of the expansion card via an I2C connector to obtain the virtual encoded information for CPU_ADDR[0:2] and Port[0:3] in each slot of the logic chip and perform decoding.

[0100] The BIOS / CPLD on the motherboard is connected to the existing I2C pins in the MCIO connector via an I2C hub. Through the MCIO cable, it is connected to the logic chip (programmable logic chip) on the expansion card, such as a CPLD or MCU. The BIOS writes the CPU / Port information as data to this chip, and the BMC / BIOS reads it from the same chip. The whole process does not add any new pins and fully reuses the I2C bus.

[0101] As a third embodiment, refer to Figure 7 The system binds low-speed communication protocols such as PCIe, UCIe, CXL, I2C, PESTI, and USB to a single connector (first connector). These low-speed communication protocols are communicated by the BIOS, CPLD, or BMC via a low-speed hub (e.g., an I2C / PESTI / USB hub, preferably I2C) to the storage chip (storage chip) behind the Mux on the device expansion card. The storage chip is typically a flash memory or EEPROM, preferably EEPROM. The BIOS and CPLD on the motherboard side encode CPU_ADDR[0:2] and Port[0:3] according to a first correspondence. This encoded information is then written to the storage chip on the device expansion card via the low-speed communication protocol. Furthermore, the BMC and BIOS on the motherboard side connect to the storage chip on the expansion card via an I2C connector to obtain the virtual encoding information of CPU_ADDR[0:2] and Port[0:3] for each slot of the storage chip and perform decoding.

[0102] The process of binding the logical address and physical address of an external device is as follows: On the motherboard side, the BMC and BIOS act as I2C hosts, connecting to different I2C connectors (I2C0_0 / I2C1_0 in I2C Bus 0, where I2C arbitration chip 0 is located, and I2C0_1 / I2C1_1 in I2C Bus 1, where I2C arbitration chip 1 is located) via multiple I2C arbitration chips. I2C connectors can be standalone connectors or added to the high-speed connector MCIO. The BMC and BIOS can control the I2C arbitration chips to set themselves as the sole I2C host, ensuring that only one I2C host can access the corresponding I2C bus at any given time.

[0103] Different I2C arbitration chips are connected to I2C connectors that represent the locations of PCIe, UCIe, and CXL expansion cards in different servers. The correspondence between the locations and connectors is predetermined in the design. Therefore, when the BMC or BIOS accesses different I2C arbitration chips, it means that the accessed PCIe, UCIe, or CXL expansion cards come from different server system locations.

[0104] The I2C connector connects to the PCIe / UCIe / CXL expansion card via a cable and switches between different channels via the I2C switching chip (I2CSwitch). When accessing channel 0, the FRU device and GPIO expansion chip can be accessed. PCIe / UCIe / CXL slot 0, PCIe / UCIe / CXL slot 1, ..., PCIe / UCIe / CXL slot 5 can be accessed by accessing channels 1, 2, ..., 6 respectively.

[0105] The BMC and BIOS can access the GPIO expansion chip or logic chip through the I2C path to obtain the CPU address encoding information and PCIe / UCIe / CXL port address encoding information of the PCIe / UCIe / CXL device in the specified PCIe / UCIe / CXL slot, and thus know the address of the PCIe / UCIe / CXL device.

[0106] The PCIe / UCIe / CXL expansion card design describes the relative physical locations of the PCIe / UCIe / CXL slots. For example, from top to bottom, they are PCIe / UCIe / CXL slot 0, PCIe / UCIe / CXL slot 1, ..., PCIe / UCIe / CXL slot 5, etc. Therefore, the BMC and BIOS can access the PCIe / UCIe / CXL device via the I2C path and I2C address to obtain the system location of the associated PCIe / UCIe / CXL expansion card and the relative position of the PCIe / UCIe / CXL device slot on the expansion card, thus obtaining the physical silkscreen location of the server where the PCIe / UCIe / CXL device is located.

[0107] For PCIe / UCIe / CXL expansion cards, their hardware characteristics should be planned in advance and filled into the second storage chip (e.g., flash, EEPROM, etc., preferably EEPROM) within the expansion card. The hardware characteristics include: the I2C switch of the PCIe / UCIe / CXL expansion card, the I2C address of the GPIO expansion chip, the channel mapping relationship of the I2C switch, the slot order of the PCIe / UCIe / CXL expansion card, and the relative position of the slots on the PCIe / UCIe / CXL expansion card. Furthermore, the BMC and BIOS can combine existing information to automatically bind the I2C path and address on the specified PCIe / UCIe / CXL slot, the physical silkscreen address of the server, and the PCIe / UCIe / CXL device address.

[0108] As another concrete example, refer to Figure 8 The server device information association method in this application embodiment may further include the following steps: S0, the BIOS controls the I2C arbitration chip at position i in sequence.

[0109] Specifically, the BMC / BIOS obtains control of PCIe / UCIe / CXL expansion cards in the server by sequentially accessing the I2C arbitration chip via I2C, that is, sequentially obtaining the PCIe / UCIe / CXL device expansion cards that are connected and inserted into positions 0, 1, ..., n.

[0110] S1, the BIOS controls the opening of switching channel 0 to obtain FRU information (including ①~⑤).

[0111] Specifically, FRU information includes the following: ① The I2C address of the first storage module, such as the I2C address of logic chips (GPIO Expander, CPLD, MCU) and storage chips (EEPROM, Flash); ② The correspondence between the first storage module and each PCIe / UCIe / CXL slot; ③ The correspondence between the channels and physical slots of the I2C switch; ④ PCIe\UCIe\CXL slot order; ⑤ The relative positions of the PCIe, UCIe, and CXL slots on the PCIe, UCIe, and CXL expansion cards; S2, the BIOS determines the physical slot silkscreen based on the location of the PCIe\UCIe\CXL expansion card, ④ and ⑤.

[0112] Specifically, BMC / BIOS can obtain the physical silkscreen of the server where all PCIe\UCIe\CXL devices are located by using the order of ④ PCIe\UCIe\CXL slots and the relative position of ⑤ PCIe\UCIe\CXL slots on the PCIe\UCIe\CXL expansion cards, combined with the location of the PCIe\UCIe\CXL expansion cards.

[0113] S3, the BIOS uses ② to obtain the presence information of PCIe devices, CPU address information and PCIe port address information on each PCIe slot.

[0114] If the first storage module is a GPIO expansion chip, then the FRU information includes the correspondence between the GPIO expansion chip and the PCIe / UCIe / CXL slots. The corresponding GPIO expansion chips for each PCIe / UCIe / CXL slot are accessed sequentially. Based on the PRSNT signals of CPU0 / 1 / 2, PE0 / 1 / 2 / 3, and the PCIe / UCIe / CXL devices, the presence information, CPU address information, and PCIe / UCIe / CXL port address information of the PCIe / UCIe / CXL devices in each PCIe / UCIe / CXL slot are obtained.

[0115] If the first storage module is a programmable logic device or a microcontroller unit, the FRU information includes the correspondence between the register ID of the first storage module and the PCIe / UCIe / CXL slot. The BMC / BIOS communicates with the logic chip of the device expansion card to obtain the presence information of the PCIe / UCIe / CXL devices in each PCIe / UCIe / CXL slot, obtains and decodes the CPU and port encoding information of each slot, and thus obtains the CPU address information and the PCIe / UCIe / CXL port address information.

[0116] If the first storage module is an erasable programmable read-only memory or flash memory, the FRU information includes the correspondence between the first storage module and the PCIe / UCIe / CXL slots. The BMC / BIOS communicates with the first storage chip of the device expansion card to obtain and decode the CPU and port encoding information of each slot, thereby obtaining the CPU address information and the PCIe / UCIe / CXL port address information.

[0117] In S4, the BIOS performs a PCIe scan, assigns a unique PCIe BDF identifier to the device, and passes it to the BMC via Redfish.

[0118] Specifically, the BIOS scans PCIe / UCIe / CXL devices in a specified order according to the CPU address information and PCIe / UCIe / CXL port address information, generating PCIe / UCIe / CXL identifiers. This means the BIOS binds a BDF identifier to each PCIe / UCIe / CXL device. For example, the BIOS uses PCIe / UCIe / CXL port 0 on CPU0 to assign the value BDF1 to the PCIe / UCIe / CXL slot 0. The BIOS establishes a binding relationship between BDF1 and either PCIe / UCIe / CXL port 0 or PCIe / UCIe / CXL slot 0 (the third correspondence). The BIOS then passes this binding relationship between the PCIe / UCIe / CXL devices and their PCIe / UCIe / CXL identifiers to the BMC.

[0119] S5, the BIOS determines the I2C switch channels 1 to 6 in sequence according to ③, and scans to obtain the I2C address of the PCIe device.

[0120] Specifically, the BMC / BIOS scans PCIe, UCIe, and CXL devices according to the channel mapping relationship of the ③I2C Switch and assigns I2C addresses, that is, binds an I2C address to each PCIe, UCIe, and CXL device.

[0121] S6, BIOS binds to the server system slot number, slot silkscreen, PCIe address and I2C address.

[0122] Specifically, the BMC / BIOS combines the physical silkscreen of the server where the PCIe / UCIe / CXL devices are located in all PCIe / UCIe / CXL slots, the binding relationship between the PCIe / UCIe / CXL devices and their identifiers, and the binding relationship between the PCIe / UCIe / CXL devices and their I2C addresses to form the binding relationship between the physical silkscreen address of the PCIe / UCIe / CXL devices, their identifiers, and their I2C addresses.

[0123] BMC / BIOS enables other functions related to PCIe / UCIe / CXL device addresses, such as asset information management, fault diagnosis and location, and thermal strategies, by leveraging the binding relationships between the physical silkscreen address, PCIe / UCIe / CXL identifier address, and I2C address of PCIe / UCIe / CXL devices.

[0124] As yet another concrete example, refer to Figure 9 The server device information association method in this application embodiment may further include the following steps: 1) On the server motherboard, the BMC chip is selected from chips with abundant GPIO and I2C resources and superior processing performance, model: AST2600.

[0125] 2) The BMC and BIOS can access the same Riser in a time-sharing manner by accessing the I2C arbitration chip. The I2C arbitration chip model is CA9641.

[0126] 3) The BMC and BIOS can access the Riser located at server positions 1 and 2 by accessing two I2C arbitration chips with different addresses. All I2C devices on the Riser are connected to different channels of the I2C Switch. The I2C Switch model is CA9548 or CA9546.

[0127] 3) Riser I2C Switch channel 0 contains EEPROM (FRU), temperature sensor, GPIO Expander chip, etc. Models include GT24C256C_DS_Cu, M24256-BRMN6TP, TMP112, EMC1413, and CA9555. Riser I2C Switch channels 1 to 6 connect to the I2C ports on PCIe, UCIe, and CXL CEM slots 0 to 5, respectively.

[0128] 4) To obtain the Riser data for server location 1, the BIOS controls the activation of I2C arbitration chip 1 and I2CSwitch channel 0. It then retrieves information stored in the EEPROM (FRU), including uplink connector data, downlink connector data, and location 1 silkscreen pattern data. After determining the total number of downlink connector slots, it reads the silkscreen information for each slot, the IO status of the corresponding GPIO Expander (CA9555), and the maximum bandwidth supported by the slot. Obtaining location information for other server slots follows the same process.

[0129] 5) The BIOS uses the CPU_ADDR, VPP_ADDR, and mapping table of slots 0 to 5 to deduce which CPU and which PCIe / UCIe / CXL Port the device in that slot belongs to. During PCIe / UCIe / CXL scanning, the BIOS binds each PCIe / UCIe / CXL Port for each CPU number to the server system slot number and slot silkscreen. The VPP_ADDR and PCIe / UCIe / CXL Port mapping table is shown in Table 1.

[0130] Table 1

[0131] 6) The BIOS sends the server system slot number, slot silkscreen, and PCIe / UCIe / CXL address binding data to the BMC via Redfish. The BMC parses and saves the data.

[0132] 7) The BIOS sequentially controls and individually opens I2C Switch channels 1 to 6, scanning the I2C addresses of PCIe, UCIe, and CXL devices. Combining the slot number, slot silkscreen, and PCIe / UCIe / CXL address binding data, it generates binding data information for the slot number, slot silkscreen, PCIe / UCIe / CXL address, and I2C address, which is then applied to functions such as location information display and fault diagnosis.

[0133] 8) To obtain the Riser data for server location 1, the BMC controls the opening of I2C arbitration chip 1 and I2CSwitch channel 0. It then retrieves information stored in the EEPROM (FRU), including uplink connector data, downlink connector data, and location 1 silkscreen pattern data. After obtaining the total number of downlink connector slots, it reads the silkscreen information for each slot, the IO status of the corresponding GPIO Expander, and the maximum bandwidth supported by the slot. Obtaining the location information for other server slots follows the same process.

[0134] 9) The BMC parses the CPU_ADDR, VPP_ADDR, and mapping table of slots 0 to 5 to determine which CPU and PCIe / UCIe / CXL port the device in that slot comes from. It then parses and saves the data, including the slot number, slot silkscreen, and PCIe / UCIe / CXL address bindings sent by the BIOS.

[0135] 10) The BMC sequentially controls and individually opens I2C switch channels 1 through 6, scanning the I2C addresses of PCIe, UCIe, and CXL devices. Combining the slot number, slot silkscreen, and PCIe / UCIe / CXL address binding data, it generates binding data information for the slot number, slot silkscreen, PCIe / UCIe / CXL address, and I2C address. This information is then applied to functions such as location information display, fault diagnosis, and slot-oriented heat dissipation strategy control.

[0136] In this way, the mechanism and method for binding the silkscreen, PCIe / UCIe / CXL address (device identifier), and I2C address of the server PCIe / UCIe / CXL external card device proposed in this paper can be implemented.

[0137] In summary, this application binds the server physical silkscreen of PCIe / UCIe / CXL devices to the PCIe / UCIe / CXL address (device identifier) ​​and I2C address, enabling the BIOS / BMC to freely access the same device via either the PCIe / UCIe / CXL path or the I2C path. This achieves dual-path management, effectively avoiding the problem of a designated device being unmanageable due to a single path failure or lack of binding, significantly improving the reliability and flexibility of server device management. Furthermore, this application achieves fully automated binding of the aforementioned addresses, eliminating the need for BIOS / BMC firmware adaptation for newly developed PCIe / UCIe / CXL expansion cards or reuse in new product models. This greatly reduces hardware development workload, lowers the development cost and cycle of BIOS and BMC firmware, and improves product iteration efficiency. In addition, the encoding / decoding and transmission methods of this application can be implemented not only through GPIOs physical pins but also through low-speed communication protocols such as I2C, USB, and PESTI in conjunction with logic chips or memory chips, effectively saving low-speed signal pin resources in high-speed connectors.

[0138] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0139] Corresponding to the above embodiments, this application also proposes a server.

[0140] See Figure 10 As shown, the server 300 of this application includes a memory 310, a processor 320, and a server device information association program stored on the memory 310 and capable of running on the processor 320. When the processor executes the server device information association program, it implements the aforementioned server device information association method.

[0141] It should be noted that the above-described embodiments and explanations of the beneficial effects of the method for associating server device information also apply to the server in the embodiments of this application. To avoid redundancy, they will not be elaborated in detail here.

[0142] Embodiments of this application also provide a computer program product.

[0143] The computer program product of this application includes a computer program / instruction, which, when executed by a processor, implements the aforementioned server device information association method.

[0144] It should be noted that the above-described embodiments and explanations of the beneficial effects of the method for associating server device information also apply to the computer program products of the embodiments of this application. To avoid redundancy, they will not be elaborated in detail here.

[0145] Embodiments of this application also provide a computer-readable storage medium.

[0146] The computer-readable storage medium of this application stores a server device information association program thereon, which, when executed by a processor, implements the aforementioned server device information association method.

[0147] It should be noted that the above-described embodiments and explanations of the beneficial effects of the method for associating server device information also apply to the computer-readable storage medium of the embodiments of this application. To avoid redundancy, they will not be elaborated in detail here.

[0148] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0149] The above provides a detailed description of a method for associating server and device information provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for associating device information on a server, characterized in that, The server includes a motherboard, the motherboard including a first processing module, a second processing module, and a first connector, the first processing module and the second processing module being respectively connected to a device expansion card via the first connector; the method includes: In response to the initialization command of the motherboard, a first correspondence is obtained through the first processing module, wherein the first correspondence is used to characterize the correspondence between the first connector and the expansion port of the second processing module; Based on the first correspondence, the identification information of the second processing module corresponding to the device expansion card and the identification information of the expansion port of the second processing module are determined; The identification information and the extended port identification information are encoded respectively to obtain the device information of the second processing module; The first processing module sends the device information to the first storage module of the corresponding device expansion card.

2. The server device information association method according to claim 1, characterized in that, The motherboard also includes a hub, wherein the hub's channels correspond one-to-one with the first connectors, and the first connectors correspond one-to-one with the expansion ports of the second processing module. The first processing module connects to the device expansion card through the channels and the corresponding first connectors; wherein, obtaining the first correspondence through the first processing module includes: The first processing module determines the first correspondence based on the first connector corresponding to the channel of the hub and the expansion port of the second processing module connected to the first connector.

3. The server device information association method according to claim 2, characterized in that, The device expansion card includes a second connector, which connects to the first connector and also connects to the first storage module; wherein... The device information is sent from the first processing module to the first storage module of the corresponding device expansion card via the hub's channel, the first connector, and the second connector.

4. The server device information association method according to claim 1, characterized in that, The first storage module is a programmable logic chip or a storage chip.

5. The server device information association method according to claim 4, characterized in that, The programmable logic chip is a complex programmable logic device or a microcontroller unit.

6. The server device information association method according to claim 4, characterized in that, The memory chip is a non-volatile memory chip.

7. The server device information association method according to claim 4, characterized in that, The programmable logic chip includes registers, wherein... The register corresponds one-to-one with the physical slot of the device expansion card and is used to store the device information of the second processing module corresponding to the device expansion card.

8. The server device information association method according to claim 4, characterized in that, The storage chip corresponds to the device expansion card, or corresponds one-to-one with a physical slot on the device expansion card, and is used to store device information of the second processing module corresponding to the device expansion card.

9. The server device information association method according to claim 1, characterized in that, The method further includes: In response to the power-on command of the motherboard, the device information stored in the first storage module is read through the first processing module; The first processing module manages the external devices connected to the device expansion card based on the device information.

10. A server, characterized in that, The system includes a memory, a processor, and a server device information association program stored in the memory and capable of running on the processor. When the processor executes the server device information association program, it implements the server device information association method according to any one of claims 1-9.

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