A design method suitable for power-on loading of a double FPGA system
Patent Information
- Application Number
- CN202511997921.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-28
- Publication Date
- 2026-10-30
AI Technical Summary
[0011]本发明的目的是：针对背景技术中提到的两个SIP芯片的上电启动加载问题和由于串接导致FPGA1和FPGA2根本无法加载的问题，提供一种适应于双FPGA系统上电加载设计方法
[0031]上述技术方案所提供的适应于双FPGA系统上电加载设计方法，FPGA的上电加载过程可以通过INIT_B信号进行控制，当INIT_B信号为低时，会控制不进行启动加载，直到INIT_B信号变为高电平，CLK信号输出，才启动程序加载；由于FPGA1与FPGA2对外引脚中CLK信号未串接在一起，因此，可以通过控制INIT_B信号，进而控制FPGA1和FPGA2的加载，实现先后加载的处理方式，本发明提出的设计方法即解决两个FPGA上电后先后加载问题，实现正常启动和IO复用功能。
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Abstract
Description
Technical Field
[0001] This invention belongs to the field of control computing technology and relates to a power-on loading design method suitable for dual FPGA systems. Background Technology
[0002] Currently, common computer hardware architectures involve DSP, FPGA, ARM, and combinations of two or three. Typically, each processor or main control chip connects to external FLASH via the SPI interface to complete the power-on boot loading design, and the SPI interface is only connected to a specific FLASH chip. This is relatively easy to understand for DSP and ARM chips, as the SPI interface will not be used for other purposes. However, FPGA is more flexible in the design and development process, and from a design perspective, there is a possibility that the SPI interface may be reused.
[0003] In the design of a certain SIP (System In a Package) chip, an FPGA, NOR FLASH, and DDR die are integrated internally. The FPGA, as the core device, mainly implements programmable logic design; the DDR is mainly used for large data storage; and the NOR FLASH is mainly used for program storage and power-on loading. The specific design block diagram is shown below. Figure 1 As shown.
[0004] Figure 1 The NOR flash chip communicates with the FPGA via an SPI interface. Besides the ground signal, the interface signals include: #CS, DO (DQ1), #WP (DQ2), DI (DQ0), CLK, and #HOLD / #RST (DQ3). During the SIP design process, for redundancy, all interface signals are routed to the FPGA's general-purpose I / O pins for easy connection of external flash chips, such as... Figure 2 As shown.
[0005] For dual FPGA systems, and systems containing Figure 1 The two SIP chips shown are arranged in accordance with... Figure 2 Each of the shown components leads to a set of SIP chips. In addition to the dual FPGAs, the entire system also includes the main control device required for system flow control and task scheduling, such as... Figure 3 As shown in the diagram. In this design, the external general-purpose I / O of the SIP chip is connected to the I / O of the main control chip. In order to facilitate the development and design of the FPGA program, the connection positions of the two SIP chips are consistent. That is, the signal connected to #CS is pin AL33 on SIP1, and the corresponding signal is also connected to pin AL33 on SIP2. The connection relationships of other pins are consistent with #CS.
[0006] against Figure 3In the dual FPGA system, whether it is SIP1 or SIP2, in addition to being connected to the FPGA, the interface signals are also led out to connect to the IO interface of the main control device, realizing the function of IO interface multiplexing. However, in the process of multiplexing, the power-on startup loading of the two SIP chips becomes a problem that needs to be solved. This patent proposes an effective method to solve this problem, which realizes the power-on startup loading function of each of the two SIP chips while meeting the multiplexing requirements.
[0007] Figure 2 When the SIP chip is powered on and loaded normally, the FPGA controller sends out the chip select #CS signal and the CLK clock signal. If the four-wire system is used to read data from the NOR FLASH, the program data will be read from the NOR FLASH into the fixed program execution space CRAM of the FPGA through the four data lines DO (DQ1), #WP (DQ2), DI (DQ0), and #HOLD / #RST (DQ3) for execution. After the program is loaded, the CLK clock signal becomes high and remains high.
[0008] During the FPGA loading process, there are two key pins: INIT_B and DONE_0. INIT_B is an input / output pin that indicates the initialization of the configuration memory (active low). When INIT_B is high, the FPGA begins loading the program from the NOR FLASH. DONE_0 is an input / output pin that indicates successful configuration (active high). By detecting whether the DONE_0 signal is high, it can be determined whether the power-on loading is complete.
[0009] Taking the #CS signal as an example, let's illustrate the current problems: Figure 4 As shown, ① is the chip select signal of FPGA1 accessing NOR FLASH1; ② is the #CS signal output by the SIP1 chip; ④ is the chip select signal of FPGA2 accessing NOR FLASH2; ③ is the #CS signal output by the SIP2 chip. Since the main control device is connected to the SIP1 and SIP2 chips respectively through the IO interface, ② and ③ are connected together. Therefore, ①②③④ are all connected in series, which means that during the power-on loading process, FPGA1 may not load the program from NOR FLASH1, and similarly, FPGA2 may not load the program from NOR FLASH2. In some cases, the series connection may even prevent FPGA1 and FPGA2 from loading at all. The power-on loading method proposed in this patent can solve this problem in dual FPGA systems. Summary of the Invention
[0010] (I) Purpose of the Invention
[0011] The purpose of this invention is to provide a power-on loading design method suitable for dual FPGA systems, addressing the power-on loading problem of two SIP chips mentioned in the background art and the problem that FPGA1 and FPGA2 cannot be loaded at all due to serial connection.
[0012] (II) Technical Solution
[0013] To address the aforementioned technical problems, this invention provides a power-on loading design method suitable for dual FPGA systems, comprising the following steps:
[0014] Step 1: Power on the system;
[0015] Step 2: Configure the PROGRAM signals of FPGA1 and FPGA2 to be at a high level;
[0016] Step 3: Pull INIT_B high for FPGA1 and pull INIT_B low for FPGA2;
[0017] Step 4: Check if the DONE_0 signal of FPGA1 is high. If yes, proceed to step 5; otherwise, continue the DONE_0 signal level detection in step 4.
[0018] Step 5: Pull INIT_B low on FPGA1 and pull INIT_B high on FPGA2;
[0019] Step 6: Check if the DONE_0 signal of FPGA2 is high. If yes, proceed to step 7; otherwise, continue the DONE_0 signal level detection in step 6.
[0020] Step 7: The dual FPGA system completes startup loading.
[0021] Furthermore, in step 1, after power-on, FPGA1 loads first and FPGA2 loads later. Before FPGA1 and FPGA2 load, ensure that the external interfaces of SIP1 and SIP2 are not input with high or low levels.
[0022] Furthermore, in step 2, the PROGRAM signal is the FPGA configuration start control signal, which is active low and is used to trigger the FPGA to load the external configuration file into the internal SRAM.
[0023] Furthermore, in step 2, when the PROGRAM signal is pulled low and the timing requirements are met, the FPGA will initialize the configuration interface and complete the configuration function. After the configuration function is completed, the signal will return to a high level.
[0024] Furthermore, in step 2, the PROGRAM signals of the two FPGAs are set to 1 to avoid repeated power-on loading of the FPGAs.
[0025] Furthermore, in step 3, FPGA1 is loaded first, and FPGA2 is not read from the program. That is, FPGA2's INIT_B is pulled low, and when INIT_B is configured to a high level, FPGA2 starts reading from the program.
[0026] Furthermore, in step 4, FPGA1 is in the loading process. After loading is completed, the DONE_0 signal of FPGA1 is pulled high. The high and low levels of the DONE_0 signal are detected to determine whether FPGA1 has completed loading. If loading is completed, step 5 is executed. If loading is not completed, the detection continues in step 4.
[0027] Furthermore, in step 5, FPGA1 has completed loading, and FPGA2 is controlled to read the program. FPGA2's INIT_B is pulled high, while FPGA1's INIT_B is pulled low to ensure that FPGA1 is not loaded.
[0028] Furthermore, in step 6, FPGA2 is in the loading process. After loading is completed, the DONE_0 signal of FPGA2 is pulled high. The high and low levels of the DONE_0 signal are detected to determine whether FPGA2 has completed loading. If loading is completed, step 7 is executed. If loading is not completed, the detection continues in step 6.
[0029] Furthermore, in step 7, both FPGAs complete the startup loading and run their respective programs, and the external pins of SIP1 and SIP2 are multiplexed.
[0030] (III) Beneficial Effects
[0031] The above-described technical solution provides a power-on loading design method suitable for dual FPGA systems. The FPGA power-on loading process can be controlled by the INIT_B signal. When the INIT_B signal is low, loading will not be initiated until the INIT_B signal goes high and the CLK signal is output, at which point program loading will begin. Since the CLK signals on the external pins of FPGA1 and FPGA2 are not connected in series, the loading of FPGA1 and FPGA2 can be controlled by controlling the INIT_B signal, thus achieving sequential loading. The design method proposed in this invention solves the problem of sequential loading of two FPGAs after power-on, realizing normal startup and I / O multiplexing functions. Attached Figure Description
[0032] Figure 1 Design a block diagram for a certain SIP chip.
[0033] Figure 2 This is a schematic diagram of the external SPI interface of a certain SIP chip.
[0034] Figure 3This is a schematic diagram of a dual FPGA system.
[0035] Figure 4 The diagram shows the cascaded connection of the #CS signal.
[0036] Figure 5 This is a flowchart of a method according to an embodiment of the present invention. Detailed Implementation
[0037] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0038] Following the principle of loading FPGA1 first and FPGA2 later after power-on, before loading FPGA1 and FPGA2, ensure that no high or low levels are input to the external interfaces of SIP1 and SIP2, that is, the multiplexed pins are not affected by external levels, and that their respective programs have been successfully programmed in the correct manner.
[0039] like Figure 5 As shown, this embodiment of the power-on loading design method for a dual FPGA system includes the following steps:
[0040] Step 1: Power on the system.
[0041] Step 2: Configure the PROGRAM signals of FPGA1 and FPGA2 to be at a high level.
[0042] The PROGRAM signal is the FPGA's configuration start control signal, typically active low, used to trigger the FPGA's startup process of loading external configuration files (such as bitstreams from FLASH) into its internal SRAM. When this signal is pulled low and timing requirements are met, the FPGA initializes its configuration interface (such as SPI or JTAG) and completes the configuration function. After the configuration function is complete, the signal returns to a high level. In this design, the PROGRAM signals of both FPGAs are set to 1 to avoid the FPGAs performing repeated power-on loading.
[0043] Step 3: Pull INIT_B high for FPGA1 and pull INIT_B low for FPGA2.
[0044] To control FPGA1 to load first, it is necessary to prevent FPGA2 from reading the program. This is achieved by pulling FPGA2's INIT_B low and waiting for INIT_B to be configured to a high level before FPGA2 can start reading the program.
[0045] Step 4: Check if the DONE_0 signal of FPGA1 is high.
[0046] In this step, FPGA1 is in the loading process. After the loading is completed, the DONE_0 signal of FPGA1 will be pulled high. By detecting the high and low levels of the DONE_0 signal, it can be determined whether FPGA1 has completed loading. If the loading is completed, proceed to step 5. If the loading is not completed, continue to detect in step 4.
[0047] Step 5: Pull INIT_B low on FPGA1 and pull INIT_B high on FPGA2.
[0048] By step 5, FPGA1 has completed loading. At this point, it is necessary to control FPGA2 to read the program, that is, pull INIT_B of FPGA2 high and pull INIT_B of FPGA1 low to ensure that FPGA1 does not load.
[0049] Step 6: Check if the DONE_0 signal of FPGA2 is high.
[0050] In this step, FPGA2 is in the loading process. After the loading is completed, the DONE_0 signal of FPGA2 will be pulled high. By detecting the high and low levels of the DONE_0 signal, it can be determined whether FPGA2 has completed loading. If the loading is completed, proceed to step 7. If the loading is not completed, continue to detect in step 6.
[0051] Step 7: The dual FPGA system completes startup loading.
[0052] By step 7, both FPGAs have completed startup loading and are running their respective programs. The external pins of SIP1 and SIP2 can be reused.
[0053] This invention describes a method for power-on loading of a dual FPGA system, which solves the power-on conflict problem caused by serial connection and enables the multiplexing function of FPGA IO pins. It provides a solution for power-on loading of dual FPGA systems and offers reference for power-on loading of multi FPGA systems. In the case of limited IO resources, it verifies the multiplexing function of SPI interface signals.
[0054] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A power-on loading design method adapted to a dual FPGA system, characterized in that, Includes the following steps: Step 1: Power on the system; Step 2: Configure the PROGRAM signals of FPGA1 and FPGA2 to be at a high level; Step 3: Pull INIT_B high for FPGA1 and pull INIT_B low for FPGA2; Step 4: Check if the DONE_0 signal of FPGA1 is high. If yes, proceed to step 5; otherwise, continue the DONE_0 signal level detection in step 4. Step 5: Pull INIT_B low on FPGA1 and pull INIT_B high on FPGA2; Step 6: Check if the DONE_0 signal of FPGA2 is high. If yes, proceed to step 7; otherwise, continue the DONE_0 signal level detection in step 6. Step 7: The dual FPGA system completes startup loading.
2. The power-on loading design method for a dual FPGA system as described in claim 1, characterized in that, In step 1, after power-on, FPGA1 loads first and FPGA2 loads later. Before FPGA1 and FPGA2 load, ensure that no high or low level is input to the external interfaces of SIP1 and SIP2.
3. The power-on loading design method for a dual FPGA system as described in claim 2, characterized in that, In step 2, the PROGRAM signal is the FPGA configuration start control signal, which is active low and is used to trigger the FPGA to load the external configuration file into the internal SRAM.
4. The power-on loading design method for a dual FPGA system as described in claim 3, characterized in that, In step 2, when the PROGRAM signal is pulled low and the timing requirements are met, the FPGA will initialize the configuration interface and complete the configuration function. After the configuration function is completed, the signal will return to a high level.
5. The power-on loading design method for a dual FPGA system as described in claim 4, characterized in that, In step 2, the PROGRAM signals of the two FPGAs are set to 1 to avoid repeated power-on loading of the FPGAs.
6. The power-on loading design method for a dual FPGA system as described in claim 5, characterized in that, In step 3, FPGA1 is loaded first, and FPGA2 is not read from the program. That is, FPGA2's INIT_B is pulled low. When INIT_B is configured to high level, FPGA2 starts reading from the program.
7. The power-on loading design method for a dual FPGA system as described in claim 6, characterized in that, In step 4, FPGA1 is in the loading process. After loading is completed, the DONE_0 signal of FPGA1 is pulled high. The high and low levels of the DONE_0 signal are detected to determine whether FPGA1 has completed loading. If loading is completed, step 5 is executed. If loading is not completed, the detection continues in step 4.
8. The power-on loading design method for a dual FPGA system as described in claim 7, characterized in that, In step 5, FPGA1 has completed loading, and FPGA2 is controlled to read the program. FPGA2's INIT_B is pulled high, while FPGA1's INIT_B is pulled low to ensure that FPGA1 is not loaded.
9. The power-on loading design method for a dual FPGA system as described in claim 8, characterized in that, In step 6, FPGA2 is in the loading process. After loading is completed, the DONE_0 signal of FPGA2 is pulled high. The high and low levels of the DONE_0 signal are detected to determine whether FPGA2 has completed loading. If loading is completed, step 7 is executed. If loading is not completed, the detection continues in step 6.
10. The power-on loading design method for a dual FPGA system as described in claim 9, characterized in that, In step 7, both FPGAs complete the startup loading and run their respective programs, and the external pins of SIP1 and SIP2 are multiplexed.