An interrupt method, device, and storage medium

Abstract

The application discloses an interrupt method, device and storage medium, the interrupt method comprises the following steps: detecting that the current device satisfies an interrupt processing condition, waking up a target interrupt processing thread, and the interrupt processing condition comprises that the current device generates an interrupt request; using the target interrupt processing thread after waking up to execute the following steps: acquiring an interrupt request cumulative quantity associated with the target interrupt processing thread, and acquiring an interrupt execution cumulative quantity of the target interrupt processing thread; in response to the interrupt request cumulative quantity being greater than the interrupt execution cumulative quantity, performing interrupt processing of a to-be-processed interrupt quantity; and in response to the interrupt processing of the to-be-processed interrupt quantity being completed, updating the interrupt execution cumulative quantity to the interrupt request cumulative quantity. Through the above method, the application can prevent interrupt loss.

Description

Technical Field

[0001] This application relates to the field of interrupt handling technology, and in particular to an interrupt method, device, and storage medium. Background Technology

[0002] In modern embedded systems and computer peripheral control, interrupt mechanisms are one of the core means of achieving asynchronous communication between hardware and software. With the development of video acquisition, machine vision, industrial automation, and other fields, the frequency of interrupts generated by hardware devices is increasing, and these interrupts often originate from multiple logical channels, such as the control channels of acquisition cards, camera control channels, and streaming channels. These channels may share the same physical interrupt line, forming a complex scenario of "single interrupt source, multiple events." Against this backdrop, interrupt handling mechanisms face challenges.

[0003] Event loss problem under high frequency interrupts: When multiple interrupts occur in succession within a very short period of time, and the system has not yet completed the processing of the previous interrupt, subsequent interrupts may be ignored or merged, resulting in event omissions and affecting data integrity and system reliability. Summary of the Invention

[0004] The main technical problem addressed by this application is to provide an interruption method, device, and storage medium that can prevent interruption loss.

[0005] To address the aforementioned technical problems, a first aspect of this application provides an interruption method, comprising: detecting that a current device meets interruption handling conditions, waking up a target interruption handling thread, wherein the interruption handling conditions include the current device generating an interrupt request; utilizing the woken-up target interruption handling thread to perform: obtaining a cumulative number of interrupt requests associated with the target interruption handling thread, and obtaining a cumulative number of interrupt executions of the target interruption handling thread; in response to the cumulative number of interrupt requests being greater than the cumulative number of interrupt executions, performing interruption handling for a pending number of interrupts, wherein the pending number of interrupts is the difference between the cumulative number of interrupt requests and the cumulative number of interrupt executions, and the interrupt handling corresponds to the target interruption handling thread; and in response to the completion of the interruption handling for the pending number of interrupts, updating the cumulative number of interrupt executions to the cumulative number of interrupt requests.

[0006] In one embodiment, after updating the cumulative number of interrupt executions to the cumulative number of interrupt requests, the method further includes: detecting whether an end signal exists; terminating the target interrupt handling thread in response to the existence of the end signal; and / or entering a sleep state in response to the absence of the end signal.

[0007] In one embodiment, the interrupt handling condition further includes the sleep duration of the target interrupt handling thread reaching a preset sleep threshold; the method further includes: entering a sleep state in response to the cumulative number of interrupt requests equaling the cumulative number of interrupt executions.

[0008] In one embodiment, the target interrupt handling thread is located in the interrupt handling thread layer, which includes multiple interrupt handling threads that are independent of each other and correspond to different interrupt events.

[0009] In one embodiment, detecting that the current device meets the interrupt handling conditions and waking up the target interrupt handling thread includes: using the interrupt service routine layer to execute: detecting the interrupt request of the current device and obtaining the interrupt flag corresponding to the interrupt request; storing the interrupt flag in the interrupt flag area; generating an interrupt request handling signal and storing the interrupt request handling signal in the task queue; using the delayed procedure call layer to execute: in response to the existence of the interrupt request handling signal in the task queue, obtaining the interrupt flag from the interrupt flag area; generating a wake-up signal corresponding to the interrupt flag, the wake-up signal being used to wake up the target interrupt handling thread.

[0010] In one embodiment, detecting an interrupt request from the current device and obtaining an interrupt flag corresponding to the interrupt request includes: obtaining a first number of interrupt numbers requested by the current device from the system and a second number of interrupt numbers allocated by the system to the current device; in response to a match between the first number of interrupt numbers and the second number of interrupt numbers, obtaining an interrupt number corresponding to the interrupt request and using the interrupt number as the interrupt flag; and / or, in response to a mismatch between the first number of interrupt numbers and the second number of interrupt numbers, obtaining an interrupt number corresponding to the interrupt request; and based on the interrupt number, obtaining an interrupt flag bit of the current device and using the interrupt flag bit as the interrupt flag.

[0011] In one embodiment, obtaining the interrupt flag bit of the current device based on the interrupt number includes: obtaining the interrupt flag bit from the base address register space of the current device based on the interrupt number.

[0012] In one embodiment, if the number of the first interrupt number does not match the number of the second interrupt number, after storing the interrupt flag in the interrupt flag area, the method further includes: generating an interrupt flag clearing instruction to instruct the current device to clear the interrupt state represented by the interrupt flag.

[0013] In one embodiment, the step of obtaining the interrupt flag from the interrupt flag area in response to the presence of the interrupt request processing signal in the task queue includes: obtaining the interrupt number from the interrupt flag area in response to a match between the first interrupt number count and the second interrupt number count; and / or, obtaining the interrupt flag bit from the interrupt flag area in response to a mismatch between the first interrupt number count and the second interrupt number count.

[0014] In one embodiment, generating a wake-up signal corresponding to the interrupt flag includes: sequentially obtaining the bit flag of the target bit in the interrupt flag; in response to the bit flag of the target bit indicating the existence of an interrupt state, determining the interrupt handling thread associated with the target bit as the target interrupt handling thread, and generating a corresponding wake-up signal for the target interrupt handling thread; and updating the bit flag of the target bit to indicate that there is no interrupt state.

[0015] To address the aforementioned technical problems, a second aspect of this application provides an electronic device, including a coupled memory and a processor, wherein the memory stores program instructions and the processor executes the program instructions to implement the aforementioned interrupt method.

[0016] To address the aforementioned technical problems, a third aspect of this application provides a computer-readable storage medium for storing program instructions that can be executed to implement the aforementioned interrupt method.

[0017] The above scheme, by detecting that the current device meets the interrupt handling conditions, wakes up the target interrupt handling thread. The woken-up target interrupt handling thread performs the following: obtains the cumulative number of interrupt requests associated with the target interrupt handling thread and the cumulative number of interrupts executed by the target interrupt handling thread. In response to the cumulative number of interrupt requests being greater than the cumulative number of interrupts executed, it performs interrupt handling for the number of interrupts to be processed, where the number of interrupts to be processed is the difference between the cumulative number of interrupt requests and the cumulative number of interrupts executed. In response to the completion of the interrupt handling for the number of interrupts to be processed, it updates the cumulative number of interrupts executed to the cumulative number of interrupt requests. This achieves alignment between the cumulative number of interrupts executed on the target interrupt handling thread side and the cumulative number of interrupt requests on the current device side, preventing interrupt loss.

[0018] Furthermore, since interrupt handling is performed on the target interrupt handling thread, multiple interrupt handling threads can be used in parallel, thereby improving interrupt handling efficiency.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0021] Figure 1 This is a flowchart illustrating an embodiment of the interruption method of this application; Figure 2 This is a flowchart illustrating another embodiment of the interruption method of this application; Figure 3 This is a flowchart illustrating another embodiment of the interruption method of this application; Figure 4 This is a schematic diagram of the structure of an embodiment of the electronic device of this application; Figure 5 This is a schematic diagram of the structure of an embodiment of the computer-readable storage medium of this application. Detailed Implementation

[0022] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0023] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0024] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "many" in this document means two or more. Moreover, the term "at least one" in this document means any combination of at least two of any one or more of a plurality of objects. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0025] Please see Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the interruption method of this application. Specifically, it may include the following steps: Step S11: If the current device meets the interrupt handling conditions, wake up the target interrupt handling thread.

[0026] The interrupt handling condition includes an interrupt request generated by the current device. The current device can be a data acquisition card, network card, memory, sensor, timer, keyboard, mouse, or other similar devices, or it can be a hardware unit connected to the system that generates an interrupt request. Upon detecting an interrupt request from the current device, the currently executing task is paused, and the target interrupt handling thread is awakened.

[0027] For example, to improve interrupt handling efficiency, the target interrupt handling thread resides in the interrupt handling thread layer. This layer comprises multiple independent interrupt handling threads, each corresponding to a different interrupt event and executing its own interrupt handling logic. For instance, interrupt events such as "Acquisition card control channel data transmission completed" and "Camera control channel data transmission completed" correspond to separate interrupt handling threads. The thread corresponding to the "Acquisition card control channel data transmission completed" event executes the "Acquisition card control channel data completion logic," which is a specific business process related to the device. After executing its corresponding interrupt handling logic, the target interrupt handling thread can enter a sleep state or wait to be woken up. When multiple interrupt requests occur simultaneously, multiple corresponding target interrupt handling threads can be woken up to synchronously execute interrupt handling, thus improving interrupt handling efficiency.

[0028] For example, to prevent interrupt loss, the interrupt handling condition also includes the target interrupt handling thread's sleep duration reaching a preset sleep threshold. A specified time period can be specified; if the target interrupt handling thread remains in a sleep state for longer than the specified time period, the target interrupt handling thread is woken up. A second check is then performed to see if any interrupt events need to be handled, preventing interrupt loss.

[0029] Execute using the target interrupt handling thread after it is woken up: Step S12: Obtain the cumulative number of interrupt requests associated with the target interrupt handling thread, and obtain the cumulative number of interrupts executed by the target interrupt handling thread.

[0030] For example, the cumulative number of interrupt requests associated with the target interrupt handling thread is obtained from the current device. Since the most recent reset, the current device records the cumulative number of interrupt requests for different interrupt handling threads. The cumulative number of interrupts executed by the target interrupt handling thread is obtained from internal storage, which records the cumulative number of interrupts executed by different interrupt handling threads. Due to the asynchronicity of interrupt requests and interrupt handling, the cumulative number of interrupt requests and the cumulative number of interrupts executed may differ, indicating that an interrupt request needs to be processed.

[0031] Step S13: In response to the cumulative number of interrupt requests exceeding the cumulative number of interrupts executed, perform interrupt handling for the number of pending interrupts.

[0032] The number of interrupts to be processed is the difference between the cumulative number of interrupt requests and the cumulative number of interrupts executed. Interrupt processing corresponds to the target interrupt processing thread.

[0033] For example, the interrupt handling condition is that when the sleep duration of the target interrupt handling thread reaches a preset sleep threshold, it enters a sleep state in response to the cumulative number of interrupt requests equaling the cumulative number of interrupt executions. When the cumulative number of interrupt requests equals the cumulative number of interrupt executions, it means that there are no interrupt events to be processed at this time, the target interrupt handling thread enters a sleep state, and the sleep duration is reset.

[0034] Step S14: In response to the completion of interrupt handling for the number of pending interrupts, update the cumulative number of interrupt executions to the cumulative number of interrupt requests.

[0035] For example, the cumulative number of interrupt executions is updated to the cumulative number of interrupt requests, and then updated in the internal storage area.

[0036] For example, in order to maintain the state of the interrupt handling thread and improve the efficiency of interrupt handling, the interrupt method in this embodiment further includes: detecting whether there is an end signal; and terminating the target interrupt handling thread in response to the existence of an end signal.

[0037] For example, the target interrupt handling thread is activated after being woken up. After updating the cumulative number of interrupt executions to the cumulative number of interrupt requests, the process further includes: detecting whether there is an end signal; and entering a sleep state in response to the absence of an end signal.

[0038] In the above embodiment, by detecting that the current device meets the interrupt handling conditions, the target interrupt handling thread is woken up. The woken target interrupt handling thread performs the following: obtaining the cumulative number of interrupt requests associated with the target interrupt handling thread and obtaining the cumulative number of interrupt executions of the target interrupt handling thread; and in response to the cumulative number of interrupt requests being greater than the cumulative number of interrupt executions, performing interrupt handling for the number of interrupts to be processed, where the number of interrupts to be processed is the difference between the cumulative number of interrupt requests and the cumulative number of interrupt executions; and in response to the completion of the interrupt handling for the number of interrupts to be processed, updating the cumulative number of interrupt executions to the cumulative number of interrupt requests. This achieves alignment between the cumulative number of interrupt executions on the target interrupt handling thread side and the cumulative number of interrupt requests on the current device side, preventing interrupt loss. Since interrupt handling is performed on the target interrupt handling thread, multi-threaded parallel processing can be used, thereby improving interrupt handling efficiency.

[0039] Please see Figure 2 , Figure 2 This is a flowchart illustrating another embodiment of the interruption method of this application. Specifically, to improve interruption processing efficiency, the following steps may be included: Execute using the interrupt service routine layer: Step S21: Detect the interrupt request of the current device and obtain the interrupt flag corresponding to the interrupt request.

[0040] For example, the system obtains the number of first interrupt numbers requested by the current device and the number of second interrupt numbers allocated by the system to the current device. In response to a match between the first and second interrupt numbers, the system obtains the interrupt number corresponding to the interrupt request, using this interrupt number as an interrupt marker. When the current device requests the allocation of the first number of interrupt numbers (representing the number of interrupt events), and the system's actual number of interrupt resources is the same as the current device's second number of interrupt numbers (e.g., the device requests 8 interrupt numbers, and the system actually allocates 8 interrupt numbers), an association between the interrupt number and the interrupt event can be established, allowing the system to identify which interrupt event initiated the interrupt request from the interrupt number. When the two numbers are different (e.g., the device requests 8 interrupt numbers, and the system actually allocates 5 interrupt numbers), meaning the number of interrupt numbers actually allocated by the system cannot match every interrupt event, the interrupt number indicates that the current device initiated an interrupt request, and the specific interrupt event can be obtained from the current device.

[0041] For example, in response to a mismatch between the number of first interrupt numbers and the number of second interrupt numbers, the interrupt number corresponding to the interrupt request is obtained; based on the interrupt number, the interrupt flag bit of the current device is obtained, and the interrupt flag bit is used as the interrupt flag.

[0042] For example, the interrupt flag bit can be obtained from the current device's base address register space. The base address register (BAR) is located in the PCI (Peripheral Component Interconnect) / PCIe (Peripheral Component Interconnect Express) device configuration space and is used to map device registers to memory or I / O (Input / Output) address space for driver reading and writing. The interrupt flag bit is a hardware-set bit used to identify the occurrence of a specific interrupt event; it is typically a 32-bit register located in the device's BAR space.

[0043] Step S22: Store the interrupt flag in the interrupt flag area.

[0044] For example, in response to a match between the first number of interrupt numbers and the second number of interrupt numbers, the interrupt number corresponding to the interrupt request is obtained, and the interrupt number is used as an interrupt marker and stored in the interrupt marker area. The interrupt marker area can be a storage area reserved for interrupt numbers. For example, the currently processed interrupt number is recorded bit by bit into a specified 32-bit memory through atomic operations. For example, for interrupt records with interrupt numbers 0 and 3, the values ​​of bits 0 and 3 are 1 (e.g., 1 indicates that an interrupt state exists, and 0 indicates that an interrupt state does not exist).

[0045] For example, in response to a mismatch between the number of first interrupt numbers and the number of second interrupt numbers, the interrupt number corresponding to the interrupt request is obtained, and based on the interrupt number, the interrupt flag bit of the current device is obtained. This interrupt flag bit is used as the interrupt marker and stored in the interrupt flag area. The interrupt flag area can be a storage area reserved for the interrupt flag bit, different from the storage area reserved for the interrupt numbers. For example, the read interrupt flag bit can be saved as is in a non-paged memory block. An interrupt flag clearing instruction can also be generated to instruct the current device to clear the interrupt status represented by the interrupt flag bit, allowing the device to trigger the interrupt again. When the number of first interrupt numbers and the number of second interrupt numbers do not match, the current device knows that after sending an interrupt request, there will be a subsequent action to obtain the interrupt flag bit from the current device. Upon receiving the interrupt flag clearing instruction, it knows that the acquisition of the interrupt flag bit has ended and can trigger the interrupt again.

[0046] Step S23: Generate an interrupt request handling signal and store the interrupt request handling signal in the task queue.

[0047] For example, an interrupt request processing signal can be passed to the delayed procedure call layer through program calls, parameter passing, etc. The interrupt request processing signal may include information such as the current device status and address.

[0048] Execution using the delayed procedure call layer: Step S24: In response to the presence of an interrupt request processing signal in the task queue, obtain the interrupt flag from the interrupt flag area.

[0049] For example, in response to a match between the first number of interrupt numbers and the second number of interrupt numbers, an interrupt number is obtained from the interrupt flag area.

[0050] For example, in response to a mismatch between the number of first interrupt numbers and the number of second interrupt numbers, interrupt flag bits are obtained from the interrupt flag area.

[0051] Step S25: Generate a wake-up signal corresponding to the interrupt flag. The wake-up signal is used to wake up the target interrupt handling thread.

[0052] For example, the bit flag of the target bit in the interrupt flag can be obtained sequentially. In response to the bit flag of the target bit indicating the existence of an interrupt state, the interrupt handling thread associated with the target bit is determined as the target interrupt handling thread, and a corresponding wake-up signal is generated for the target interrupt handling thread. After the wake-up signal is generated, the bit flag of the target bit is updated to indicate that there is no interrupt state.

[0053] Execute using the target interrupt handling thread after it is woken up: Step S26: Obtain the cumulative number of interrupt requests associated with the target interrupt handling thread, and obtain the cumulative number of interrupts executed by the target interrupt handling thread. Refer to step S12, which will not be repeated here.

[0054] Step S27: In response to the cumulative number of interrupt requests exceeding the cumulative number of interrupts executed, interrupt handling for the pending interrupt count is performed. Refer to step S13; details are omitted here.

[0055] Step S28: In response to the completion of interrupt handling for the number of pending interrupts, update the cumulative number of interrupt executions to the cumulative number of interrupt requests. Refer to step S14, which will not be repeated here.

[0056] In the above embodiment, by detecting that the current device meets the interrupt handling conditions, the target interrupt handling thread is awakened. The awakened target interrupt handling thread then performs the following: obtaining the cumulative number of interrupt requests associated with the target interrupt handling thread, and obtaining the cumulative number of interrupt executions of the target interrupt handling thread. In response to the cumulative number of interrupt requests being greater than the cumulative number of interrupt executions, interrupt handling is performed for the number of pending interrupts, where the number of pending interrupts is the difference between the cumulative number of interrupt requests and the cumulative number of interrupt executions. Upon completion of the interrupt handling for the number of pending interrupts, the cumulative number of interrupt executions is updated to the cumulative number of interrupt requests. This aligns the cumulative number of interrupt executions on the target interrupt handling thread side with the cumulative number of interrupt requests on the current device side, preventing interrupt loss. Since interrupt handling is performed on the target interrupt handling thread, multi-threaded parallel processing can be used, thereby improving interrupt handling efficiency. By utilizing the interrupt service routine layer and the delayed procedure call layer to handle short-duration tasks, and by utilizing multiple interrupt handling threads in the interrupt handling thread layer to handle batch interrupt tasks, interrupt handling efficiency and stability are improved.

[0057] Please see Figure 3 , Figure 3 This is a flowchart illustrating another embodiment of the interruption method of this application. The interruption method in this embodiment is executed sequentially by the Interrupt Service Routine (ISR) layer, the Delayed Procedure Call (DPC) dispatch layer, and the interrupt handling thread layer.

[0058] The Interrupt Service Routine (ISR) layer's processing logic includes: when a hardware device triggers an interrupt, the CPU jumps to the corresponding ISR entry point. The ISR process first executes single / multiple interrupt handling logic based on whether the current number of interrupts meets the requirements. If the actual number of valid interrupts allocated by the system matches the device's requirements, it is recorded as "interrupt count meets requirements"; otherwise, it is recorded as "interrupt count does not meet requirements." For example, if the device expects 8 interrupts, but the system actually allocates less than 8, then the interrupt count is considered insufficient.

[0059] The single interrupt handling logic (where the number of interrupts does not meet the requirements) at the Interrupt Service Routine (ISR) layer includes: Read interrupt flag: Based on the current interrupt number, read a 32-bit unsigned integer from register A in the BAR space of the acquisition card device. Each bit of this data represents a specific interrupt event source (acquisition card control channel, camera control / stream channel). This data is defined as the interrupt flag.

[0060] Record state: Save the read interrupt flag bit as is to a non-paged memory block allocated by the driver as a snapshot of the hardware state.

[0061] Clear hardware interrupt: Write 0 to register A in the BAR space to clear the interrupt status flag on the hardware side, allowing the device to trigger the interrupt again.

[0062] Request DPC: Call the operating system API to queue the interrupt request for further processing via DPC.

[0063] End ISR: Complete the top half of the interrupt handling.

[0064] The multi-interrupt handling logic (interrupt count meets requirements) at the Interrupt Service Routine (ISR) layer includes: Record interrupt number: Record the currently processed interrupt number bit by bit into the 32-bit memory specified by the driver through atomic operations. For example, the decimal value of the interrupt record for interrupt numbers 0 and 3 is 9 (binary number 1001, with bits 0 and 3 having a value of 1).

[0065] Request DPC: Call the operating system API (Application Programming Interface) to queue the interrupt request for further processing via DPC.

[0066] End ISR: Complete the upper half of the interrupt processing.

[0067] The processing logic of the Delayed Procedure Call (DPC) dispatch layer includes: DPC executes slightly after ISR, but still within the interrupt context (lower priority than ISR), and is responsible for dispatching interrupt events to specific worker threads. DPC first executes single / multiple interrupt handling logic based on whether the current number of valid interrupts can meet business needs; this handling logic corresponds to the handling logic in ISR.

[0068] The single interrupt handling logic of the Delayed Procedure Call (DPC) dispatch layer (corresponding to the single interrupt case in the ISR) includes: Read interrupt flag: Read the interrupt flag saved from the ISR in memory.

[0069] Traversal and Dispatch: Each bit of the interrupt flag is checked sequentially. When a bit is 1, it indicates that the specific event corresponding to that bit (such as "data transmission completed in the acquisition card control channel," "data transmission completed in the camera control channel," "data transmission completed in the camera stream channel," etc.) needs to be processed. The control channel or stream channel interrupt handling thread pre-bound to that flag is then woken up, and the bit is written to 0. The traversal is complete when the interrupt flag is 0.

[0070] End DPC: The DPC logic ends after the traversal is complete.

[0071] The multi-interrupt handling logic of the Delayed Procedure Call (DPC) dispatch layer (corresponding to the multi-interrupt case in the ISR) includes: Read Interrupt Number: Read the interrupt number recorded in the ISR from memory.

[0072] Traversal and Dispatch: Based on the interrupt numbers recorded in memory, the interrupt numbers are traversed bit by bit. When a certain bit is 1, it indicates that the specific event corresponding to that interrupt number (such as "data transmission of the acquisition card control channel has ended", "data transmission of the camera control channel has ended", "data transmission of the camera stream channel has ended", etc.) needs to be processed. Then, the control channel or stream channel interrupt handling thread pre-bound to that flag bit is woken up, and that bit is written to 0.

[0073] End DPC: After wake-up is complete, the DPC logic ends.

[0074] The interrupt handling thread layer's processing logic includes: each control channel or flow channel has its own independent interrupt handling thread. The main body of this thread is a loop, waiting to be woken up by a DPC or by a timeout.

[0075] The loop logic includes: Wake-up and Read: After a thread is woken up, it reads a 32-bit unsigned integer from the device's BAR space. This data is a hardware-maintained interrupt count, representing the total number of interrupts that have occurred since the device was reset.

[0076] Calculate the number of pending events: Obtain a 32-bit unsigned integer record from the driver software, representing the current number of processed interrupts. Calculate the difference: Difference = Interrupt count - Current number of processed interrupts. This difference represents the number of new hardware-generated interrupts that have not yet been processed by the software since the last thread processing.

[0077] Judgment and processing: If the difference is 0: it means that this wake-up may be due to other reasons (such as timeout), and no new hardware interrupt event has arrived, so the business processing logic is skipped. If the difference is not 0, it means that there is a new interrupt to be processed.

[0078] Among them, the new interrupts to be processed include: The interrupt handling logic for the number of times the difference is executed in a loop (this logic is a specific business process related to the device, such as the data completion logic of the acquisition card control channel, the data completion logic of the camera control channel, the data completion logic of the camera stream channel, etc.).

[0079] After all the difference processing is completed, the number of currently processed interrupts inside the driver is updated to the interrupt count value read from the hardware, thereby achieving software and hardware state synchronization.

[0080] Loop Check: After completing the wake-up and read operations, calculating the number of pending events, and checking and processing, the thread checks if it has received a termination signal. If the thread has not terminated, it enters the waiting state again, waiting to be woken up by the DPC or timed out, and continues to execute the wake-up and read operations, calculating the number of pending events, checking and processing, and loop check steps. If the thread should terminate, it exits the loop and the thread terminates.

[0081] The above scheme, by detecting that the current device meets the interrupt handling conditions, wakes up the target interrupt handling thread. The woken target interrupt handling thread then performs the following: obtains the cumulative number of interrupt requests associated with the target interrupt handling thread, and obtains the cumulative number of interrupt executions of the target interrupt handling thread. If the cumulative number of interrupt requests is greater than the cumulative number of interrupt executions, it performs interrupt handling for the number of pending interrupts, where the number of pending interrupts is the difference between the cumulative number of interrupt requests and the cumulative number of interrupt executions. Upon completion of the interrupt handling for the number of pending interrupts, it updates the cumulative number of interrupt executions to the cumulative number of interrupt requests. This aligns the cumulative number of interrupt executions on the target interrupt handling thread side with the cumulative number of interrupt requests on the current device side, preventing interrupt loss and avoiding interrupt event loss due to interrupt density in high-frequency interrupt scenarios. Since interrupt handling is performed on the target interrupt handling thread, it can be processed in parallel by multiple threads, and the thread's IRQL (Interrupt Request) is consistent. The interrupt request level (IRQL) is relatively low, resulting in strong scalability (ISR and DPC operate at high IRQL levels, limiting the range of APIs they can call—for example, they cannot access paged memory or perform blocking operations; in comparison, threads have strong scalability), thus improving interrupt handling efficiency. A complete interrupt handling architecture is provided, including ISR (recording flags / interrupt numbers), DPC (resolving flags / interrupt numbers and waking up threads), threads (waiting to be woken up), and batch processing (counting difference loop). Under a single interrupt source, the decoupling and parallelization of multiple operation logics enables parallel and decoupled processing of multiple different types of interrupt events from the same interrupt source, fully utilizing the parallel computing capabilities of multi-core CPUs. This embodiment uses independent threads corresponding to interrupt flags to achieve decoupling and parallel processing of multiple operation logics corresponding to a single interrupt source. Compared to existing technologies that place related logic in DPC, this approach offers stronger scalability. The processing in the ISR and DPC in this embodiment is relatively simple, containing no specific business logic, and has extremely short processing time, solving the system anomaly problem caused by long interrupt processing times and increasing system stability. It allows for more flexible implementation of various business logics. In this embodiment, because the interrupt handling thread has a lower IRQL, it can access paged memory, call WDF (Windows Driver Framework) framework interfaces (such as registry read / write operations), which have IRQL restrictions, and can perform blocking operations. If business logic is performed in DPC, blocking and related operations cannot be performed due to the higher interrupt level of DPC.

[0082] Please see Figure 4 , Figure 4This is a schematic diagram of an embodiment of the electronic device of this application. The electronic device 40 includes a memory 41 and a processor 42 coupled together. The memory 41 stores program instructions, and the processor 42 is used to execute the program instructions stored in the memory 41 to implement the steps in any of the above-described interrupt method embodiments. In a specific implementation scenario, the electronic device 40 may include, but is not limited to, a microcomputer or a server. In addition, the electronic device 40 may also include mobile devices such as laptops and tablets, which are not limited here.

[0083] Specifically, processor 42 controls itself and memory 41 to implement the steps in any of the above-described interrupt method embodiments. Processor 42 may also be referred to as a CPU (Central Processing Unit). Processor 42 may be an integrated circuit chip with signal processing capabilities. Processor 42 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). The processor can be a Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. The general-purpose processor can be a microprocessor or any conventional processor. Furthermore, the processor 42 can be implemented using integrated circuit chips.

[0084] Please see Figure 5 , Figure 5 This is a schematic diagram of an embodiment of the computer-readable storage medium of this application. The computer-readable storage medium 50 is used to store program instructions 51, which can be executed to implement the steps in any of the above-described interrupt method embodiments.

[0085] The aforementioned storage media include: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media that can store program code.

[0086] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here. The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods in the various embodiments of this application.

Claims

1. An interruption method, characterized in that, The method includes: If the current device is found to meet the interrupt handling conditions, the target interrupt handling thread is woken up, wherein the interrupt handling conditions include the current device generating an interrupt request; Execute using the target interrupt handling thread after it is woken up: Obtain the cumulative number of interrupt requests associated with the target interrupt handling thread, and obtain the cumulative number of interrupts executed by the target interrupt handling thread; In response to the cumulative number of interrupt requests being greater than the cumulative number of interrupt executions, interrupt handling for the number of pending interrupts is performed, wherein the number of pending interrupts is the difference between the cumulative number of interrupt requests and the cumulative number of interrupt executions, and the interrupt handling corresponds to the target interrupt handling thread; In response to the completion of interrupt handling for the number of pending interrupts, the cumulative number of interrupts executed is updated to the cumulative number of interrupt requests.

2. The method according to claim 1, characterized in that, After updating the cumulative number of interrupt executions to the cumulative number of interrupt requests, the method further includes: Detect whether an end signal is present; In response to the presence of the termination signal, the target interrupt handling thread is terminated; and / or, In response to the absence of the termination signal, it enters a sleep state.

3. The method according to claim 1, characterized in that, The interrupt handling conditions also include the target interrupt handling thread's sleep duration reaching a preset sleep threshold; The method further includes: When the cumulative number of interrupt requests equals the cumulative number of interrupt executions, the system enters a sleep state.

4. The method according to claim 1, characterized in that, The target interrupt handling thread is located in the interrupt handling thread layer, which includes multiple interrupt handling threads. These multiple interrupt handling threads are independent of each other and correspond to different interrupt events.

5. The method according to claim 1, characterized in that, The step of detecting that the current device meets the interrupt handling conditions and waking up the target interrupt handling thread includes: Execute using the interrupt service routine layer: An interrupt request from the current device is detected, and the interrupt flag corresponding to the interrupt request is obtained; Store the interruption flag in the interruption flag area; Generate an interrupt request processing signal and store the interrupt request processing signal in the task queue; Execution using the delayed procedure call layer: In response to the presence of the interrupt request processing signal in the task queue, the interrupt flag is obtained from the interrupt flag area; A wake-up signal corresponding to the interrupt flag is generated, and the wake-up signal is used to wake up the target interrupt handling thread.

6. The method according to claim 5, characterized in that, The step of detecting an interrupt request from the current device and obtaining the interrupt flag corresponding to the interrupt request includes: Obtain the number of first interrupt numbers requested by the current device from the system, and the number of second interrupt numbers allocated by the system to the current device; In response to a match between the first number of interrupt numbers and the second number of interrupt numbers, the interrupt number corresponding to the interrupt request is obtained, and the interrupt number is used as the interrupt marker; and / or, In response to a mismatch between the number of the first interrupt number and the number of the second interrupt number, the interrupt number corresponding to the interrupt request is obtained; based on the interrupt number, the interrupt flag bit of the current device is obtained, and the interrupt flag bit is used as the interrupt flag.

7. The method according to claim 6, characterized in that, The step of obtaining the interrupt flag bit of the current device based on the interrupt number includes: Based on the interrupt number, the interrupt flag bit is obtained from the base address register space of the current device; And / or, If the number of the first interrupt number does not match the number of the second interrupt number, after storing the interrupt flag in the interrupt flag area, the method further includes: Generate an interrupt flag clear instruction to instruct the current device to clear the interrupt status represented by the interrupt flag.

8. The method according to claim 6, characterized in that, The step of retrieving the interrupt flag from the interrupt flag area in response to the presence of the interrupt request processing signal in the task queue includes: In response to a match between the first number of interrupt numbers and the second number of interrupt numbers, the interrupt number is obtained from the interrupt flag region; and / or, In response to a mismatch between the number of the first interrupt number and the number of the second interrupt number, the interrupt flag bit is obtained from the interrupt flag area.

9. The method according to claim 5, characterized in that, The generation of the wake-up signal corresponding to the interrupt flag includes: The target bit in the interrupt flag is obtained sequentially. In response to the target bit indicating the existence of an interrupt state, the interrupt handling thread associated with the target bit is determined as the target interrupt handling thread, and a corresponding wake-up signal is generated for the target interrupt handling thread. Update the bit flag of the target bit to indicate that there is no interruption state.

10. An electronic device, characterized in that, The electronic device includes a coupled memory and a processor, the memory storing program instructions, and the processor executing the program instructions to implement the interrupt method as described in any one of claims 1-9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store program instructions that can be executed to implement the interrupt method as described in any one of claims 1-9.

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