A bank read-write balanced scheduling method based on a multi-stage pipeline, a chip and a network card

Abstract

The application provides a Bank read-write balance scheduling method based on a multi-stage pipeline, a chip and a network card, relates to the technical field of Bank read-write balance scheduling, and the method comprises the following steps: dividing N Banks into three mutually exclusive priority levels of high, medium and low; in the first time cycle of the pipeline, a first-stage selection mask corresponding to each level is generated; in the second time cycle of the pipeline, a multi-stage series selection logic that rejects the selected Bank identifier is used for serial distribution; in the third time cycle of the pipeline, the effective Bank results obtained after series selection of the three levels of high, medium and low are logically aggregated, and the final selection mask corresponding to each priority group is uniformly output; the remaining requirements are sequentially delayed to the next level for arbitration selection; and the application can improve the resource utilization rate of the overall memory bank and the high-concurrency bearing capacity of the system.

Description

Technical Field

[0001] This invention relates to the field of Bank read / write balancing scheduling technology, and in particular to a Bank read / write balancing scheduling method, chip, and network interface card based on multi-stage pipeline. Background Technology

[0002] In the hardware design of multi-core processors or large-capacity storage systems, to improve data concurrency access capabilities, physical storage resources are typically divided into multiple independent banks to support the parallel execution of multiple read and write requests. However, due to the inherent characteristics of physical single-port devices, read and write operations cannot be performed simultaneously within the same bank in the same clock cycle. When multiple sets of concurrent access requests are initiated simultaneously in the system, there is a high probability that multiple read and write requests will hit the same bank at the same time, leading to severe bank conflicts. This physical hardware constraint not only forces multiple accesses to be serialized, causing pipeline stalls and access delays, but also creates the risk of data races.

[0003] Existing conventional techniques for mitigating this problem typically employ static partitioning or multi-round independent polling scheduling. The former results in extremely poor flexibility in Bank resource utilization, easily leading to idle local Banks while other Banks become congested. The latter, lacking a hierarchical mutual exclusion mechanism between concurrent requests, often requires additional comparison control logic to avoid Bank overlap, thus exacerbating the difficulty of hardware timing convergence. Therefore, how to achieve intelligent hierarchical allocation based on the real-time dynamic idle status of each Bank using a multi-level pipeline architecture, while considering the priority allocation of concurrent requests and physical constraint avoidance, to improve the overall resource utilization of the storage and the high-concurrency carrying capacity of the system, is a technical problem that current high-performance scheduling solutions for storage systems urgently need to solve. Summary of the Invention

[0004] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows:

[0005] According to a first aspect of this application, a Bank read / write balanced scheduling method based on a multi-level pipeline is provided, comprising the following steps:

[0006] S100: Based on the real-time free memory depth of each Bank, divide the N Banks into three mutually exclusive priority levels: high, medium, and low; the intersection of any two sets of Bank IDs of different levels is empty, and the union of the sets of Bank IDs of all levels is all N Banks.

[0007] S200 compares the current free memory depth of each Bank with the high, medium and low three-level thresholds pre-configured by the system in the first time cycle of the pipeline, and generates the first-level selection mask corresponding to each priority level based on the comparison results.

[0008] S300, in the second time cycle of the pipeline, for the M parallel write requests that arrive simultaneously in the current batch, based on the first-level selection mask, a multi-level serial selection logic that gradually eliminates the selected Bank identifier is used to perform serial allocation, so that the selected Bank numbers of the M requests in the current batch do not overlap.

[0009] S400, in the third time cycle of the pipeline, logically aggregates the valid Bank results obtained after the high, medium and low levels are selected in series, and outputs the final selection mask corresponding to each priority level. Among them, when performing actual write operation allocation, high level takes precedence over medium level, medium level takes precedence over low level, and the Bank number selected in the current cycle is not physically adjacent to the Bank number selected in the previous cycle.

[0010] S500: When the available Bank resources at the high level are insufficient to meet the needs of the M write requests in the current batch, the remaining requests are sequentially deferred to the medium level for arbitration selection. If the available Bank resources at the medium level are still insufficient to meet the remaining requests, the remaining requests are further deferred to the low level for arbitration selection until all M write requests in the current batch are allocated or all available Bank resources at all levels are exhausted, so as to maintain the overall load balance of Bank resource allocation.

[0011] According to another aspect of this application, a chip is also provided, including an on-chip cache scheduling circuit; the on-chip cache scheduling circuit is used to execute the Bank read-write balanced scheduling method based on multi-stage pipeline as described in the first aspect, so as to arbitrate and allocate read and write access to the physical memory inside the chip.

[0012] According to another aspect of this application, a network interface card (NIC) is also provided, including a high-speed data packet caching module and a cache read / write control circuit connected to the high-speed data packet caching module; the cache read / write control circuit is configured to execute a Bank read / write balanced scheduling method based on multi-stage pipeline as described in the first aspect, so as to allocate and schedule concurrent write requests to multiple physical Banks within the high-speed data packet caching module.

[0013] The present invention has at least the following beneficial effects:

[0014] The Bank read / write balanced scheduling method based on a multi-level pipeline of the present invention firstly divides each Bank into three mutually exclusive priority levels (high, medium, and low) according to its real-time free memory depth, and utilizes the parallel threshold comparison and first-level selection mask generation in the first time step of the pipeline to achieve accurate perception and efficient pre-classification of the system's free storage resources. Secondly, in the second time step of the pipeline, for the M parallel write requests arriving simultaneously, a multi-level serial selection logic that gradually eliminates the selected Bank identifier is used for serial allocation. Starting from the source of physical allocation, it is forcibly ensured that the Bank numbers selected by the M requests in the current processing batch are absolutely unique. This stacking mechanism fundamentally avoids port conflicts and pipeline congestion caused by multiple requests hitting the same Bank. Furthermore, by logically aggregating results at each level through the third time tick of the pipeline, strictly adhering to the principle of prioritizing high-priority requests over medium and low-priority requests, and combining this with the constraint that the current Bank number is not physically adjacent to the previous cycle's Bank number, it effectively balances load balancing and physical layout adaptability. Finally, when faced with high-load conditions where high-priority available Bank resources are insufficient to meet the current batch's demand, it implements a flexible, tiered allocation strategy based on the actual system load by sequentially deferring remaining requests to medium and even low-priority levels for arbitration. This mechanism requires no additional physical fusion logic for resource pools, significantly improving the overall storage's resource utilization under extreme high-concurrency pressure while ensuring physical isolation between levels. It effectively prevents deadlocks caused by the exhaustion of high-priority resources leading to subsequent request backlogs, significantly improving the overall storage's resource utilization and the system's high-concurrency carrying capacity. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A flowchart of a Bank read / write balancing scheduling method based on a multi-stage pipeline provided in an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of the hardware circuit for implementing a Bank read / write balanced scheduling method based on a multi-stage pipeline, as provided in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that, based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Furthermore, this device and / or practice the method can be implemented using other structures and / or functionalities besides one or more of the aspects set forth herein.

[0020] The following will refer to Figure 1 The flowchart shown is a Bank read / write balanced scheduling method based on multi-level pipelines, which introduces a Bank read / write balanced scheduling method based on multi-level pipelines.

[0021] The Bank read / write load balancing scheduling method based on multi-stage pipelines may include the following steps:

[0022] S100: Based on the real-time free memory depth of each Bank, divide the N Banks into three mutually exclusive priority levels: high, medium, and low; the intersection of any two sets of Bank IDs of different levels is empty, and the union of the sets of Bank IDs of all levels is all N Banks.

[0023] In this embodiment, before scheduling and allocation begin, the status of all physical banks in the system is first checked. Since the write load of each bank is dynamically changing, its remaining free depth also fluctuates in real time. This step dynamically divides each bank into three completely mutually exclusive priority levels: high, medium, and low, by obtaining the free memory depth of each bank in real time. This division mechanism breaks the static physical isolation, making the bank resources of the entire storage system like a "tiered resource pool" dynamically combined according to free rate. When a bank is full, it can be promptly downgraded to a lower priority; and once free space is released, it can be upgraded again. The high, medium, and low priority levels directly determine the order in which they acquire write request service rights, which is the primary foundation for achieving overall load balancing.

[0024] Furthermore, in step S100, the value of N is 16; the number of Banks at the high, medium, and low levels is dynamically adjusted according to the proportion of memory space used.

[0025] In this embodiment, the total number of storage banks in the system is N=16 (i.e., there are 16 physical banks numbered from 0 to 15). To support the dynamic partitioning in step S100, a "level allocation configuration register group" is pre-configured inside the hardware circuit or microcontroller. This register group stores the memory usage percentage thresholds used to trigger level switching (e.g., a high-level downgrade threshold corresponds to 10% memory usage, a medium-level allocation threshold corresponds to 40% memory usage, and a low-level allocation threshold corresponds to 70% memory usage). Simultaneously, the system has a global "free space depth statistics module" that summarizes the total used space and total free space of the 16 banks in real time, thereby calculating the overall memory usage percentage of the entire storage system.

[0026] When the overall system memory usage changes, the hardware state machine or control logic polls the configuration registers in real time to dynamically update the Bank quantity configuration corresponding to the high, medium, and low levels. This "proportional allocation" is not random, but is automatically locked by an internal "level mapping selector" based on the level value to a specific Bank physical number.

[0027] The specific adjustment logic is as follows (taking a percentage threshold as an example):

[0028] Initial state (usage rate <10%): The system identifies this as a low-load period. The mapping selector marks all 16 banks' level attributes as "high level" (high=16, medium=0, low=0).

[0029] Light load (10% ≤ usage rate < 40%): The system determines that it has entered a medium load period. The logic allocates some banks from the 16 banks (e.g., high = 8, medium = 8, low = 0) to ensure that the remaining high-level banks meet the high-frequency write requirements.

[0030] Medium to high load (40% ≤ usage rate < 70%): The system determines that it has entered a high load period. The selector will further reduce the number of high-level channels and open low-level channels (e.g., high = 4, medium = 8, low = 4).

[0031] Deep high load (usage ratio ≥70%): The system determines that it has entered the full load period. The selector will ensure that at least 1 to 2 banks with a very low number of "high-level" banks are reserved for real-time response, and the rest are all placed in medium and low-level banks (e.g., high=2, medium=6, low=8).

[0032] To ensure absolute isolation of physical banks between different levels, the control logic employs a "mutually exclusive bitmap mapping" mechanism when adjusting levels. Each time the number of banks in each level is updated, a "level-physical bank index mapping table" is updated synchronously. Once a bank is classified as "medium level" in the mapping table, it no longer participates in the arbitration mask calculation for "higher levels," thus ensuring that the sets of level numbers are disjoint and that the union of all banks is always 16.

[0033] For example, suppose the load on the 16 banks is highly uneven. Banks 0 to 7 are fully written (with almost zero free depth), while banks 8 to 15 are only half occupied. At this point, the global memory usage is 45% (between 40% and 70%). Based on the logic of this step, the system dynamically classifies banks 0-3 as high-priority, banks 4-11 as medium-priority, and banks 12-15 as low-priority. When a sudden surge of high-priority write requests occurs, although banks 0-7 are blocked, the system, by dynamically reducing the number of high-priority banks, directly allocates the high-priority requests to banks within banks 0-3 that still have space. This avoids the deadlock phenomenon of "no bank available for high-priority requests" caused by fixed bank partitioning.

[0034] This step enables physical storage resources to function like a dynamic resource pool, elastically expanding and contracting as the overall system load increases or decreases. It ensures that high-priority requests always have a smooth physical channel under various extreme scenarios (avoiding the risk of high-priority requests crashing due to resource exhaustion), while also preventing low-priority requests from being in a state of prolonged "starvation." This significantly improves the stability of the hardware storage system and the overall utilization of physical resources under sudden surges in traffic from multiple services.

[0035] Furthermore, in this embodiment, the overall hardware circuit architecture is as follows: Figure 2 As shown, the main body of this hardware circuit consists of 16 physical memory banks (Bank0~Bank15), three sets of parallel idle depth comparators, a multi-stage serial polling arbitration micropipeline, and a logic aggregation output module. The core objective of the circuit is to resolve concurrent access conflicts of a single-port physical bank and to achieve hierarchical scheduling of data flow through three parallel "high, medium, and low" priority channels.

[0036] Pipeline first time step (t0): Parallel comparison and premask generation

[0037] In the first time step (t0) of the hardware pipeline, the circuit primarily performs the "raw screening" of the basic states of the 16 banks. At the input, each of the 16 banks outputs its own idle depth count signal from _0 to _15 in real time. These signals are simultaneously fed into three parallel modules: a high-level idle depth comparator, a medium-level idle depth comparator, and a low-level idle depth comparator. Simultaneously, these three comparators also receive pre-configured system parameters: high-level idle depth configuration, medium-level idle depth configuration, low-level idle depth configuration, and write bank bitmasks (used to carry additional constraints such as physical adjacency constraints).

[0038] Within the same clock cycle, the comparator performs fully parallel logic comparisons. After the comparison is completed, it generates three preliminary results: high, medium, and low Bank bit masks. These results are then fed into the pre-generated Bank mask module for initial cleaning. Finally, at clock cycle t0, the pre-generated Bank bit masks (high, medium, and low) are output to the next level as the first-level 16-bit first-stage selection masks.

[0039] Second time cycle (t1) of the pipeline: serial polling arbitration and dynamic feedback shielding

[0040] Entering the second time tick (t1), firstly, the three sets of first-level selection masks from t0 are synchronized across ticks via their respective D flip-flops. After synchronization, the high, medium, and low-level masks enter three identical cascaded micropipelines. Figure 2 For example, the "high-level" path at the top of the middle:

[0041] First-level selection: The 16-bit first-level mask is first input to the polling arbitrator _0. This arbitrator selects the first valid Bank number in the current processing batch from the 16-bit mask.

[0042] First round of mask stripping: After arbiter _0 selects the Bank number, it immediately passes it to the adjacent mask processing module. This module sets all valid bits in the current bitmap except for the selected Bank number to zero, stripping out a single-bit mask containing only the selected Bank number.

[0043] The second and third levels of serial selection: The stripped single-bit mask is directly passed to the next level polling arbitrator_1. Arbitrator_1 selects a new bank number from the remaining valid candidate banks and sends it to the second mask processing module for the same stripping and elimination process. Finally, the stripping result is passed to polling arbitrator_2 to complete the final serial selection.

[0044] Key feedback loops: such as Figure 2As shown, the feedback signal of the mask processing module is connected to the previous-level polling arbitrators _0 and _1. This hardware loop enables dynamic state updates, ensuring that when the subsequent arbitrator selects a new Bank, the state of the previous arbitrator is locked accordingly. This makes the multi-level cascaded selection behave like a pipeline, forcibly ensuring that the Bank numbers selected by the M requests in this batch are absolutely non-overlapping.

[0045] Third time step (t2) of the pipeline: Logic aggregation and final time step output

[0046] Entering the third time cycle (t2), the circuit enters the final stage of arbitration result determination and output. In cycle t1, the high, medium, and low-frequency micropipelines each output their own arbitration results. These results are then merged into the OR logic aggregation module on the right side in cycle t2. Figure 2 The symbol with a forward slash and "16" indicates that this module is a 16-bit wide data bus aggregation / combinatorial logic unit. This aggregation module combines the arbitration results of the three levels in an orderly manner according to a preset high, medium, and low priority strategy (high priority takes precedence over medium and low priority).

[0047] To meet the stringent timing requirements of the subsequent write control circuit, the aggregated 16-bit final result is not output immediately. Instead, it is synchronized across cycles by passing through a series-connected D flip-flop at the end. Finally, at the end of cycle t2, the hardware circuit stably outputs 16-bit final selection masks (i.e., indicators of the Bank number actually assigned to the current cycle's write operation) corresponding to high, medium, and low priorities, for the back-end write control circuit to perform the physical write operation.

[0048] Furthermore, the first, second, and third time cycles are synchronized by data timing registers set on each pipeline node. The selection mask and allocation status output by the previous time cycle are stably transmitted to the next processing circuit on the next rising edge of the clock, forming a closed-loop three-stage hardware pipeline structure.

[0049] In this embodiment, the three-stage hardware pipeline relies on a timing synchronization network composed of synchronous clock registers (D flip-flops, D-FF). The entire circuit operates under the same global clock signal (CLK). The "D flip-flop" blocks connecting the various main functional modules in the circuit diagram correspond to standard edge-triggered D flip-flops at the physical hardware level (i.e., when the clock signal CLK is at the rising edge, the data at the input terminal D is instantaneously latched to the output terminal Q and remains stable throughout the entire clock cycle until the next rising edge arrives).

[0050] During hardware signal transmission, combinational logic circuits (such as comparators, pre-generated mask modules, polling arbiters, mask processing modules, etc.) will generate a certain signal transmission delay. To ensure that data does not cause timing conflicts (i.e., hardware race hazards) between pipeline stages due to "excessive signal transmission speed" or "inconsistent arrival times," in this embodiment, D flip-flops are forcibly inserted at the boundary of adjacent pipeline cycles.

[0051] The transition from t0 to t1: In the first time step (t0), the three results of the "pre-generated Bank bit mask_high / medium / low" calculated by the pre-generated Bank bit mask module are fed into the D flip-flop connected in series to its right. When the rising edge of the clock arrives, the output of t0 is completely "frozen" and entered into the t1 step, ensuring that the polling arbiter_0 in the t1 step can obtain completely stable input data before the start of the next cycle.

[0052] The transition from clock cycle t1 to t2: Similarly, the result of multi-level cascade arbitration and OR logic aggregation completed in clock cycle t1 is fed into the final D flip-flop. Only when the next rising edge of the clock arrives is the aggregation result of t1 officially released to the next stage, outputting the final "Bank bitmask_high / medium / low". This D flip-flop ensures that the back-end write execution circuitry does not generate erroneous signal sampling due to the combinational logic delay of t1.

[0053] The mask processing module in stage t1 has feedback connections, which are respectively connected back to the preceding polling arbitrators _0 and _1. To ensure stable and reliable state feedback, a D flip-flop is also set up inside the feedback path for multi-cycle synchronization. Its hardware logic is as follows: when the mask processing module selects a Bank number and generates a single-bit mask, the result will pass through the D flip-flop on the feedback path and update the state register of the preceding polling arbitrator on the next rising edge of the clock, thereby realizing a continuous closed-loop arbitration state of "after selecting a Bank this time, the arbitration pointer is automatically adjusted in the next cycle and the Bank is no longer selected".

[0054] Through the aforementioned three-stage closed-loop hardware pipeline structure composed of cascaded synchronous clock registers, this invention offers significant engineering value. Its beneficial effects are as follows: First, the clock registers decompose the originally large and complex cross-comparison, multi-level arbitration, and logic aggregation operations into three independent clock cycles, greatly shortening the delay depth of a single combinational logic path, enabling the entire arbitration circuit to operate at extremely high system clock frequencies. Second, the forced pacing between pipeline cycles completely eliminates the metastable competition risk caused by the parallel propagation of multiple signals, ensuring the absolute stability and reliability of the final Bank selection mask output to the back-end write controller. Finally, the internal feedback D flip-flops enable the polling arbitrator within cycle t1 to accurately store the state of "current batch allocated Banks," supporting high-speed concurrent batch processing requests with extremely high timing margins, significantly reducing the timing convergence difficulty in the manufacturing process, and possessing strong feasibility for mass production.

[0055] S200 compares the current free memory depth of each Bank with the pre-configured high, medium, and low thresholds in the first time step of the pipeline, and generates the first-level selection mask corresponding to each priority level based on the comparison results.

[0056] In the first time step (t0) of the hardware circuit pipeline in this embodiment, it mainly relies on three sets of fully parallel hardware comparator arrays (i.e., the high / medium / low level idle depth comparators on the left side of the figure) and the pre-generated Bank mask module that follows.

[0057] In terms of physical circuit implementation, 16 banks output their respective free depth count signals (fbm_free_cnt_0 to fbm_free_cnt_15) based on memory usage in real time. These 16 signals are divided into three paths at the same time using a parallel bus wiring method and sent to the high, medium and low comparator arrays respectively.

[0058] The parallel threshold comparison logic is as follows:

[0059] Input parameters: In addition to the 16 Bank idle depth signals, each comparator array also synchronously receives the system's preset threshold configuration signals: high-level idle depth configuration, medium-level idle depth configuration, and low-level idle depth configuration.

[0060] Specific comparison operation: These three comparators perform 16 simultaneous comparisons in full parallel within one clock cycle. For example, the high-level idle depth comparator compares the current idle depth of each Bank from Bank0 to Bank15 with the high-level configuration value. If the real-time idle depth of a Bank is greater than or equal to the high-level configuration value, the output of the comparator corresponding to that Bank is set to a valid "1"; otherwise, it is set to "0".

[0061] The preliminary result directly output by the comparator is Figure 2 The comparison results in the Bank bitmask (high / medium / low). However, this is not the final first-level mask; it is directly input into a tightly coupled pre-generated Bank mask module for physical constraint preprocessing. In this module, the comparison results are combined with a special input signal—the write Bank bitmask—through combinational logic. This signal carries the physical masking information that "the current Bank number must not be adjacent to the previous period's Bank number."

[0062] The pre-generated Bank mask module performs an AND operation between the comparator result and the write Bank bit mask, directly clearing the Bank bits that are forcibly "prohibited" by physical adjacency constraints to zero in advance at clock t0.

[0063] After this combinational logic cleanup, the module outputs a fully usable pre-generated Bank bitmask (high / medium / low) at the end of the t0 clock cycle, which is the first-level selection mask. These three bits are registered by the D flip-flops at the end of the t0 clock cycle to synchronize with the next clock cycle.

[0064] For example: Suppose at a certain moment, Bank5 has an idle depth of 80%, Bank9 has an idle depth of 30%, and Bank12 has an idle depth of 5%. The system's preset high-level threshold is 50%, medium-level threshold is 20%, and low-level threshold is 5%. In cycle t0:

[0065] Higher-level comparator judgment: Bank5 (80%>50%) -> set to 1; Bank9 (30%<50%) and Bank12 (5%<50%) -> set to 0.

[0066] The intermediate level comparator determines the following: Bank9 (30%>20%) -> set to 1; Bank5 is not affected by the intermediate comparator because it has already been classified as a high level; Bank12 (5%<20%) -> set to 0.

[0067] Low-level comparator judgment: Bank12 (5%≥5%) -> set to 1.

[0068] Then, the pre-generated Bank mask module is entered: assuming that Bank4 was just written in the previous cycle, Bank3, Bank4, and Bank5 are prohibited according to the "physical non-adjacent constraint".

[0069] The pre-generation logic takes effect immediately: the high-level result (including Bank5) obtained by the comparator is cleaned with the write Bank bitmask. Bank5 is forcibly cleared to zero due to adjacency constraints.

[0070] The final first-level selection mask output at clock t0 is as follows: only other valid banks are retained in the higher-level mask; Bank 9 is entered into the medium-level mask; and Bank 12 is entered into the lower-level mask. These three sets of masks are registered in clock t1 for use by the arbitrator.

[0071] In this embodiment, by operating three sets of fully hardware parallel comparators simultaneously, the system can complete the noise floor scan of all 16 Bank idle states within a very short first clock cycle, significantly improving the initial response speed for handling concurrent requests and avoiding the huge time overhead caused by software polling. Secondly, when generating the first-level mask, the constraint of writing the Bank bit mask is directly introduced for hardware-level preprocessing, filtering out stringent back-end constraints such as physical adjacency in advance at the t0 cycle. This prevents invalid or non-compliant Banks from entering the subsequent complex arbitration chain, significantly reducing the combinational logic burden of the polling arbiter and mask processing module in the second cycle (t1) of the pipeline. In addition, the data pausing D flip-flops at the end of the t0 cycle also effectively isolate the combinational logic delay of the long chain comparators, ensuring that no matter how the input signals of the 16 Banks change, the first-level selection mask output to the next stage always maintains a highly stable synchronization timing, laying a solid physical foundation for the high-frequency arbitration operation in the back end.

[0072] In S300, during the second time cycle of the pipeline, for the M parallel write requests that arrive simultaneously in the current batch, based on the first-level selection mask, a multi-level serial selection logic is used to sequentially allocate the requests by gradually eliminating the selected Bank identifiers, so that the selected Bank numbers of the M requests in the current batch do not overlap.

[0073] Upon entering the second cycle (t1) of the pipeline, a batch processing task is encountered: M parallel write requests arrive simultaneously. Because the same single-port physical bank cannot be selected by two requests at the same time, the S300 undertakes the task of precise "flow splitting." It employs a "multi-level serial selection logic" for serial processing: the first request selects a bank, and after selection, subsequent processing logic immediately "removes" the selected bank number from the current valid mask. Then, when the second request makes its selection, the previously selected bank is no longer in its field of view. This "select one, remove one" step-by-step stripping mechanism ensures from the allocation source that the bank numbers selected by the M requests in this batch are absolutely non-overlapping, completely preventing hardware conflicts caused by overlapping bank numbers.

[0074] Furthermore, the hardware implementation of the multi-level serial selection logic in step S300 is as follows: it is executed through a hardware micropipeline consisting of an M-level RR polling arbitration unit and an M-level mask processing unit connected in an alternating series configuration; the multi-level serial selection logic includes:

[0075] Each level of RR polling arbitration unit receives the current valid mask bitmap and selects a valid Bank number from it. Then, the corresponding adjacent mask processing unit sets all other valid bits in the current valid mask except for the bit corresponding to the selected Bank number to an invalid mask state, thereby generating a new single-bit mask that only retains the selected Bank number. This new single-bit mask is then directly passed as input to the next level of RR polling arbitration unit.

[0076] In this embodiment, during the second time cycle (t1) of the pipeline, the pre-generated masks of high, medium, and low levels enter their respective independent arbitration channels. Taking the high-level channel at the top of the diagram as an example, this channel is not a single polling arbitration, but rather a micropipeline composed of three-level RR polling arbitration units and three-level mask processing units connected in series with hardwired connections in an alternating manner. This series structure does not rely on an additional central controller, but rather on the sequential recursion of physical hardwires to complete the concurrent allocation of multiple concurrent requests within the same clock cycle.

[0077] The core stripping logic, including "mask bit division" and "single-bit new mask" generation, is as follows:

[0078] Logical Action: After receiving the current 16-bit valid mask bitmap, each level of the RR polling arbiter (e.g., polling arbiter_0) selects a valid Bank number based on its internal pointer state. At the moment of selection, the mask processing module adjacent to that arbiter immediately performs a special bit clearing operation.

[0079] Specific implementation: The mask processing module reads the Bank number index output by the arbiter in the previous step, and then generates a one-hot code on the 16-bit data bus using this index (i.e., 1 << selected_index). This module forcibly clears all other bits in the currently input 16-bit valid mask, and only retains and forcibly activates the bit corresponding to the selected Bank number. After this logical processing, the output mask changes from the original possible multiple valid bits to a new mask with only "one valid bit", that is, a new single-bit mask.

[0080] After generating the "new single-bit mask", no caching or clock synchronization is required, and the result is directly connected to the next-stage polling arbiter_1 as a physical connection. Since only one bit of the mask input to the polling arbiter_1 is a valid "1", no matter how the arbiter_1 polls, the only operation it can perform in the current clock cycle is to "confirm" the Bank number that has been selected by the previous stage. This physically and logically ensures that this Bank will never be selected repeatedly in the current batch.

[0081] As shown in Figure 2 the mask processing module is connected in series with a D flip-flop, and its output is fed back to the state input terminals of the polling arbiter_0 and the polling arbiter_1 respectively, which forms a hardware closed-loop feedback. Through this feedback, the arbiter can record the gating state of the current batch within one clock cycle, and automatically adjust the starting pointer of arbitration polling at the beginning of the next clock cycle (or the next batch), so as to realize continuous absolutely conflict-free arbitration in the scenario of multi-batch serial processing.

[0082] For example: assume that the number of parallel write requests in the current batch is M=3. At the start of the t1 cycle, the valid mask of a certain level is ...100101..., in which Bank_1, Bank_3, and Bank_5 are valid.

[0083] First-stage allocation: The polling arbiter_0 selects Bank_3.

[0084] Mask stripping: The adjacent mask processing module directly clears all bits in the valid mask except those corresponding to Bank_3, and outputs the "new single-bit mask" ...000100... .

[0085] Subsequent allocation: This single-bit mask that only marks Bank_3 is transmitted as input to the polling arbiter_1. The arbiter_1 "traverses" this mask and "selects" Bank_3, after which the second-stage mask processing module confirms again and outputs ...000100... (still only containing Bank_3).

[0086] Feedback Update: Simultaneously, the D flip-flop on the feedback loop latches and feeds back the state that Bank_3 is selected, indicating that at the start of the next batch, the pointer of the polling arbiter_0 will skip Bank_3 to avoid conflicts. In this way, the initial allocation of the three requests is completed safely.

[0087] The hardware micropipeline logic, which interleaves and sequentially strips the RR polling arbiter and mask processing module to generate a new single-bit mask, achieves the following: First, at the physical hardware level, it replaces the complex and expensive multi-path parallel comparison and conflict detection backoff logic in traditional designs with a simplified "one-hot code stripping," greatly shortening the depth of the combinational logic chain. This allows the entire arbitration micropipeline to successfully achieve timing closure even at extremely high system clock frequencies. Second, by forcibly compressing the selection result of the previous stage into a new single-bit mask and passing it to the next stage, concurrent requests are directly eliminated at the circuit physical connection level. The possibility of overlapping Bank selections is eliminated, removing the need for post-processing judgment at the software level and effectively eliminating pipeline stalls and data race risks caused by Bank conflicts. In addition, the continuous feedback loop formed by D triggers cascaded on the internal path enables the arbitrator to accurately record the gating state of the previous batch when multiple batches of requests are handed over. This ensures that a rigorous and fair polling logic is maintained between concurrent write requests in different batches, thereby significantly improving the overall throughput and operational stability of the hardware storage system when faced with sudden high concurrency requests with extremely low hardware gate overhead.

[0088] In the third time cycle of the pipeline, S400 logically aggregates the valid Bank results obtained after the high, medium and low priority levels are selected in series, and outputs the final selection mask corresponding to each priority level. When performing actual write operation allocation, the high priority level takes precedence over the medium priority level, the medium priority level takes precedence over the low priority level, and the Bank number selected in the current cycle is not physically adjacent to the Bank number selected in the previous cycle.

[0089] After multi-stage cascading selection by the S300, the high, medium, and low priority levels each obtain valid bank selection results within their respective levels. In the third cycle (t2) of the pipeline, the S400 logically aggregates the discrete results from these three levels, packages them into a unified output, and forms the final selection mask for each priority level within that cycle. Furthermore, during the final actual write operation, the S400 imposes two stringent constraints: first, it must strictly adhere to the priority configuration of "high priority > medium priority > low priority," ensuring that high-priority requests receive absolute priority responses; second, it enforces a "physical adjacency constraint," requiring that the bank number selected in the current cycle must not be physically adjacent to the bank number just written in the previous cycle. This is to prevent continuous erasing and writing of adjacent banks from causing hardware-level thermal effects or electromagnetic interference, enhancing the physical reliability of the system.

[0090] Furthermore, the constraint in step S400 that the Bank number selected in the current period is not physically adjacent to the Bank number selected in the previous period is achieved through a bitmap masking operation, including:

[0091] Before executing step S300, the Bank number selected in the previous cycle and the Bank number adjacent to it in the physical address are all set to a masked state in the corresponding position of the 16-bit Bitmap. The unselectable Bank is masked in advance before entering the serial selection logic.

[0092] like Figure 2 As shown, the system specifically introduces an input signal to write the Bank bitmask. This signal is fed into the pre-generated Bank mask module via hardware wiring. Within this module, it is used as a "mask out" vector and combined with the Bank bitmask output from the high / medium / low comparators to perform logical combinations.

[0093] The specific logic for generating the physical adjacency shielding vector (core hardware implementation) is as follows:

[0094] The hardware implementation of this constraint requires the construction of a small "adjacent bank masking logic unit". The final valid bank number selection result output in the previous cycle (t2 clock) is stored in a D flip-flop as a historical state. Before entering the next cycle at t0 clock, the hardware logic generates a 16-bit masking state vector based on the historical bank numbers. Assuming the bank index selected in the previous cycle is X: generate adjacent bank numbers: X-1, X, X+1. Set the 3 bits corresponding to indices X-1, X, and X+1 to logic 0 in the 16-bit register (indicating masking, disallowing use), and set the remaining 13 bits to logic 1 (indicating permission). This generated 16-bit masking vector is the write bank bit mask signal for the next cycle, which is input to the pre-generated bank mask module at the beginning of t0 clock.

[0095] The logical combination (pre-cleaning) with the comparison results is as follows:

[0096] In the pre-generated Bank mask module of the t0 cycle, the module performs a bitwise AND operation or masking operation on the preliminary results output by the high / medium / low idle depth comparator and the write Bank bit mask.

[0097] The specific operational logic is as follows: First-level selection mask = comparison-after Bank bit mask & write-Bank bit mask. Through this one-time bit operation, any Bank that is physically adjacent to the Bank of the previous cycle, or the previous cycle itself, will be forced to be cleared to zero in the first-level selection mask. In this way, unselectable Banks are physically "pre-masked" before entering the multi-level serial selection logic of the second time tick (t1) of the pipeline.

[0098] For example: Suppose that in the previous cycle, Bank5 was ultimately selected for the write operation at clock t2. When entering the next cycle at clock t0, the system automatically generates a mask signal based on Bank5: clearing the corresponding bits of Bank4, Bank5, and Bank6 (marking them as masked), and setting the corresponding bits of other banks to 1. Suppose that in this cycle, the idle depth comparator of a certain level determines that the current physical banks: Bank3, Bank5, and Bank7 meet the idle depth condition. This preliminary result [Bank3, Bank5, Bank7] enters the pre-generated bank mask module. A bitwise AND operation is performed with the mask vector: [Bank3, Bank5, Bank7] AND (valid for all except 4, 5, and 6).

[0099] The final output of the first-level selection mask shows that only Bank3 and Bank7 are valid. Bank5, being adjacent to itself, and Bank4 and Bank6, being adjacent physical banks, are all successfully cleaned and masked by the front-end logic and cannot enter the t1 arbitration chain, thus avoiding continuous writes to adjacent banks.

[0100] In this embodiment, by constructing a dedicated hardware vector generation module, the strict physical backend constraint that "two consecutive Bank numbers cannot be adjacent" is directly transformed into a pure combinational logic "bitwise AND" operation. This intercepts Banks that may trigger physical thermal effects or trace crosstalk hazards from the source of hardware allocation, completely avoiding the huge clock overhead caused by using traditional software polling or software table lookup. At the same time, this mandatory "pre-cleaning" means that the multi-level RR polling arbitrator in the second time tick (t1) of the pipeline no longer needs to care about physical trace constraints. This greatly simplifies the combinational logic complexity of the arbitration micropipeline, reduces critical path delay, and plays a decisive and stabilizing role in ensuring the correctness of the layout and routing and the reliable operation of high-speed, high-frequency integrated circuits.

[0101] S500: When the available Bank resources at the high level are insufficient to meet the needs of the M write requests in the current batch, the remaining requests are sequentially deferred to the medium level for arbitration selection. If the available Bank resources at the medium level are still insufficient to meet the remaining requests, the remaining requests are further deferred to the low level for arbitration selection until all M write requests in the current batch are allocated or all available Bank resources at all levels are exhausted, so as to maintain the overall load balance of Bank resource allocation.

[0102] This step requires a judgment to be made before the arbitration result is generated in the second time tick (t1) of the pipeline and before the aggregation in the third time tick (t2). At the hardware level, this is implemented through a "demand comparison monitoring logic": monitoring the number of valid banks ultimately selected by the polling arbitrator_2 in the high-level channels of the current batch. If this number is less than the number of parallel write requests M in the current batch, it is determined that "high-level valid bank resources are insufficient," and a cross-level demand deferral allocation mechanism is triggered.

[0103] After the high-level channel finishes processing, the system calculates the number of unfulfilled write requests in the current batch (i.e., M - the number of high-level selected valid banks). These unfulfilled write request signals are directly coupled from the output of the high-level arbitration micropipeline to the input of the mid-level arbitration micropipeline. The mid-level arbitrator, based on its own valid candidate mask, allocates mid-level valid banks to these deferred requests.

[0104] If, during the above recursion process, the available Bank resources at the intermediate level are still insufficient to meet the remaining write requests in the current batch, the system will continue to deferred the number of write requests that still cannot be met after being processed at the intermediate level to the input of the low-level arbitration micropipeline through the physical data path, where the available Bank resources at the low level will make the final allocation.

[0105] This "top-down request cascading" will continue until one of the following two conditions is met: first, all M parallel write requests in the current batch are responded to and allocated by the physical bank; second, all available bank resources at the high, medium, and low levels are exhausted, and the system declares the current batch "resource full" and ends the arbitration process. A specific hardware processing example is described below:

[0106] Assume the number of parallel write requests in the current batch is M=4.

[0107] The high-level arbitration micropipeline, based on its initial valid masks Bank0, Bank1, and Bank2, ultimately selected Bank0 and Bank1 (satisfying two requests). At this point, the high-level valid resources are insufficient, and 4-2=2 write requests remain unsatisfied.

[0108] Deferred to the intermediate level: The remaining two write requests are directly sent to the input of the intermediate-level arbitration micropipeline. The intermediate level arbitrates based on its current valid masks Bank4, Bank5, and Bank6, and ultimately selects Bank4 (satisfying one request). At this point, the available resources in the intermediate level are still insufficient to fill the gap, and 2-1=1 write requests remain unsatisfied.

[0109] Deferred to lower level: The remaining write request is deferred to the lower-level arbitration micropipeline. The lower level arbitrates based on its valid mask (e.g., Bank12), successfully selecting Bank12, thus completing the allocation of the last write request. At this point, all four requests in this batch have been allocated.

[0110] By using the cascading request recursion mechanism between the high, medium, and low-level arbitration micropipelines, the complex operation of overlaying resource bitmaps through bitwise OR operations in the traditional scheme is completely abandoned, resulting in a more simplified hardware logic.

[0111] In this embodiment, a pure hardware cascading pipeline strategy is adopted, where the level with available resources responds, and the next lower level takes over if the current level cannot complete the response. This strategy strictly maintains the isolation boundary of physical bank resources between high, medium, and low priority levels, avoiding priority confusion that may be caused by cross-level mask fusion. At the same time, this cascading mechanism enables the system to achieve elastic tiered degradation allocation with extremely low hardware overhead when facing sudden concentrated write traffic. This ensures that even if high-level resources are exhausted, subsequent requests can still receive responses by cascading down the pipeline, effectively preventing the system from falling into a global deadlock due to local resource blockage. This greatly improves the overall utilization of hardware resources and the system's stress resistance in high-concurrency extreme environments.

[0112] Furthermore, the first-level selection mask in step S200, the intermediate mask generated by the serial selection of each level in step S300, and the final selection mask in S400 all use a 16-bit Bitmap structure for data transmission. Utilizing the hardware characteristic of the natural mutual exclusion of each bit in the Bitmap, combined with the logic of step-by-step elimination in step S300, the Bank numbers selected by the M write requests in the current batch are forcibly isolated from the source of hardware physical allocation, ensuring that no two Bank numbers overlap.

[0113] In this embodiment, each mask is essentially a 16-bit binary bitmap. Each bit strictly corresponds to a physical bank. For example, bit 0 of the bitmap represents Bank 0, bit 3 represents Bank 3. If a bit is "1", it means that the bank is currently valid and can be selected; if it is "0", the opposite is true.

[0114] At the hardware circuit level, the 16 bits are absolutely independent (i.e., naturally mutually exclusive). A specific bit (such as the 5th bit) can only be "0" or "1" at any given time, and it is absolutely impossible for it to represent both Bank 5 and Bank 6 at the same time. This hardware characteristic is the physical cornerstone of data security.

[0115] In the second cycle (t1) of the pipeline, when the first-level arbiter selects a Bank, the adjacent mask processing module immediately performs a special action: forcibly setting all bits in the entire 16-bit bitmap except for the bit of the currently selected Bank to "0" (i.e. generating a new single-bit mask).

[0116] In this new 16-bit bitmap, only one bit is "1", and the remaining 15 bits are all "0". When this "single-bit new mask" is passed to the next level arbiter, since the only "1" in the bitmap received by the next level arbiter is exactly the Bank bit selected by the previous level, this physically prevents the possibility of subsequent requests to select a different Bank bit.

[0117] Through this sequential process of "selecting one, stripping it into a single bit, and then passing it on," the valid position of "1" in the Bitmap passed through by all M requests in the current batch is always unique and absolutely fixed. Because the hardware bitmap itself cannot be split, the Bank numbers allocated in this batch will inevitably be different from each other, completely blocking the risk of conflict due to overlapping Bank numbers from the physical source.

[0118] Furthermore, the hardware circuit for implementing the Bank read / write balanced scheduling method based on multi-stage pipelines includes:

[0119] The system has 16 physical bank free memory depth status data input interfaces, which are used to obtain the fill status of each bank in real time.

[0120] like Figure 2 As shown, the data awareness and configuration interface (left input) consists of "16 physical bank idle depth input interfaces" and "internal configuration register group". It is responsible for capturing the current remaining idle space status of the 16 banks in real time and reading the system's preset high, medium and low three-level switching thresholds, and is the "data source" of the entire arbitration logic.

[0121] An internal configuration register set is used to store the dynamic switching depth threshold configurations of high, medium, and low.

[0122] The comparator array module is used to receive free memory depth data and threshold configuration in parallel and output the first-level selection mask.

[0123] The system receives Bank states and three-level thresholds in parallel, quickly determining which Banks meet which priority admission criteria. After comparison, it directly generates the first-level selection mask, essentially pre-converting the physical Bank states into a 16-bit bitmap for filtering.

[0124] A two-level arbitration micropipeline, consisting of multiple RR polling arbitration units and mask processing units interleaved in series, is used to execute the step-by-step serial allocation logic in step S300.

[0125] The two-level arbitration micropipeline consists of multiple RR polling arbitration units interleaved with mask processing units. Its core function is to perform a "step-by-step stripping and elimination" operation: whichever bank the previous arbitrator selects, the adjacent mask module immediately "clears" all other banks, ensuring that the next-level arbitrator can only "confirm" that bank. This completely eliminates the possibility of concurrent requests selecting the same bank at the hardware physical connection level.

[0126] The logic aggregation module is used to select and combine the output results of the high, medium and low micropipelines, and output the final selection mask.

[0127] Logical aggregation module corresponding Figure 2 The "OR" module in the code prioritizes and combines the results obtained from serial arbitration of the high, medium, and low channels, and finally outputs the "final selection mask" (Bank bit mask_high / medium / low) to the subsequent write control circuit.

[0128] And cross-cycle synchronous timing registers, which are set between adjacent production line cycles to achieve stable synchronous data transmission.

[0129] This is the foundation for the stable operation of the entire circuit. It is "set up separately between adjacent pipeline cycles" and also exists in the feedback loop within cycle t1. Its function is to synchronously latch the combinational logic result of the previous stage on the rising edge of the next clock and pass it to the next stage. This effectively isolates the complex combinational logic paths at each stage, ensuring that the entire arbitration system will not experience data corruption, metastability, or race conditions even when operating at extremely high hardware clock frequencies.

[0130] This hardware circuit achieves stable and efficient distribution of M concurrent write requests to non-overlapping physical banks by performing coarse screening and classification at time t0, mutual exclusion arbitration using series RR at time t1, and result aggregation at time t2, in conjunction with D flip-flops throughout for timing synchronization, at the cost of extremely simple gate-level circuitry.

[0131] Furthermore, step S500 is achieved through the cascading of hardware data paths between the high-level arbitration micropipeline, the medium-level arbitration micropipeline, and the low-level arbitration micropipeline, including:

[0132] When the high-level valid Bank resources cannot satisfy the remaining write requests of the current batch, the remaining write requests that have not been allocated by the high-level arbitration micropipeline are directly coupled and input to the input end of the medium-level arbitration micropipeline through the data path.

[0133] After the high-level arbitration micropipeline selects all the banks it can choose, if there are still M requests that have not been processed, they are directly input into the medium-level arbitrator through the data path.

[0134] If any remaining write requests are still not satisfied after arbitration by the intermediate-level arbitration micropipeline, the unsatisfied portions continue to be coupled to the input of the low-level arbitration micropipeline through the data path for arbitration selection.

[0135] The intermediate-level requests take the remaining requests and continue selecting. If the intermediate-level requests have also been selected and there are still unprocessed requests, then they are passed on to the lower-level requests.

[0136] Each level of arbitration micropipeline is based on data path cascading, responding to and processing parallel write requests within each batch in descending order of priority, until all M write requests in the current batch are allocated or all valid Bank resources at all levels are exhausted.

[0137] The lower-level requests will continue to be processed until all M requests are allocated, or the Bank resources of the high, medium, and low levels are exhausted.

[0138] In this embodiment, a simplified recursive logic of "high-priority priority, low-priority fallback" is achieved through hardware cascading between high, medium, and low-priority arbitration micropipelines. This cascading transmission eliminates the need for complex bitmap overlay operations, greatly simplifying hardware circuit design. Simultaneously, it perfectly solves the request blocking problem after high-priority resources are exhausted, ensuring that all physical bank resources are utilized to the maximum extent, significantly improving the overall stability and throughput of the system under sudden high-concurrency write scenarios.

[0139] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0140] Embodiments of the present invention also provide a chip, including an on-chip cache scheduling circuit; the on-chip cache scheduling circuit is used to execute the Bank read-write balanced scheduling method based on multi-stage pipeline as described in the above embodiments, so as to arbitrate and allocate read and write access to the physical memory inside the chip.

[0141] Embodiments of the present invention also provide a network interface card (NIC), including a high-speed data packet caching module and a cache read / write control circuit connected to the high-speed data packet caching module; the cache read / write control circuit is configured to execute a Bank read / write balanced scheduling method based on multi-stage pipelines as described in the above embodiments, so as to allocate and schedule concurrent write requests to multiple physical Banks within the high-speed data packet caching module.

[0142] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and are not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention.

Claims

1. A Bank read / write balanced scheduling method based on multi-stage pipelines, characterized in that, Includes the following steps: S100 divides N banks into three mutually exclusive priority levels: high, medium, and low, based on the real-time free memory depth of each bank. The intersection of any two sets of Bank IDs is empty, and the union of all N Banks is the set of Bank IDs. S200 compares the current free memory depth of each Bank with the high, medium and low three-level thresholds pre-configured by the system in the first time cycle of the pipeline, and generates the first-level selection mask corresponding to each priority level based on the comparison results. S300, in the second time cycle of the pipeline, for the M parallel write requests that arrive simultaneously in the current batch, based on the first-level selection mask, a multi-level serial selection logic that gradually eliminates the selected Bank identifier is used to perform serial allocation, so that the selected Bank numbers of the M requests in the current batch do not overlap. S400, in the third time cycle of the pipeline, logically aggregates the valid Bank results obtained after the high, medium and low levels are selected in series, and outputs the final selection mask corresponding to each priority level. Among them, when performing actual write operation allocation, high level takes precedence over medium level, medium level takes precedence over low level, and the Bank number selected in the current cycle is not physically adjacent to the Bank number selected in the previous cycle. S500: When the available Bank resources at the high level are insufficient to meet the needs of the M write requests in the current batch, the remaining requests are sequentially deferred to the medium level for arbitration selection. If the available Bank resources at the medium level are still insufficient to meet the remaining requests, the remaining requests are further deferred to the low level for arbitration selection until all M write requests in the current batch are allocated or all available Bank resources at all levels are exhausted, so as to maintain the overall load balance of Bank resource allocation.

2. The method according to claim 1, characterized in that, In step S100, N is 16; the number of Banks at the high, medium, and low levels is dynamically adjusted according to the proportion of memory space used.

3. The method according to claim 1, characterized in that, Between the first, second, and third time cycles, data is synchronized by using synchronous clock registers set on each pipeline node. The selection mask and allocation status output from the previous time cycle are stably transmitted to the next processing circuit on the next rising edge of the clock, forming a closed-loop three-stage hardware pipeline structure.

4. The method according to claim 1, characterized in that, The hardware implementation of the multi-level serial selection logic in step S300 is as follows: it is executed by a hardware micropipeline consisting of an M-level RR polling arbitration unit and an M-level mask processing unit connected in an alternating series. Multi-level serial selection logic includes: Each level of RR polling arbitration unit receives the current valid mask bitmap and selects a valid Bank number from it. Then, the corresponding adjacent mask processing unit sets all other valid bits in the current valid mask except for the bit corresponding to the selected Bank number to an invalid mask state, thereby generating a new single-bit mask that only retains the selected Bank number. This new single-bit mask is then directly passed as input to the next level of RR polling arbitration unit.

5. The method according to claim 1, characterized in that, Step S500 is achieved through the cascading of hardware data paths between the high-level arbitration micropipeline, the medium-level arbitration micropipeline, and the low-level arbitration micropipeline, including: When the high-level valid Bank resources cannot meet the remaining write requests of the current batch, the remaining write requests that have not been allocated by the high-level arbitration micropipeline are directly coupled and input to the input end of the medium-level arbitration micropipeline through the data path. If there are still unmet parts of the remaining write requests after arbitration by the intermediate-level arbitration micropipeline, the unmet parts continue to be coupled to the input of the low-level arbitration micropipeline through the data path for arbitration selection; Each level of arbitration micropipeline is based on data path cascading, responding to and processing parallel write requests within each batch in descending order of priority, until all M write requests in the current batch are allocated or all valid Bank resources at all levels are exhausted.

6. The method according to claim 1, characterized in that, The first-level selection mask in step S200, the intermediate mask generated by the serial selection of each level in step S300, and the final selection mask in S400 all use a 16-bit Bitmap structure for data transmission. Utilizing the hardware characteristic of the natural mutual exclusion of each bit in the Bitmap, combined with the logic of step-by-step elimination in step S300, the Bank numbers selected by the M write requests in the current batch are forcibly isolated from the source of hardware physical allocation, ensuring that no two Bank numbers overlap.

7. The method according to claim 6, characterized in that, The constraint in step S400 that the Bank number selected in the current period is not physically adjacent to the Bank number selected in the previous period is achieved through a bitmap masking operation, including: Before executing step S300, the Bank number selected in the previous cycle and the Bank number adjacent to it in the physical address are all set to a masked state in the corresponding position of the 16-bit Bitmap. The unselectable Bank is masked in advance before entering the serial selection logic.

8. The method according to claim 1, characterized in that, The hardware circuit for implementing the Bank read / write balanced scheduling method based on multi-stage pipelines includes: 16 physical bank free memory depth status data input interfaces are used to obtain the fill status of each bank in real time; An internal configuration register set is used to store the dynamic switching depth threshold configurations of high, medium, and low. The comparator array module is used to receive free memory depth data and threshold configuration in parallel and output the first-level selection mask; A two-level arbitration micropipeline, consisting of multiple RR polling arbitration units and mask processing units interleaved and connected in series, is used to execute the step-by-step serial allocation logic in step S300. The logic aggregation module is used to select and combine the output results of the high, medium and low micropipelines, and output the final selection mask; And cross-cycle synchronous timing registers, which are set between adjacent production line cycles to achieve stable synchronous data transmission.

9. A chip, characterized in that, It includes an on-chip cache scheduling circuit; the on-chip cache scheduling circuit is used to execute the Bank read-write balanced scheduling method based on multi-stage pipeline as described in any one of claims 1 to 8, so as to arbitrate and allocate read and write access to the physical memory inside the chip.

10. A network interface card (NIC), characterized in that, The system includes a high-speed data packet caching module and a cache read / write control circuit connected to the high-speed data packet caching module; the cache read / write control circuit is configured to execute the Bank read / write balancing scheduling method based on multi-stage pipeline as described in any one of claims 1 to 8, so as to allocate and schedule concurrent write requests to multiple physical banks within the high-speed data packet caching module.

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