A storage resource intelligent scheduling decision method based on machine learning situation prediction

Abstract

The application relates to the technical field of storage resource scheduling, and discloses a storage resource intelligent scheduling decision method based on machine learning situation prediction, which solves the problems of front-end congestion, solid-state disk overheating and frequency reduction, and queue accumulation caused by the inability to perceive CPU lock conflict in existing scheduling. The method comprises the following steps: collecting cache consistency, medium thermodynamics and queue delay characteristic input prediction model; when the split lock frequency and information entropy are overlimited, shielding the initial scheduling instruction output by the model, aggregating discrete writing into additional writing operation, and reconstructing the routing weight according to the multiplicative equation composed of the thermodynamics and lock characteristic operator to distribute the target block; and in the execution cycle, solving the control equation according to the tail delay to adjust the bandwidth rate. The application eliminates the bus lock conflict, slows down the physical wear and tear, and prevents the business read-write timeout.

Description

Technical Field

[0001] This invention relates to the field of storage resource scheduling technology, and in particular to a smart storage resource scheduling decision-making method based on machine learning situation prediction. Background Technology

[0002] In high-concurrency storage scheduling of enterprise-level databases or cloud storage nodes, existing technologies typically employ time-series forecasting models to allocate write traffic to storage nodes. In scenarios involving massive concurrent writes of small files, multiple CPU cores frequently access and modify metadata in the same file directory, triggering cross-core cache line failures and underlying memory bus split-lock conflicts. Time-series forecasting models only collect macroscopic throughput data and cannot detect the microscopic split-lock conflict state of the CPU cores. They continue to issue concurrent write commands, resulting in the CPU bus clock cycles being continuously occupied, causing front-end write request queuing and congestion.

[0003] When front-end write requests become congested, discrete write requests are centrally distributed to the non-volatile dual-channel solid-state drive (SSD), causing a surge in the instantaneous write load on the internal flash memory chips and a corresponding increase in physical junction temperature. At high temperatures, leakage current in the insulating oxide layer of the flash memory chips increases, accelerating the rate of physical wear. Existing routing mechanisms do not consider physical junction temperature and block lifetime in their scheduling, continuously writing data to high-temperature and aged physical blocks, thus accelerating the depletion of the lifespan of these local physical blocks.

[0004] When the physical block junction temperature reaches the safety threshold of the SSD hardware controller, the controller triggers a low-level thermal throttling mechanism to force a reduction in frequency. This mechanism causes a sharp drop in the SSD's physical write bandwidth. As a result, input / output requests from the operating system's block device layer accumulate in the queue due to the inability to be written to disk in a timely manner, leading to a surge in tail-end latency data in the core front-end business logic and ultimately causing data read / write timeouts at the application layer. Summary of the Invention

[0005] This invention provides a storage resource intelligent scheduling decision-making method based on machine learning situation prediction to solve the technical problem that the existing storage resource scheduling model cannot detect the central processing unit split lock conflict and continuously issues concurrent write instructions, which leads to front-end request congestion and concentrated issuance to the solid-state drive, causing local high temperature and accelerated aging of physical blocks. The local high temperature triggers the thermal throttling forced frequency reduction mechanism at the bottom layer of the solid-state drive, ultimately causing input and output requests to accumulate in the operating system queue and causing business read and write timeouts.

[0006] In view of the above problems, the present invention provides a storage resource intelligent scheduling decision-making method based on machine learning situation prediction, comprising the following steps:

[0007] Step 1: Collect multi-dimensional feature vectors of the storage resource pool, including cache consistency features, media thermodynamic features, and queue latency features;

[0008] Step 2: Input the multidimensional feature vector and historical load time series data into the pre-trained time series prediction model, and output the initial resource scheduling instruction vector;

[0009] Step 3: When the cache consistency feature in the multidimensional feature vector does not meet the preset exception triggering condition, the initial resource scheduling instruction vector is issued; when the cache consistency feature meets the preset exception triggering condition, the initial resource scheduling instruction vector is masked, and a mutation routing instruction sequence is generated based on the media thermodynamic feature and the cache consistency feature. The mutation routing instruction sequence includes a local append write operation instruction and a physical address routing mapping table allocated to the target physical block in the storage resource pool.

[0010] Step 4: During the execution cycle of the mutated routing instruction sequence, based on the queue delay characteristics, a throttling control tensor is generated by solving the differential control equation, and the execution bandwidth rate of the mutated routing instruction sequence is adjusted using the throttling control tensor.

[0011] The technical solution provided in this application has at least the following technical effects:

[0012] By calculating the local Shannon information entropy and the split-lock assertion frequency, when both exceed a preset threshold, the output of the time series prediction model is masked, and discrete write requests are aggregated in the memory buffer and appended to the local write operation instruction. This step transforms multi-core concurrent overwrite writes into single-threaded sequential append writes, avoiding concurrent comparison and swapping of the same cache line status bits at the physical execution level, thereby eliminating CPU clock cycle occupation and front-end request congestion caused by bus lock conflicts.

[0013] By extracting the physical junction temperature and percentage of used lifetime, a dielectric degradation characterization is generated using a complementary exponential decay operator. This characterization is then multiplied as a reduction term into the initial baseline score of the target physical block. This step proportionally reduces the routing decision weight as the physical junction temperature increases and the used lifetime decreases, thereby reducing the write traffic allocated to high-temperature and aging blocks during the routing distribution process. This reduces the physical wear of the insulating oxide layer caused by increased leakage current under high-temperature conditions.

[0014] By constructing a thermal inertia look-ahead prediction term based on the junction temperature change rate, a logistic operator is applied to the temperature deviation variable to generate a monotonically decreasing suppression weight. Within the execution cycle, the latency deviation is calculated based on the preset quantile tail latency, and the execution bandwidth rate is adjusted using a proportional-integral-differential equation to output a throttling control tensor. This step reduces the write bandwidth to the physical block at the operating system kernel level before the physical junction temperature reaches the hardware-forced frequency reduction threshold, preventing the SSD hardware controller from triggering uncontrollable thermal throttling and frequency reduction. This maintains the stability of the block device's I / O queue resident depth and prevents a surge in tail latency for core services. Attached Figure Description

[0015] Figure 1 A flowchart of a storage resource intelligent scheduling decision-making method based on machine learning situation prediction is provided in an embodiment of the present invention;

[0016] Figure 2 This is a system architecture diagram of the present invention. Detailed Implementation

[0017] The above technical solutions will now be described in detail with reference to the accompanying drawings and specific embodiments to provide a better understanding of them. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. It should be understood that the present invention is not limited to the exemplary embodiments used only to explain the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Furthermore, it should be noted that, for ease of description, only the parts related to the present invention are shown in the drawings, not all of them.

[0018] Example: Please refer to Figure 1 and Figure 2 The intelligent scheduling decision-making method for storage resource pools operates in a heterogeneous hardware and software environment that includes both physical and logical layers. The physical topology of this heterogeneous hardware and software environment is constructed from a multi-core CPU architecture, non-uniform memory access architecture nodes, peripheral component interconnect buses, and non-volatile dual-channel solid-state drives (SSDs). Multiple cores within the multi-core CPU architecture achieve state synchronization through an internal ring bus and are connected to the non-volatile dual-channel SSDs via the peripheral component interconnect bus, forming a physical data transmission path.

[0019] Along with the establishment of the physical topology, the logical topology of the heterogeneous hardware and software operating environment is constructed layer by layer within the host operating system. The kernel space of the host operating system is divided from top to bottom into the resource isolation group layer, the extended Berkeley packet filter sandbox runtime state, and the block device driver I / O queue layer. The resource isolation group layer is bound to the computing cores and memory resources of the multi-core central processing unit architecture for allocation; the extended Berkeley packet filter sandbox runtime state is embedded in the kernel space as an independent virtual machine instance, monitoring the underlying system call behavior of the block device driver I / O queue layer.

[0020] Based on the hierarchical logical and physical topologies, a bypass acquisition mechanism for multi-dimensional feature vectors is initialized and activated. This bypass acquisition mechanism includes parallel, independent data extraction paths that generate cache consistency features, media thermodynamic features, and queue latency features, thereby constructing a multi-dimensional feature vector for the storage resource pool.

[0021] Once the multidimensional feature vectors are generated, historical load time-series data and the multidimensional feature vectors are simultaneously fed into the time-series prediction model to generate the initial resource scheduling instruction vector. The time-series prediction model employs a Long Short-Term Memory (LSTM) network topology. This topology uses the multidimensional feature vectors from a predetermined number of past clock cycles as input tensors, and through fully connected layers, outputs an initial resource scheduling instruction vector representing the expected future throughput of each physical block. The network weights of the time-series prediction model are trained and solidified offline via backpropagation using historical load log data.

[0022] When the cache consistency feature in the multidimensional feature vector fails to meet the preset exception triggering condition, the initial resource scheduling instruction vector is issued to perform normal resource scheduling. When the cache consistency feature meets the preset exception triggering condition, the initial resource scheduling instruction vector is masked, and the mutated routing instruction sequence is reconstructed and generated based on the cache consistency feature and the media thermodynamic feature, and then issued to the non-volatile dual-channel solid-state drive. During the lifecycle of the mutated routing instruction sequence execution and disk write, the differential control equation is solved using the queue delay feature to generate a throttling control tensor, which is then injected into the block device input / output controller to perform closed-loop dynamic adjustment of the bandwidth rate.

[0023] To address the cache consistency feature in the multi-dimensional feature vector, the host operating system kernel initiates an extended performance monitoring system call. This call crosses the user-mode and kernel-mode boundary, addressing read instructions to a specific model-specific register within the multi-core CPU architecture. By extracting the number of memory bus transaction flag flips recorded in the specific model-specific register, the lock assertion frequency is extracted at the microsecond level. Simultaneously, at the file system level, the host operating system kernel mounts a trace point at the file descriptor allocation function to intercept the currently active file descriptor. The parent directory identifier of the currently active file descriptor is pushed into a sliding window data structure. This structure is configured with a fixed-depth FIFO queue and a frequency hash map. When the parent directory identifier of the currently active file descriptor is pushed into the FIFO queue, the corresponding frequency key in the frequency hash map is incremented by 1; when an old parent directory identifier overflows the FIFO queue and is dequeued, the corresponding frequency key is decremented by 1. Based on the frequency key value distribution within the frequency hash map, the local Shannon information entropy is obtained by multiplying the accumulated frequency key values ​​by the logarithm of the frequency key values.

[0024] Based on the thermodynamic characteristics of the medium in the multidimensional feature vector, the storage device controller issues an asynchronous log page fetch command conforming to the non-volatile memory host controller interface specification to the peripheral component interconnect bus channel. The log identifier field within the asynchronous log page fetch command is assigned a preset standard log identifier. After receiving the asynchronous log page fetch command, the non-volatile dual-channel solid-state drive returns a standardized health information telemetry log byte stream. The hexadecimal field at a predetermined offset in the standardized health information telemetry log byte stream is extracted to obtain the physical junction temperature parameter and the percentage of lifetime used.

[0025] To address the queue latency feature in the multidimensional feature vector, the Berkeley packet filter sandbox runtime extends by attaching an entry probe at the input / output request dispatch function in the block device driver layer and a return probe at the input / output request completion function. The entry probe records the start timestamp of a single input / output request being pushed into the block device input / output queue layer; the return probe records the end timestamp when the input / output request triggers a hardware completion interrupt. The single discrete request latency is obtained by subtracting the start timestamp from the end timestamp. A quantile aggregation operation is performed on the collected discrete request latency. Specifically, the discrete request latency is mapped to logarithmic latency histogram buckets, and the latency boundary values ​​corresponding to the latency histogram buckets whose cumulative frequency reaches a preset quantile (e.g., but not limited to 99.9%) are extracted as the preset quantile tail latency parameters for the core front-end business logic.

[0026] For the response mechanism to multi-dimensional feature vector input, the cross-domain multi-dimensional constraint scheduling and reconstruction arbitration unit is internally configured with parallel low-frequency prediction channels and high-frequency fast channels. The low-frequency prediction channel maintains the forward propagation computation graph of the time series prediction model. The high-frequency fast channel is connected to the polling interrupt controller of the kernel performance monitoring register to read the split lock assertion frequency.

[0027] When the split lock assertion frequency in the multidimensional feature vector exceeds a preset first lock threshold and the local Shannon information entropy exceeds a preset first entropy threshold, an Advanced Programmable Interrupt Controller (APCDC) signal is triggered in the high-frequency fast channel. The APCDC signal registers a preemptive task with the host operating system kernel scheduler and sends a suspension instruction to the processing core where the low-frequency prediction channel resides, interrupting the execution clock cycle of the time series prediction model. With the time series prediction model suspended, the initial resource scheduling instruction vector generated by the low-frequency prediction channel is masked, and control is transferred to the structural dimensionality reduction engine within the high-frequency fast channel.

[0028] After the structural dimensionality reduction engine acquires the discrete write requests currently captured by the system, it allocates a contiguous circular memory buffer in main memory. The payload data blocks and metadata pointers carried by the discrete write requests are pushed into the circular memory buffer in timestamp order, transforming them into local append write operation instructions under single-thread control. Single-threaded sequential append writes utilize hardware atomic addition instructions to move the tail pointer of the circular memory buffer, completing memory mapping without acquiring mutex locks, thus bypassing the metadata comparison and instruction sequence exchange caused by multi-core concurrent writes.

[0029] After the local append write operation instruction is encapsulated, the target physical block Routing decision weights The calculation is based on the double-constraint multiplicative equation, which is expressed as follows:

[0030] The routing decision weights; The initial benchmark score; This is the preset medium attenuation control constant, and ;

[0031] This is a medium degradation characterization quantity generated via the medium degradation attenuation operator; The preset route weighting coefficient, and ; This refers to the lock storm response factor generated via the lock storm weighting operator. The temperature control suppression weights are generated via the temperature control suppression operator; This serves as the index identifier for the target physical block. The dual-constraint multiplicative equations employ a multiplicative independent structure, ensuring that the medium degradation attenuation operator has an independent reduction constraint on the initial benchmark score when the lock storm weighting operator is at zero output.

[0032] The logic for determining the lock storm response factor is as follows: the sum of the preset first lock threshold and the preset regularization constant is used as the denominator, and the split lock assertion frequency is used as the numerator to calculate the quotient value. The quotient value is then multiplied and mapped with the local Shannon information entropy, and a hyperbolic tangent saturation operator is applied to clamp the output value within the range of greater than or equal to 0 and less than 1.

[0033] The logic for determining the medium degradation characterization quantity is as follows: extract the temperature difference ratio when the physical junction temperature exceeds the preset calibration room temperature, apply a truncation operator with zero value bottoming attribute to the temperature difference ratio to shield temperature interference, apply a complementary exponential decay operator in combination with the preset thermal activation sensitivity index, and perform multiplication mapping with the complement of the used lifetime percentage. Subtract the aforementioned multiplication mapping result from the overall constant 1 to converge the output value to a closed interval between 0 and 1.

[0034] The logic for determining the temperature control suppression weight is as follows: multiply the junction temperature change rate by the preset thermal inertia time constant to construct a thermal inertia look-ahead prediction term; add the thermal inertia look-ahead prediction term to the physical junction temperature, subtract the preset critical physical junction temperature red line, and normalize the result by dividing it by the critical physical junction temperature red line to generate a temperature deviation variable; apply the logistic operator to the temperature deviation variable to generate a suppression weight that monotonically decreases as the temperature approaches the critical physical junction temperature red line.

[0035] As the sequence of mutated routing instructions is issued, the delay negative feedback physical current limiting control unit reads the preset quantile tail delay within the queue delay characteristics. The clock period of the operating system kernel's high-precision timer is extracted and set as the discretized sampling step size of the differential control equation. Within a single discretized sampling step size, the preset tail delay protection threshold is subtracted from the preset quantile tail delay to generate the delay deviation.

[0036] The differential control equation is a proportional-integral-differential equation. The calculation logic for the current limiting penalty factor written in the background is as follows: the proportional gain, integral gain, and differential gain are calibrated using the Ziegler-Nichols empirical parameter tuning method. The throttling control tensor is obtained by adding the proportional gain, integral gain, and differential gain terms derived from the time delay deviation, based on the time variable of the current control cycle. The specific solution steps are: multiply the time delay deviation by the proportional gain to construct the proportional gain term; multiply the time derivative of the time delay deviation by the differential gain to construct the differential gain term; perform time integration on the time delay deviation, use the integral limiting operator to clamp the upper and lower boundaries of the integration result, and multiply the clamped cumulative value by the integral gain to construct the integral gain term. The aforementioned proportional gain term, integral gain term, and differential gain term are added together, and the final output is the current limiting penalty factor written in the background. Among them, when the time delay deviation remains negative within multiple consecutive discretization sampling steps, the cumulative value of the integral term is absolutely locked to the preset integral lower limit constant.

[0037] Simultaneously, the zero-point reset mechanism monitors the sign bit of the delay deviation. When the tail delay of the preset quantile falls below the tail delay protection threshold, causing the sign of the delay deviation to change from negative to positive, the reset mechanism is triggered, instantly clearing the accumulated value of the integral term to zero. The proportional-integral-differential equation outputs the final throttling control tensor, which is written into the relevant register interface of the operating system block device input / output controller to complete the adjustment of the bandwidth rate of the variable routing instruction sequence execution.

[0038] To ensure that the routing decision weights output by the dual-constraint multiplicative equations align with hardware performance metrics, internal constant thresholds are set at calibration domain boundaries. The critical physical junction temperature redline constant is set based on the first temperature limit determined by the SSD thermal throttling forced frequency reduction standard. The calibration room temperature constant is set based on the second temperature limit determined by the standard laboratory thermodynamic room temperature environment, serving as the fundamental benchmark for extracting the physical junction temperature difference ratio.

[0039] The medium degradation control constant in the equation is configured within a closed interval of pure decimals. The boundary value of the medium degradation control constant limits the maximum baseline reduction magnitude performed by the medium degradation operator on the initial baseline score. Under the condition that the medium degradation characterization quantity physically approaches 1, linear scaling is performed using the medium degradation control constant so that the initial baseline score, after deducting the physical lifetime loss mapping, still retains the minimum scheduling weight ratio calculated based on the physical lifetime loss index.

[0040] When the system is in a cold start phase and parameter initialization has not yet been completed, resulting in the first lock threshold being 0, the denominator of the lock storm response factor ratio is configured with a preset regularization constant. Therefore, the calculation path for splitting the lock assertion frequency into the first lock threshold ratio is transformed into a non-zero algebraic operation with the regularization constant as the denominator. At this point, the ratio approaches its maximum value. After smoothing with the hyperbolic tangent saturation operator, the lock storm response factor output is clamped to a scalar approaching 1, avoiding processor division-by-zero crashes.

[0041] When the physical junction temperature of the target physical block drops below the preset calibration temperature, the ratio of the physical junction temperature exceeding the calibration temperature is less than or equal to 0. The truncation operator with zero-value floor property overwrites the output to 0. The complementary exponential decay operator, combined with the preset thermal activation sensitivity index, degenerates into taking the natural exponent with respect to 0, and the output scalar of the complementary exponential decay operator is a constant 1. The constant 1 is multiplied and mapped to the complement of the used lifetime percentage, and then subtracted by the global constant 1, resulting in the final medium degradation characterization output value being strictly equal to the used lifetime percentage, which conforms to the physical model of thermal stress-accelerated degradation under low-temperature conditions.

[0042] When the used lifetime percentage of the target physical block reaches 1, and the physical junction temperature rises to its extreme condition, the temperature difference ratio exceeding the calibrated ambient temperature increases. This temperature difference ratio is then fed into the complementary exponential decay operator after being truncated. Since the exponential independent variable is a negative maximum, the extreme output value of the complementary exponential decay term approaches 0. At this point, regardless of the used lifetime percentage, the product of the complement of the used lifetime percentage and 0 is always 0. After subtracting this from the global constant 1, the output value of the dielectric degradation characterization strictly converges to 1. Substituting the dielectric degradation characterization of 1 into the main architecture, the physical decay term is transformed into 1 minus the dielectric decay control constant. Because the dielectric decay control constant is limited to a pure decimal open interval, the final algebraic result of the physical decay term is always greater than 0, maintaining the positive monotonicity of the output score and avoiding the anomaly of inverted decision direction.

[0043] In the firmware layer of a controller with limited computation cycles or instruction sets, the logistic operator inside the temperature control suppression operator can be equivalently replaced by a one-sided half-Gaussian decay function. The one-sided half-Gaussian decay function uses the squared deviation of the equivalent predicted temperature from the warning temperature as the negative exponential variable. When the equivalent predicted temperature exceeds the warning temperature, the one-sided half-Gaussian decay function utilizes the property that the slope of the squared deviation term monotonically increases after crossing the critical point to output the corresponding suppression value.

[0044] Meanwhile, the natural exponential structure within the dielectric degradation attenuation operator can be equivalently replaced by a nonlinear power-law model based on algebraic power laws. The algebraic power-law nonlinear power-law model extracts the ratio of the calibration room temperature to the physical junction temperature and applies a preset integer power greater than or equal to 4 as the attenuation exponent. When the physical junction temperature is at room temperature, the ratio approaches 1, and the power-law output remains 1. When the physical junction temperature increases, the property of rapidly decaying to 0 with a fractional power similarly drives the final output dielectric degradation characterization quantity to approach 1, achieving an equivalent functional control range.

[0045] For applications with limited computation cycles, the hyperbolic tangent saturation operator within the lock storm weighting operator can be discretized and converted into a hardware-level lookup table acceleration architecture. Continuous hyperbolic tangent curves are sampled at equal intervals according to a preset step size, generating a read-only data structure containing discretized hyperbolic tangent mapping values, which is then burned into the controller's read-only memory circuit. After the ratio of the split lock assertion frequency to the first lock threshold is multiplied and mapped with the local Shannon information entropy, the multiplication mapping output value is truncated into an integer index and a fractional remainder. The integer index is used to address the read-only data structure, extracting two adjacent basic reference discrete values. The hardware multiply-accumulator performs linear interpolation on the two adjacent basic reference discrete values ​​based on the fractional remainder, converting the nonlinear output into a discrete addressable and interpolated level output.

[0046] The mutation routing instruction sequence is ultimately mapped to the entity intelligent scheduling decision system. The intelligent scheduling decision system internally comprises a non-volatile storage medium, main memory, and a processor coupled between the non-volatile storage medium and main memory. The non-volatile storage medium consists of a vertically stacked three-dimensional array of flash memory cells. An embedded temperature sensor network generates and outputs signals of the physical junction temperature and its rate of change. The main memory uses dynamic random access memory chips to temporarily store the forward propagation computation graph objects of the time series prediction model and the data structures of the mutation routing instruction sequence. The processor uses a central processing unit (CPU) chip with multi-core concurrent instruction execution capabilities, extracting computer program instructions from main memory through a memory controller interface to drive the data read / write channels of the non-volatile storage medium.

[0047] The code logic for acquiring feature vectors, masking instruction vectors, and generating tensors is compiled into a binary machine instruction file and packaged into a loadable module for the operating system kernel. This loadable module is loaded into the host operating system's kernel space and executes the code logic under a privileged ring. After the throttling control tensor is generated, the loadable module addresses the starting memory address of the resource isolation group control block. Through memory address offset calculation, it locates the maximum input / output byte rate register interface corresponding to the block device's input / output controller. The loadable module writes the state value of the throttling control tensor into the maximum input / output byte rate register interface. This write operation triggers the block device's direct memory access controller to adjust data transfer bus transactions, converting the logical tensor into a limitation on the physical channel's transmission bandwidth.

[0048] Computer program instructions carrying out multidimensional feature vector extraction operations, control flow logic, and dual-constraint multiplicative equation operations are permanently or temporarily stored in a computer-readable storage medium. Computer-readable storage media include non-transient information carriers such as electrically erasable programmable read-only memory, optical disc media, magnetic hard disk drives, or main memory. When the computer program instructions stored within the computer-readable storage medium are acquired, decoded, and executed by the processor, they drive multidimensional feature vector acquisition, mutation routing instruction sequence generation, and execution bandwidth rate adjustment actions according to the instruction timing sequence, realizing the execution steps of cross-domain state coordination logic on the physical hardware platform.

Claims

1. A storage resource intelligent scheduling decision-making method based on machine learning situation prediction, characterized in that, Includes the following steps: Step 1: Collect multi-dimensional feature vectors of the storage resource pool, including cache consistency features, media thermodynamic features, and queue latency features; Step 2: Input the multidimensional feature vector and historical load time series data into the pre-trained time series prediction model, and output the initial resource scheduling instruction vector; Step 3: When the cache consistency feature in the multidimensional feature vector does not meet the preset exception triggering condition, the initial resource scheduling instruction vector is issued; when the cache consistency feature meets the preset exception triggering condition, the initial resource scheduling instruction vector is masked, and a mutation routing instruction sequence is generated based on the media thermodynamic feature and the cache consistency feature. The mutation routing instruction sequence includes a local append write operation instruction and a physical address routing mapping table allocated to the target physical block in the storage resource pool. Step 4: During the execution cycle of the mutated routing instruction sequence, based on the queue delay characteristics, a throttling control tensor is generated by solving the differential control equation, and the execution bandwidth rate of the mutated routing instruction sequence is adjusted using the throttling control tensor.

2. The method according to claim 1, characterized in that, In step one: The cache coherence characteristics are obtained by reading the CPU's kernel performance monitoring register, specifically including the split lock assertion frequency and the change trajectory of the parent directory identifier of the currently active file descriptor. The thermodynamic characteristics of the medium are obtained by reading the health log of the non-volatile dual-channel solid-state drive, specifically including physical junction temperature, junction temperature change rate, and percentage of lifetime used. The queue delay characteristics are obtained by extracting tracking points in the operating system kernel block device driver layer, specifically including the preset quantile tail delay of the front-end core business.

3. The method according to claim 2, characterized in that, Step three, which involves masking the initial resource scheduling instruction vector and generating a mutated routing instruction sequence, specifically includes the following preset exception triggering logic: The local Shannon information entropy is calculated within a preset sliding window using the changed trajectory. When the split lock assertion frequency is greater than a preset first lock threshold and the local Shannon information entropy is greater than a preset first entropy threshold, it is determined that the preset abnormal triggering condition is met, the initial resource scheduling instruction vector output by the time series prediction model is blocked, and the discrete write requests currently captured by the system are aggregated into the local append write operation instruction.

4. The method according to claim 3, characterized in that, When generating the physical address routing mapping table, the routing decision weight of the target physical block is obtained based on the following logical operations: Obtain the initial benchmark score of the target physical block, and apply the medium degradation attenuation operator, the lock storm weighting operator, and the temperature control suppression operator to the initial benchmark score respectively; The media degradation attenuation operator and the lock storm weighting operator maintain a multiplicative independent relationship in the calculation of the routing decision weight, so that when the lock storm weighting operator is in a state of zero output, the media degradation attenuation operator has an independent reduction constraint on the initial benchmark score.

5. The method according to claim 4, characterized in that, The routing decision weights are specifically calculated using the following double-constraint multiplicative equation: In the formula, The routing decision weights; The initial benchmark score; This is the preset medium attenuation control constant, and ; This is a medium degradation characterization quantity generated via the medium degradation attenuation operator; The preset route weighting coefficient, and ; This refers to the lock storm response factor generated via the lock storm weighting operator. The temperature control suppression weights are generated via the temperature control suppression operator; This is the index identifier for the target physical block.

6. The method according to claim 4, characterized in that, The lock storm response factor output by the lock storm weighting operator and the medium degradation characterization quantity output by the medium degradation attenuation operator are obtained through the following logic: The logic for determining the lock storm response factor is as follows: using the sum of the first lock threshold and the preset regularization constant as the denominator, and the split lock assertion frequency as the numerator, the quotient is calculated, and the quotient is multiplied and mapped with the local Shannon information entropy. Then, a hyperbolic tangent saturation operator is applied to clamp the output value within the range of greater than or equal to 0 and less than 1. The determination logic of the medium degradation characterization quantity is as follows: extract the temperature difference ratio of the physical junction temperature exceeding the preset calibration room temperature, apply a truncation operator with zero value bottoming attribute to it to shield temperature interference, apply a complementary exponential decay operator in combination with the preset thermal activation sensitivity index, and perform multiplication mapping with the complement of the used lifetime percentage. By subtracting the aforementioned multiplication mapping result from the overall constant 1, the output value is converged to a closed interval between 0 and 1.

7. The method according to claim 4, characterized in that, The temperature control suppression weights output by the temperature control suppression operator are obtained through the following logic: The junction temperature change rate is multiplied by a preset thermal inertia time constant to construct a thermal inertia look-ahead prediction term; After adding the thermal inertia look-ahead prediction term to the physical junction temperature, subtracting the preset critical physical junction temperature red line, and then normalizing the result by dividing it by the critical physical junction temperature red line, a temperature deviation variable is generated. A logistic operator is applied to the temperature deviation variable to generate a suppression weight that monotonically decreases as the temperature approaches the critical physical junction temperature redline.

8. The method according to claim 2, characterized in that, In step four, the differential control equation is a proportional-integral-differential equation, and the throttling control tensor is obtained by solving based on the time delay deviation, which is the difference between a preset tail delay protection threshold and a preset quantile tail delay. Its control solution logic includes the following boundary constraints: The integral terms of the proportional-integral-differential equation are clamped at the upper and lower boundaries by an integral limiting operator; When the preset quantile tail delay is detected to fall below the tail delay protection threshold in real time, causing the sign of the delay deviation to change from negative to positive, a reset mechanism is triggered to clear the accumulated value of the integral term to zero.

9. A storage resource intelligent scheduling and decision-making system based on machine learning situation prediction, characterized in that, include: Non-volatile storage media used to provide physical layer candidate storage blocks; Main memory is used to store computer program instructions; A processor, coupled to the non-volatile storage medium and the main memory, is configured to execute the computer program instructions to implement the method steps as described in any one of claims 1 to 8.

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