A heterogeneous computing system and memory expansion method based on UMA unified memory architecture and CXL memory pooling

Abstract

The application discloses a heterogeneous computer system based on unified and pooled memory and a memory allocation method, and the system comprises a local node and a remote node connected through an optical fiber, and a unified pooled memory resource view is constructed for a local host.The local node comprises a heterogeneous computing chip, a UMA local memory, a CXL controller, an on-board extended memory and a near-end optical engine; the remote node comprises a remote optical engine, a remote interconnection control module and a pooled memory resource open to the local host.The application combines UMA and CXL protocols, realizes cross-node interconnection in combination with the optical engine, and maps the local host poolable memory resource and the pooled memory resource open to the remote node into unified addressable resources.The memory allocation method schedules an access request according to a local service load, a link state, a target data position and an access priority.The application can improve the memory capacity, the access efficiency and the resource utilization rate of the heterogeneous computing system, and is suitable for AI large model training and other big data intensive scenarios.

Description

Technical Field

[0001] This invention relates to the field of computer memory technology, and more specifically to a heterogeneous computer system and memory allocation method based on a unified memory architecture and pooled memory. Background Technology

[0002] With the rapid development of applications such as large-scale AI model training, high-performance graph computing, and real-time data analysis, the demand for memory capacity and bandwidth in computing systems is growing exponentially. Taking large-scale language model training as an example, the scale of model parameters has expanded from tens of billions to trillions, and the memory capacity required for a single training session can reach several terabytes or even tens of terabytes, far exceeding the physical capacity limit of the local DRAM of a single computing node. At the same time, the widespread deployment of heterogeneous computing power (such as dedicated accelerators like GPUs, FPGAs, and DPUs) has made multi-node collaborative computing the norm, further placing higher demands on the sharing capability and access efficiency of memory resources.

[0003] In existing technologies, two main approaches are used to address the aforementioned needs: The first approach is to increase DRAM capacity within a Unified Memory Architecture (UMA) or expand local memory using traditional memory expansion technologies (such as DDR memory channel expansion). However, limited by the number of physical slots on the motherboard, the addressing capabilities of the CPU memory controller, and power consumption constraints, the expansion space for local DRAM is extremely limited, and the cost of large-capacity DRAM remains high, leading to a sharp increase in the total cost of ownership. Furthermore, this approach cannot solve the problem of memory resource sharing among multiple nodes; the memory of each computing node remains an isolated resource island. The second approach is to connect remote memory nodes or storage nodes via high-speed networks (such as InfiniBand and RoCE) and utilize remote direct memory access protocols to achieve cross-node data access.

[0004] In recent years, the Compute Express Link (CXL) protocol, as a novel high-speed interconnect technology, supports semantic memory access and cache consistency, providing a new technical path for memory expansion. Existing commercial and industry solutions have demonstrated that UMA can reduce explicit data copying between heterogeneous computing units, CXL can expand addressable memory and support resource pooling, and operating systems can also perform page migration through tiered memory strategies. For example, Chinese patent application CN120849328A, entitled "Storage System Using Compute Express Link (CXL) Interface," provides a storage system that connects the host and storage device via a CXL interface. However, this solution only achieves device-level access or partial sharing, lacking unified discovery, global addressing, cross-board allocation, state synchronization, and fault isolation mechanisms for multi-node physically distributed resources. It has not yet formed a complete technical solution combining distributed hardware deployment and global memory pooling management, especially for scenarios where extended memory is located on multiple computing motherboards or computing nodes. Summary of the Invention

[0005] To address the technical problems mentioned in the background section, this invention proposes a heterogeneous computer system based on a unified memory architecture and pooled memory.

[0006] This heterogeneous computer system includes: local nodes and remote nodes physically connected via optical fiber; the local nodes establish a unified pooled memory resource view for the local host based on local poolable memory resources and poolable memory resources exposed to them by the remote nodes, for performing memory allocation and management; wherein, the local nodes include: Computing chip module; Local memory based on a unified memory access architecture, wherein the local memory is coupled to the computing chip module; The computing fast link controller connected to the computing chip module is used to receive and parse computing fast link transactions sent by the computing chip module, perform address resolution, access routing and protocol processing according to the address mapping relationship, and forward the access request to the onboard extended memory or near-end optical engine module. Several onboard extended memory modules connected to the compute fast link controller; A near-end optical engine module connected to the compute fast link controller is used to perform electro-optical conversion on the electrical signals output by the compute fast link controller and send them to the remote node, and to perform photoelectric conversion on the optical signals from the remote node and transmit them to the compute fast link controller. The remote node includes a remote optical engine module, a remote interconnect control module connected to the remote optical engine module, and a poolable memory module connected to the remote interconnect control module; the remote optical engine module is used to receive the optical signal from the near-end optical engine module and perform photoelectric conversion, and the remote interconnect control module is used to perform fast link transaction processing, access routing, and memory access control on the recovered electrical signal.

[0007] Furthermore, the computing chip module includes at least one of the following: a general-purpose processing unit, a graphics or parallel computing unit, a neural network acceleration unit, and other computing acceleration units, which are interconnected via an on-chip high-speed bus.

[0008] Furthermore, the onboard extended memory includes one or more sets of extended memory chips disposed on the computing motherboard of the local node, and the extended memory chips are connected to the computing fast link controller through printed circuit board traces on the computing motherboard.

[0009] Furthermore, the poolable memory module of the remote node includes compute fast link extended memory located on the remote computing motherboard and is made available to the local node through the remote interconnect control module.

[0010] It is foreseeable that the heterogeneous computer system based on a unified memory architecture and pooled memory, as described in this invention, integrates the advantages of the UMA and CXL architectures, achieving innovation at the hardware physical layer. On one hand, this invention abstracts local nodes, remote nodes, and external heterogeneous nodes into a unified "memory pool" through UMA unified address mapping and CXL consistent interconnection. Authorized computing nodes can access their allocated or authorized pooled memory resources based on a unified address view, thus achieving resource pooling. On the other hand, a co-packaged optical engine module (CPO) coupled to the CXL controller is set up across nodes, replacing the traditional copper physical link with optical fiber, thereby forming a layered physical connection architecture of "direct onboard connection within nodes and CPO optical interconnection between nodes." Furthermore, when computing tasks surge, more external nodes can be connected according to system configuration, and the system automatically establishes address views and permissions for them; when tasks decrease, external nodes can exit, releasing resources. The entire process requires no downtime or restart, supporting dynamic resource elastic scaling. This heterogeneous computer system provides a novel integrated design technical path for applications such as large-scale artificial intelligence model training, high-performance graph computing, and real-time data analysis.

[0011] Furthermore, this invention also proposes a memory allocation method for heterogeneous computers based on unified and pooled memory. This memory allocation method includes: The system initializes and verifies the device availability of local and remote nodes; For the local host, the memory of the local node is divided into local exclusive memory and pooled shared memory; The pooled shared memory, the onboard extended memory of the local node, and the poolable memory module that the remote node exposes to the local host through computing fast links and optical engine links are used to construct a unified pooled memory resource pool for the local host through a unified address mapping relationship. The unified pooled memory resource pool is logically partitioned, and access priorities and access permissions are set. When responding to a data access request initiated locally, the local memory, local onboard extended memory, or remote poolable memory module where the target data is located is determined based on the request address. If the target data is located in a remote poolable memory module, cross-node access is performed by calculating the fast link controller and the optical engine link. After the access request is completed, the access priority of the accessed data is updated in the unified pooled memory resource pool. When responding to a data access request initiated by an external heterogeneous computing node, the external heterogeneous computing node is first authenticated and its permissions are verified. Then, based on the local business load and the traffic of the optical engine module, the access of the external heterogeneous computing node to the unified pooled memory resource pool is controlled.

[0012] Furthermore, when responding to a data access request initiated locally, it also includes: If the data is found to be located in the local memory of the local node, the data is accessed through the on-chip high-speed bus of the computing chip module. If the data is found to be located in the onboard extended memory of the local node, memory semantic access is performed through the compute fast link controller; if the data is found to be located in the poolable memory module that the remote node exposes to the local node, cross-node compute fast link memory semantic access is performed through the local compute fast link controller, the near-end optical engine module, the fiber optic link, the remote optical engine module, and the remote interconnection control module.

[0013] Furthermore, it also includes an access scheduling and migration mechanism: when a local data access request experiences a page fault, the target data is located in an extended or remote memory layer with priority access latency relative to local memory, or the target data belongs to the main computing path data of the current computing task, the scheduling priority of the data access request is increased and / or the target data is migrated to local memory, and the corresponding address mapping is updated.

[0014] Furthermore, when responding to a data access request initiated by an external heterogeneous computing node, the method for controlling the access of the external heterogeneous computing node to the unified pooled memory resource pool is as follows: Get the current load rate of the local service. If the load rate of the local service is higher than the first threshold, insert the data access request of the external heterogeneous computing power node into the low priority queue. The current signal quality indicators and available bandwidth of the optical engine module are obtained. The signal quality indicators include at least one of bit error rate, optical power, synchronization lock state or link training state. If the current signal quality of the optical engine module is lower than the second threshold or the available bandwidth is lower than the third threshold, the data access request of the external heterogeneous computing power node will be delayed. The system obtains the number of external heterogeneous computing nodes currently occupying the optical fiber physical link and the link bandwidth occupancy of each external heterogeneous computing node, and allocates the execution timing of the data access request based on a weighted round-robin or fair queue algorithm.

[0015] Furthermore, it also includes an exception handling mechanism: when the external heterogeneous computing power node exits or an exception occurs, the address mapping and access permissions of the external heterogeneous computing power node are revoked, and its unfinished transactions are cleaned up.

[0016] Furthermore, it also includes fault tolerance mechanisms: continuously monitoring the system link status, optical engine module status, memory status, and power failure events. When an anomaly or fault is detected, at least one fault tolerance process is executed according to the anomaly type, such as restricting new transactions, retraining the link, marking the affected address as unreachable, switching to a backup path, data migration, address remapping, or fault memory isolation.

[0017] It is foreseeable that the heterogeneous computer memory allocation method based on unified and pooled memory of the present invention, under the aforementioned heterogeneous computer system architecture, constructs a unified pooled memory resource pool through application-layer management functions and sets priority levels. On the one hand, the system can keep frequently accessed hot data in local UMA memory and place cold data or large-capacity sparse data in CXL extended memory, which is beneficial for balancing performance requirements and memory capacity utilization. On the other hand, external nodes can directly read and write shared cache data through CXL memory semantic access, reducing the data migration overhead of traditional network protocol stacks, thereby helping to reduce cross-node shared access latency. At the same time, through permission and traffic control mechanisms, it ensures fair competition for bandwidth among multiple external heterogeneous computing power nodes, preventing a situation where one external heterogeneous computing power node saturates the link, causing other nodes to be unable to access it, thereby improving the utilization of computing resources in distributed and high-concurrency computing. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0019] Figure 1 This is the overall logical structure diagram of the heterogeneous computer system of the present invention; Figure 2 This is a schematic diagram of the hardware structure of the heterogeneous computer system of the present invention; Figure 3 This is a schematic diagram of the memory allocation method for a heterogeneous computer system according to the present invention; Figure 4 This is a schematic diagram of the external heterogeneous computing node access process for the memory allocation method of the heterogeneous computer system of the present invention; Figure 5 This is a schematic diagram of the fault tolerance mechanism of the memory allocation method for heterogeneous computer systems according to the present invention.

[0020] The following are the symbol definitions: 100 - Local node; 200 - Remote node; 110 - Computing chip module; 120 - Local memory; 130 - Computing fast link controller; 140 - Onboard extended memory; 150 - Near-end optical engine module; 210 - Remote optical engine module; 220 - Remote poolable memory module; 230 - Remote interconnect control module.

[0021] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0023] Example 1: Heterogeneous Computer System Based on Unified and Pooled Memory Figure 1This is a general logical structure diagram of a heterogeneous computer system based on a unified memory architecture and pooled memory, provided in Embodiment 1 of the present invention. The overall logical structure is divided into a hardware physical layer, a control mapping layer, and a software scheduling layer. The hardware physical layer includes heterogeneous computing chips (CPU, GPU, NPU, and other optional acceleration units), an on-chip high-speed bus, UMA local main memory, onboard CXL extended memory, a CXL controller, and CPO optical engines located at both ends of the cross-node link. The CPU, GPU, NPU, and other optional acceleration units share the UMA local main memory via the on-chip high-speed bus and access the onboard CXL extended memory via the CXL controller.

[0024] The control mapping layer is responsible for device discovery, unified addressing, page table or data block directory maintenance, access permission marking, cache consistency status management, and electro-optical link status mapping. The address space unified mapping unit creates a unified virtual address space covering the local layer and the extended layer, establishes the initial page table or data block directory, and writes the location, permissions, and health status.

[0025] The software scheduling layer is responsible for data popularity assessment, cross-layer migration decisions, task priority arbitration, optical link load control, and anomaly recovery. The memory tier manager loads data classification rules and migration strategies, the hot and cold data identification module initializes the observation state, and the task scheduler establishes priority queues and link throttling strategies.

[0026] The onboard extended memory within a node is directly connected to the CXL controller via the PCB. Cross-node access involves the physical layer electrical signals output by the CXL controller being converted into optical signals by the local CPO optical engine, transmitted through fiber optic cable to the remote CPO optical engine, and then restored to electrical signals. The semantics of the CXL link layer, transaction layer, and memory remain unchanged, and the layers interact bidirectionally through address requests, status feedback, migration instructions, and completion notifications.

[0027] Unlike traditional methods that use UMA and CXL as independent resources, this invention does not simply add extended memory, but rather integrates local main memory and onboard CXL extended memory into the same data lifecycle management system. Services do not need to explicitly distinguish physical storage locations; the system can change the data hierarchy based on data activity, task stage, available space, and link load, thereby achieving greater capacity flexibility while maintaining the advantages of local access. Furthermore, control information and data flow are separated in the system. Intra-node data flow completes reading, writing, and migration along the on-chip bus or onboard CXL memory semantic link; cross-node data flow sequentially passes through the CXL controller, the local CPO optical engine, the fiber optic physical link, and the remote CPO optical engine. The control flow is jointly generated by the address space unified mapping unit, memory hierarchy manager, and task scheduler, used to select local or remote access paths, establish migration batches, set priorities, implement throttling, and confirm consistency and optical link status. This design allows the CPO to replace only the underlying physical transmission medium of the CXL without changing the upper-layer protocols and software interfaces.

[0028] One of the innovations of this invention lies in its hardware structure, such as... Figure 2 As shown, for the hardware physical layer system architecture, the system includes a local node 100 and a remote node 200 physically connected via optical fiber. The local node 100 establishes a unified pooled memory resource view for the local host based on its local poolable memory resources and the poolable memory resources exposed to it by the remote node 200, which is used for memory allocation and management.

[0029] Specifically, the local node 100 includes: a computing chip module 110, local memory 120 based on Unified Memory Architecture (UMA), a Compute ExpressLink (CXL) controller 130, several onboard extended memory modules 140, and a near-end optical engine module 150.

[0030] The computing chip module 110 is the core computing unit of the local node. Optionally, the computing chip module 110 includes at least one of a general-purpose processing unit (CPU), a graphics or parallel computing unit (GPU), a neural network acceleration unit (NPU), and other computing acceleration units interconnected via an on-chip high-speed bus. This combination of heterogeneous computing chips can meet the diverse computing power requirements of complex application scenarios such as large-scale artificial intelligence model training and high-performance graph computing. Each computing unit shares address translation, access arbitration, and data path through the on-chip high-speed bus, and can directly access common data objects in the UMA's local main memory. The on-chip bus is responsible for order control and bandwidth arbitration between concurrent requests, and forwards memory requests that need to access the extension layer to the CXL controller.

[0031] The local memory 120 is coupled to the computing chip module 110. The UMA local main memory serves as the priority storage domain for the main computing path, used to hold active model weights, key-value caches for the current task, frequently accessed feature data, intermediate tensors, runtime metadata, and critical operating system data. Its physical location is tightly coupled with the heterogeneous computing chip and is shared by all computing units. The memory tier manager reserves necessary space for the local memory according to the business stage, prioritizing data that is sensitive to response or has been continuously accessed recently. Based on the UMA architecture, it enables each processing unit (such as CPU, GPU, NPU) in the computing chip module 110 to access the local memory 120 through a unified address space, thereby avoiding the cumbersome data copying and format conversion overhead of traditional heterogeneous computing and reducing programming complexity.

[0032] The CXL controller 130 is connected to the computing chip module 110 and serves as the core hub connecting the computing unit and memory resources. The CXL controller 130 receives and parses CXL transactions issued by the computing chip module 110, performs address resolution, access routing, CXL memory semantic transaction processing, and forwards requests for local extended memory or remote links based on address mapping relationships. In specific implementations, it can execute corresponding protocol or instruction conversions based on the target memory interface.

[0033] The CXL controller is responsible for device discovery, link establishment, protocol parsing, memory semantic transaction processing, cache consistency maintenance, and access routing. The CXL controller registers onboard extended memory as a uniformly addressable physical resource and arbitrates requests based on their origin, address attributes, and current link status. When main computing access, background migration, and maintenance requests arrive concurrently, the CXL controller selects the service order based on priority and throttling information issued by the task scheduler, preventing background operations from continuously congesting critical access paths.

[0034] In cross-node access scenarios, the CXL controller also provides high-speed electrical signals that meet the CXL physical layer requirements to the CPO optical engine and receives signals recovered from remote photoelectric sources, eliminating the need for upper-layer protocol processing logic to be aware of changes in the transmission medium. For distributed deployments of multiple compute motherboards or compute nodes, the CXL controller of each compute motherboard or compute node, or the CXL switching logic connected to it, completes cross-board routing based on the compute motherboard or compute node identifier and target address window, and reports compute motherboard or compute node-level capacity, bandwidth, latency, reachability, and fault status to the CXL control mapping layer to support unified addressing and dynamic allocation of the global memory pool. The onboard extended memory 140 comprises several units, all connected to the CXL controller 130. Each onboard extended memory 140 includes one or more sets of extended memory chips directly soldered or fixedly mounted on the computing motherboard of the local node 100. These onboard extended memory 140s communicate with the CXL controller 130 via the CXL protocol, supplementing the capacity of the local memory 120. The capacity and number of the extended memory chips can be configured according to the computing motherboard design, providing scalable memory resources for the system. Simultaneously, the onboard CXL extended memory resources distributed across different computing nodes need to be uniformly managed and addressed at the software level through address mapping and state synchronization mechanisms, forming an extended memory pool transparent to upper-layer applications.

[0035] The onboard CXL expansion memory chips are directly soldered to the motherboard and connected to the CXL controller via dedicated PCB traces, eliminating the need for pluggable expansion cards and intermediate connectors. The motherboard traces are specifically designed around impedance continuity, return paths, crosstalk suppression, and clock coordination to minimize the impact of connector contacts and additional paths on signal quality. This expansion memory can be configured with compatible mainstream volatile memory chips or compatible expansion media depending on the system implementation, primarily carrying cold model parameters, historical key-value caches, low-frequency graph data, and intermediate results that can be accessed later.

[0036] In one embodiment of the present invention, the system includes multiple independent computing motherboards or computing nodes. Each computing motherboard may be equipped with one or more sets of onboard CXL extended memory chips, and correspondingly record the computing node identifier, capacity information, physical address window and health status. The poolable resources of different computing nodes participate in memory pooling for the local host after being uniformly registered.

[0037] The onboard direct-connect method makes the CXL extended memory a fixed component of the computing motherboard, enabling coordinated arrangement around heterogeneous computing chips and memory control paths. Compared to general plug-in card solutions, this method reduces external connection layers and mechanical interface requirements, which is beneficial for improving system integration and provides a hardware foundation for unified heat dissipation, power supply, and link management. Multiple computing motherboards can each adopt the above-mentioned onboard direct-connect method, with each computing motherboard maintaining a short-path fixed integration. Different computing motherboards are interconnected through CXL / CPO links, thus forming a hardware organization method of "fixed onboard direct connection, optical interconnection between nodes, and unified memory pooling".

[0038] The near-end optical engine module 150 is connected to the CXL controller 130 and is used to perform photoelectric conversion on the electrical signals of the CXL controller 130 and transmit them to the remote node 200 via optical fiber. It can also receive optical signals from the remote node 200 and convert them into electrical signals. Using a co-packaged optical engine module (CPO) to replace the traditional copper physical link can overcome the limitations of signal transmission distance and bandwidth, enabling high-speed, low-latency interconnection between nodes.

[0039] In one possible implementation, the local CPO optical engine module is tightly coupled to the CXL controller to convert CXL physical layer electrical signals into optical signals; the remote CPO optical engine module performs photoelectric conversion and sends the recovered electrical signal to the remote CXL switching or memory control logic. Fiber optic links replace traditional cross-node copper physical links, while upper-layer CXL device discovery, memory semantic access, cache consistency, and transaction confirmation mechanisms remain unchanged. The CPO module also reports optical power, link training, synchronization locking, and error status to the control mapping layer to support access throttling, path switching, and fault isolation. In scenarios with distributed deployment of multiple compute motherboards, CPO optical interconnect interfaces can be set on the CXL side of different compute motherboards or compute nodes to connect two or more physically independent compute nodes, ensuring that the distance between compute motherboards, chassis location, or cabling configuration does not affect the upper-layer global memory pooling semantics.

[0040] The remote node 200 includes a remote optical engine module 210, a remote interconnect control module 230 connected to the remote optical engine module 210, and a remote poolable memory module 220 connected to the remote interconnect control module 230. The remote optical engine module 210 receives optical signals sent by the near-end optical engine module 150 and performs photoelectric conversion, or converts electrical signals output by the remote interconnect control module 230 into optical signals and sends them back to the local node 100. The remote poolable memory module 220 may include CXL extended memory directly mounted on the remote computing motherboard and made available to the local node 100 by the remote interconnect control module 230; the remote node's own private UMA memory is generally not included in this poolable memory resource. Through the fiber optic link, the local node 100 can incorporate the poolable memory resource 220 made available to it by the remote node 200 into a unified address view, realizing cross-node pooling of memory.

[0041] The heterogeneous computer system in this embodiment achieves an innovative design at the hardware physical layer by integrating the UMA architecture and the CXL protocol and introducing an optical engine module for cross-node interconnection. On one hand, the system abstracts local memory, onboard extended memory, and remote memory into a unified "memory pool" through UMA's unified address mapping and CXL's consistent interconnection. This allows computing units with corresponding access permissions to access allocated or authorized pooled memory data based on a unified address view, thus achieving resource pooling. On the other hand, direct onboard connections are used within nodes, while CPO optical interconnects are used between nodes, forming a layered physical connection architecture that provides a solid hardware foundation for building large-scale, high-performance heterogeneous computing systems.

[0042] In addition to the hardware structure mentioned above, a system needs corresponding software to realize its specific functions, according to... Figure 1 As shown, it is necessary to provide a brief explanation of the software module composition: The core software runs on the operating system kernel, device drivers, and optional runtime management layer, mainly including an address space unified mapping unit, a memory tiering manager, a hot / cold data identification module, a cross-tier memory migration controller, and a task scheduler. All modules share a unified metadata directory and maintain consistency in data location, popularity, migration status, and access permissions through event notifications and status write-back. For multi-board physically distributed structures, the unified metadata directory also records the compute motherboard or compute node identifier, on-board address, cross-board path, compute motherboard or compute node health status, and compute motherboard or compute node-level resource usage information to support global memory pooling management.

[0043] (1) Address Space Unified Mapping Unit This unit registers the local exclusive area, pooled shared area, local CXL extended memory, and CXL pooled memory resources exposed by remote nodes to the local host in the local UMA according to resource attributes to a unified address view, and establishes a contiguous virtual address space for upper-layer processes or runtime. Mapping can be managed at the page or data block level. The metadata directory records the virtual address range, current physical location, associated task, access permissions, consistency attributes, hot status, migration status, and fault flags. When an access occurs, the address translation logic first queries the mapping directory; if the data is located in the local layer, a local access is directly formed; if it is located in the local board or remote CXL extended layer, a corresponding CXL memory semantic request is generated and forwarded via the CPO link when the target resource is located on a remote node; if the data is being migrated, controlled processing such as waiting, redirection, or reading the old copy is performed according to the migration stage. When extended memory is distributed across multiple computing motherboards or computing nodes, the current physical location includes at least the target computing motherboard or computing node identifier and the physical page or data block address of that computing motherboard or computing node; the unified mapping unit maps the discrete physical address windows of different computing motherboards or computing nodes to the same global addressing view, and incrementally updates the mapping relationship when a computing motherboard or computing node is added, removed, or fault isolated.

[0044] (2) Memory tier manager The manager defines the UMA local main memory as the priority service domain and the onboard CXL extended memory as the capacity extension domain, determining the initial placement location based on data type, business priority, lifecycle, and access characteristics. Weights, active key-value caches, and highly reusable intermediate results required for the current computation phase of the model are prioritized for the local layer; historical session caches, temporarily inactive model parameters, low-frequency graph data, and data that can be reconstructed but has a high reconstruction cost can enter the extension layer. The manager continuously receives spatial water level, heat changes, and task status, adjusting the data hierarchy without altering the upper-layer virtual address. Resource allocation in the extension layer is also performed among multiple member computing motherboards or computing nodes. The manager can select target computing motherboards or computing nodes based on the remaining capacity, access latency, link load, fault domain, and data affinity of each computing node, and avoids local overload of a single computing motherboard or computing node while other nodes are idle through cross-board capacity balancing.

[0045] (3) Hot and cold data recognition module This module integrates information such as access time relationships, continuous access trends, read / write direction, reuse intervals, task stages, data types, and whether it is on the critical path of the main computation to form a heat status, rather than relying on a single access count. Hot data refers to data that is currently participating in the main computation or has been continuously reused recently; warm data refers to data that has potential reuse value but is not currently accessed continuously; cold data refers to data that is accessed less frequently in the current task stage, can be used later, or will consume local resources if it resides for a long time. The module smooths out short-term bursts of access and sets a stable observation state after migration to avoid triggering reverse migration due to slight changes in heat.

[0046] (4) Cross-layer memory migration controller The controller employs an asymmetric dual-threshold waterline mechanism to manage migration out and in, enabling the management of CXL pooled memory resources on member compute motherboards / compute nodes. Migration out conditions focus on local main memory pressure, data cooling level, and reclaimable space, while migration in conditions focus on data warming trends, the upcoming compute phase, and main path access requirements. These two types of conditions use different decision boundaries, coupled with hysteresis zones and migration cooling states, ensuring that data only moves across layers when the state change is persistent. The migration process includes candidate screening, target space reservation, data replication, write confirmation, mapping switching, consistency processing, and old copy reclamation. If link congestion or increased main compute requests occur, the CXL controller can pause or reduce migration batches. The migration includes cross-layer migration between UMA local main memory and any member compute node, migration between remote nodes and local nodes via the CXL control module + CPO link, and cross-node rebalancing migration between different member compute nodes. After cross-node migration is completed, the compute node or compute motherboard identifier, physical location, and consistency status are updated synchronously.

[0047] (5) Task scheduler The task scheduler integrates computation tasks, page fault handling, data prefetching, background migrations, and maintenance requests into a unified arbitration. The primary computation path and its urgent page fault requests have high priority, while background migrations utilize idle windows between computation phases. The scheduler throttles based on CXL link load, breaking large-scale migrations into interruptible batches and initiating predictive migrations before model layer switching, expert activation, long context expansion, or changes in the graph computation phase. Through a pipelined approach, data migration can overlap with heterogeneous computation, with the migration completion event driving subsequent tasks to continue execution.

[0048] For cross-node access, the scheduler simultaneously reads the health and congestion status of the CPO optical link. When the optical link is available, a remote access queue is established. In the event of synchronization anomalies, optical power anomalies, or persistent bit errors, new requests are restricted and backup paths or local migrations are triggered. When multiple member compute nodes or compute motherboards can simultaneously serve the target data, the task scheduler combines the bandwidth, queue depth, link distance, and fault domain of the compute nodes or compute motherboards to select the access or migration path, and can distribute different requests to different compute nodes or compute motherboards for parallel execution.

[0049] The aforementioned software modules form a closed loop through a unified metadata directory: the address mapping unit provides location and access facts, the hot / cold identification module updates data status, the hierarchical manager generates placement targets, the migration controller implements location changes, and the task scheduler determines execution timing and link occupancy. If any module detects a fault or inconsistency in status, it can prevent mapping switching and trigger a recovery process to ensure the stability of upper-layer access semantics. This closed loop uses a unified pooled memory resource view for the local host as the management object, and compute nodes or compute motherboards, onboard CXL extended memory resources, and CPO / fiber links as the corresponding resource and fault granularities. While maintaining the physical deployment independence of each compute node, it achieves unified discovery, allocation, and reclamation of cross-node resources.

[0050] Example 2: A heterogeneous computer memory allocation method based on unified and pooled memory Based on the aforementioned hardware foundation and software module logical architecture design, this embodiment also provides a heterogeneous computer memory allocation method based on unified and pooled memory, which can be applied to the heterogeneous computer system as described in Embodiment 1. Figure 3 This is a flowchart illustrating the memory allocation method provided in Embodiment 2 of the present invention. The method includes the following steps: Step S301: Initialize the system and verify the device availability of the local node and the remote node.

[0051] After system startup, initialization operations are performed first. This includes, but is not limited to, self-testing and configuring the hardware of local node 100, such as the computing chip module 110, local memory 120, CXL controller 130, onboard extended memory 140, and near-end optical engine module 150. Simultaneously, through the interaction between the near-end optical engine module 150 and the far-end optical engine module 210, the availability of the equipment on the far-end node 200 is detected and verified, confirming the fiber optic link status and the capacity and access method of the poolable memory resources connected to the interconnection control module of the far-end node. This step is a prerequisite for building a unified memory pool, ensuring that all hardware resources participating in the pooling are in normal working order.

[0052] Step S302: Divide the memory of the local node into local exclusive memory and pooled shared memory for the local host.

[0053] According to the configuration strategy, the system logically partitions the physical memory of local node 100 (mainly based on local memory 120 of the UMA architecture). One portion is designated as a dedicated local memory zone, used exclusively by the computing chip module 110 of local node 100 itself. This zone stores operating system kernels, critical process data, or frequently accessed hot data that are extremely sensitive to access latency, ensuring access performance and determinism. The other portion is designated as a pooled shared memory zone. This memory is used as a contribution resource to build a unified pooled memory resource pool, which is incorporated into a unified address view as a poolable or migrateable local resource for the local host. Cross-node access by external heterogeneous computing nodes is limited by independent address views and access permissions. This partitioning ensures both the memory performance of core local services and the sharing of idle memory resources.

[0054] Step S303: The pooled shared area memory, the onboard extended memory of the local node, and the poolable memory module that the remote node opens to the local host through the computing fast link and optical engine link are used to construct a unified pooled memory resource pool for the local host through a unified address mapping relationship.

[0055] The system establishes a unified address mapping relationship through the CXL controller 130. Specifically, the pooled shared memory area, the onboard extended memory 140 of the local node 100, and the poolable memory modules of the remote node 200, which were partitioned in step S302, are addressed or mapped in the unified address view of the local host to construct a logically continuous and unified pooled memory resource pool. In this process, the system establishes corresponding logical addresses for each physical memory resource in the pool and maintains an address mapping table, so that any access request initiated by any computing unit can be correctly routed to the corresponding physical memory location according to its target address. For extended memory that is scattered across multiple computing motherboards or computing nodes, this step integrates it into a single virtual memory pool through global addressing and a unified discovery mechanism, shielding the complexity of the underlying physical distribution.

[0056] Step S304: Logically partition the unified pooled memory resource pool and set access priorities and access permissions.

[0057] To more effectively manage and utilize the unified pooled memory resource pool, the system further logically partitions it. For example, based on data access frequency and importance, the pool can be divided into hot data, warm data, and cold data areas; or based on data usage, it can be divided into compute data, cache data, and metadata areas, etc. Simultaneously, access priorities and access permissions are set for different partitions or memory objects. Access priorities determine which data or requests can be served first during resource contention; access permissions specify the read, write, or execute permissions of different computing units (including local and external) for specific memory areas, thereby ensuring data security and resource isolation in multi-tenant or multi-tasking environments. This step is crucial for achieving fine-grained management and ensuring service quality.

[0058] In the system's pooling process, the control mapping layer collects the available range, reserved range, health status, and access attributes of the UMA local main memory and onboard CXL extended memory, and registers them as different levels in the unified resource pool.

[0059] The memory tier manager determines the priority scope of the local tier based on operating system reservation requirements, current business type, and main computing path needs, and includes the remaining available resources in dynamic allocation. When an application requests memory, the system first establishes a unified virtual address, and then selects the initial physical location based on the data type and task stage.

[0060] During operation, the system continuously monitors the water level and link status of each layer of space; after task release, data failure, or migration is completed, the corresponding physical pages are reclaimed and the resource catalog is updated to ensure that the resource pool status is consistent with the actual occupancy.

[0061] For onboard CXL extended memory distributed across multiple compute motherboards or compute nodes, the control mapping layer collects information on each compute motherboard or compute node, including board-by-board identifier, onboard address window, available capacity, link status, and fault domain information. Each compute motherboard or compute node is then registered as a member resource in the global memory pool. The global resource catalog provides a unified capacity view while preserving the physical boundaries of each compute motherboard or compute node. During allocation, the system first selects the target member compute motherboard or compute node from the global memory pool, and then selects physical pages or data blocks within that compute motherboard or compute node. When a compute motherboard or compute node is added, removed, its capacity changes, or it is fault-isolated, the system updates the member list and the global available capacity, and performs cross-compute rebalancing as needed.

[0062] Step S305: When responding to a data access request initiated locally, determine the local memory, local onboard extended memory, or remote poolable memory module where the target data is located based on the request address. If the target data is located in a remote poolable memory module, perform cross-node access by calculating the fast link controller and the optical engine link. After the access request is completed, update the access priority of the accessed data in the unified pooled memory resource pool.

[0063] When the computing chip module 110 of the local node 100 initiates a data access request, the memory management unit or CXL controller 130 will determine the location of the data based on the target address of the request and perform corresponding scheduling.

[0064] Optionally, if the unified address view determines that the data is located in the private UMA or UMA pooled shared area of ​​the local node 100, the data can be accessed directly through the on-chip high-speed bus of the computing chip module 110 to reduce access latency.

[0065] Optionally, if the data is found to be located in the onboard extended memory 140 of the local node 100, memory semantic access is performed through the CXL controller 130. That is, the CXL controller 130 converts the access request into a message conforming to the CXL protocol and sends it to the corresponding onboard extended memory 140 via the onboard link to complete the data read / write operation. This process can maintain the corresponding consistency state under the support of the adopted CXL consistency or memory semantic mechanism.

[0066] After an access request is completed, the system updates the access priority of the accessed data in the unified pooled memory resource pool based on the characteristics of this access (such as access frequency, data volume, whether it is a write operation, etc.). For example, a page in a frequently accessed cold data area may have its access priority increased and may be considered for migration to a faster storage medium in subsequent memory management strategies (such as page migration). This dynamic priority update mechanism is the foundation for realizing data "hot" and "cold" identification and hierarchical management.

[0067] In one possible implementation, after a local large model training, inference, or graph computation task initiates a memory access request, the address space unified mapping unit resolves the virtual address and queries the data location.

[0068] If the data is located in the UMA's local main memory, it is accessed directly by the on-chip high-speed bus, and the access event is sent to the hot and cold data identification module. If the data is located in the onboard CXL extended memory, the memory semantic access is performed by the CXL controller.

[0069] For extension layer accesses occurring in the main computing path, the task scheduler determines whether to increase priority or trigger migration; if a page fault occurs or target data is being migrated, the system creates an emergency processing request to prioritize target space reservation, data acquisition, and mapping updates.

[0070] After the visit ends, the popularity status, reuse trend, and task stage are updated synchronously to provide a basis for subsequent placement decisions.

[0071] Step S306: When responding to a data access request initiated by an external heterogeneous computing power node, first perform identity authentication and permission verification on the external heterogeneous computing power node, and then control the access of the external heterogeneous computing power node to the unified pooled memory resource pool according to the local business load and the traffic of the optical engine module.

[0072] When an external heterogeneous computing node requests access to the unified pooled memory resource pool of this system via a fiber optic link, the system first authenticates the external heterogeneous computing node to verify its legitimacy, and performs permission verification according to the predefined access control list (ACL) to confirm whether it has the permission to access the memory region specified in the request.

[0073] After authentication and permission verification are successful, the system does not immediately grant access. Instead, it further evaluates the current system status to ensure the Quality of Service (QoS) of local services. The specific control methods are as follows: First, the current load rate of the local service is obtained. The load rate can be determined based on at least one of the following: CPU, GPU or NPU utilization, memory bandwidth usage, queue depth, or main computing task status. If the load rate of the local service is higher than a first threshold, data access requests from external heterogeneous computing nodes are inserted into a low-priority queue to reduce the impact on the local service. The first threshold can be set according to system configuration; for example, the corresponding utilization threshold can be set to 80%.

[0074] Secondly, the system obtains the current signal quality indicators and available bandwidth of the optical engine module. These signal quality indicators include at least one of the following: bit error rate, optical power, synchronization lock status, or link training status. If the current signal quality of the optical engine module is lower than a second threshold (e.g., increased bit error rate) or the available bandwidth is lower than a third threshold (e.g., less than 20% of the total bandwidth remaining), it indicates that the fiber optic link is in poor condition or is close to saturation. In this case, continuing to execute external heterogeneous computing node access requests may lead to increased latency or transmission failure. Therefore, the system will delay the execution of the request until the link status is restored.

[0075] Finally, the system obtains the number of external heterogeneous computing nodes currently occupying the fiber optic physical link and the link bandwidth usage of each external heterogeneous computing node. To make fair and efficient use of limited inter-node bandwidth resources, the system dynamically allocates the execution timing of data access requests from each external heterogeneous computing node based on a weighted round-robin or fair queue algorithm. This ensures that there will be no unfair phenomena such as "starvation" or "bandwidth contention" among multiple external heterogeneous computing nodes, thus guaranteeing overall performance in scenarios with concurrent access from multiple external heterogeneous computing nodes.

[0076] like Figure 4 As shown, in one possible implementation, when an external heterogeneous computing node is connected, a physical fiber optic link is first established through the CPO optical engines at both ends, and the optical module status, CXL link capability, node identity, and access range are verified.

[0077] After verification, the control mapping layer establishes a restricted address view for external heterogeneous computing nodes and synchronizes the address directory and consistency attributes of their accessible data.

[0078] After the data request from the external heterogeneous computing power node arrives, the permission arbitration logic verifies the correspondence between the node, the task, and the target area. The task scheduler then allocates access opportunities based on the local business load, CPO optical link status, and link occupancy.

[0079] For data requests from external heterogeneous computing nodes that continuously occupy the link, the system implements bandwidth limiting and queue reshaping to avoid affecting the local main computing path.

[0080] When an external node reads or writes data to the authorized pooled memory resources, the CXL controller and consistency management logic complete the state transition, failure notification, and write confirmation. The CPO module only undertakes the lower-level physical signal conversion and transmission. When a node exits or an exception occurs, the system revokes its address mapping and permissions and cleans up any incomplete transactions.

[0081] The memory allocation method in this embodiment, based on the aforementioned system architecture, constructs a unified pooled memory resource pool through refined software management and achieves intelligent scheduling of access requests from local and external heterogeneous computing nodes. This method can dynamically adjust the storage location or priority of data based on its access frequency, achieving a balance between performance and cost. Simultaneously, through identity authentication, permission verification, and traffic control mechanisms, it ensures security and fairness of multi-node access in the memory pooled environment, effectively improving resource utilization efficiency in distributed and high-concurrency computing scenarios.

[0082] Example 3: Access scheduling and migration mechanism.

[0083] Based on the above method embodiments, this system also has an access scheduling and migration mechanism to ensure the stability and reliability of the system.

[0084] Data access scheduling: When a page fault occurs during local access, the target data is located in an extended or remote memory layer with higher access latency than the local UMA, or the target data belongs to the main computation path data of the current computation task, the system increases the scheduling priority of the corresponding access request and may trigger the migration of the target data to the local UMA, target space reservation, and address mapping update. For address or media failures such as reclaimed pages or ECC errors, an independent fault-tolerance process is initiated, performing fault isolation, data recovery, or address remapping.

[0085] External heterogeneous computing node anomaly handling mechanism: The system continuously monitors the status of external heterogeneous computing nodes. When an external heterogeneous computing node is detected to have exited normally or encountered an anomaly (such as link interruption or timeout failure), the system will proactively revoke the node's address mapping and access permissions, clean up its unfinished transactions, release the system resources it occupies, and prevent resource leakage and error propagation.

[0086] Furthermore, the system incorporates a built-in fault-tolerance mechanism. Through dedicated monitoring threads or modules, it continuously monitors system link status (including fiber optic links and onboard links), optical engine module status (such as temperature and optical power), memory status (such as ECC error counts), and whether power outages have occurred. When any anomaly or fault is detected, the system handles it according to predefined fault-tolerance strategies. For example, for correctable memory errors, only logs are recorded; for link degradation, data traffic on that link is reduced; for fatal faults, system-level failover or safe shutdown is triggered, and the administrator is notified. This continuous proactive monitoring and tiered fault-tolerance processing improves the system's reliability and serviceability under long-term, high-load operation.

[0087] like Figure 5 As shown, in one possible implementation, the system continuously monitors the CXL protocol status, CPO optical engine synchronization status, fiber optic link signal anomalies, memory particle access failures, bus or optical link congestion, and computing unit page faults.

[0088] When an optical link anomaly is detected, the local CPO optical engine suspends new transactions in the affected direction, retains the confirmed status, and re-executes synchronization and link training with the remote CPO optical engine. If the link cannot be restored, the control mapping layer marks the affected address as temporarily unreachable and triggers backup optical path switching, data migration, or address remapping.

[0089] When a memory media failure is detected, the system isolates the faulty page or data block, recovers the data from a valid copy, upper-level cache, or a reconstructable source, and updates the unified catalog.

[0090] When bandwidth congestion occurs, the task scheduler reduces the background migration rate, shrinks the migration batches, and prioritizes serving the main compute requests.

[0091] When a page fault occurs, the system establishes an emergency scheduling channel to suspend non-critical migrations and prioritize the migration of required data.

[0092] After the anomaly is resolved, each module checks the mapping, consistency, heat level, and optical link status, and gradually restores normal scheduling.

[0093] In one embodiment of the present invention, when the system includes multiple computing motherboards or computing nodes, each process further includes the following cooperative operations: During the system initialization process, the firmware and driver read the node identifier, onboard CXL extended memory capacity, address window, CXL / CPO port status and health status of each compute node or compute motherboard on a board-by-board basis, and establish a list of member compute nodes; compute motherboards / compute nodes that pass self-test and link verification are added to the global memory pool, and abnormal compute motherboards / compute nodes are kept isolated.

[0094] In the resource pooling process, the control mapping layer registers each compute motherboard / compute node as a member resource in the global memory pool. The global resource catalog provides a unified capacity view upwards while preserving the physical boundaries of each compute motherboard / compute node. During allocation, the system selects the target member compute motherboard / compute node in the global memory pool, and then selects a physical page or data block within that compute motherboard / compute node.

[0095] In the local business access process, when the address space unified mapping unit finds that the target data is located in the CXL extended memory of a member computing motherboard / computing node, the CXL controller completes cross-computing motherboard / computing node routing based on the computing motherboard / computing node identifier and the target address window.

[0096] In the external heterogeneous computing node access process, the external heterogeneous computing node accesses the global memory pool through a restricted address view, and multiple member computing motherboards / computing nodes undertake different access queues in parallel.

[0097] In the fault tolerance process, the system uses member computing motherboards or computing nodes as the fault isolation granularity. When a single computing motherboard or computing node or a single link fails, the corresponding computing motherboard or computing node is removed from the allocatable set, and the global memory pool service is maintained through other healthy computing motherboards or computing nodes.

[0098] The technical solution of this invention may be effective in the following application scenarios: (1) Large model training scenario During the training of large language models, model weights, optimizer states, activation values, and key-value caches require a large amount of memory.

[0099] In the initial stage, the system places the model weights and optimizer state in the UMA's local main memory to ensure computational efficiency in the early stages of training.

[0100] As training progresses, the hot and cold data identification module monitors the access frequency of each data block. For historical activation values ​​and some optimizer states with low access frequency, the memory tier manager migrates them to the onboard CXL extended memory, freeing up local memory space for the hot data required for the current iteration computation.

[0101] When training enters a new phase (such as switching from pre-training to fine-tuning), the task scheduler predictively triggers data migration, loading the parameters to be used into local memory in advance, thus achieving overlap between computation and migration.

[0102] (2) Collaborative inference scenario with multiple external heterogeneous computing power nodes When multiple external heterogeneous computing nodes (such as inference accelerator cards) collaboratively execute large model inference tasks: Each external heterogeneous computing node establishes a physical fiber optic link through the CPO optical engine and connects to the system after identity authentication and permission verification.

[0103] The control mapping layer establishes a restricted address view for each external heterogeneous computing node, limiting it to accessing only the model parameter area and preventing it from accessing other task data.

[0104] When an external heterogeneous computing node initiates a read request, the permission arbitration logic verifies the correspondence between its identity and the target region, and the task scheduler dynamically allocates access opportunities based on the local business load.

[0105] For external nodes that continuously read model parameters, the system implements bandwidth limiting to ensure that local training tasks always have priority bandwidth.

[0106] When an external heterogeneous computing node exits, the system automatically revokes its address mapping and permissions, cleans up any unfinished transactions, and does not affect the normal service of other nodes.

[0107] (3) Scenarios of single computing motherboard or computing node fault isolation Assume the system contains four compute motherboards or compute nodes A, B, C, and D, and each compute motherboard has onboard CXL extended memory soldered directly to the motherboard; if compute node B experiences a memory chip access failure in its onboard CXL extended memory: The system continuously detects timeouts or excessive error rates in the onboard CXL extended memory access of compute node B.

[0108] The control mapping layer marks the faulty CXL extended memory resources of compute node B as faulty, removes the corresponding capacity information from the unified resource catalog, and marks the corresponding physical address window as unreachable.

[0109] The task scheduler suspends access requests to the failed CXL extended memory resources of compute node B. Data already allocated to the failed resources is restored to the CXL extended memory resources of other healthy compute nodes through valid copies or reconstructable sources.

[0110] The system updates the global resource catalog and recalculates the total available capacity. The healthy CXL extended memory resources of the remaining compute nodes A, C, and D continue to provide services, and the global memory pool service is uninterrupted.

[0111] After the faulty resources are repaired and the self-test and link training are completed again, the system re-identifies the corresponding resources and adds them to the set of allocable resources, thereby achieving dynamic resource recovery.

[0112] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural transformations made using the contents of the specification and drawings of the present invention under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of the present invention.

Claims

1. A heterogeneous computer system based on unified and pooled memory, characterized in that, include: Local and remote nodes are physically connected via optical fiber. The local node establishes a unified pooled memory resource view for the local host based on its local poolable memory resources and the poolable memory resources exposed to it by the remote node, for performing memory allocation and management; wherein, the local node includes: Computing chip module; Local memory based on a unified memory access architecture, wherein the local memory is coupled to the computing chip module; The computing fast link controller is connected to the computing chip module, and a plurality of onboard extended memory units are connected to the computing fast link controller. The computing fast link controller is used to receive and parse computing fast link transactions issued by the computing chip module, perform address resolution, access routing and protocol processing according to the address mapping relationship, and forward access requests to the onboard extended memory or the near-end optical engine module. A near-end optical engine module connected to the compute fast link controller is used to perform electro-optical conversion on the electrical signals output by the compute fast link controller and send them to the remote node, and to perform photoelectric conversion on the optical signals from the remote node and transmit them to the compute fast link controller. The remote node includes a remote optical engine module, a remote interconnect control module connected to the remote optical engine module, and a poolable memory module connected to the remote interconnect control module; the remote optical engine module is used to receive the optical signal from the near-end optical engine module and perform photoelectric conversion, and the remote interconnect control module is used to perform fast link transaction processing, access routing, and memory access control on the recovered electrical signal.

2. The heterogeneous computer system as described in claim 1, characterized in that, The computing chip module includes at least one of the following: a general-purpose processing unit, a graphics or parallel computing unit, a neural network acceleration unit, and other computing acceleration units, which are interconnected via an on-chip high-speed bus.

3. The heterogeneous computer system as described in claim 1, characterized in that, The onboard extended memory includes one or more sets of extended memory chips disposed on the computing motherboard of the local node, and the extended memory chips are connected to the computing fast link controller through printed circuit board traces on the computing motherboard.

4. The heterogeneous computer system as described in claim 1, characterized in that, The poolable memory module of the remote node includes compute fast link extended memory located on the remote computing motherboard and accessible to the local node through the remote interconnect control module.

5. A heterogeneous computer memory allocation method based on unified and pooled memory, applied to the heterogeneous computer system described in any one of claims 1 to 4, characterized in that, The memory allocation method includes: The system initializes and verifies the device availability of local and remote nodes; For the local host, the memory of the local node is divided into local exclusive memory and pooled shared memory; The pooled shared memory, the onboard extended memory of the local node, and the poolable memory module that the remote node exposes to the local host through the fast computing link and optical engine link are used to construct a unified pooled memory resource pool for the local host through a unified address mapping relationship. The unified pooled memory resource pool is logically partitioned, and access priorities and access permissions are set. When responding to a data access request initiated locally, the local memory, local onboard extended memory, or remote poolable memory module where the target data is located is determined based on the request address. If the target data is located in a remote poolable memory module, cross-node access is performed by calculating the fast link controller and the optical engine link. After the access request is completed, the access priority of the accessed data is updated in the unified pooled memory resource pool. When responding to a data access request initiated by an external heterogeneous computing node, the external heterogeneous computing node is first authenticated and its permissions are verified. Then, based on the local business load and the traffic of the optical engine module, the access of the external heterogeneous computing node to the unified pooled memory resource pool is controlled.

6. The heterogeneous computer memory allocation method as described in claim 5, characterized in that, When responding to a data access request initiated locally, it also includes: If the data is found to be located in the local memory of the local node, the data is accessed through the on-chip high-speed bus of the computing chip module. If the data is found to be located in the onboard extended memory of the local node, memory semantic access is performed through the compute fast link controller; if the data is found to be located in poolable memory resources opened by the remote node to the local node, cross-node compute fast link memory semantic access is performed through the local compute fast link controller, near-end optical engine module, fiber link, remote optical engine module, and remote interconnection control module.

7. The heterogeneous computer memory allocation method as described in claim 6, characterized in that, It also includes access scheduling and migration mechanisms: when a local data access request results in a page fault, the target data is located in an extended or remote memory layer with priority access latency relative to local memory, or the target data belongs to the main computing path data of the current computing task, the scheduling priority of the data access request is increased and / or the target data is migrated to local memory, and the corresponding address mapping is updated.

8. The heterogeneous computer memory allocation method as described in claim 5, characterized in that, When responding to a data access request initiated by an external heterogeneous computing node, the method for controlling the access of the external heterogeneous computing node to the unified pooled memory resource pool is as follows: Get the current load rate of the local service. If the load rate of the local service is higher than the first threshold, insert the data access request of the external heterogeneous computing power node into the low priority queue. The current signal quality indicators and available bandwidth of the optical engine module are obtained. The signal quality indicators include at least one of bit error rate, optical power, synchronization lock status and link training status. If the current signal quality of the optical engine module is lower than the second threshold or the available bandwidth is lower than the third threshold, the data access request of the external heterogeneous computing power node will be delayed. The system obtains the number of external heterogeneous computing nodes currently occupying the optical fiber physical link and the link bandwidth occupancy of each external heterogeneous computing node, and allocates the execution timing of the data access request based on a weighted round-robin or fair queue algorithm.

9. The heterogeneous computer memory allocation method as described in claim 8, characterized in that, It also includes an exception handling mechanism: when the external heterogeneous computing power node exits or an exception occurs, the address mapping and access permissions of the external heterogeneous computing power node are revoked, and its unfinished transactions are cleaned up.

10. The heterogeneous computer memory allocation method as described in claim 5, characterized in that, It also includes fault tolerance mechanisms: continuously monitoring system link status, optical engine module status, memory status, and power outage events. When an anomaly or fault is detected, at least one fault tolerance process is executed based on the anomaly type, including restricting new transactions, retraining the link, marking affected addresses as unreachable, switching to backup paths, data migration, address remapping, and fault memory isolation.

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