A fault response method, apparatus, device and readable storage medium

Abstract

The present specification provides a fault response method, device, equipment and readable storage medium, which is applied to a baseboard management controller (BMC), and the method comprises the following steps: in response to an in-band interrupt request sent by a complex programmable logic device (CPLD) through an I3C bus, suspending a task being executed, initiating a read request to the CPLD, and obtaining fault state information stored in the CPLD; the in-band interrupt request is automatically generated by the CPLD when a hardware component is monitored to have a fault; the fault state information is recorded in a fault state register of the CPLD by the CPLD when the hardware component is monitored to have the fault; and a fault hardware is identified according to the fault state information, and a preset fault processing is performed. Through the technical scheme of the present specification, transient fault capture and active alarm can be realized, and fault alarm fast response can be realized while reducing hardware overhead.

Description

Technical Field

[0001] This specification relates to the field of communication technology, and in particular to a fault response method, apparatus, device, and readable storage medium. Background Technology

[0002] As the core equipment of a data center, the stable operation of servers is crucial. Hardware failures (such as power overcurrent, voltage regulator malfunction, and overheating) that are not detected and addressed promptly can lead to business interruptions, data loss, or even hardware damage. Therefore, efficient and reliable fault monitoring of server hardware is a key aspect of ensuring the stable operation of a data center.

[0003] Currently, servers commonly use a Baseboard Management Controller (BMC) to poll the hardware for out-of-band monitoring. However, the fault detection time in this approach depends entirely on the polling cycle, and the polling scheme results in significant resource waste. Another existing technology relies on GPIO hardware interrupt pins for fault reporting. However, this approach suffers from GPIO resource bottlenecks and high motherboard wiring complexity. Summary of the Invention

[0004] In view of this, this specification provides a fault response method, apparatus, electronic device, and readable storage medium to improve the problems of low resource utilization and lack of transient fault capture mechanism in server fault monitoring.

[0005] Specifically, the technical solution is as follows: This specification provides a fault response method. It is applied to a Baseboard Management Controller (BMC), which is used for server management. The fault alarm signal pins of the managed hardware components are connected to a Complex Programmable Logic Device (CPLD). The CPLD is connected to the BMC via an I3C bus. The method includes: In response to an in-band interrupt request sent by the CPLD via the I3C bus, the executing task is paused, and a read request is sent to the CPLD to obtain the fault status information stored in the CPLD. The in-band interrupt request is actively generated by the CPLD when it detects a hardware component failure. The fault status information is recorded by the CPLD in the CPLD's fault status register when it detects a hardware component failure. Based on the fault status information, identify the faulty hardware and execute the preset fault handling.

[0006] Furthermore, the in-band interrupt request includes CPLD device information and an interrupt status identifier; The CPLD device information is used to determine the source of the interrupt request; the interrupt status identifier is used to carry the basic fault type so that the BMC can call the processing routine corresponding to the basic type to read the fault status information.

[0007] Furthermore, the execution of preset fault handling includes: Record a fault log; the fault log includes a timestamp. An alarm is issued based on the fault status information; In response to a fault that threatens system security, perform a shutdown or isolate the faulty hardware.

[0008] This specification also provides a fault response device applied to a baseboard management controller (BMC). The BMC is used for server management, and the fault alarm signal pins of the managed hardware components are connected to a complex programmable logic device (CPLD). The CPLD is connected to the BMC via an I3C bus. The device includes: The fault acquisition module is used to respond to the in-band interrupt request sent by the CPLD via the I3C bus, suspend the executing task, initiate a read request to the CPLD, and obtain the fault status information stored in the CPLD; the in-band interrupt request is actively generated by the CPLD when it detects a hardware component failure; the fault status information is recorded by the CPLD in the CPLD's fault status register when it detects a hardware component failure. The fault handling module is used to identify faulty hardware based on the fault status information and execute preset fault handling.

[0009] Furthermore, the in-band interrupt request includes CPLD device information and an interrupt status identifier; The CPLD device information is used to determine the source of the interrupt request; the interrupt status identifier is used to carry the basic fault type so that the BMC can call the processing routine corresponding to the basic type to read the fault status information.

[0010] Furthermore, the fault handling module includes: The logging module is used to record fault logs; the fault logs include timestamps. The fault alarm module is used to issue alarms based on fault status information; The security module responds to faults that threaten system security by performing shutdown or hardware isolation.

[0011] This specification also provides an electronic device including a processor and a readable storage medium storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the aforementioned fault response method.

[0012] This specification also provides a readable storage medium storing machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the aforementioned fault response method.

[0013] The technical solutions provided in this specification offer at least the following beneficial effects: The technical solution described in this manual enables transient fault capture and proactive alarm, achieving rapid fault alarm response while reducing hardware overhead. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings of the embodiments of this specification.

[0015] Figure 1 This is a flowchart of a fault response method in one embodiment of this specification; Figure 2 This is a schematic diagram of the fault response hardware connection in one embodiment of this specification; Figure 3 This is a flowchart of a fault response method in one embodiment of this specification; Figure 4 This is a structural diagram of a fault response device according to one embodiment of this specification; Figure 5 This is a hardware structure diagram of an electronic device according to one embodiment of this specification. Detailed Implementation

[0016] The terminology used in the embodiments described herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The singular forms “a,” “described,” and “the” as used in this specification and claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to any and all possible combinations comprising one or more of the associated listed items.

[0017] It should be understood that although the terms first, second, third, etc., may be used to describe various information in embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" may also be interpreted as "when," "when," or "in response to a determination."

[0018] As the core equipment of a data center, the stable operation of servers is crucial. Server hardware failures (such as power overcurrent, voltage regulator malfunction, and overheating) that are not detected and addressed promptly can lead to business interruptions, data loss, or even hardware damage. Therefore, efficient and reliable fault monitoring of server hardware is a key aspect of ensuring the stable operation of a data center. Currently, servers commonly use Baseboard Management Controllers (BMCs) for out-of-band hardware monitoring. A BMC is an independent embedded system that does not rely on the server's main CPU or operating system, enabling remote management and monitoring of the server.

[0019] The current mainstream implementation involves the BMC connecting to various hardware components (such as power modules, fans, temperature sensors, and voltage regulators) via low-speed serial buses like I2C. The monitoring software within the BMC periodically (usually once per second or every few seconds) sends read commands to each hardware component to query its status register or sensor data. It determines whether a fault has occurred by checking if the read values ​​exceed preset thresholds. When a fault is detected, the BMC records an event log, reports an alarm, and may execute preset protection actions (such as a reset). However, this approach has several drawbacks. First, the fault detection time depends entirely on the polling cycle and cannot capture transient faults. Second, this polling scheme results in significant resource waste. Most of the time, the hardware components are in normal working order, but the polling mechanism continues to perform numerous invalid read operations, consuming the BMC's CPU processing time and bus bandwidth, and impacting the efficiency of other management tasks.

[0020] Besides polling, another existing technical solution is a fault reporting method based on GPIO hardware interrupt pins. This solution utilizes dedicated GPIO interrupt pins to achieve real-time fault reporting. Specifically, a dedicated GPIO interrupt pin is added to the hardware component during design. This pin is directly connected to the GPIO input pin of the BMC. When the hardware component detects a fault (such as overcurrent or overtemperature), it actively pulls the interrupt pin high or outputs a pulse signal. Upon detecting the level change, the BMC's GPIO controller triggers a hardware interrupt. The BMC CPU immediately responds to the interrupt, reading the hardware component's fault status register via I2C or other buses to obtain detailed fault status information and execute corresponding processing. Although the hardware interrupt pin-based solution is faster than polling, it suffers from issues in practical server applications, such as occupying GPIO pins and increasing motherboard wiring complexity.

[0021] In view of this, this specification provides a fault response method, apparatus, electronic device, and readable storage medium to improve the problems of low resource utilization and lack of transient fault capture mechanism in server fault monitoring.

[0022] Specifically, the technical solution is described below.

[0023] This specification provides a fault response method applied to a Baseboard Management Controller (BMC). The BMC is used for server management. The fault alarm signal pins of the managed hardware components are connected to a Complex Programmable Logic Device (CPLD). The CPLD is connected to the BMC via an I3C bus. The method includes: In response to an in-band interrupt request sent by the CPLD via the I3C bus, the executing task is paused, and a read request is sent to the CPLD to obtain the fault status information stored in the CPLD. The in-band interrupt request is actively generated by the CPLD when it detects a hardware component failure. The fault status information is recorded by the CPLD in the CPLD's fault status register when it detects a hardware component failure. Based on the fault status information, identify the faulty hardware and execute the preset fault handling.

[0024] Specifically, such as Figure 1 This includes the following steps: Step S11: In response to the in-band interrupt request sent by the CPLD via the I3C bus, the executing task is paused, a read request is sent to the CPLD, and the fault status information stored in the CPLD is obtained.

[0025] The in-band interrupt request is actively generated by the CPLD when it detects a hardware component failure; the fault status information is recorded by the CPLD in the CPLD's fault status register when it detects a hardware component failure.

[0026] In one embodiment, the hardware connection is as follows Figure 2 As shown. Connect the fault alarm signal pins of the hardware components in the server (such as secondary power supply modules, voltage regulators, etc.; this manual does not limit the monitored hardware components) to the input pins of the CPLD; connect the CPLD as a slave device on the I3C bus to the I3C controller of the BMC; the CPLD internally implements the fault signal acquisition logic and the I3C slave device interface logic.

[0027] The CPLD monitors fault alarm signals (level changes or pulses) of each critical hardware component in real time. When any hardware component alarm signal is detected to be valid, the CPLD immediately sends an I3C in-band interrupt (IBI) request to the BMC via the I3C bus. The I3C IBI interrupt is transmitted through the bus protocol without the need for additional hardware pins. The interrupt request contains CPLD device information and interrupt status identifier.

[0028] Upon receiving an IBI request, the BMC's I3C controller hardware can immediately trigger the BMC processor to respond to the interrupt via a hardware interrupt mechanism, even if the BMC processor is processing other tasks. Due to the characteristics of IBI interrupts, the BMC processor may need to interrupt other tasks to ensure a response to the IBI request. In response to the interrupt, the BMC processor initiates a read operation to the CPLD via the I3C bus within microseconds, reading the fault status register maintained internally by the CPLD. The fault status register records the specific hardware component number that triggered the interrupt and the fault type.

[0029] Step S12: Identify the faulty hardware based on the fault status information and perform preset fault handling.

[0030] The preset fault handling is based on the user-preset handling scheme, which may only issue an alarm, or perform further fault isolation and / or system operation strategy adjustments; this specification does not impose any limitations. In one embodiment, the preset fault handling includes notifying the user terminal via software or illuminating a hardware fault indicator. In another embodiment, the preset fault handling includes isolating the faulty device. If the isolated faulty device affects the overall system operation, a critical alarm flag will be triggered and / or the system will be shut down according to the actual operating scenario and safety requirements, following the preset fault handling.

[0031] In one embodiment, the in-band interrupt request includes CPLD device information and an interrupt status identifier; The CPLD device information is used to determine the source of the interrupt request; the interrupt status identifier is used to carry the basic fault type so that the BMC can call the processing routine corresponding to the basic type to read the fault status information.

[0032] The CPLD device information includes the CPLD device address, enabling the BMC to distinguish the CPLD device that issued the interrupt from other devices (CPLD devices and / or non-CPLD devices) on the I3C bus, thereby identifying the CPLD device that issued the interrupt and reading the fault status information from the fault status register of the CPLD device that issued the interrupt.

[0033] If necessary, for example, in cases of complex faults, the BMC can utilize the basic fault type carried in the interrupt status identifier to prioritize calling the required processing routines derived from the basic fault type before reading the contents of the fault status register, thereby further improving the response speed of fault handling.

[0034] In one embodiment, the execution of preset fault handling includes: Record a fault log; the fault log includes a timestamp. An alarm is issued based on the fault status information; In response to a fault that threatens system security, perform a shutdown or isolate the faulty hardware.

[0035] One possible monitoring process is as follows: Figure 3 As shown. After the CPLD detects an alarm, it sends an IBI to the BMC via the I3C bus. The BMC responds to the interrupt based on the read fault status information. Since the IBI generally does not contain the specific hardware identifier of the fault, the BMC needs to further read the fault status register. After recognizing the content read from the fault status register, the BMC records the fault event in the System Event Log (SEL) with a precise timestamp. The BMC illuminates the fault indicator light of the corresponding hardware component; if the fault endangers system safety (such as CPU overvoltage), it immediately triggers system shutdown or isolation; after execution, the CPLD clears the fault status register, preparing to detect the next fault. It should be noted that the alarm method can be a highly visual hardware method (such as a fault indicator light), or a software method or other methods that can implement alarm functions; this manual does not limit the alarm method.

[0036] By applying the solutions in this manual, transient faults can be captured and actively alarmed, achieving rapid fault alarm response while reducing hardware overhead.

[0037] This specification also provides a fault response device 41, such as Figure 4 As shown, an application is made to a baseboard management controller (BMC), which is used for server management. The fault alarm signal pins of the managed hardware components are connected to a complex programmable logic device (CPLD). The CPLD is connected to the BMC via an I3C bus. The device includes: The fault acquisition module 42 is used to respond to the in-band interrupt request sent by the CPLD via the I3C bus, suspend the executing task, initiate a read request to the CPLD, and obtain the fault status information stored in the CPLD; the in-band interrupt request is actively generated by the CPLD when it detects a hardware component failure; the fault status information is recorded by the CPLD in the CPLD's fault status register when it detects a hardware component failure. The fault handling module 43 is used to identify faulty hardware based on the fault status information and perform preset fault handling.

[0038] In one embodiment, the in-band interrupt request includes CPLD device information and an interrupt status identifier; The CPLD device information is used to determine the source of the interrupt request; the interrupt status identifier is used to carry the basic fault type so that the BMC can call the processing routine corresponding to the basic type to read the fault status information.

[0039] In one embodiment, the fault handling module includes: The logging module is used to record fault logs; the fault logs include timestamps. The fault alarm module is used to issue alarms based on fault status information; The security module responds to faults that threaten system security by performing shutdown or hardware isolation.

[0040] The implementation methods of the apparatus are the same as or similar to the corresponding implementation methods, and will not be described again here.

[0041] In one embodiment, this specification provides an electronic device 51, such as... Figure 5 It includes a processor 52 and a readable storage medium 53, the readable storage medium storing machine-executable instructions 54 that can be executed by the processor, the processor executing the machine-executable instructions to implement the aforementioned fault response method.

[0042] In one embodiment, this specification provides a readable storage medium storing machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the aforementioned fault response method.

[0043] Here, a readable storage medium can be any electronic, magnetic, optical, or other physical storage device that can contain or store information, such as executable instructions, data, etc. For example, a readable storage medium can be: RAM (Random Access Memory), volatile memory, non-volatile memory, flash memory, storage drives (such as hard disk drives), solid-state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or combinations thereof.

[0044] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which can take the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email sending and receiving device, game console, tablet computer, wearable device, or any combination of these devices.

[0045] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware components.

[0046] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification can take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software and hardware aspects. Furthermore, embodiments of this specification can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0047] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments thereof. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0048] Furthermore, these computer program instructions can also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in the process. Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0049] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0050] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification can take the form of a completely hardware implementation, a completely software implementation, or an implementation combining software and hardware aspects. Furthermore, this specification can take the form of a computer program product implemented on one or more computer-usable storage media (which may include, but are not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0051] The above description is merely an embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims of this specification.

Claims

1. A fault response method, characterized in that, The method is applied to a baseboard management controller (BMC) used for server management. The fault alarm signal pins of the managed hardware components are connected to a complex programmable logic device (CPLD). The CPLD is connected to the BMC via an I3C bus. The method includes: In response to an in-band interrupt request sent by the CPLD via the I3C bus, the executing task is paused, and a read request is sent to the CPLD to obtain the fault status information stored in the CPLD. The in-band interrupt request is actively generated by the CPLD when it detects a hardware component failure. The fault status information is recorded by the CPLD in the CPLD's fault status register when it detects a hardware component failure. Based on the fault status information, identify the faulty hardware and execute the preset fault handling.

2. The method according to claim 1, characterized in that, The in-band interrupt request includes CPLD device information and an interrupt status identifier; The CPLD device information is used to determine the source of the interrupt request; the interrupt status identifier is used to carry the basic fault type so that the BMC can call the processing routine corresponding to the basic type to read the fault status information.

3. The method according to claim 1, characterized in that, The execution of preset fault handling includes: Record a fault log; the fault log includes a timestamp. An alarm is issued based on the fault status information; In response to a fault that threatens system security, perform a shutdown or isolate the faulty hardware.

4. A fault response device, characterized in that, An application is provided in a baseboard management controller (BMC) for server management. The fault alarm signal pins of the managed hardware components are connected to a complex programmable logic device (CPLD). The CPLD is connected to the BMC via an I3C bus. The device includes: The fault acquisition module is used to respond to the in-band interrupt request sent by the CPLD via the I3C bus, suspend the executing task, initiate a read request to the CPLD, and obtain the fault status information stored in the CPLD; the in-band interrupt request is actively generated by the CPLD when it detects a hardware component failure; the fault status information is recorded by the CPLD in the CPLD's fault status register when it detects a hardware component failure. The fault handling module is used to identify faulty hardware based on the fault status information and execute preset fault handling.

5. The apparatus according to claim 4, characterized in that, The in-band interrupt request includes CPLD device information and an interrupt status identifier; The CPLD device information is used to determine the source of the interrupt request; the interrupt status identifier is used to carry the basic fault type so that the BMC can call the processing routine corresponding to the basic type to read the fault status information.

6. The apparatus according to claim 4, characterized in that, The fault handling module includes: The logging module is used to record fault logs; the fault logs include timestamps. The fault alarm module is used to issue alarms based on fault status information; The security module responds to faults that threaten system security by performing shutdown or hardware isolation.

7. An electronic device, characterized in that, include: A processor and a readable storage medium storing machine-executable instructions that can be executed by the processor to implement the method of any one of claims 1-3.

8. A readable storage medium, characterized in that, The readable storage medium stores machine-executable instructions that, when invoked and executed by a processor, cause the processor to implement the method described in any one of claims 1-3.

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