Detection circuit, fpga and method based on triple modular redundancy soft error mitigation core

Abstract

The present disclosure relates to the technical field of electronic device reliability design and aerospace application, in particular to a detection circuit, FPGA and method based on a triple modular redundancy soft error mitigation core. The detection circuit based on the triple modular redundancy soft error mitigation core comprises: a triple modular redundancy soft error mitigation core configured to manage data states of a configuration memory area based on a working state, generate and output state information identifying occurrence of a single event upset error, determine and output an error type, and perform error correction processing on error data; a state code monitoring circuit configured to receive the state information and store the state information to the configuration memory area; a switch debugging circuit configured to control a running state of the triple modular redundancy soft error mitigation core; and an error detection and correction counting circuit configured to count cumulative occurrence times of the error type. Not only can the fault tolerance of the system be enhanced, but also the maintainability and reliability of the system can be improved.

Description

Technical Field

[0001] This disclosure relates to the fields of electronic device reliability design technology and aerospace application technology, specifically to a detection circuit based on a triple-modular redundancy soft error mitigation core, an FPGA based on static random access memory, a data management method, and a computer-readable storage medium. Background Technology

[0002] In recent years, the rapid development of satellite technology has placed higher demands on the performance of onboard FPGA devices due to increasingly powerful functional requirements. Static Random Access Memory (SRAM) FPGAs, with their high density, high speed, and reprogrammable characteristics, have significant advantages over antifuse FPGAs and application-specific integrated circuits (ASICs). However, SRAM FPGAs are sensitive devices. Impacts from space particle radiation can cause Single Event Upsets (SEUs), where the data stored in the SRAM changes from 1 to 0 or from 0 to 1. This flip can cause data anomalies in memory or registers. When this flip occurs in the configuration RAM (CRAM) area, it can lead to FPGA malfunction and prevent the FPGA from functioning properly. Although SEU does not affect the electrically erasable programmable read-only memory (EEPROM) that stores the bit stream, and the contents of the CRAM can be restored after restarting the FPGA, SEU occurs frequently in the space irradiation environment. If the FPGA is restarted once an SEU occurs, the onboard FPGA will not work properly. Therefore, a separate SEU-resistant circuit and method must be designed for the onboard SRAM FPGA. Summary of the Invention

[0003] To overcome the problems existing in related technologies, an exemplary embodiment of this disclosure provides a detection circuit based on a triple modular redundancy (TMR) soft error mitigation core, comprising: a TMR soft error mitigation core configured to manage the data state of a configuration memory region based on its operating state, generate and output state information identifying a single-event flip error, determine and output the error type, and perform error correction processing on the error data; the operating states include: a monitoring state, an error detection state, and an error correction state; a status code monitoring circuit connected to the TMR soft error mitigation core, configured to receive status information and store the status information in the configuration memory region; a serial-to-parallel conversion circuit connected to the TMR soft error mitigation core; a switch debugging circuit connected to the serial-to-parallel conversion circuit and the status code monitoring circuit, connected to the TMR soft error mitigation core through the serial-to-parallel conversion circuit, the switch debugging circuit being configured to control the operating state of the TMR soft error mitigation core based on its operating state; and an error correction and detection counting circuit connected to the serial-to-parallel conversion circuit, connected to the TMR soft error mitigation core through the serial-to-parallel conversion circuit, configured to count the cumulative occurrence count of error types.

[0004] In some embodiments, the serial-to-parallel conversion circuit includes a parallel-to-serial circuit and a serial-to-parallel circuit; the switch debugging circuit is connected to the error correction and counting circuit through the parallel-to-serial circuit; and the triple-modular redundancy soft error mitigation core is connected to the error correction and counting circuit through the serial-to-parallel circuit.

[0005] In some embodiments, the status code monitoring circuit, the parallel-to-serial conversion circuit, the serial-to-parallel conversion circuit, the switch debugging circuit, and the error correction and detection counting circuit all include three input terminals and one output terminal to achieve triple-modulus redundancy.

[0006] In some embodiments, the parallel-to-serial conversion circuit includes: three parallel-to-serial sub-circuits, each connected to a switch debugging circuit, configured to receive an enable signal and data to be processed sent in parallel by the switch debugging circuit, and to generate a serial candidate result corresponding to the enable signal through a built-in first triple-modulus redundancy counter; and a first majority voter, connected to each parallel-to-serial sub-circuit and to the triple-modulus redundancy soft error mitigation core, configured to receive the serial candidate results output by all parallel-to-serial sub-circuits, determine the target serial result, and send the target serial result to the switch debugging circuit to determine the control command to be sent to the triple-modulus redundancy soft error mitigation core, the control command being used to switch the operating state of the triple-modulus redundancy soft error mitigation core in the monitoring state.

[0007] In some embodiments, the triple modulus redundancy soft error mitigation core is configured to generate and output state information identifying a single-event upset error in the error detection state, and to determine and output the error type; the serial-to-parallel circuit includes: three serial-to-parallel circuits, each connected to the triple modulus redundancy soft error mitigation core, the serial-to-parallel sub-circuit being configured to receive the state information and error type serially transmitted by the triple modulus redundancy soft error mitigation core, and to generate parallel candidate results corresponding to the state information through a built-in second triple modulus redundancy counter; and a second majority voter, each serial-to-parallel sub-circuit being connected to and the error correction and detection counting circuit, the second majority voter being configured to receive the parallel candidate results output by all serial-to-parallel circuits, determine the target parallel result, and send the target parallel result to the error correction and detection counting circuit.

[0008] In some embodiments, the error correction and detection counting circuit includes: three error correction and detection counting sub-circuits, each connected to a second majority voter, configured to receive the target parallel result and determine candidate data error information; a third majority voter, each connected to one of the error correction and detection counting sub-circuits, configured to receive the candidate data error information output by all the error correction and detection counting sub-circuits and determine the target data error information; and an error count register, connected to the third majority voter, configured to count the cumulative number of times the target data error information corresponds to the error type.

[0009] In some embodiments, the error count register includes: an uncorrectable error count register and a correctable error count register; the uncorrectable error count register is connected to a third majority voter and is configured to count the cumulative number of times the target data error information corresponds to the uncorrectable error type; the correctable error count register is connected to the third majority voter and is configured to count the cumulative number of times the target data error information corresponds to the correctable error type; the error detection and correction counting circuit further includes: a stored error address register connected to the third majority voter, the stored error address register being configured to store the error address corresponding to the correctable error type, the error address being determined based on the target data error information.

[0010] In some embodiments, the triple-modular redundancy soft error mitigation core is also configured to perform flipping processing on error data based on the error address, and to trigger and send a circuit restart prompt when the error type corresponding to the error data is identified as an uncorrectable error type.

[0011] In some embodiments, the operating state further includes an error injection state; the switch debugging circuit includes: a switch circuit and an error injection debugging circuit connected to the switch circuit; the switch circuit, connected to the triple-modulus redundancy soft error mitigation core via a serial-to-parallel conversion circuit, is configured to send a power-on command when a rising edge is detected at the input of the switch signal and the triple-modulus redundancy soft error mitigation core is in a standby state, and to send a power-off command when a falling edge is detected at the input of the switch signal and the triple-modulus redundancy soft error mitigation core is in a detection state; the error injection debugging circuit, connected to the triple-modulus redundancy soft error mitigation core via a serial-to-parallel conversion circuit, is configured to send an error injection command when a rising edge is detected at the input of the switch signal and the triple-modulus redundancy soft error mitigation core is in a standby state, to control the triple-modulus redundancy soft error mitigation core to enter the error injection state and perform toggling processing on the error data at the specified error address.

[0012] Secondly, this disclosure also provides an FPGA based on static random access memory, including the detection circuit based on the triple-modular redundancy soft error mitigation core provided in any of the above aspects.

[0013] Thirdly, this disclosure also provides a data management method applied to the triple-modular redundancy soft error mitigation core of the FPGA based on static random access memory provided in any of the above aspects. The method includes: in a monitoring state, monitoring and receiving a control command sent by a switching debugging circuit; in response to the control command being a power-on command, switching the monitoring state to an error detection state and detecting the data status of the configuration memory region; if a single-event upset error is detected in the configuration memory region, generating status information and determining the error type; storing the status information through an error correction and detection counting circuit; counting the cumulative occurrence of the error type through the error correction and detection counting circuit; and in response to switching to an error correction state, performing error correction processing on the erroneous data in the configuration memory region.

[0014] In some embodiments, the error type includes correctable error type or non-correctable error type; the cumulative occurrence of error type is counted by the error correction and detection counting circuit, including: in response to the error type being correctable error type, the number of correctable errors is incremented by one by the error correction and detection counting circuit to update the cumulative occurrence of correctable error type, and the error address corresponding to correctable error type is saved;

[0015] In response to an error type that is uncorrectable, the number of uncorrectable errors is incremented by one by the error detection and correction counting circuit to update the cumulative number of occurrences of the uncorrectable error type.

[0016] In some embodiments, the method further includes: in response to an error type being correctable, performing a flipping operation on the error data based on the error address; or in response to an error type being uncorrectable, triggering and sending a circuit restart prompt.

[0017] In some embodiments, in the monitoring state, in response to receiving a control command sent by the switch debugging circuit, switching the monitoring state to the error detection state includes: in the monitoring state, in response to receiving a power-on command sent by the switch debugging circuit, switching the monitoring state to the error detection state; or in the monitoring state, in response to receiving an error injection command sent by the switch debugging circuit, switching the monitoring state to the error injection state, so as to perform flipping processing on the error data at the specified error address.

[0018] In some embodiments, the method further includes: in the error detection state, if the control command received from the switch debugging circuit is a power-off command, then entering the standby state.

[0019] Fourthly, this disclosure also provides a computer-readable storage medium storing a program for performing the data management method provided in any of the foregoing aspects.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure.

[0021] The technical solutions provided by the embodiments of this disclosure can include the following beneficial effects: According to the detection circuit based on a triple-modular redundancy soft error mitigation core provided by this disclosure, by using the triple-modular redundancy soft error mitigation core as a processing module, the fault tolerance of the system can be increased by utilizing the triple-modular redundancy principle without sacrificing performance. Furthermore, by combining multiple circuit modules, targeted management of data in the configuration area memory can be performed under different operating states or working conditions. This can minimize the impact of erroneous data in the event of a single-event upset, thereby improving data error correction accuracy and reducing the generation and impact of erroneous data. Moreover, by modularly designing the detection circuit based on the triple-modular redundancy soft error mitigation core, each circuit module can be guaranteed to have its corresponding function. This allows for targeted maintenance during subsequent module maintenance, reducing the difficulty of troubleshooting and thus contributing to the long-term development and upgrade of the system. In other words, the detection circuit based on a triple-modular redundancy soft error mitigation core provided by this disclosure not only enhances the fault tolerance of the system but also helps improve the maintainability and reliability of the system.

[0022] Furthermore, the detection circuit based on the triple-modal redundancy soft error mitigation core provided in this disclosure eliminates the need for adding a new FPGA as a single-event upset (SED) processing chip, effectively saving hardware costs. Attached Figure Description

[0023] This disclosure can be better understood by describing exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, in which:

[0024] Figure 1This is a structural framework diagram of a detection circuit based on a triple-modular redundancy soft error mitigation core, as shown in an exemplary embodiment of this disclosure.

[0025] Figure 2 This is a structural framework diagram of another detection circuit based on a triple-modular redundancy soft error mitigation core, as shown in an exemplary embodiment of this disclosure;

[0026] Figure 3 This is a circuit framework diagram of a circuit module shown in an exemplary embodiment of the present disclosure;

[0027] Figure 4 This is a structural framework diagram of a conventional state machine shown in an exemplary embodiment of the present disclosure;

[0028] Figure 5 This is a structural framework diagram of a state machine shown in an exemplary embodiment of the present disclosure;

[0029] Figure 6 This is a structural framework diagram of a conventional counter shown in an exemplary embodiment of the present disclosure;

[0030] Figure 7 This is a structural framework diagram of a counter shown in an exemplary embodiment of the present disclosure;

[0031] Figure 8 This is a schematic diagram of the control flow of a parallel-to-serial sub-circuit shown in an exemplary embodiment of the present disclosure;

[0032] Figure 9 This is a schematic diagram of the control flow of a serial-to-parallel converter circuit as shown in an exemplary embodiment of the present disclosure;

[0033] Figure 10 This is a schematic diagram of the control flow of an error detection and correction counting sub-circuit shown in an exemplary embodiment of the present disclosure;

[0034] Figure 11 This is a schematic diagram of the internal control flow of a switch debugging circuit as shown in an exemplary embodiment of the present disclosure;

[0035] Figure 12 This is a schematic diagram illustrating the instruction format received by an error injection interface in a linear frame address, as shown in an exemplary embodiment of this disclosure.

[0036] Figure 13 This is a flowchart illustrating a data management method according to an exemplary embodiment of the present disclosure;

[0037] Figure 14 This is a flowchart illustrating another data management method as shown in another exemplary embodiment of the present disclosure. Detailed Implementation

[0038] The following describes specific embodiments of this disclosure. It should be noted that, in order to provide a concise description, this specification cannot exhaustively describe all features of the actual embodiments. It should be understood that, in the actual implementation of any embodiment, just as in any engineering or design project, various specific decisions are often made to achieve the developer's specific goals and to meet system-related or business-related constraints, and this can change from one embodiment to another. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this disclosure, changes in design, manufacturing, or production based on the technical content disclosed in this disclosure are merely conventional technical means and should not be construed as insufficient content of this disclosure.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms “a” or “one,” etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” etc., mean that the element or object preceding “comprising” or “including” encompasses the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected,” “linked,” etc., are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections.

[0040] In related technologies, to address the single-event upset (SOME) problem in spaceborne FPGAs, an additional anti-fuse FPGA and three configuration areas storing the same configuration program are used to replace the data frames experiencing SOME. However, this approach not only increases hardware and storage costs, limiting its application scope, but also complicates error diagnosis and repair because the exact location of the erroneous data cannot be determined.

[0041] To address the aforementioned problems, an exemplary embodiment of this disclosure provides a detection circuit based on a triple-modular-redundant soft error mitigation core. For example... Figure 1 As shown, the detection circuit 100 based on the triple-modular redundancy soft error mitigation core may include: a triple-modular redundancy soft error mitigation core 110, a status code monitoring circuit 120, a serial-to-parallel conversion circuit 130, a switch debugging circuit 140, and an error correction and detection counting circuit 150. Figure 1The clock signal and reset signal are omitted, and all circuits are in the same clock domain.

[0042] The Tri-Mode Redundancy Soft Error Mitigation Core 110 is configured to manage the data status of the configuration memory region based on the working state, generate and output status information that identifies a single-event flip error, determine and output the error type, and perform error correction processing on the erroneous data. The working states include: monitoring state, error detection state, and error correction state.

[0043] Triple Modular Redundancy (TMR) is a reliability technique that achieves fault tolerance through redundant design and majority voting mechanisms. The TMR soft error mitigation core 110 can be understood as a processing module used to mitigate soft errors caused by single-event upsets, and it can utilize the principle of triple redundancy to increase the system's fault tolerance.

[0044] The Triple Modular Redundancy Soft Error Mitigation Core 110 is configured to manage the data status of the configuration memory region based on its operating state. This allows it to detect whether errors due to single-event upsets (SEORs) have occurred within the configuration region. Upon detecting an SEOR error, it generates and outputs corresponding status information, determines and outputs the corresponding error type, and enables timely error correction to mitigate the anomalies caused by SEORs, thus meeting the data management needs of different operating states. These operating states include: monitoring state, error detection state, and error correction state. For example, in the monitoring state, the Triple Modular Redundancy Soft Error Mitigation Core 110 can be configured to monitor the data status within the configuration memory region. In the error detection state, it can generate and output status information indicating the occurrence of an SEOR error, and determine and output the error type. In the error correction state, it can be configured to perform error correction processing on the erroneous data.

[0045] By employing the Triple Modular Redundancy Soft Error Mitigation Core 110 as the main logic circuit module, error data can be corrected using Repair or Enhanced Repair modes to reduce the interference of erroneous data on the system. In Repair mode, ECC check can be used to correct single-bit event-of-flight (SOF) events. In Enhanced Repair mode, Error Checking and Correcting (ECC) and Cyclic Redundancy Check (CRC) can be used simultaneously to correct SOF events between two adjacent bits. In some application scenarios, since SOF events are caused by high-energy particle bombardment, the probability of SOF events between two adjacent bits is relatively high; therefore, Enhanced Repair mode can be used as the repair mode for identifying and processing erroneous data.

[0046] The status code monitoring circuit 120, connected to the triple-modular redundancy soft error mitigation core 110, is configured to receive status information and store the status information in the configuration memory area.

[0047] The status code monitoring circuit 120 can be understood as a circuit module used to determine and record the status of the triple modular redundancy soft error mitigation core 110. By connecting the status code monitoring circuit 120 to the triple modular redundancy soft error mitigation core 110, the working or running state of the triple modular redundancy soft error mitigation core 110 can be determined. Furthermore, by storing the status information output by the triple modular redundancy soft error mitigation core 110 to the configuration memory area, it can help the triple modular redundancy soft error mitigation core 110 locate the problem and perform targeted processing based on the stored configuration information when the data in the configuration memory area is abnormal.

[0048] In some application scenarios, the status code monitoring circuit 120 can be connected to the monitoring interface of the triple-modulus redundancy soft error mitigation core 110. Since the Universal Asynchronous Receiver / Transmitter (UART) protocol is easier to implement, and the number of inputs and outputs should be minimized to resist SEU interference in space irradiation environments, the UART protocol is preferred as the data transmission protocol actually used by the monitoring interface. The UART serial port receives commands and prints report information in American Standard Code for Information Interchange (ASCII) format. Commands can be status query commands, allowing the status code monitoring circuit 120 to query the status of the triple-modulus redundancy soft error mitigation core 110 by sending a status query command to it.

[0049] The serial-to-parallel conversion circuit 130, connected to the triple modular redundancy soft error mitigation core 110, performs serial-to-parallel conversion on the data to be transmitted. For example, if the data was originally transmitted in serial format, the serial-to-parallel conversion circuit 130 can convert it to parallel format so that the triple modular redundancy soft error mitigation core 110 or other circuit modules can process the data quickly. As another example, if the data was originally transmitted in parallel format, the serial-to-parallel conversion circuit 130 can convert it to serial format so that the triple modular redundancy soft error mitigation core 110 or other circuit modules can process the data quickly.

[0050] The serial-to-parallel conversion circuit 130 can perform serial-to-parallel conversion on the data to be sent to the triple-modulus soft error mitigation core 110 or the data sent by the triple-modulus soft error mitigation core 110. This ensures that the triple-modulus soft error mitigation core 110 or other circuit modules connected to the serial-to-parallel conversion circuit 130 can process the data quickly, thereby helping to reduce data processing time, improve data transmission efficiency, and thus ensure the performance of the entire system.

[0051] The switch debugging circuit 140 is connected to the serial-to-parallel conversion circuit 130 and the status code monitoring circuit 120, and is connected to the triple-modulus redundancy soft error mitigation core 110 through the serial-to-parallel conversion circuit 130. The switch debugging circuit 140 is configured to control the operating status of the triple-modulus redundancy soft error mitigation core 110 based on the triple-modulus redundancy soft error mitigation core 110.

[0052] The switch debugging circuit 140 can be understood as a circuit module used for debugging and control. Its purpose is to manage and adjust the operating status of the triple modular redundancy soft error mitigation core 110. Connecting the switch debugging circuit 140 to the triple modular redundancy soft error mitigation core 110 through the serial-to-parallel conversion circuit 130 can enhance data format compatibility, ensure that data formats between different modules can interact normally, and meet the needs of managing and adjusting the operating status of the triple modular redundancy soft error mitigation core 110.

[0053] In some application scenarios, the switch debugging circuit 140 is connected to the status interface of the triple-modulus redundancy soft error mitigation core 110 via the serial-to-parallel conversion circuit 130. The status interface can use either UART or AXI protocol. Since the UART protocol is easier to implement and the number of inputs and outputs should be minimized to resist SEU interference in space irradiation environments, the UART protocol is preferred as the data transmission protocol used in practice. The UART serial port receives instructions and prints report information in American Standard Code for Information Interchange (ASCII) format. For example, the switch debugging circuit 140 can send control commands to the triple-modulus redundancy soft error mitigation core 110 via the serial-to-parallel conversion circuit 130 to change the operating state of the triple-modulus redundancy soft error mitigation core 110 according to its current operating state. The operating state can include standby state or operating state.

[0054] The error detection and counting circuit 150 is connected to the serial-to-parallel conversion circuit 130, and is connected to the triple-modular redundancy soft error mitigation core 110 through the serial-to-parallel conversion circuit 130. It is configured to count the cumulative occurrence of error types.

[0055] The error detection and counting circuit 150 can be understood as a circuit module that counts and statistically analyzes different error types. Error types can include correctable error types and non-correctable error types. Correctable error types can include, but are not limited to, single-bit errors and adjacent-bit errors. Non-correctable error types can include, but are not limited to, unlocatable errors and multi-bit errors.

[0056] By configuring the error detection and counting circuit 150, it is possible to determine when there are abnormalities in the data in the configuration area memory, so that errors can be identified and corrected in a timely manner to reduce the risk of data corruption and facilitate targeted optimization of system performance.

[0057] According to the detection circuit based on a triple-modal-redundancy (TMR) soft error mitigation core provided in this disclosure, by using the TMR soft error mitigation core as a processing module, the fault tolerance of the system can be increased without sacrificing performance, leveraging the TMR principle. Furthermore, by combining multiple circuit modules, targeted management of data in the configuration area memory can be performed under different operating states or working conditions. This can minimize the impact of erroneous data in the event of a single-event upset (SEE), thereby improving data error correction accuracy and reducing the generation and impact of erroneous data. Moreover, by modularly designing the detection circuit based on the TMR soft error mitigation core, each circuit module can be guaranteed to have its corresponding function. This allows for targeted maintenance during subsequent module maintenance, reducing the difficulty of troubleshooting and thus contributing to the long-term development and upgrade of the system. In other words, the detection circuit based on the TMR soft error mitigation core provided in this disclosure not only enhances the fault tolerance of the system but also helps improve its maintainability and reliability.

[0058] Furthermore, the detection circuit based on the triple-modal redundancy soft error mitigation core provided in this disclosure eliminates the need for adding a new FPGA as a single-event upset (SED) processing chip, effectively saving hardware costs.

[0059] It should be noted that the functions of each circuit module in the detection circuit based on the triple-redundant soft error mitigation core are not limited to those mentioned in this disclosure, and can be configured and adjusted according to actual needs.

[0060] In some embodiments, such as Figure 2 As shown, the serial-to-parallel conversion circuit 130 includes a parallel-to-serial circuit 131 and a serial-to-parallel circuit 132. The switch debugging circuit 140 is connected to the triple-modulus redundancy soft error mitigation core 110 via the parallel-to-serial circuit 131, thereby enabling transmission with fewer lines, reducing signal interference and cost, and improving the control reliability and stability of the operating state. The triple-modulus redundancy soft error mitigation core 110 is connected to the error detection and counting circuit 150 via the serial-to-parallel circuit 132, thereby improving error statistics efficiency.

[0061] By connecting the triple-redundant soft error mitigation core 110 to the switch debugging circuit 140 and the error detection and counting circuit 150 respectively through the above connection method, it can be ensured that the data conversion process is relatively independent, and each circuit module can focus on its own function, reduce interference, and make the processing more focused and efficient.

[0062] In some embodiments, the status code monitoring circuit 120, parallel-to-serial conversion circuit 131, serial-to-parallel conversion circuit 132, switch debugging circuit 140, and error correction and detection counting circuit 150 each include three input terminals and one output terminal to achieve triple modular redundancy. That is, for the status code monitoring circuit 120, parallel-to-serial conversion circuit 131, serial-to-parallel conversion circuit 132, switch debugging circuit 140, and error correction and detection counting circuit 150, each circuit module has three independent input terminals used to perform the same operation, ensuring that if any input terminal or component in the corresponding circuit module fails, other components can still operate normally, thereby improving the system's reliability and fault tolerance. For example, by comparing the results of the three input terminals, the system can detect a fault. If two or three results are inconsistent, the system can determine that a fault exists and switch to a normal module. Therefore, even if individual modules within a circuit module malfunction, the system can continue to operate without service interruption, ensuring the system's reliability and stability. In some application scenarios, the circuit framework diagrams of the above circuit modules can be as follows: Figure 3 As shown, it includes three input terminals and one output terminal to achieve triple modular redundancy. Among them, Figure 3 This is only a sample circuit structure. The connection method between the three input terminals and one output terminal, as well as the intermediate components, can be determined according to the actual function and configuration requirements of the corresponding circuit module, and are not restricted here.

[0063] For example, the status code monitoring circuit 120 employs three inputs and one output to achieve triple modular redundancy, ensuring that other circuit modules of the detection circuit based on the triple modular redundancy soft error mitigation core can operate as expected. The parallel-to-serial converter 131 employs three inputs and one output to achieve triple modular redundancy, ensuring the consistency and reliability of format conversion. The serial-to-parallel converter 132 employs three inputs and one output to achieve triple modular redundancy, ensuring the accuracy and consistency of format conversion. The switch debugging circuit 140 employs three inputs and one output to achieve triple modular redundancy, ensuring the accuracy and consistency of data management. The error detection and counting circuit 150 employs three inputs and one output to achieve triple modular redundancy, ensuring the accuracy and consistency of error detection.

[0064] By implementing triple redundancy in each circuit module through hardware configuration, the redundancy of the system can be increased, achieving global resistance to single-event upsets, thereby significantly improving the reliability and stability of the system.

[0065] In some examples, to ensure the reliability and stability of each circuit module, the state machine and counter of each circuit module were also modified with triple redundancy to further improve fault tolerance and ensure the system's resistance to single-event upsets.

[0066] For example, the structure of a traditional state machine can be as follows: Figure 4 As shown. By modifying the structure of this state machine with triple modular redundancy, we can obtain the following: Figure 5 The state machine shown is used for deployment within any circuit module of this disclosure. (Through...) Figure 5 It can be seen that modifying the state machine structure with triple redundancy can be considered as treating the state register as a staged output. Furthermore, each redundant logic uses a separate majority voter to generate feedback. This is because although the majority voter is a combinational circuit, the combinational circuit may be affected by the SEU at some point and output an incorrect result. Therefore, the output terminal also outputs three results, which are then voted on by the submodule of the next module, which can offset the effect of single-event upset to the greatest extent.

[0067] The structure of a traditional counter can be as follows: Figure 6 As shown. Since a counter can be viewed as a state machine that continuously increments a state register and assigns values ​​under specific conditions, it can be used... Figure 7 The method shown performs triple modulo redundancy on the counter, resulting in a counter that can be deployed within any circuit module of this disclosure. Because the counter's output is used internally within the module, in addition to achieving triple modulo redundancy at the input, majority voting is also performed at the output to ensure counting reliability.

[0068] For example, to improve the reliability of counter calls, a counter template can be constructed by using basic units such as logic gates and asynchronous reset flip-flops. Then, the counter template can be called in the code in the form of macros to achieve triple redundancy of the counter, so as to ensure that the Electronic Design Automation (EDA) tool can correctly call the macro module inside the circuit module to implement the carry logic.

[0069] In some embodiments, the status code monitoring circuit 120 can store the received status information into a two-byte register as output to determine the state of the triple-modulus redundancy soft error mitigation core 110. Although the status code monitoring circuit 120 has no complex logic or state transitions internally, triple-modulus redundancy processing is still required to ensure redundant inputs to the switch debugging circuit 140.

[0070] In some application scenarios, the triple-modular redundancy soft error mitigation core 110 will set the corresponding bit high when it is in the corresponding working state. The specific correspondence is shown in Table 1.

[0071]

[0072] Table 1

[0073] In some embodiments, the parallel-to-serial conversion circuit 131 includes: three parallel-to-serial sub-circuits, each connected to the switch debugging circuit, configured to receive an enable signal and data to be processed sent in parallel by the switch debugging circuit 140, and to generate a serial candidate result corresponding to the enable signal through a built-in first triple modulo redundancy counter; and a first majority voter, each connected to the parallel-to-serial sub-circuit and the triple modulo redundancy soft error mitigation core 110, configured to receive the serial candidate results output by all the parallel-to-serial sub-circuits, determine the target serial result, and send the target serial result to the switch debugging circuit to determine the control command to be sent to the triple modulo redundancy soft error mitigation core 110.

[0074] That is, the parallel-to-serial conversion circuit 131 contains three sets of functionally identical parallel-to-serial sub-circuits. Each parallel-to-serial sub-circuit receives an enable signal and data to be processed from the switch debugging circuit 140 in parallel. Each parallel-to-serial sub-circuit uses an internal triple-modulus counter to time the input according to the baud rate of the triple-modulus soft error mitigation core 110, converting the parallel input into a serial output to the UART serial port of the triple-modulus soft error mitigation core 110, obtaining the corresponding serial candidate result, and then outputting it along with the parallel-to-serial conversion completion signal to the first majority voter. Finally, the first majority voter determines the target serial result based on multiple serial candidate results and outputs the determined target serial result to the switch and error debugging circuit 140 to determine the control command to be sent to the triple-modulus soft error mitigation core 110. The control command is used to switch the operating state of the triple-modulus soft error mitigation core 110 in the monitoring state. For example, if the control command is a power-on command, the triple-modular redundancy soft error mitigation core 110 can be controlled to switch from monitoring state to error detection state; if the control command is a power-off command, the triple-modular redundancy soft error mitigation core 110 can be controlled to maintain monitoring state. This can effectively reduce data transmission errors, improve fault tolerance, and thus ensure the accuracy of control command transmission.

[0075] In some application scenarios, the control flow of any parallel-to-serial sub-circuit within the parallel-to-serial conversion circuit 131 can be as follows: Figure 8As shown, the process includes: In the default state, the parallel-to-serial converter is in the initial state. If the parallel-to-serial converter detects a low level at the enable interface of the switch debugging circuit 140, indicating the arrival of a new byte, the enable signal input to the switch debugging circuit 140 is buffered in the status register. The counter is incremented by one for each clock cycle. If the counter reaches [clock frequency / baud rate], the count is reset to zero. If the counter is [(clock frequency / baud rate) - 1], it is determined whether the parallel-to-serial converter is in the initial state. If the parallel-to-serial converter is in the initial state, the level of the output Tx_data is set low, indicating the start of a byte transmission, and the state is set to the transmit state, continuing to count the number of bytes per clock cycle. If the parallel-to-serial converter is in the initial state, it indicates that the parallel-to-serial converter is in the receive state. If the bit count is less than 8, the output is set to the value of the corresponding bit in the register for the current bit count, and the bit count is incremented by one, continuing to count the number of bytes per clock cycle. If the bit count is 8, it indicates that a byte transmission has ended. At this time, the level output of Tx_data is set high, and in response to the conversion completion signal being set high, the bit count is cleared to zero, and then the process enters the initial state to prepare for the next operation.

[0076] In some embodiments, the triple modulus redundancy soft error mitigation core 110 is configured to generate and output state information indicating a single-event upset (SEE) error has occurred, and to determine and output the error type, in the error detection state. The serial-to-parallel conversion circuit 132 includes: three serial-to-parallel circuits, each connected to the triple modulus redundancy soft error mitigation core 110; each serial-to-parallel sub-circuit is configured to receive the state information and error type serially transmitted by the triple modulus redundancy soft error mitigation core 110, and to generate parallel candidate results corresponding to the state information through a built-in second triple modulus redundancy counter; and a second majority voter, connected to each serial-to-parallel sub-circuit and to the error correction and detection counting circuit, the second majority voter being configured to receive the parallel candidate results output by all serial-to-parallel circuits, determine the target parallel result, and send the target parallel result to the error correction and detection counting circuit 150. That is, when the triple modulus redundancy soft error mitigation core 110 is in the error detection state, it can generate and output state information indicating a single-event upset (SEE) error has occurred, and determine and output the error type. In the serial-to-parallel conversion circuit 132, three sets of functionally identical serial-to-parallel circuits can respectively receive the status information and error type sent serially by the Tri-Mode Redundancy Soft Error Mitigation Core 110 via the UART serial port. Then, based on the baud rate of the Tri-Mode Redundancy Soft Error Mitigation Core 110, an internal Tri-Mode Redundancy counter is used for timing, and the serially input report information of the Tri-Mode Redundancy Soft Error Mitigation Core 110 is converted into parallel data byte by byte. The corresponding parallel candidate results are then output along with the serial-to-parallel conversion completion signal to the second majority voter. Finally, the second majority voter determines the target parallel result based on multiple parallel candidate results and outputs the determined target parallel result to the error correction and detection counting circuit 150. This allows the system to continue operating when an error is detected without causing system crashes or data loss, effectively resisting false alarms caused by single-event upsets, thus significantly enhancing fault tolerance.

[0077] In some application scenarios, the control flow of any serial-to-parallel sub-circuit within the serial-to-parallel conversion circuit 132 can be as follows: Figure 9As shown, the process includes: In the default state, the serial-to-parallel converter is in the initial state. If a low level is detected on the transmit data interface (UART_Rx), it indicates that a new byte has arrived. The internal counter is incremented by one for each clock cycle. If the counter reaches [clock frequency / baud rate], the count is reset to zero. If the counter is [clock frequency / (2*baud rate)], it is determined whether the serial-to-parallel converter is in the initial state. If it is in the initial state, the conversion completion signal is set low, and then the state of the serial-to-parallel converter is set to the receive state to continue counting the count for each clock cycle. If the serial-to-parallel converter is not in the initial state, it indicates that the serial-to-parallel converter is in the receive state, and then it is determined whether the bit count is less than 8. If the bit count is less than 8, the input of the current transmit data interface UART_Rx is sampled, and the corresponding bit of the current bit count in the register is assigned a value, the bit count is incremented by one, and then the count for each clock cycle continues to be counted. If the bit count is 8, it indicates that a byte transmission has ended. At this time, the conversion completion signal is set high, the bit count is cleared to zero, and the serial-to-parallel converter 132 is switched to the start state to prepare for the next operation.

[0078] In some embodiments, the error correction and detection counting circuit 150 includes: three error correction and detection counting sub-circuits, each connected to a second majority voter, configured to receive the target parallel result and determine candidate data error information; a third majority voter, each connected to one of the error correction and detection counting sub-circuits, configured to receive the candidate data error information output by all the error correction and detection counting sub-circuits and determine the target data error information; and an error count register, connected to the third majority voter, configured to count the cumulative number of times the target data error information corresponds to the error type. That is, the error correction and detection counting circuit 150 has three sets of functionally identical sub-error correction and detection counting sub-circuits. Each error correction and detection counting sub-circuit receives the target parallel result output in ASCII format from the second majority voter of the serial-to-parallel conversion circuit. When a key character is detected, the internal triple modulo redundancy counter counts the serial-to-parallel conversion completion signal to extract the triple modulo redundancy soft error mitigation core 110 from the output report of the triple modulo redundancy soft error mitigation core 110. The error count register counts the cumulative number of error types corresponding to the target data error information to determine the cumulative situation of single-event upset errors. This can improve the accuracy of error detection, enhance the error identification capability, and ensure that even in complex systems, errors can be reliably detected and counted, thereby helping to ensure the reliability of the system.

[0079] In some embodiments, the error counting register includes: an uncorrectable error counting register and a correctable error counting register; the uncorrectable error counting register is connected to a third majority voter and configured to count the cumulative number of uncorrectable error types corresponding to the target data error information; the correctable error counting register is also connected to the third majority voter and configured to count the cumulative number of correctable error types corresponding to the target data error information; the error detection and correction counting circuit further includes: a stored error address register connected to the third majority voter, configured to store the error address corresponding to the correctable error type. That is, to improve the accuracy and reliability of error statistics, the cumulative number of errors is counted by error type. Each error type corresponds one-to-one with a counting register. Specifically, the counting register corresponding to the uncorrectable error type is the uncorrectable error counting register; the counting register corresponding to the correctable error type is the correctable error counting register. By separately counting the cumulative number of corresponding error types using the uncorrectable error counting register and the correctable error counting register, the frequency and impact of different types of errors can be better understood. Furthermore, since the data corresponding to correctable error types is self-recoverable, the error address corresponding to the correctable error type can be stored in the error address register. This allows the triple-modular redundancy soft error mitigation core 110 to perform targeted recovery of the correctable error data based on the error address, reducing the interference of error data on the system. The error address is determined based on the target data error information, which includes the type of error data and its location.

[0080] In some embodiments, the triple modular redundancy soft error mitigation core 110 is further configured to perform flipping processing on erroneous data based on the error address, and to trigger and send a circuit restart prompt when the error type corresponding to the erroneous data is identified as an uncorrectable error type. That is, the triple modular redundancy soft error mitigation core 110 can locate abnormal erroneous data based on the error address, and then perform flipping processing on it to correct the error, thereby reducing the impact of erroneous data on system performance. If the triple modular redundancy soft error mitigation core 110 identifies the error type corresponding to the erroneous data as an uncorrectable error type, it indicates that the erroneous data needs to be recovered through reinitialization via a restart. Therefore, a circuit restart prompt is triggered and sent to notify the system administrator or processor core that the system needs to restart to attempt to recover to a stable state, thereby simplifying the error handling process and reducing manual intervention.

[0081] In some application scenarios, the control flow of any error correction and detection counting sub-circuit within the error correction and detection counting circuit 150 can be as follows: Figure 10As shown, it includes: an error correction and detection counting sub-circuit that determines whether a new byte has arrived based on the conversion completion signal (target parallel result) sent by the serial-to-parallel conversion circuit 130. When a new byte arrives, it combines the previous few bytes stored in the internal register for judgment. If 'SC 04' is detected, it indicates that the triple-modulus redundancy soft error mitigation core 110 has entered the error correction state. If 'SC 04' is not detected, reception continues.

[0082] After sending 'SC 04', the Triple Modular Redundancy Soft Error Mitigation Core 110 will immediately follow with two newline characters ' / r / n', and then output the error type to determine whether it is an uncorrectable error (CRC) or a multi-bit error (BFR). If it is an uncorrectable error or a multi-bit error, it is considered an uncorrectable error, the uncorrectable error count is incremented by one, the error address remains unchanged, and a message is displayed indicating that the FPGA needs to be restarted; otherwise, normal operation cannot be guaranteed. The Triple Modular Redundancy Soft Error Mitigation Core 110 will also automatically enter standby mode after this error occurs, and will resume normal operation after the FPGA restarts.

[0083] If it is a single-bit error (SED) or a two-bit error (DED), the correctable count is incremented by one, the corresponding error address is determined, and the error address is stored in the error address register. For example, for a single-bit error, the lower 4 bits of the frame address + 7 bits of the word address + 5 bits of the bit address, totaling 16 bits, can be extracted as the error address to be saved. For a two-bit error, the lower 4 bits of the frame address + 'DED', i.e., '111011111110', totaling 16 bits, can be extracted as the error address to be saved.

[0084] If the error type does not fall under any of the above conditions, it indicates that the error code was caused by a single-event upset. In this case, the output and state transition are no longer important, and the redundant logic of the other two error correction and detection counter circuits will determine the next state transition.

[0085] In some embodiments, the operating state further includes an error injection state; the switch debugging circuit 140 includes: a switch circuit and an error injection debugging circuit connected to the switch circuit; the switch circuit, connected to the triple modulo redundancy soft error mitigation core 110 via a serial-to-parallel conversion circuit, is configured to send a power-on command when a rising edge is detected at the input of the switch signal and the triple modulo redundancy soft error mitigation core 110 is in a standby state, and to send a power-off command when a falling edge is detected at the input of the switch signal and the triple modulo redundancy soft error mitigation core 110 is in a detection state; the error injection debugging circuit, connected to the triple modulo redundancy soft error mitigation core 110 via a serial-to-parallel conversion circuit, is configured to send an error injection command when a rising edge is detected at the input of the switch signal and the triple modulo redundancy soft error mitigation core 110 is in a standby state, to control the triple modulo redundancy soft error mitigation core 110 to enter the error injection state and perform toggling processing on the error data at the specified error address. The error injection state can be understood as an operating state used to simulate operation under space irradiation conditions in a non-space irradiation environment. The switching circuit and error-injection debugging circuit employ a pulse-controlled triple-modulus redundancy soft error mitigation core 110. This prevents repeated power-on attempts due to the switch remaining at a high level when an uncorrectable error occurs, and it also indicates the need for an FPGA restart through uncorrectable error counting, saving resource consumption. Furthermore, an error-injection debugging function is added, allowing simulation of circuit operation after a single-event upset in non-space irradiation environments. This verifies the functionality of the detection circuit based on the triple-modulus redundancy soft error mitigation core 110, enabling targeted debugging and optimization of the detection circuit to ensure its reliability and stability, thereby improving system performance.

[0086] By dividing the switching debugging circuit 140 into a switching circuit and an error injection debugging circuit according to its function, the triple-modular redundancy soft error mitigation core 110 can be flexibly switched between the working state and the error injection state, thereby facilitating the needs of testing and debugging and ensuring the effectiveness of the error detection and correction mechanism.

[0087] In some application scenarios, the control flow inside the switch debugging circuit 140 can be as follows: Figure 11 As shown, it includes: if the triple-modulus redundancy soft error mitigation core 110 is detected to be in the monitoring state, then only attention is paid to whether there is a falling edge at the switch signal input terminal. If there is, the enable is set high and the output byte is set to ASCII code I, i.e., 8'h49. After receiving the conversion completion signal sent by the serial-to-parallel conversion circuit, it continues to detect whether the triple-modulus redundancy soft error mitigation core 110 is in the monitoring state.

[0088] If the Tri-Mode Redundancy Soft Error Mitigation Core 110 is detected to be in standby mode, the switch signal should be low in this state. At this time, first check if there is a rising edge at the switch signal input terminal. If there is, set the enable high and set the output byte to ASCII code O, i.e., 8'h4F. After receiving the conversion completion signal sent by the serial-to-parallel conversion circuit, continue to detect whether the Tri-Mode Redundancy Soft Error Mitigation Core 110 is in monitoring mode.

[0089] If the triple-modulus redundancy soft error mitigation core 110 is detected to be in standby mode and the switching signal remains unchanged, then the error injection debugging signal is monitored. If a rising edge is detected, the enable is set high, and the output byte is set to the ASCII code N, i.e., 8'h4E. Afterwards, each time a conversion completion signal is received from the serial-to-parallel conversion circuit, one more byte is sent, ultimately sending 'NC00000A5A5'. Then, the system continues to monitor whether the triple-modulus redundancy soft error mitigation core 110 is in monitoring mode. This is used to simulate single-event upsets in non-irradiated environments. The receiving format is 'N C0XXXXXXXX', where N is the fixed beginning of the error injection instruction for the monitoring interface, followed by a space and then a 10-digit hexadecimal actual effective instruction, identical to the receiving format of the ordinary TMR core error injection interface. It is important to note that these instructions are still received in ASCII format. For example, if the error injection interface itself requires the instruction to start with 1100, the corresponding hexadecimal value is C, but the actual transmitted instruction is the uppercase C, corresponding to 8'h43. The instruction format received by the error injection interface using the linear frame address is as follows... Figure 12 As shown, S is the Super Logic Region (SLR) number of the Stacked Silicon Interconnect (SSI) device, set to 00 in non-SSI devices; L is the 17-bit linear frame address; W is the 7-bit word address; and B is the 5-bit bit address. Since the error injection function is only used to verify system functionality, the address is fixed at 0000A5A5, and the final instruction is 'NC00000A5A5'. Upon receiving the error injection instruction, the Tri-Mode Redundancy Soft Error Mitigation Core 110 first enters the error injection state, flips the bits at address 0000A5A5, and then enters the standby state. If a power-on instruction is received at this time, the TMR SEM core will detect the error after entering the monitoring state and correct it.

[0090] It should be noted that if the Tri-Mode Redundancy Soft Error Mitigation Core 110 is in standby mode but the switch signal is high, it means that the Tri-Mode Redundancy Soft Error Mitigation Core 110 has automatically shut down due to the detection of an uncorrectable error. At this time, the error injection operation cannot be performed, and the power-on signal should not be resent. If the Tri-Mode Redundancy Soft Error Mitigation Core 110 is powered on at this time, it will shut down again due to the detection of the same error.

[0091] Based on the same inventive concept, this disclosure also provides an FPGA based on static random access memory, including any of the detection circuits based on the triple modal redundancy soft error mitigation cores provided above. This enables the implementation of single-event upset (SOME) protection without the need for additional external hardware such as RS422 chips or antifuse FPGAs, thereby enhancing the practicality of FPGAs based on static random access memory. Furthermore, the SOME protection function is simple and intuitive to operate, making FPGAs based on static random access memory highly versatile.

[0092] Based on the same inventive concept, this disclosure also provides a data management method applicable to the triple-modular redundancy soft error mitigation core included in any of the FPGAs based on static random access memory provided in this disclosure.

[0093] like Figure 13 As shown, the data management method may include the following steps:

[0094] Step S210: In the monitoring state, monitor and receive control commands sent by the switch debugging circuit. When the triple-modular redundancy soft error mitigation core is in the monitoring state, monitor whether the switch debugging circuit sends control commands so that the operating state can be switched in a timely manner according to the received control commands to meet the corresponding data management requirements.

[0095] In step S220, in response to a power-on control command, the monitoring state is switched to the error detection state, and the data status of the configuration memory region is detected. The switch from monitoring to error detection in response to a power-on control command enables the triple-modular redundancy soft error mitigation core to perform targeted detection of the data status of the configuration memory region and identify whether a single-event upset (SEE) problem has occurred.

[0096] Step S230: If a single-event upset (SEE) error is detected in the configuration memory region, status information is generated and the error type is determined. This process is used to determine whether the error can be autonomously repaired.

[0097] In step S240, the status information is stored through the error detection and counting circuit. This allows for quick location of erroneous data, timely error correction, and reduced interference from erroneous data on the system.

[0098] Step S250 involves using an error detection and counting circuit to count the cumulative occurrences of different error types. This helps determine the cumulative occurrence of single-event upset errors, thereby improving the accuracy of error detection, enhancing error identification capabilities, and ensuring that errors can be reliably detected and counted even in complex systems, thus contributing to system reliability.

[0099] In step S260, in response to switching to error correction state, error correction processing is performed on the erroneous data in the configuration memory area. Since correctable error types can recover autonomously, in order to reduce the interference of erroneous data on the system, error correction processing is performed on the erroneous data in the configuration memory area when the working state is error correction state, so as to eliminate the impact of data errors caused by single-event upsets in a timely manner, improve the system's fault tolerance, and thus help improve system performance.

[0100] According to the data management method provided in this disclosure, targeted management of data in the configuration memory region can be performed under different operating states of the triple-modular redundancy soft error mitigation core, thereby effectively handling and mitigating single-event upset errors. This data management method helps improve the robustness and reliability of the system, especially in applications facing radiation environments or with high reliability requirements, enabling the system to more accurately identify and repair errors, thus reducing the impact of errors on system performance.

[0101] In some embodiments, the error type may include a correctable error type. Step S250 may include: in response to an error type being a correctable error type, incrementing the correctable error count by one through the error detection and correction counting circuit to update the cumulative occurrence count of the correctable error type, and saving the error address corresponding to the correctable error type. That is, when the detected error type is determined to be correctable (e.g., an error caused by a single-event upset), the cumulative occurrence count of correctable errors can be counted through the error detection and correction counting circuit. The count is incremented by one each time correctable error type data is detected. By saving the error address corresponding to the correctable error type, the subsequent triple-modular redundancy soft error mitigation core can perform targeted recovery of the correctable error data based on the error address, reducing the interference of error data on the system.

[0102] In other embodiments, the data management method further includes: in response to an error type being a correctable error type, performing a flipping process on the error data based on the error address to correct the error, thereby reducing the impact of the error data on system performance.

[0103] In some embodiments, the error type may further include an uncorrectable error type. Step S250 may include: in response to an error type being an uncorrectable error type, incrementing the number of uncorrectable errors by one via the error detection and correction counting circuit to update the cumulative occurrence count of the uncorrectable error type. That is, when the system detects an error and determines that the error cannot be corrected by conventional error correction mechanisms, it is classified as an uncorrectable error type. Because of the uncorrectable error type, to determine the occurrence of this type of error, the number of uncorrectable errors is incremented by one via the error detection and correction counting circuit to update the cumulative occurrence count of the uncorrectable error type.

[0104] In other embodiments, the data management method further includes: in response to an error type that is uncorrectable, triggering and sending a circuit restart prompt to prevent uncorrectable errors from continuing to affect the stability and security of the system, thereby avoiding system crashes caused by errors, which helps to protect the data integrity in the configuration memory area and prevent data corruption caused by errors.

[0105] In some embodiments, step S210 may include: in the monitoring state, if the received control command from the switch debugging circuit is a power-on command, switching the monitoring state to an error detection state; or, in the monitoring state, if the received control command from the switch debugging circuit is an error injection command, switching the monitoring state to an error injection state, so as to perform flipping processing on the erroneous data at the specified error address. This allows for the simulation and testing of error detection and correction mechanisms without disrupting the actual system operation, evaluating the system's behavior and performance when encountering errors, thereby facilitating system optimization and improving the system's robustness and reliability.

[0106] In some embodiments, the data management method further includes: in the error detection state, if the control command received from the switch debugging circuit is a power-off command, then entering the standby state to save performance.

[0107] In some optional application scenarios, such as Figure 14 As shown, the data management process using any of the three-modular redundancy soft error mitigation cores included in an FPGA based on static random access memory provided in this disclosure can be as follows:

[0108] The triple-modal redundancy soft error mitigation core automatically starts upon power-up of the FPGA based on static random access memory, and enters the monitoring state after initialization.

[0109] In monitoring mode, the system continuously scans the configuration memory region. If a shutdown command is received during this time, it enters standby mode. If a single-event upset error is detected, the triple modulo redundancy soft error mitigation core enters error detection mode.

[0110] The triple modulus redundancy soft error mitigation kernel is in error detection state, which identifies and outputs the error type. If the error type is a localizable single-bit or two adjacent bit error, the triple modulus redundancy soft error mitigation kernel corrects it and outputs the error address. After entering the classification state, it re-enters the error detection state to continue single-event flip detection.

[0111] If the error type is an uncorrectable, unlocatable error (CRC checksum error only) or a multi-bit error, the triple-modulus redundancy soft error mitigation core enters a standby state after entering the classification state, waiting for the FPGA based on static random access memory to restart. At this time, although the triple-modulus redundancy soft error mitigation core is in standby state and the switch signal is high, it can be powered on using a power-on command. However, it will still return to S306 due to the uncorrectable error. Only after restarting the FPGA based on static random access memory and returning to initialization can the normal process be restored.

[0112] The triple-redundant soft error mitigation core is in standby mode, and the switch signal is low. If a power-on command is received at this time, it enters the error detection mode; otherwise, if an error injection command is received, it enters the error correction mode to perform flipping processing on the erroneous data at the specified error address.

[0113] In other application scenarios, if the configuration memory area of ​​the triple modal redundancy soft error mitigation core logic is affected by a single event flip and cannot be recovered even with triple modal redundancy technology, the FPGA based on static random access memory must be restarted to restore normal operation.

[0114] Based on the same inventive concept, this disclosure also provides a computer-readable storage medium storing a program for executing the data management method of any of the foregoing embodiments.

[0115] This disclosure uses specific terms to describe embodiments of the present disclosure. Terms such as "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the present disclosure. Therefore, it should be emphasized and noted that references to "an embodiment," "one embodiment," or "an alternative embodiment" in different locations throughout this specification do not necessarily refer to the same embodiment. Furthermore, certain features, structures, or characteristics in one or more embodiments of the present disclosure can be appropriately combined.

[0116] In the context of this disclosure, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of expressly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0117] Similarly, it should be noted that, in order to simplify the description of this disclosure and thus aid in the understanding of one or more embodiments, the foregoing description of embodiments of this disclosure may sometimes combine multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of this disclosure requires more features than the features claimed. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0118] The basic concepts have been described above. It is obvious that the above disclosure is merely illustrative and does not constitute a limitation of this disclosure. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to this disclosure by those skilled in the art. Such modifications, improvements, and corrections are suggested in this disclosure and therefore remain within the spirit and scope of the embodiments of this disclosure.

Claims

1. A detection circuit based on a triple-modular redundancy soft error mitigation core, comprising: The triple-modal redundancy soft error mitigation core is configured to manage the data state of the configuration memory region based on the working state, generate and output state information that identifies a single-event flip error, determine and output the error type, and perform error correction processing on the erroneous data. The working states include: monitoring state, error detection state, and error correction state. A status code monitoring circuit, connected to the triple-modular redundancy soft error mitigation core, is configured to receive the status information and store the status information in the configuration memory area. The serial-to-parallel conversion circuit is connected to the triple-modulus redundancy soft error mitigation core; A switch debugging circuit is connected to the serial-to-parallel conversion circuit and the status code monitoring circuit, so as to connect to the triple modular redundancy soft error mitigation core through the serial-to-parallel conversion circuit. The switch debugging circuit is configured to control the operating state of the triple modular redundancy soft error mitigation core based on the working state of the triple modular redundancy soft error mitigation core. The error detection and counting circuit, connected to the serial-to-parallel conversion circuit, is configured to count the cumulative occurrences of the error type through the serial-to-parallel conversion circuit and the triple-modular redundancy soft error mitigation core.

2. The detection circuit based on a triple-modular redundancy soft error mitigation core according to claim 1, wherein, The serial-to-parallel conversion circuit includes a parallel-to-serial conversion circuit and a serial-to-parallel conversion circuit; The switch debugging circuit is connected to the triple-modular redundancy soft error mitigation core through the parallel-to-serial conversion circuit; The triple-modular redundancy soft error mitigation core is connected to the error detection and counting circuit through the serial-to-parallel conversion circuit.

3. The detection circuit based on a triple-modular redundancy soft error mitigation core according to claim 2, wherein, The status code monitoring circuit, the parallel-to-serial conversion circuit, the serial-to-parallel conversion circuit, the switch debugging circuit, and the error correction and detection counting circuit all include three input terminals and one output terminal to achieve triple-modulus redundancy.

4. The detection circuit based on a triple-modular redundancy soft error mitigation core according to claim 3, wherein, The parallel-to-serial conversion circuit includes: Three parallel-to-serial sub-circuits are respectively connected to the switch debugging circuit. These sub-circuits are configured to receive enable signals and data to be processed in parallel from the switch debugging circuit, and to generate serial candidate results corresponding to the enable signals via a built-in first three-modulus redundancy counter. The enable signals characterize control commands that control the operating state of the three-modulus redundancy soft error mitigation core. A first majority voter is connected to each of the parallel-to-serial sub-circuits and to the triple-modular-redundancy soft error mitigation core. The first majority voter is configured to receive the serial candidate results output by all the parallel-to-serial sub-circuits, determine the target serial result, and send the target serial result to the switch debugging circuit to determine the control command to be sent to the triple-modular-redundancy soft error mitigation core.

5. The detection circuit based on a triple-modular redundancy soft error mitigation core according to claim 3 or 4, wherein, The triple-modular redundancy soft error mitigation kernel is configured to generate and output the state information that identifies a single-event flip error in the error detection state, and to determine and output the error type. The serial-to-parallel conversion circuit includes: Three serial-to-parallel conversion circuits are respectively connected to the three-mode-redundant soft error mitigation core. The serial-to-parallel conversion sub-circuit is configured to receive the status information and the error type serially sent by the three-mode-redundant soft error mitigation core, and to generate parallel candidate results corresponding to the status information through a built-in second three-mode-redundant counter. as well as The second majority voter is connected to each of the serial-to-parallel sub-circuits and to the error correction and detection counting circuit. The second majority voter is configured to receive parallel candidate results output by all the serial-to-parallel circuits, determine a target parallel result, and send the target parallel result to the error correction and detection counting circuit.

6. The detection circuit based on a triple-modular redundancy soft error mitigation core according to claim 5, wherein, The error correction and detection counting circuit includes: Three error correction and detection counting sub-circuits are respectively connected to the second majority voter. The error correction and detection counting sub-circuit is configured to receive the target parallel result and determine the candidate data error information. A third majority voter is connected to each of the error correction and detection counting sub-circuits. The third majority voter is configured to receive the candidate data error information output by all the error correction and detection counting sub-circuits and determine the target data error information. An error count register, connected to the third majority voter, is configured to count the cumulative number of error types corresponding to the target data error information.

7. The detection circuit based on a triple-modular redundancy soft error mitigation core according to claim 6, wherein, The error count register includes: an uncorrectable error count register and a correctable error count register; The uncorrectable error count register is connected to the third majority voter and is configured to count the cumulative number of uncorrectable error types corresponding to the target data error information; The correctable error count register is connected to the third majority voter and is configured to count the cumulative number of correctable error types corresponding to the target data error information; The error correction and detection counting circuit further includes: a stored error address register connected to the third majority voter, wherein the stored error address register is configured to store the error address corresponding to the correctable error type, and the error address is determined based on the target data error information.

8. The detection circuit based on a triple-modular redundancy soft error mitigation core according to claim 7, wherein, The triple-modular redundancy soft error mitigation core is also configured to perform flipping processing on the error data based on the error address, and to trigger and send a circuit restart prompt when the error type corresponding to the error data is identified as an uncorrectable error type.

9. The detection circuit based on a triple-modular redundancy soft error mitigation core according to claim 1, wherein, The working state also includes the error injection state; The switch debugging circuit includes: a switch circuit and an error-injection debugging circuit connected to the switch circuit; The switching circuit, connected to the triple modular redundancy soft error mitigation core via the serial-to-parallel conversion circuit, is configured to send a power-on command when a rising edge is detected at the input of the switching signal and the triple modular redundancy soft error mitigation core is in standby mode, and to send a power-off command when a falling edge is detected at the input of the switching signal and the triple modular redundancy soft error mitigation core is in detection mode. The error injection debugging circuit is connected to the triple modular redundancy soft error mitigation core through the serial-to-parallel conversion circuit. It is configured to send an error injection command when a rising edge is detected at the input of the switch signal and the triple modular redundancy soft error mitigation core is in standby mode, so as to control the triple modular redundancy soft error mitigation core to enter the error injection state and perform flipping processing on the error data at the specified error address.

10. An FPGA based on static random access memory, comprising the detection circuit based on a triple-modular redundancy soft error mitigation core as described in any one of claims 1-9.

11. A data management method applied to the triple modular redundancy soft error mitigation core of the FPGA based on static random access memory as described in claim 10, the method comprising: In monitoring mode, it monitors and receives control commands sent by the switch debugging circuit; In response to the control command being a power-on command, the monitoring state is switched to the error detection state, and the data status of the configuration memory area is detected; If a single-event flip error is detected in the configured memory region, status information is generated and the error type is determined; The status information is stored through an error correction and detection counting circuit; The cumulative number of occurrences of the error type is counted using an error detection and correction counting circuit. In response to switching to the error correction state, error correction processing is performed on the erroneous data in the configuration memory area.

12. The data management method according to claim 11, wherein, The error types include correctable error types or non-correctable error types; The step of counting the cumulative occurrences of the error type using the error correction and detection counting circuit includes: In response to the error type being a correctable error type, the number of correctable errors is incremented by one through the error detection and correction counting circuit to update the cumulative occurrence count of the correctable error type, and the error address corresponding to the correctable error type is saved. In response to the error type being an uncorrectable error type, the number of uncorrectable errors is incremented by one by the error detection and correction counting circuit to update the cumulative occurrence count of the uncorrectable error type.

13. The data management method according to claim 12, wherein, The method further includes: If the error type is a correctable error type, then the error data is flipped based on the error address; or If the error type is an uncorrectable error type, a circuit restart prompt is triggered and sent.

14. The data management method according to claim 11, wherein, In the monitoring state, in response to receiving a control command sent by the switch debugging circuit, the monitoring state is switched to the error detection state, including: In monitoring mode, if a power-on command is received from the switch debugging circuit, the monitoring mode is switched to error detection mode; or In the monitoring state, in response to receiving a control command sent by the switch debugging circuit that is an error injection command, the monitoring state is switched to the error injection state to perform flipping processing on the error data at the specified error address.

15. The data management method according to claim 11, wherein, The method further includes: In the error detection state, if the control command received from the switch debugging circuit is a power-off command, then the system enters the standby state.

16. A computer-readable storage medium storing a program for performing the data management method according to any one of claims 11-15.

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