Test controller and method of operation thereof, memory and system

Abstract

Embodiments of the present disclosure provide a test controller and an operating method, a memory and a system thereof, and relate to the technical field of integrated circuits. The test controller comprises an interface unit, a first-in-first-out queue (FIFO) group and a control logic unit. The interface unit is configured to receive a first data signal and output a second data signal; the FIFO group is coupled with the interface unit; the control logic unit is coupled with the interface unit and the FIFO group, wherein the FIFO group comprises a first asynchronous FIFO configured to buffer the first data signal; the control logic unit is configured to generate a first ready signal indicating whether the test controller is capable of receiving the first data signal according to a fullness state of the first asynchronous FIFO; and / or, the FIFO group comprises a second asynchronous FIFO configured to buffer the second data signal; the control logic unit is configured to generate a second ready signal indicating whether the test controller is capable of outputting the second data signal according to a fullness state of the second asynchronous FIFO.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of integrated circuit technology, and in particular to a test controller, a memory, a memory system, and a method for operating the test controller. Background Technology

[0002] The test controller (also known as the Local Test Controller (LTC)) is a hardware module within the memory used for testing, initialization, and repair management. It can be located within the memory's buffer chip. The test controller can communicate with devices outside the memory (hereinafter referred to as external devices) via a bus, and also with the test management controller (also known as the Global Test Controller (GTC)) inside the buffer chip. On one hand, the test controller can receive the first data signal (e.g., test vectors, repair information, etc.) written by the external device; on the other hand, the test controller can output the second data signal (e.g., test results, failure bitmaps, etc.) from the memory to the external device or the test management controller. Therefore, there are two data streams in opposite directions within the test controller, where the incoming data stream flows from the external device to the test controller, and the outgoing data stream flows from the test controller to the external device or the test management controller.

[0003] With the miniaturization and increasing integration of memory, the amount of data that test controllers need to process is increasing daily, placing higher demands on data transmission efficiency. In scenarios such as memory power-on initialization, factory testing, and failure repair, test controllers need to perform a large amount of data interaction, and inbound and outbound data transmissions often need to be performed independently and efficiently.

[0004] However, in some related solutions, the lack of an effective decoupling mechanism between the data transmission and internal data processing of the test controller leads to low data transmission efficiency. Furthermore, this problem becomes even more pronounced when both inbound and outbound data flows need to be processed simultaneously. Therefore, there is an urgent need in the art for a test controller and its operating method that can achieve efficient decoupling of data flows, improve data transmission efficiency, and effectively control hardware overhead. Summary of the Invention

[0005] Embodiments of this disclosure provide a test controller, a memory, a memory system, and a method of operating the test controller that can at least partially solve the above-described problems or other problems in the art.

[0006] According to a first aspect of this disclosure, a test controller is provided, comprising: an interface unit, a FIFO (First In First Out) group, and a control logic unit. The interface unit is configured to receive a first data signal and output a second data signal. The FIFO group is coupled to the interface unit. The control logic unit is coupled to the FIFO group and the interface unit, wherein the FIFO group includes a first asynchronous FIFO for buffering the first data signal; the control logic unit is configured to generate a first ready signal indicating whether the test controller can receive the first data signal based on the empty / full state of the first asynchronous FIFO; and / or, the FIFO group includes a second asynchronous FIFO for buffering the second data signal; the control logic unit is configured to generate a second ready signal indicating whether the test controller can output the second data signal based on the empty / full state of the second asynchronous FIFO.

[0007] According to a second aspect of this disclosure, a memory is provided, comprising: at least one layer of memory die; and a buffer chip coupled to the at least one layer of memory die, the buffer chip comprising a test controller as described in the first aspect and any possible implementation thereof.

[0008] According to a third aspect of this disclosure, a memory system is provided, comprising: a memory as described in the second aspect and any possible implementation thereof; and a memory controller coupled to the memory and used to control the memory to store data.

[0009] According to a fourth aspect of this disclosure, a method for operating a test controller is provided. The test controller includes an interface unit, a FIFO group, and a control logic unit. The FIFO group includes at least one of a first asynchronous FIFO and a second asynchronous FIFO. The method includes at least one of the following operations: receiving a first data signal through the interface unit and buffering the first data signal through the first asynchronous FIFO, wherein the control logic unit generates a first ready signal indicating whether the test controller can receive the first data signal based on the empty / full state of the first asynchronous FIFO; buffering a second data signal through the second asynchronous FIFO and outputting the second data signal through the interface unit, wherein the control logic unit generates a second ready signal indicating whether the test controller can output the second data signal based on the empty / full state of the second asynchronous FIFO.

[0010] The present disclosure provides a test controller, a memory, a memory system, and an operation method for the test controller. The test controller includes at least one of a first asynchronous FIFO and a second asynchronous FIFO. The first asynchronous FIFO buffers a first data signal entering the test controller. After the first data signal is written to the first asynchronous FIFO by the interface unit, it is temporarily stored and then read by the internal logic for subsequent data flow. Since the writing and reading of the first asynchronous FIFO do not block each other, data reception and internal data flow are decoupled. The second asynchronous FIFO buffers a second data signal. After the second data signal is written to the second asynchronous FIFO internally, it is temporarily stored and then read by the interface unit for output. Since the writing and reading of the second asynchronous FIFO do not block each other, internal data supply and data output are decoupled. Furthermore, the control logic unit generates a ready signal based on the empty / full state of at least one of the first and second asynchronous FIFOs to indicate whether the test controller can receive or output the corresponding data signal. This improves the data transmission efficiency of the test controller while effectively controlling hardware overhead.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description.

[0012] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0013] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic block diagram of a test controller provided according to an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of a memory provided according to an exemplary embodiment of the present disclosure; Figure 3 This is a schematic block diagram of a system provided according to exemplary embodiments of the present disclosure; Figure 4 This is a timing diagram of the power-on initialization process between an external device and a test controller, provided according to an exemplary embodiment of this disclosure. Figure 5 This is a timing diagram of the external device and the test controller during the test process according to an exemplary embodiment of this disclosure; Figure 6 This is a timing diagram of the test controller and test management controller during the failure bitmap reading process according to an exemplary embodiment of this disclosure; Figures 7 to 8 These are flowcharts of the operation method of the test controller provided according to the exemplary embodiments of this disclosure. Detailed Implementation

[0014] The various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0015] The term “exemplary” as used herein means “serving as an example, implementation method, or illustration.” Any implementation method illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other implementation methods.

[0016] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, apparatuses, means, elements, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0017] Some embodiments of this disclosure provide a test controller. Figure 1 This is a schematic block diagram of a test controller 100 provided according to an exemplary embodiment of the present disclosure.

[0018] like Figure 1As shown, the test controller 100 includes an interface unit 101, a FIFO group 102, and a control logic unit 103. The interface unit 101 receives a first data signal and outputs a second data signal. The FIFO group 102 is coupled to the interface unit 101, and the control logic unit 103 is coupled to both the FIFO group 102 and the interface unit 101. In some embodiments of this disclosure, the FIFO group 102 includes a first asynchronous FIFO 1021 for buffering the first data signal, and the control logic unit 103 generates a first ready signal indicating whether the test controller 100 can receive the first data signal based on the empty / full state of the first asynchronous FIFO 1021. In other embodiments of this disclosure, the FIFO group 102 includes a second asynchronous FIFO 1022 for buffering the second data signal, and the control logic unit 103 generates a second ready signal indicating whether the test controller 100 can output the second data signal based on the empty / full state of the second asynchronous FIFO 1022. In some other embodiments of this disclosure, the FIFO group 102 includes a first asynchronous FIFO 1021 for buffering a first data signal and a second asynchronous FIFO 1022 for buffering a second data signal. The control logic unit 103 is configured to generate a first ready signal indicating whether the test controller 100 can receive the first data signal based on the empty / full state of the first asynchronous FIFO 1021, and to generate a second ready signal indicating whether the test controller 100 can output the second data signal based on the empty / full state of the second asynchronous FIFO 1022.

[0019] Therefore, according to at least one embodiment of this disclosure, the test controller (hereinafter also referred to as LTC) includes at least one of a first asynchronous FIFO and a second asynchronous FIFO. The first asynchronous FIFO is used to buffer the first data signal entering the LTC. After the first data signal is written to the first asynchronous FIFO by the interface unit, it is temporarily stored and then read by the internal logic for subsequent data flow. Since the writing and reading of the first asynchronous FIFO do not block each other, the data reception and internal data flow of the LTC are decoupled. The second asynchronous FIFO is used to buffer the second data signal. After the second data signal is written to the second asynchronous FIFO by the internal logic unit, it is temporarily stored and then read by the interface unit for output. Since the writing and reading of the second asynchronous FIFO do not block each other, the internal data supply and data output of the LTC are decoupled. In addition, the control logic unit generates a ready signal according to the empty / full state of at least one of the first asynchronous FIFO and the second asynchronous FIFO to indicate whether the test controller can receive or output the corresponding data signal. This improves the data transmission efficiency of the LTC while effectively controlling the hardware overhead of the LTC.

[0020] Specifically, the LTC is a hardware module used to perform testing, initialization, and repair management of the memory. In some implementations, the LTC may be located within the memory's buffer die. In other implementations, the LTC may be located in other locations within the memory. Furthermore, the LTC may be located in or integrated with a memory controller coupled to the memory. Alternatively, the memory may include Dynamic Random Access Memory (DRAM), such as three-dimensional stacked DRAM or two-dimensional DRAM.

[0021] It is understood that this disclosure does not limit the specific type of memory or the specific location of the LTC in the memory system. For ease of description, the following description will take the example of the LTC being located within the memory's buffer chip, but this does not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art can place the LTC in an appropriate location according to the actual application scenario, and the technical principles and implementation methods are similar to those described below.

[0022] The LTC can communicate with external devices via a bus (e.g., an APB (Advanced Peripheral Bus)). Additionally, the LTC can communicate with the GTC inside the buffer chip. For example, the GTC can be used to read failure bitmap data from the LTC after memory testing is complete for subsequent hardware repair.

[0023] Therefore, the LTC has two data streams flowing in opposite directions: the inbound data stream flows from the external device to the LTC, and the outbound data stream flows from the LTC to the external device or GTC. The inbound data stream may include redundancy repair information or test vectors sent by the external device, while the outbound data stream may include test results or failure bitmap data sent by the LTC to the external device or GTC. With this configuration, the LTC can perform bidirectional data transmission with the external device or GTC in different scenarios and according to different operating stages and task requirements.

[0024] As memory becomes smaller and more integrated, the amount of data that LTCs need to process is increasing, placing higher demands on data transfer efficiency. In scenarios such as power-on initialization, factory testing, and failure repair, LTCs need to perform a large amount of data interaction, and inbound and outbound data transfers often need to be performed independently and efficiently.

[0025] In some related schemes, LTC can use a register file as a data cache. A register file is a collection of registers, each of which can consist of multiple cascaded flip-flops. For example, the flip-flops can include D flip-flops (DFFs). Taking LTC caching a 32-bit data signal as an example, it requires 32 flip-flops to form one register; when caching multiple data signals, LTC needs multiple sets of cascaded registers to form a register file. As the cache depth increases, the number of flip-flops required by LTC increases exponentially, leading to a linear increase in the hardware area overhead of LTC.

[0026] Furthermore, in this type of technical solution, the incoming and outgoing data flows of the LTC typically share the same set of register files. This register file operates under the control of a synchronous clock domain. The external device's data writing signals to the register file and the LTC's internal logic's data reading signals from the register file are constrained by the same control logic, and the two cannot occur simultaneously. In other words, the LTC's internal logic must wait for the current data signal to be read from and processed from the register file before the external device can write the next data signal to the register file. Therefore, although this structure can temporarily store data, it cannot achieve independent parallel writing and reading, resulting in a lack of effective decoupling mechanism between data transmission from external devices and internal data processing within the LTC.

[0027] To at least address the aforementioned technical problems, embodiments of this disclosure provide an LTC 100, comprising: an interface unit 101, a FIFO group 102, and a control logic unit 103. The interface unit 101 receives a first data signal and outputs a second data signal. The FIFO group 102 is coupled to the interface unit 101, and the control logic unit 103 is coupled to both the FIFO group 102 and the interface unit 101.

[0028] In some embodiments of this disclosure, the FIFO group 102 includes a first asynchronous FIFO 1021 for buffering a first data signal, and the control logic unit 103 is configured to generate a first ready signal indicating whether the test controller 100 can receive the first data signal based on the empty / full state of the first asynchronous FIFO 1021. In other embodiments of this disclosure, the FIFO group 102 includes a second asynchronous FIFO 1022 for buffering a second data signal, and the control logic unit 103 is configured to generate a second ready signal indicating whether the test controller 100 can output the second data signal based on the empty / full state of the second asynchronous FIFO 1022. In some other embodiments of this disclosure, the FIFO group 102 includes a first asynchronous FIFO 1021 for buffering a first data signal and a second asynchronous FIFO 1022 for buffering a second data signal. The control logic unit 103 is configured to generate a first ready signal indicating whether the test controller 100 can receive the first data signal based on the empty / full state of the first asynchronous FIFO 1021, and to generate a second ready signal indicating whether the test controller 100 can output the second data signal based on the empty / full state of the second asynchronous FIFO 1022.

[0029] Figure 2 This is a schematic diagram of the structure of the memory 10 provided according to an exemplary embodiment of the present disclosure. Figure 3 This is a schematic block diagram of system 1 provided according to an exemplary embodiment of the present disclosure.

[0030] like Figures 1 to 3 As shown, in some embodiments of this disclosure, LTC 100 may be disposed in buffer chip 11 of memory 10, wherein LTC 100 may be coupled to external device 30 located outside memory 10, and external device 30 may be used to send a first data signal to LTC 100.

[0031] Specifically, memory 10 may include DRAM. Exemplarily, memory 10 may include three-dimensional stacked DRAM, which features high bandwidth, low latency, and high-density integration, and is widely used in high-performance computing, artificial intelligence training, data centers, and other scenarios. The solutions provided by the embodiments of this disclosure are applicable to three-dimensional stacked DRAM (e.g., High Bandwidth Memory (HBM)) designs, but their technical principles are also applicable to other types of memory, such as two-dimensional DRAM. Exemplarily, two-dimensional DRAM may include Synchronous Dynamic Random Access Memory (SDRAM). SDRAM may include Double Data Rate SDRAM (DDR SDRAM), Low Power Double Data Rate SDRAM (LPDDR), etc., and this disclosure does not limit it to these types.

[0032] Taking a three-dimensional stacked DRAM as an example, the memory 10 may include a buffer chip 11 and a multilayer memory die 12. The buffer chip 11 may be located at the bottom of the memory 10, and the multilayer memory die 12 may be vertically stacked on one side of the buffer chip 11. An LTC 100 may be disposed inside the buffer chip 11 to manage the test, initialization, and repair operations of the memory 10 in close proximity. The buffer chip 11 and the multilayer memory die 12 are electrically and physically connected through through-silicon vias (TSVs) 13 and a hybrid bonding layer, thereby enabling data communication between the buffer chip 11 and the multilayer memory die 12.

[0033] In some embodiments of this disclosure, system 1 may include an external device 30 and a memory system 40 coupled to the external device 30. The memory system 40 may include a memory 10 and a memory controller 20 coupled to the memory 10, wherein the memory controller 20 is used to control the memory 10 to store data. Exemplarily, the memory system 40 may be a memory module, such as a dual in-line memory module (DIMM). In this embodiment, the memory controller 20 may be located inside the memory system 40, integrated with the memory 10 in the same module or package.

[0034] The LTC 100 may be disposed in the buffer chip 11 of the memory 10, and the LTC 100 may be coupled to an external device 30 located outside the memory 10. In some embodiments of this disclosure, the external device 30 may be used to send a first data signal to the LTC 100. For example, during the power-on initialization process of the memory 10, the external device 30 may be an off-chip flash memory controller for sending redundancy repair information to the LTC 100; during the factory testing process of the memory 10, the external device 30 may be a test bench for sending test vectors to the LTC 100. In other embodiments, the external device 30 may also be used to receive a second data signal from the LTC 100, for example, after the memory 10 completes the failure bitmap reading, the external device 30 may obtain failure bitmap data from the LTC 100.

[0035] Optionally, the interface unit 101 of the LTC 100 may include multiple ports, such as a first port, a second port, an nth port, etc., where n is a positive integer greater than 2, wherein the first asynchronous FIFO 1021 may be coupled to the first port, and the second asynchronous FIFO 1022 may be coupled to the second port.

[0036] Furthermore, the first asynchronous FIFO 1021 may include a write end and a read end. The write end of the first asynchronous FIFO 1021 may be coupled to a first port to write the data received by the interface unit 101 from the interface unit 101 into the first asynchronous FIFO 1021. The second asynchronous FIFO 1022 may also include a write end and a read end. The read end of the second asynchronous FIFO 1022 may be coupled to a second port to output the second data signal buffered in the second asynchronous FIFO 1022 via the interface unit 101.

[0037] By placing the LTC within the buffer chip, the LTC can directly interact with at least one layer of bare memory via TSV for high-speed data exchange. Simultaneously, the LTC is coupled to external devices located outside the memory via a bus (e.g., APB), thus establishing a bidirectional data path between off-chip data loading and on-chip storage. Furthermore, external devices communicate with the memory system via the bus; external devices can access the memory through the memory controller or communicate directly with the LTC, thereby flexibly supporting the control and data interaction needs of the memory at different operational stages (e.g., memory initialization, testing, and repair).

[0038] refer to Figure 1 and Figure 3In some embodiments of this disclosure, the first asynchronous FIFO 1021 may include: a first write clock terminal (not shown) and a first read clock terminal (not shown), wherein the first write clock terminal is used to receive a first clock signal; and the first read clock terminal is used to receive a second clock signal asynchronous with the first clock signal, wherein the first clock signal is the clock signal of the clock domain in which the external device 30 is located, and the second clock signal is the clock signal of the clock domain in which the LTC 100 is located.

[0039] In digital circuit design, a clock domain refers to a collection of sequential logic circuits driven by the same clock signal. When two clock signals have different frequencies and / or no fixed phase relationship, they belong to different clock domains and can be called asynchronous clock domains. When data signals are transmitted directly between different clock domains, setup time or hold time violations may occur because the receiving end cannot determine the valid sampling time of the data from the sending end. This can cause flip-flops to enter a metastable state, leading to data sampling errors, uncertain logic states, or even system malfunctions.

[0040] The first write clock input of the first asynchronous FIFO 1021 can be used to receive a first clock signal, which controls the write operation of the first asynchronous FIFO 1021. In other words, the external device 30 can write a first data signal into the first asynchronous FIFO 1021 at the trigger edge (e.g., rising edge) of the first clock signal. The first read clock input of the first asynchronous FIFO 1021 can be used to receive a second clock signal, which controls the read operation of the first asynchronous FIFO 1021. In other words, the internal logic of LTC 100 can read the first data signal from the first asynchronous FIFO 1021 at the trigger edge of the second clock signal.

[0041] Because the first clock signal is asynchronous with the second clock signal, the write and read operations of the first asynchronous FIFO 1021 are controlled by two independent clock domains. On the one hand, the asynchronous FIFO, through its internal memory array and read / write pointer synchronization mechanism, isolates the write clock domain of the external device 30 from the read clock domain inside the LTC 100, enabling stable and reliable data transmission across clock domains and avoiding metastability issues. On the other hand, since the write and read operations are performed independently in different clock domains, the speed at which the external device 30 writes the first data signal to the first asynchronous FIFO 1021 is not limited by the read speed of the LTC 100's internal logic, and the speed at which the LTC 100's internal logic reads the first data signal from the first asynchronous FIFO 1021 is also not limited by the write speed of the external device 30. Therefore, the data transmission of the external device 30 and the data processing inside the LTC 100 can be performed independently and in parallel in different clock domains, achieving decoupling between the two and effectively eliminating the waiting time of the external device 30. Furthermore, since the two clock domains are isolated from each other, external devices 30 and LTC 100 can operate at their own suitable clock frequencies without needing to adapt to each other, thus improving the system's flexibility and compatibility.

[0042] Similarly, the second asynchronous FIFO 1022 may include: a second write clock terminal (not shown) and a second read clock terminal (not shown), the second write clock terminal being used to receive a second clock signal; and the second read clock terminal being used to receive a first clock signal asynchronous to the second clock signal, wherein the first clock signal is the clock signal of the clock domain in which the external device 30 is located, and the second clock signal is the clock signal of the clock domain in which the LTC 100 is located.

[0043] The second write clock input of the second asynchronous FIFO 1022 is used to receive a second clock signal, which controls the write operation of the second asynchronous FIFO 1022. In other words, the second data signal can be written to the second asynchronous FIFO 1022 at the trigger edge of the second clock signal. The second read clock input of the second asynchronous FIFO 1022 is used to receive a first clock signal, which controls the read operation of the second asynchronous FIFO 1022. In other words, the second data signal can be output to the external device 30 or GTC 300 via the interface unit 101 at the trigger edge of the first clock signal.

[0044] Because the second clock signal is asynchronous with the first clock signal, the write and read operations of the second asynchronous FIFO 1022 are controlled by two independent clock domains. The second asynchronous FIFO 1022 isolates the write clock domain inside the LTC 100 from the read clock domain of the external device 30 (or, GTC 300), enabling the second data signal to be stably and reliably transmitted from internal to external. Since the write and read operations are performed independently in different clock domains, the speed at which the LTC 100 supplies the second data signal is not limited by the external read speed, nor is the external read speed limited by the internal supply speed. Therefore, internal data supply and external data output are decoupled, eliminating the time that the external device 30 or GTC 300 spends waiting for internal data to be ready, effectively improving the transmission efficiency of the second data signal.

[0045] Alternatively, the control logic unit 103 can also be used to: generate a first ready signal in an active state based on the first asynchronous FIFO 1021 being in a non-full state, and output it to the external device 30, wherein the first ready signal in an active state indicates that the LTC 100 can receive the first data signal; and generate a first ready signal in an invalid state based on the first asynchronous FIFO 1021 being in a full state, and output it to the external device 30, wherein the first ready signal in an invalid state indicates that the LTC 100 cannot receive the first data signal.

[0046] Specifically, in this embodiment, "empty / full state" can be understood as the storage state of the first asynchronous FIFO 1021, which includes a non-full state and a full state. A non-full state indicates that there is still unoccupied storage space in the first asynchronous FIFO 1021, which can receive new first data signals written by the external device 30; a full state indicates that all storage space in the first asynchronous FIFO 1021 has been occupied, and new first data signals cannot be received.

[0047] When the first asynchronous FIFO 1021 is not full, the control logic unit 103 can generate a first ready signal in a valid state (e.g., high level) and output it to the external device 30. The valid first ready signal indicates that the LTC 100 can currently receive the first data signal, and the external device 30 can continue sending the next first data signal. When the first asynchronous FIFO 1021 is full, the control logic unit 103 can generate a first ready signal in an invalid state (e.g., low level) and output it to the external device 30. The invalid first ready signal indicates that the LTC 100 cannot currently receive the first data signal, and the external device 30 needs to pause transmission until the first ready signal returns to a valid state.

[0048] Since the valid and invalid states of the first ready signal are determined in real time by the empty / full state of the first asynchronous FIFO 1021, the external device 30 does not need to wait for the LTC 100 to finish processing before sending the next piece of data. Instead, it only needs to determine whether there is still available storage space in the first asynchronous FIFO 1021 based on the first ready signal. As long as the first ready signal is valid, the external device 30 can continuously send data, effectively eliminating the waiting time of the external device 30. Therefore, the data transmission of the external device 30 is not limited by the speed of data processing inside the LTC 100, improving bus utilization and data transmission efficiency.

[0049] Refer again Figures 1 to 3 In some embodiments of this disclosure, the buffer chip 11 may include: a storage interface control unit 200, which may be coupled to at least one layer of memory die 12 of the memory 10; the LTC 100 may also include: a processing unit 104, which may be coupled to the first asynchronous FIFO 1021 and the storage interface control unit 200, and is used to read and process a first data signal from the first asynchronous FIFO 1021, and output the processed first data signal to the storage interface control unit 200 for writing to at least one layer of memory die 12. The above processing may include converting the first data signal into an instruction format that matches the interface protocol of the at least one layer of memory die 12.

[0050] The processing unit 104 can read a first data signal from the first asynchronous FIFO 1021 and process the first data signal. For example, the processing may include converting the first data signal into an instruction format that matches the interface protocol of at least one layer of memory die 12. The interface protocol of the memory die 12 can be understood as the read / write control timing and command specifications followed by the memory die 12, such as the instruction encoding and timing requirements corresponding to row activation, column read / write, precharge, and other operations defined in the DRAM interface protocol.

[0051] After the processing unit 104 converts the first data signal into the instruction format required by the aforementioned interface protocol, the storage interface control unit 200 can correctly write the first data signal into at least one layer of memory die 12. The processed first data signal is provided to the storage interface control unit 200 via the processing unit 104, and the storage interface control unit 200 writes the processed first data signal into at least one layer of memory die 12. Thus, the first data signal travels from the external device 30 through the interface unit 101, the first asynchronous FIFO 1021, the processing unit 104, and the storage interface control unit 200, and is finally written into at least one layer of memory die 12, completing the complete transmission path of the incoming data stream.

[0052] In some embodiments of this disclosure, the processing unit 104 reads the first data signal from the first asynchronous FIFO 1021 and the external device 30 writes the first data signal to the first asynchronous FIFO 1021 independently in different clock domains, and the two do not block each other.

[0053] Furthermore, since the first asynchronous FIFO 1021 buffers the first data signal written by the external device 30, even if the processing speed of the processing unit 104 is lower than the writing speed of the external device 30 for a period of time, the data will not be lost, thus improving the system's fault tolerance and data reliability. After the processing unit 104 performs format conversion on the first data signal, the storage interface control unit 200 can directly write the converted data to the memory die 12 without needing to perform format adaptation again at the storage interface control unit 200, further improving the processing efficiency of the incoming data stream and effectively ensuring the reliability of the memory 10.

[0054] In some embodiments of this disclosure, the interface unit 101 may also be used to: receive the next first data signal when the first ready signal is in a valid state, wherein the operation of receiving the next first data signal is performed in parallel with the operation of the processing unit 104 processing the current first data signal.

[0055] In this embodiment, "current" and "next" describe two data entries that are adjacent in time during continuous data stream transmission. "Current" can be understood as the data entry that the processing unit 104 is currently reading from and processing from the first asynchronous FIFO 1021; "next" can be understood as the next data entry that the external device 30 will write to the first asynchronous FIFO 1021 immediately following the current data entry.

[0056] "Parallel execution" refers to the execution of two or more operations that at least partially overlap in time. Therefore, in the context of this disclosure, the operation of external device 30 writing the next first data signal to the first asynchronous FIFO 1021 and the operation of processing unit 104 reading and processing the current first data signal from the first asynchronous FIFO 1021 at least partially overlap in time. Since the write and read operations of the first asynchronous FIFO 1021 are controlled by different clock domains and do not block each other, the write and read operations can be performed simultaneously. It should be noted that "parallel" does not require the two operations to start and end strictly synchronously in every clock cycle, but rather means that, in terms of macroscopic timing, the two operations can overlap in time; for example, a write operation can begin before a read operation is completed, thus forming a pipelined data transmission.

[0057] For example, when the external device 30 writes the current first data signal to the first asynchronous FIFO 1021, the processing unit 104 cannot process the data immediately because the data has not yet been completely written to the first asynchronous FIFO 1021. However, after the current data is written to the first asynchronous FIFO 1021, the processing unit 104 can start reading and processing the current data. At the same time, since the first asynchronous FIFO 1021 is not full, the external device 30 can continue to write the next first data signal to the first asynchronous FIFO 1021. Thus, while the current data is being processed, the next data has been written to the FIFO, and the write operation and read operation overlap in time, realizing pipelined parallel processing.

[0058] Figure 4 This is a timing diagram of the power-on initialization process between an external device and a test controller, provided according to an exemplary embodiment of this disclosure.

[0059] Combination Figures 1 to 4 For example, the interface unit 101 may receive redundancy repair information as a first data signal in response to a power-on initialization command.

[0060] Taking the power-on initialization scenario of memory 10 as an example, this scenario can occur during the power-on initialization phase of memory 10. LTC 100 needs to load redundancy repair information from external device 30 (e.g., off-chip flash memory controller) to repair any faulty memory cells that may exist in memory 10, ensuring the reliability of memory 10. After being received by LTC 100, the redundancy repair information needs to be finally written into at least one layer of redundancy repair circuitry (e.g., redundant word lines or redundant bit lines) in the memory die 12 to complete the repair operation during the power-on initialization process.

[0061] Figure 4The signal timing diagram between external device 30 and LTC 100 during the power-on initialization phase is shown. The signals on the APB side may include: PCLK, PADDR, PSEL, PENABLE, PWRITE, PWDATA, and PREADY. PCLK represents the APB clock signal, which can be understood as the first clock signal in the clock domain of external device 30. PADDR represents the APB address signal, used to indicate the target address of the current APB transmission. PSEL represents the APB slave selection signal; a high level indicates that LTC 100 has been selected as the APB slave device. PENABLE represents the APB enable signal; a high level indicates that the APB transmission has entered the data phase. PWRITE represents the APB write enable signal; a high level indicates that the current transmission is a write operation. PWDATA represents the APB write data signal, i.e., the first data signal written by external device 30 to LTC 100. PREADY represents the APB slave device ready signal, which is the first ready signal returned by LTC100 to external device 30. A high level indicates that LTC100 can receive the first data signal, and a low level indicates reverse voltage. Reverse voltage means that LTC100 actively instructs external device 30 to pause data transmission by pulling PREADY low, thereby preventing data from continuing to be written to the full first asynchronous FIFO 1021.

[0062] Figure 4The document also shows relevant signals internal to the LTC 100, including: LTC_CLK, FIFO_FULL, FIFO_EMPTY, FIFO_WR_PTR, FIFO_WR_PTR_S1, FIFO_WR_PTR_S2, FIFO_RD_PTR, FIFO_RD_PTR_S1, FIFO_RD_PTR_S2, FIFO_RD_EN, and RDN_BUSY. LTC_CLK is the internal operating clock signal of the LTC 100, which can be understood as the second clock signal in the clock domain of the LTC 100. FIFO_FULL is the FIFO full flag signal; a high level indicates that the first asynchronous FIFO 1021 is full, and all its storage space is occupied. FIFO_EMPTY is the FIFO empty flag signal; a high level indicates that the first asynchronous FIFO 1021 is empty, and it does not buffer any data. FIFO_WR_PTR is the write pointer signal for the first asynchronous FIFO 1021, used to indicate the storage location corresponding to the current write operation; FIFO_WR_PTR_S1 and FIFO_WR_PTR_S2 are synchronization status signals for the write pointer, used to achieve synchronous transmission of the write pointer between different clock domains. FIFO_RD_PTR is the read pointer signal for the first asynchronous FIFO 1021, used to indicate the storage location corresponding to the current read operation; FIFO_RD_PTR_S1 and FIFO_RD_PTR_S2 are synchronization status signals for the read pointer, used to achieve synchronous transmission of the read pointer between different clock domains. FIFO_RD_EN is the FIFO read enable signal; a high level indicates that the read operation of the first asynchronous FIFO 1021 is valid; RDN_BUSY is the RDN (Redundancy) loading busy signal; a high level indicates that the LTC 100 is currently performing an RDN loading operation, and cannot receive new RDN repair information at this time. The aforementioned internal signals are used together to control the read and write operations of the first asynchronous FIFO 1021 and the determination of its empty or full state, and to collaboratively complete the caching and loading process of RDN repair information.

[0063] In the first clock cycle of PCLK ( Figure 4 During the period indicated by the number 1 above the PCLK waveform, valid address and data information appears on PADDR and PWDATA, but PSEL is low, indicating that LTC 100 has not yet been selected in the current period. At this time, the first asynchronous FIFO 1021 of LTC 100 is not full. PREADY remains low because LTC 100 has not yet been selected by PSEL, and APB transmission has not officially started.

[0064] In the second clock cycle of PCLK ( Figure 4During the period represented by the number 2 above the PCLK waveform, PSEL goes high and PWRITE goes high. A high PSEL level indicates that the APB has currently selected LTC 100 as an APB slave device, and a high PWRITE level indicates that the current transfer is a write operation. PENABLE remains low, indicating that the APB transfer is still in the address phase. At this time, the first asynchronous FIFO 1021 is not full, and the control logic unit 103 sets PREADY high to indicate that LTC 100 can currently receive the first data signal.

[0065] In the third clock cycle of PCLK ( Figure 4 The PENABLE signal goes high (representing the period indicated by the number 3 above the PCLK waveform), indicating that the APB transmission has entered the data phase. The interface unit 101 of the LTC 100 samples the first data signal on PWDATA on the rising edge of PCLK and writes it into the first asynchronous FIFO 1021. Because PREADY remains high, the external device 30 can prepare to send the next first data signal without waiting for the LTC 100's internal processing to complete after writing the current first data signal.

[0066] In the fourth clock cycle of PCLK ( Figure 4 The PENABLE signal remains high (represented by the number 4 above the PCLK waveform), indicating that the APB transmission continues in the data phase. The LTC 100's interface unit 101 completes the sampling and writing operation of the current first data signal. At the end of the fourth clock cycle of PCLK, PENABLE transitions from high to low, with the falling edge indicating that the current transmission has been completed.

[0067] exist Figure 4 In the subsequent clock cycles shown, the timing relationship between the address phase and the data phase described above is repeated cyclically. PSEL goes high again to reselect LTC 100, and PENABLE then goes high again to enter the data phase of the next transmission. External device 30 continuously sends redundancy repair information to LTC 100, while LTC 100 internally processes the received data in parallel, thereby realizing pipelined data transmission.

[0068] When the first asynchronous FIFO 1021 is full of data (i.e., FIFO_FULL becomes high), the control logic unit 103 can set PREADY to low (i.e., reverse voltage). After the external device 30 detects that PREADY is low, it can pause transmission until the data buffered in the first asynchronous FIFO 1021 is read by the processing unit 104 and restored to a non-full state (FIFO_FULL becomes low). Then PREADY becomes high again, and the external device 30 continues to transmit.

[0069] exist Figure 4 During the multiple PCLK cycles shown, as redundancy repair information is written to the first asynchronous FIFO 1021 one by one, FIFO_WR_PTR is continuously incremented to point to the next write position, and the FIFO_FULL and FIFO_EMPTY flags are updated accordingly. When RDN_BUSY is high, it indicates that LTC 100 is currently performing an RDN loading operation, and external device 30 must wait for RDN_BUSY to go low before it can continue to send new redundancy repair information.

[0070] It should be noted that this disclosure uses the process of the first data signal being buffered by the first asynchronous FIFO within one transmission cycle as an example. The signal changes and operations in subsequent transmission cycles can be deduced by analogy. Through this method, the speed at which the external device 30 sends redundancy repair information to the LTC 100 is not limited by the internal processing speed of the LTC 100. The non-full state of the first asynchronous FIFO 1021 can trigger PREADY to be active, allowing the external device 30 to continuously send redundancy repair information. Furthermore, the LTC 100 independently reads and processes the buffered data from the first asynchronous FIFO 1021 using its own operating clock. The data writing by the external device 30 and the data processing within the LTC 100 are performed in parallel under different clock domains, without blocking each other. Therefore, the external device 30 does not need to wait for the LTC 100 to complete its internal processing before sending the next data, effectively eliminating the waiting time of the external device 30, improving bus utilization and data transmission efficiency, and significantly shortening the power-on initialization time of the memory 10. In addition, the data caching method of the first asynchronous FIFO 1021 can effectively control chip area overhead in scenarios where a large amount of redundant repair information is cached.

[0071] Figure 5 This is a timing diagram of the external device 30 and the test controller during the test process according to an exemplary embodiment of this disclosure.

[0072] Combination Figures 1 to 3 , Figure 5 For example, interface unit 101 may receive a test vector as a first data signal in response to a built-in self-test command.

[0073] Taking the factory testing scenario of memory 10 as an example, this scenario can occur during the testing phase of memory 10. LTC 100 needs to load test vectors from external device 30 (e.g., test equipment) to perform functional testing and performance verification on memory 10, ensuring the yield and reliability of memory 10. After being received by LTC 100, the test vectors need to be written into the memory array in at least one layer of memory die 12 to complete the test operation.

[0074] Figure 5 The signal timing diagram between external device 30 and LTC 100 during the testing phase is shown. The signals on the APB side may include: PCLK, PADDR, PSEL, PENABLE, PWRITE, PWDATA, and PREADY. PCLK represents the APB clock signal, which can be understood as the first clock signal in the clock domain of external device 30. PADDR represents the APB address signal, used to indicate the target address of the current APB transmission. PSEL represents the APB slave device selection signal; a high level indicates that LTC100 has been selected as the APB slave device. PENABLE represents the APB enable signal; a high level indicates that the APB transmission has entered the data phase. PWRITE represents the APB write enable signal; a high level indicates that the current transmission is a write operation. PWDATA represents the APB write data signal, i.e., the first data signal written by external device 30 to LTC 100. PREADY represents the APB ready signal from the device, that is, the first ready signal returned by LTC 100 to external device 30. A high level indicates that LTC 100 can receive the first data signal, and a low level indicates reverse voltage. Reverse voltage means that LTC 100 actively instructs external device 30 to pause data transmission by pulling PREADY low, so as to prevent data from continuing to be written to the full first asynchronous FIFO 1021.

[0075] In addition, relevant signals within the LTC 100 include: PLL_400M, FIFO_WR_EN, wr_ptr_gray_f, wr_ptr_gray, wr_ptr_bin_sync, FIFO_RD_EN, FIFO_RDATA, LTC_REGWR_EN, LTC_REGADD, and LTC_REGDIN. PLL_400M is a 400MHz clock signal output from the Phase-Locked Loop (PLL), used to provide the operating clock for the internal logic of the LTC 100; it can be understood as the second clock signal in the clock domain of the LTC 100. FIFO_WR_EN is the FIFO write enable signal; a high level indicates that current data is being written to the first asynchronous FIFO 1021. wr_ptr_gray_f and wr_ptr_gray are Gray code synchronization signals for the write pointer, and wr_ptr_bin_sync is the binary synchronization signal for the write pointer; all three are used together to ensure stable transmission of the write pointer between different clock domains. FIFO_RD_EN is the FIFO read enable signal; a high level indicates that a read operation of the first asynchronous FIFO 1021 is valid. FIFO_RDATA is the FIFO read data signal, which can be understood as the first data signal read from the first asynchronous FIFO 1021. LTC_REGWR_EN is the LTC register write enable signal, LTC_REGADD is the LTC register address signal, and LTC_REGDIN is the LTC register write data input signal. These register control signals are used to configure the internal registers of the LTC 100 during testing.

[0076] The relevant signals within the aforementioned LTC 100 are used together to control the read / write operations and full / empty status of the first asynchronous FIFO 1021, and to collaboratively complete the caching and processing of the test vector. In the first clock cycle of PCLK ( Figure 5 The period indicated by the number 1 above the PCLK waveform shows valid address information on PADDR and valid test vector data on PWDATA, but PSEL is low, indicating that LTC 100 has not been selected in the current period. Additionally, FIFO_WR_EN is low, indicating that a write operation to the first asynchronous FIFO 1021 has not yet begun.

[0077] In the second clock cycle of PCLK ( Figure 5During the period represented by the number 2 above the PCLK waveform, PSEL goes high and PWRITE goes high, indicating that the current transmission is a write operation. FIFO_WR_EN goes high, and interface unit 101 writes the first data signal into the first asynchronous FIFO 1021. At this time, the first asynchronous FIFO 1021 of LTC 100 is not full, and control logic unit 103 sets PREADY high to indicate that LTC 100 can currently receive the first data signal. PENABLE remains low, indicating that APB transmission is in the address stage.

[0078] In the third clock cycle of PCLK ( Figure 5 The PENABLE signal goes high (representing the period indicated by the number 3 above the PCLK waveform), indicating that the APB transmission has entered the data phase. The FIFO_WR_EN signal goes low, indicating that the write operation has been completed in the address phase, and no further write operations are performed in the data phase. The processing unit 104 of the LTC 100 reads the current first data signal from the first asynchronous FIFO 1021 and processes it. Since PREADY remains high, the external device 30 can continue to send the next first data signal.

[0079] In the fourth clock cycle of PCLK ( Figure 5 The PENABLE signal remains high, indicating that the APB transmission continues in the data phase. The PREADY signal remains high, indicating that the LTC 100 can still receive the first data signal, and the external device 30 can continue sending the next first data signal after the current transmission is completed. The FIFO_WR_EN signal is low, indicating that the write enable of the first asynchronous FIFO 1021 is disabled, and no write operation to the first asynchronous FIFO 1021 is performed during the current data phase. The LTC 100 internally processes the buffered data independently using its own operating clock.

[0080] In the fifth clock cycle of PCLK ( Figure 5 When the number 5 above the PCLK waveform indicates the period, the PENABLE signal goes low, indicating the end of the current APB data transmission phase. When the PREADY signal goes low, it indicates that the current transmission is complete, the LTC 100 is no longer in a receiveable state, and the external device 30 must wait for PREADY to go high again before initiating the next transmission.

[0081] The above process is executed cyclically. External device 30 continuously sends test vectors to LTC 100, while LTC 100 internally processes the received data in parallel, thereby realizing pipelined data transmission. When the first asynchronous FIFO 1021 is full of data (FIFO_FULL becomes high), the control logic unit 103 can set PREADY to low (i.e., reverse voltage). After external device 30 detects that PREADY is low, it can pause transmission until the data buffered in the first asynchronous FIFO 1021 is read by the processing unit 104 and restored to a non-full state (FIFO_FULL becomes low). Then PREADY becomes high again, and external device 30 continues transmission.

[0082] It should be noted that this disclosure uses the process of the first data signal being buffered by the first asynchronous FIFO within one transmission cycle as an example. The signal changes and operations in subsequent transmission cycles can be deduced by analogy. Through this method, the speed at which the external device 30 sends test vectors to the LTC 100 is not limited by the internal processing speed of the LTC 100. The non-full state of the first asynchronous FIFO 1021 can trigger PREADY to be active, allowing the external device 30 to continuously send test vectors. Furthermore, the LTC 100 independently reads and processes the buffered data from the first asynchronous FIFO 1021 using its own operating clock. The data writing by the external device 30 and the data processing within the LTC 100 are performed in parallel under different clock domains, without blocking each other. Therefore, the external device 30 does not need to wait for the LTC 100 to complete its internal processing before sending the next test vector, effectively eliminating the waiting time of the external device 30, improving bus utilization and data transmission efficiency, and significantly shortening the testing time of the memory 10. In addition, the first asynchronous FIFO 1021's data caching method can effectively control chip area overhead in scenarios where a large number of test vectors are cached.

[0083] In addition, it should be noted that, Figure 4 and Figure 5 The power-on initialization scenario and the test scenario are illustrated separately. These two scenarios occur at different stages of the memory process: power-on initialization occurs during chip power-on, and the test occurs during factory testing. Since the two scenarios do not overlap in time, they can be time-division multiplexed using the same first asynchronous FIFO 1021, eliminating the need for separate cache structures for each scenario and further reducing hardware overhead. This multiplexing relationship only applies to the first asynchronous FIFO 1021 within the LTC 100. In the incoming data flow scenario, the redundancy repair information loaded during power-on initialization and the test vector loaded during testing can be cached using the same first asynchronous FIFO 1021.

[0084] refer to Figures 1 to 2In some embodiments of this disclosure, the storage interface control unit 200 can be used to read a second data signal from at least one layer of memory die 12 and provide the second data signal to a second asynchronous FIFO 1022.

[0085] In this embodiment, the storage interface control unit 200 is coupled to at least one layer of memory die 12 and can provide the second data signal read from the at least one layer of memory die 12 to the second asynchronous FIFO 1022. Thus, the second data signal enters the second asynchronous FIFO 1022 from the at least one layer of memory die 12 via the storage interface control unit 200, completing the source acquisition of the outgoing data stream.

[0086] The writing of the second data signal from the storage interface control unit 200 to the second asynchronous FIFO 1022 and the reading of the second data signal from the second asynchronous FIFO 1022 by the interface unit 101 are performed independently in different clock domains and do not block each other. In other words, the speed at which the storage interface control unit 200 supplies the second data signal to the second asynchronous FIFO 1022 is not limited by the read speed of the external device 30 or GTC 300, and the speed at which the interface unit 101 reads the second data signal from the second asynchronous FIFO 1022 is also not limited by the supply speed of the storage interface control unit 200.

[0087] While the storage interface control unit 200 continuously provides the second data signal to the second asynchronous FIFO 1022, the interface unit 101 can read the buffered data from the second asynchronous FIFO 1022 in parallel and output it to the external device 30 or GTC 300, thereby ensuring the efficient flow of data outgoing from the LTC 100. Furthermore, since the second asynchronous FIFO 1022 buffers the second data signal provided by the storage interface control unit 200, even if the read speed of the external device 30 or GTC 300 is lower than the supply speed of the storage interface control unit 200 for a period of time, data will not be lost, improving the system's fault tolerance and data reliability.

[0088] Optionally, the second data signal may include test results or failure bitmap data from memory 10. In this embodiment, the storage interface control unit 200 may also, in response to a repair data read command, read the failure bitmap data as the second data signal from at least one layer of memory die 12 and provide the failure bitmap data to the second asynchronous FIFO 1022.

[0089] Optionally, the GTC 300 can also read the second data signal output by the interface unit 101 when the second ready signal is active. Thus, the second data signal reaches the GTC 300 after passing through the second asynchronous FIFO 1022 and the interface unit 101, completing the full transmission path of the outgoing data stream. The data flows from at least one layer of memory die 12 through the storage interface control unit 200, the second asynchronous FIFO 1022, and the interface unit 101 to the GTC 300.

[0090] It is understood that the above embodiments are described using GTC 300 as the receiver of the outgoing data stream, but this disclosure is not limited thereto. In other embodiments, the receiver of the second data signal may also be an external device 30 (such as...). Figure 3 (As shown), for example, an off-chip flash memory controller or a test bench. When the external device 30 is the receiver, the interface unit 101 can also output a second data signal to the external device 30 when the second ready signal is valid. Its operation and working principle are similar to those described above with reference to GTC 300, and will not be repeated here. GTC 300 (or, external device 30, etc.) initiates reading based on the valid state of the second ready signal, without polling or waiting, further improving the reading efficiency of the LTC 100's outgoing data stream.

[0091] For example, the control logic unit 103 may generate a second ready signal in an active state and output it to the GTC 300 when the second asynchronous FIFO 1022 is in a non-empty state, wherein the active second ready signal indicates that the LTC 100 can output the second data signal; and generate a second ready signal in an invalid state and output it to the GTC 300 when the second asynchronous FIFO 1022 is in an empty state, wherein the invalid second ready signal indicates that the LTC 100 cannot output the second data signal.

[0092] Specifically, in this embodiment, "full / empty state" can be understood as the storage state of the second asynchronous FIFO 1022, which may include a non-empty state and an empty state. A non-empty state indicates that there is a cached second data signal in the second asynchronous FIFO 1022, which can be read by the GTC 300; an empty state indicates that no second data signal is cached in the second asynchronous FIFO 1022, and there is no data available for reading.

[0093] When the second asynchronous FIFO 1022 is not empty, the control logic unit 103 can generate a valid second ready signal and output it to the GTC 300. This valid second ready signal indicates that the LTC 100 can currently output the second data signal, and the GTC 300 can read the second data signal from the second asynchronous FIFO 1022. When the second asynchronous FIFO 1022 is empty, the control logic unit 103 can generate an invalid second ready signal and output it to the GTC 300. This invalid second ready signal indicates that the LTC 100 cannot currently output the second data signal, and the GTC 300 must pause reading until the second ready signal becomes valid again.

[0094] Since the valid and invalid states of the second ready signal are determined in real time by the empty / full state of the second asynchronous FIFO 1022, the GTC 300 does not need to wait for the LTC 100 to prepare the next second data signal before initiating a read operation. Instead, it only needs to determine whether the second asynchronous FIFO 1022 is not empty based on the second ready signal. As long as the second ready signal is valid, the GTC 300 can continuously read data, while the storage interface control unit 200 can simultaneously write new second data signals to the second asynchronous FIFO 1022. Therefore, internal data supply and GTC 300 data reading occur in parallel under different clock domains, effectively eliminating the waiting time of the GTC 300 and improving the transmission efficiency of the outgoing data stream.

[0095] Furthermore, in some embodiments of this disclosure, the interface unit 101 may also be used to: output the current second data signal when the second ready signal is in a valid state, wherein the operation of outputting the current second data signal and the operation of the storage interface control unit 200 providing the next second data signal to the second asynchronous FIFO 1022 are performed in parallel.

[0096] Specifically, interface unit 101 can output the current second data signal when the second ready signal is active. "Current" can be understood as the second data signal that interface unit 101 is currently reading from the second asynchronous FIFO 1022 and outputting; "next data" refers to the next second data signal that the storage interface control unit 200 will provide to the second asynchronous FIFO 1022 immediately following the current data. The two are sequential in time. While the current data is being output, the next data has not yet been provided to the second asynchronous FIFO 1022.

[0097] "Parallel execution" refers to the execution of two or more operations that at least partially overlap in time. In the context of this disclosure, the operation of the storage interface control unit 200 to provide the next second data signal to the second asynchronous FIFO 1022 (i.e., the provide operation) and the operation of the interface unit 101 to read from the second asynchronous FIFO 1022 and output the current second data signal (i.e., the output operation) at least partially overlap in time.

[0098] Since the write and read operations of the second asynchronous FIFO 1022 are controlled by different clock domains and do not block each other, the aforementioned supply and output operations can be performed simultaneously. It should be noted that "parallelism" does not require the two operations to start and end strictly synchronously in every clock cycle, but rather means that, in terms of macroscopic timing, the two operations can overlap in time, thereby forming a pipelined data transmission.

[0099] When the storage interface control unit 200 provides the current second data signal to the second asynchronous FIFO 1022, the interface unit 101 cannot immediately output the data because the data has not yet been fully written into the second asynchronous FIFO 1022. However, after the current data is provided to the second asynchronous FIFO 1022, the interface unit 101 can start reading and output the current data. At the same time, since the second asynchronous FIFO 1022 is not full, it means that the second asynchronous FIFO 1022 still has available storage space, and the storage interface control unit 200 can continue to provide the next second data signal to the second asynchronous FIFO 1022. Thus, while the current data is being output, the next data has been provided to the FIFO, and the provision and output operations overlap in time, realizing pipelined parallel processing of the outgoing data stream.

[0100] In this manner, the storage interface control unit 200 provides the next second data signal to the second asynchronous FIFO 1022, and the interface unit 101 outputs the current second data signal in parallel under different clock domains, without blocking each other. External device 30 (such as...) Figure 3 As shown in the figure, the GTC 300 can read continuously without waiting for the LTC 100 to prepare the next data, effectively eliminating the waiting time of the external device 30 or GTC 300 and improving the transmission efficiency of the LTC 100 outgoing data stream.

[0101] Figure 6 This is a timing diagram of the test controller and test management controller during the failure bitmap reading process according to an exemplary embodiment of this disclosure.

[0102] refer to Figure 1 , Figure 2 and Figure 6For example, the storage interface control unit 200 may, in response to a repair data read command, read failure bitmap data as a second data signal from at least one layer of memory die 12 and provide the failure bitmap data to the second asynchronous FIFO 1022.

[0103] Taking the failure bitmap reading scenario of memory 10 as an example, this scenario can occur after memory 10 completes BIST (Built-In Self-Test). LTC 100 needs to report the failure bitmap data read from at least one layer of memory die 12 to GTC 300 for subsequent hardware repair. The failure bitmap data records the location information of the failed memory cell in memory 10, and its accurate and efficient transmission to GTC 300 is crucial for subsequent repair operations.

[0104] Figure 6 The signal timing diagram between the LTC 100 and GTC 300 during the failure bitmap read phase is shown. Figure 4 , Figure 5 The external device 30, acting as the APB master, writes data to the LTC 100 differently. Figure 6 The GTC 300, acting as the APB master, reads data from the LTC100.

[0105] Figure 6 The signals on the APB side include: PCLK, PADDR, PSEL, PENABLE, PWRITE, PRDATA, and PREADY. PCLK represents the APB clock signal, which can be understood as the first clock signal in the clock domain of the GTC 300. PADDR represents the APB address signal, used to indicate the target address of the current APB transmission; it can also be understood as the register address in the LTC 100 that stores the failure bitmap data. PSEL represents the APB slave select signal; a high level indicates that the LTC 100 has been selected as the APB slave. PENABLE represents the APB enable signal; a high level indicates that the APB transmission has entered the data phase. PWRITE represents the APB write enable signal; a low level indicates that the current transmission is a read operation. PRDATA represents the APB read data signal, which is the second data signal output by the LTC100 to the GTC 300. PREADY represents the APB slave device ready signal, or the second ready signal returned from LTC 100 to GTC 300. A high level indicates that LTC 100 can output a second data signal, while a low level indicates reverse voltage. Reverse voltage means that LTC 100 actively instructs GTC 300 to pause data reading by pulling PREADY low, thereby preventing the reading of invalid data from the empty second asynchronous FIFO 1022.

[0106] Figure 6The relevant signals inside the LTC 100 may include: LTC_REGDOUT, FIFO_MEM, FIFO_WR_EN, FIFO_WR_PTR[1:0], FIFO_WR_PTR_S1, FIFO_WR_PTR_S2, FIFO_EMPTY, FIFO_RD_PTR[1:0], FIFO_RD_PTR_S1[1:0], and FIFO_RD_PTR_S2[1:0]. LTC_REGDOUT is the LTC register data output signal, which can be understood as the second data signal output by the LTC 100 to the GTC 300. FIFO_MEM is the FIFO storage array signal, used to indicate the data content stored in the second asynchronous FIFO 1022. FIFO_WR_EN is the FIFO write enable signal; a high level indicates that invalid bitmap data has been written to the second asynchronous FIFO 1022. FIFO_WR_PTR[1:0] is the write pointer signal of the second asynchronous FIFO 1022, used to indicate the storage location corresponding to the current write operation; FIFO_WR_PTR_S1 and FIFO_WR_PTR_S2 are the synchronization status signals of the write pointer, used to achieve stable transmission of the write pointer between different clock domains. FIFO_EMPTY is the FIFO empty flag signal, a high level indicates that the second asynchronous FIFO 1022 is empty. FIFO_RD_PTR[1:0] is the read pointer signal of the second asynchronous FIFO 1022, used to indicate the storage location corresponding to the current read operation; FIFO_RD_PTR_S1[1:0] and FIFO_RD_PTR_S2[1:0] are the synchronization status signals of the read pointer, used to achieve stable transmission of the read pointer between different clock domains. The above internal signals are used together to control the read and write operations and the judgment of empty and full states of the second asynchronous FIFO 1022, and to coordinate the caching and reading process of the failed bitmap data.

[0107] It should be noted that, Figure 6 The basic functions and timing relationships of PCLK, PADDR, PSEL, PENABLE, PWRITE, and PREADY have been explained above. Figure 4 and Figure 5 The following description will use the same definitions and will not be repeated.

[0108] In the first clock cycle of PCLK ( Figure 6(The period represented by the number 1 above the PCLK waveform). GTC 300 sets PSEL high and PWRITE low. A high PSEL level indicates that APB has currently selected LTC 100 as an APB slave device, and a low PWRITE level indicates that the current transfer is a read operation. Valid address information appears on PADDR. At this time, LTC 100's second asynchronous FIFO 1022 has not yet buffered valid invalid bitmap data, and control logic unit 103 sets PREADY low to indicate that LTC 100 is not yet ready to output the second data signal.

[0109] From the second clock cycle to the eighth clock cycle of PCLK ( Figure 6 During the PCLK waveform (represented by numbers 2 to 8), PSEL and PENABLE remain high, and APB transmission continues in the data phase. In the second to fifth clock cycles, PREADY remains low, indicating that valid failure bitmap data has not yet been cached in the second asynchronous FIFO 1022, and LTC 100 cannot output the second data signal. During this period, the storage interface control unit 200 continuously reads failure bitmap data from at least one layer of memory die 12 and provides it to the second asynchronous FIFO 1022. In the sixth clock cycle, PREADY goes high, indicating that valid failure bitmap data has been cached in the second asynchronous FIFO 1022, and LTC 100 is now able to output the second data signal. The interface unit 101 of LTC 100 drives the current second data signal in the second asynchronous FIFO 1022 to PRDATA, and GTC 300 samples this data. In the seventh and eighth clock cycles, PREADY goes low. After the eighth clock cycle of PCLK, PSEL and PENABLE transition from high to low, indicating that the current transfer has been completed.

[0110] The above process is executed cyclically. The GTC 300 continuously reads failed bitmap data from the LTC 100, while the storage interface control unit 200 provides new data to the second asynchronous FIFO 1022 in parallel, thus achieving pipelined data transmission. When the second asynchronous FIFO 1022 is empty, the control logic unit 103 can set PREADY to a low level (i.e., reverse voltage). Upon detecting that PREADY is low, the GTC 300 can pause reading until data is written to the second asynchronous FIFO 1022 again, restoring it to a non-empty state. Then, PREADY returns to a high level, and the GTC 300 continues reading.

[0111] It should be noted that the textual description in this disclosure uses the process of the second data signal being buffered by the second asynchronous FIFO 1022 within one transmission cycle as an example. The signal changes and operations in subsequent transmission cycles can be deduced by analogy with the above description. Through the above method, the speed at which the storage interface control unit 200 provides the failure bitmap data to the second asynchronous FIFO 1022 is not limited by the read speed of the GTC 300. The non-empty state of the second asynchronous FIFO 1022 can trigger PREADY to be valid, allowing the GTC 300 to continuously read the failure bitmap data. Furthermore, the storage interface control unit 200 writes data to the second asynchronous FIFO 1022 independently using the internal operating clock of the LTC 100. The data supply of the storage interface control unit 200 and the data reading of the GTC 300 are performed in parallel under different clock domains, and the two do not block each other. Therefore, the GTC 300 can continuously read data without waiting for the LTC 100 to prepare the next data, effectively eliminating the waiting time of the GTC 300, improving bus utilization and data transmission efficiency, and significantly shortening the read time of the failure bitmap data. In addition, the second asynchronous FIFO 1022's data caching method can effectively control chip area overhead in scenarios where a large amount of invalid bitmap data is cached.

[0112] Optionally, the buffer capacity of the first asynchronous FIFO 1021 can be a power of 2, where N is a positive integer; alternatively, the buffer capacity of the second asynchronous FIFO 1022 can be a power of 2, where M is a positive integer. Alternatively, the buffer capacity of the first asynchronous FIFO 1021 can be a power of 2, and the buffer capacity of the second asynchronous FIFO 1022 can be a power of 2, where both N and M are positive integers. In this embodiment, as one option, N and M can be equal positive integers; as another option, N and M can be unequal positive integers.

[0113] In the context of FIFO, "buffer capacity" refers to the number of data entries that the FIFO can store simultaneously; in the field of digital circuits, it can also be called "depth." Optionally, the buffer capacity of the first asynchronous FIFO 1021 is a power of 2, such as 2, 4, 8, 16, etc. Optionally, the buffer capacity of the second asynchronous FIFO 1022 is a power of 2, such as 2, 4, 8, 16, etc. Furthermore, the buffer capacity of the first asynchronous FIFO 1021 and the buffer capacity of the second asynchronous FIFO 1022 can be equal, and both can have a buffer capacity of 2.

[0114] This implementation allows the read and write pointers of the FIFOs (e.g., the first asynchronous FIFO 1021 and the second asynchronous FIFO 1022) to be synchronized across clock domains using Gray code, ensuring the accurate generation of empty / full flags. With a cache capacity of 2, the FIFO can promptly respond to external write or read requests when not full, avoiding frequent triggering of full signals and interruption of pipeline transmission when the cache capacity is 1, and also preventing wasted chip area due to excessive depth. Thus, a balance is achieved between chip area overhead and data transmission efficiency while ensuring data transmission reliability.

[0115] Figures 7 to 8 These are flowcharts of the operation method 2 of the test controller provided according to the exemplary embodiments of this disclosure.

[0116] like Figure 7 and Figure 8 As shown, some embodiments of this disclosure provide a method 2 for operating a test controller.

[0117] In some embodiments of this disclosure, the operation method 2 of the test controller includes: Step S11: Receive the first data signal through the interface unit.

[0118] Step S12: The first data signal is buffered by the first asynchronous FIFO, wherein a first ready signal is generated by the control logic unit according to the empty or full state of the first asynchronous FIFO to indicate whether the LTC can receive the first data signal.

[0119] In some embodiments of this disclosure, the operation method 2 of the test controller includes: Step S21: The second data signal is buffered by the second asynchronous FIFO, wherein a second ready signal is generated by the control logic unit according to the empty or full state of the second asynchronous FIFO to indicate whether the LTC can output the second data signal.

[0120] Step S22: Output the second data signal through the interface unit.

[0121] In some embodiments of this disclosure, the operation method 2 of the test controller includes: Step S11: Receive the first data signal through the interface unit.

[0122] Step S12: The first data signal is buffered by the first asynchronous FIFO, wherein a first ready signal is generated by the control logic unit according to the empty or full state of the first asynchronous FIFO to indicate whether the LTC can receive the first data signal.

[0123] Step S21: The second data signal is buffered by the second asynchronous FIFO, wherein a second ready signal is generated by the control logic unit according to the empty or full state of the second asynchronous FIFO to indicate whether the LTC can output the second data signal.

[0124] Step S22: Output the second data signal through the interface unit.

[0125] In other words, the test controller operation method 2 includes at least one of an LTC input operation and an output operation, wherein the input operation involves receiving and buffering a first data signal and generating a first ready signal; the output operation involves buffering and outputting a second data signal and generating a second ready signal. The above-mentioned input and output operations can be independent of each other, executed separately or simultaneously in parallel, and this disclosure does not limit this.

[0126] Specifically, the LTC is a hardware module within the memory used for testing, initialization, and repair management, and can be located within the memory's buffer chip. The LTC can communicate with external devices via a bus (e.g., APB). Additionally, the LTC can also communicate with the GTC within the buffer chip. For example, the GTC can be used to read failure bitmap data from the LTC after memory testing is complete, for subsequent hardware repair.

[0127] Therefore, the LTC has two data streams flowing in opposite directions: the inbound data stream flows from the external device to the LTC, and the outbound data stream flows from the LTC to the external device or GTC. The inbound data stream may include redundancy repair information or test vectors sent by the external device, while the outbound data stream may include test results or failure bitmap data sent by the LTC to the external device or GTC. With this configuration, the LTC can perform bidirectional data transmission with the external device or GTC in different scenarios and according to different operating stages and task requirements.

[0128] As memory becomes smaller and more integrated, the amount of data that LTCs need to process is increasing, placing higher demands on data transfer efficiency. In scenarios such as power-on initialization, factory testing, and failure repair, LTCs need to perform a large amount of data interaction, and inbound and outbound data transfers often need to be performed independently and efficiently.

[0129] According to at least one embodiment of this disclosure, the LTC includes at least one of a first asynchronous FIFO and a second asynchronous FIFO. The first asynchronous FIFO buffers a first data signal entering the LTC. The first data signal is temporarily stored after being written to the first asynchronous FIFO by the interface unit, and is then read by the internal logic for subsequent data flow. Since the writing and reading of the first asynchronous FIFO do not block each other, data reception and internal data flow of the LTC are decoupled. The second asynchronous FIFO buffers a second data signal. The second data signal is temporarily stored after being written to the second asynchronous FIFO, and is then output after being read by the interface unit. Since the writing and reading of the second asynchronous FIFO do not block each other, internal data supply and data output of the LTC are decoupled. Furthermore, the control logic unit generates a ready signal based on the empty / full state of at least one of the first and second asynchronous FIFOs to indicate whether the test controller can receive or output the corresponding data signal. This improves the data transmission efficiency of the LTC while effectively controlling its hardware overhead.

[0130] refer to Figures 1 to 3 , Figure 7 The LTC 100 is located in the buffer chip 11 of the memory 10. The LTC 100 is coupled to an external device 30 located outside the memory 10. The operation method 2 of the test controller may also include: sending a first data signal from the external device 30 to the LTC 100.

[0131] For example, during the power-on initialization process of memory 10, external device 30 may be an off-chip flash memory controller used to send redundancy repair information to LTC 100; during the factory testing process of memory 10, external device 30 may be a test bench used to send test vectors to LTC 100. In other embodiments, external device 30 may also be used to receive a second data signal from LTC 100, for example, after memory 10 completes the failure bitmap reading, external device 30 may obtain failure bitmap data from LTC 100.

[0132] By placing the LTC within the buffer chip, the LTC can directly interact with at least one layer of bare memory via TSV for high-speed data exchange. Simultaneously, the LTC is coupled to external devices located outside the memory via a bus (e.g., APB), thus establishing a bidirectional data path between off-chip data loading and on-chip storage. Furthermore, external devices communicate with the memory system via the bus; external devices can access the memory through the memory controller or communicate directly with the LTC, thereby flexibly supporting the control and data interaction needs of the memory at different operational stages (e.g., memory initialization, testing, and repair).

[0133] In some embodiments of this disclosure, the operation method 2 of the test controller may further include: receiving a first clock signal through the first write clock terminal of the first asynchronous FIFO 1021, and receiving a second clock signal asynchronous to the first clock signal through the first read clock terminal of the first asynchronous FIFO 1021, wherein the first clock signal is the clock signal of the clock domain where the external device 30 is located, and the second clock signal is the clock signal of the clock domain where the LTC 100 is located.

[0134] In digital circuit design, a clock domain refers to a collection of sequential logic circuits driven by the same clock signal. When two clock signals have different frequencies and / or no fixed phase relationship, they belong to different clock domains and can be called asynchronous clock domains. When data signals are transmitted directly between different clock domains, setup or hold time violations may occur because the receiving end cannot determine the valid sampling time of the data from the transmitting end. This can cause flip-flops to enter a metastable state, leading to data sampling errors, uncertain logic states, or even system malfunctions.

[0135] The first write clock input of the first asynchronous FIFO 1021 can be used to receive a first clock signal, which controls the write operation of the first asynchronous FIFO 1021. In other words, the external device 30 can write a first data signal into the first asynchronous FIFO 1021 at the trigger edge (e.g., rising edge) of the first clock signal. The first read clock input of the first asynchronous FIFO 1021 can be used to receive a second clock signal, which controls the read operation of the first asynchronous FIFO 1021. In other words, the internal logic of LTC 100 can read the first data signal from the first asynchronous FIFO 1021 at the trigger edge of the second clock signal.

[0136] Because the first clock signal is asynchronous with the second clock signal, the write and read operations of the first asynchronous FIFO 1021 are controlled by two independent clock domains. On the one hand, the asynchronous FIFO, through its internal memory array and read / write pointer synchronization mechanism, isolates the write clock domain of the external device 30 from the read clock domain inside the LTC 100, enabling stable and reliable data transmission across clock domains and avoiding metastability issues. On the other hand, since the write and read operations are performed independently in different clock domains, the speed at which the external device 30 writes the first data signal to the first asynchronous FIFO 1021 is not limited by the read speed of the LTC 100's internal logic, and the speed at which the LTC 100's internal logic reads the first data signal from the first asynchronous FIFO 1021 is also not limited by the write speed of the external device 30. Therefore, the data transmission of the external device 30 and the data processing inside the LTC 100 can be performed independently and in parallel in different clock domains, achieving decoupling between the two and effectively eliminating the waiting time of the external device 30. Furthermore, since the two clock domains are isolated from each other, external devices 30 and LTC 100 can operate at their own suitable clock frequencies without needing to adapt to each other, thus improving the system's flexibility and compatibility.

[0137] Similarly, the operation method 2 of the test controller may also include: receiving a second clock signal through the second write clock terminal of the second asynchronous FIFO 1022, and receiving a first clock signal asynchronous with the second clock signal through the second read clock terminal of the second asynchronous FIFO 1022, wherein the first clock signal is the clock signal of the clock domain where the external device 30 is located, and the second clock signal is the clock signal of the clock domain where the LTC 100 is located.

[0138] The second write clock input of the second asynchronous FIFO 1022 is used to receive a second clock signal, which controls the write operation of the second asynchronous FIFO 1022. In other words, the second data signal can be written to the second asynchronous FIFO 1022 at the trigger edge of the second clock signal. The second read clock input of the second asynchronous FIFO 1022 is used to receive a first clock signal, which controls the read operation of the second asynchronous FIFO 1022. In other words, the second data signal can be output to the external device 30 or GTC 300 via the interface unit 101 at the trigger edge of the first clock signal.

[0139] Because the second clock signal is asynchronous with the first clock signal, the write and read operations of the second asynchronous FIFO 1022 are controlled by two independent clock domains. The second asynchronous FIFO 1022 isolates the write clock domain inside the LTC 100 from the read clock domain of the external device 30 (or, GTC 300), enabling the second data signal to be stably and reliably transmitted from internal to external. Since the write and read operations are performed independently in different clock domains, the speed at which the LTC 100 supplies the second data signal is not limited by the external read speed, nor is the external read speed limited by the internal supply speed. Therefore, internal data supply and external data output are decoupled, eliminating the time that the external device 30 or GTC 300 spends waiting for internal data to be ready, effectively improving the transmission efficiency of the second data signal.

[0140] In some embodiments of this disclosure, step S12, which generates a first ready signal indicating whether the LTC can receive the first data signal based on the empty / full state of the first asynchronous FIFO, may include: generating a first ready signal in an active state based on the first asynchronous FIFO 1021 being in a non-full state, and outputting it to the external device 30, wherein the active first ready signal indicates that the LTC 100 can receive the first data signal; and generating a first ready signal in an inactive state based on the first asynchronous FIFO 1021 being in a full state, and outputting it to the external device 30, wherein the inactive first ready signal indicates that the LTC 100 cannot receive the first data signal.

[0141] Specifically, in this embodiment, "empty / full state" can be understood as the storage state of the first asynchronous FIFO 1021, which includes a non-full state and a full state. A non-full state indicates that there is still unoccupied storage space in the first asynchronous FIFO 1021, which can receive new first data signals written by the external device 30; a full state indicates that all storage space in the first asynchronous FIFO 1021 has been occupied, and new first data signals cannot be received.

[0142] When the first asynchronous FIFO 1021 is not full, a first ready signal in a valid state (e.g., high level) can be generated and output to the external device 30. The valid first ready signal indicates that the LTC 100 can currently receive the first data signal, and the external device 30 can continue sending the next first data signal. When the first asynchronous FIFO 1021 is full, a first ready signal in an invalid state (e.g., low level) can be generated and output to the external device 30. The invalid first ready signal indicates that the LTC 100 cannot currently receive the first data signal, and the external device 30 needs to pause transmission until the first ready signal returns to a valid state.

[0143] Since the valid and invalid states of the first ready signal are determined in real time by the empty / full state of the first asynchronous FIFO 1021, the external device 30 does not need to wait for the LTC 100 to finish processing before sending the next piece of data. Instead, it only needs to determine whether there is still available storage space in the first asynchronous FIFO 1021 based on the first ready signal. As long as the first ready signal is valid, the external device 30 can continuously send data, effectively eliminating the waiting time of the external device 30. Therefore, the data transmission of the external device 30 is not limited by the speed of data processing inside the LTC 100, improving bus utilization and data transmission efficiency.

[0144] Furthermore, in some embodiments of this disclosure, the LTC operation method 2 may further include: reading and processing a first data signal from a first asynchronous FIFO 1021 via a processing unit 104, and outputting the processed first data signal to a storage interface control unit 200 to write to at least one layer of memory die 12, wherein the processing includes converting the first data signal into an instruction format that matches the interface protocol of at least one layer of memory die 12.

[0145] The interface protocol of the memory die 12 can be understood as the read / write control timing and command specifications followed by the memory die 12, such as the instruction encoding and timing requirements corresponding to row activation, column read / write, precharge, and other operations defined in the DRAM interface protocol. After converting the first data signal into the instruction format required by the aforementioned interface protocol, the storage interface control unit 200 can correctly write the first data signal into at least one layer of the memory die 12. The processed first data signal is provided to the storage interface control unit 200 via the processing unit 104, and the storage interface control unit 200 writes the processed first data signal into at least one layer of the memory die 12. Thus, the first data signal travels from the external device 30 through the interface unit 101, the first asynchronous FIFO 1021, the processing unit 104, and the storage interface control unit 200, and is finally written into at least one layer of the memory die 12, completing the complete transmission path of the incoming data stream.

[0146] Since the first asynchronous FIFO 1021 buffers the first data signal written by the external device 30, even if the processing speed of the processing unit 104 is lower than the writing speed of the external device 30 for a period of time, the data will not be lost, thus improving the system's fault tolerance and data reliability. Furthermore, after format conversion of the first data signal, the storage interface control unit 200 can directly write the converted data to the memory die 12 without needing to perform format adaptation again at the storage interface control unit 200, further improving the processing efficiency of the incoming data stream and effectively ensuring the reliability of the memory 10.

[0147] Furthermore, in some embodiments of this disclosure, the LTC operation method 2 may further include: receiving the next first data signal through the interface unit 101 when the first ready signal is in an active state, wherein the operation of receiving the next first data signal is performed in parallel with the operation of processing the current first data signal.

[0148] In this implementation, "current" and "next" describe two data entries that are temporally adjacent during continuous data stream transmission. "Current" can be understood as the data entry that is being read from and processed by the first asynchronous FIFO 1021; "next" can be understood as the next data entry that will be written to the first asynchronous FIFO 1021 immediately following the current data entry.

[0149] "Parallel execution" refers to the execution of two or more operations that at least partially overlap in time. Therefore, in the context of this disclosure, the operation of writing the next first data signal to the first asynchronous FIFO 1021 and the operation of reading and processing the current first data signal from the first asynchronous FIFO 1021 at least partially overlap in time. Thus, while the current data is being processed, the next data is being written to the FIFO, and the write and read operations overlap in time, achieving pipelined parallel processing.

[0150] For example, step S11, receiving the first data signal through the interface unit, may include: in response to a power-on initialization command, receiving redundancy repair information as the first data signal through the interface unit 101.

[0151] In this embodiment, the memory 10 may be in the power-on initialization phase. The LTC 100 needs to load redundancy repair information from the external device 30 (e.g., an off-chip flash memory controller) to repair any faulty memory cells that may exist in the memory 10, ensuring the reliability of the memory 10. After being received by the LTC 100, the redundancy repair information needs to be finally written into at least one layer of redundancy repair circuitry (e.g., redundant word lines or redundant bit lines) in the memory die 12 to complete the repair operation during the power-on initialization process.

[0152] By setting a first asynchronous FIFO 1021 in the LTC 100 and buffering the first data signal in the first asynchronous FIFO 1021, a first ready signal indicating whether the LTC 100 can receive the first data signal is generated by the control logic unit 103 according to the empty / full state of the first asynchronous FIFO 1021. The speed at which the external device 30 sends redundancy repair information to the LTC 100 is not limited by the internal processing speed of the LTC 100. The non-full state of the first asynchronous FIFO 1021 can trigger PREADY to be active, allowing the external device 30 to continuously send redundancy repair information; in addition, the LTC 100 independently reads and processes the buffered data from the first asynchronous FIFO 1021 using its own operating clock. The data writing by the external device 30 and the data processing inside the LTC 100 are performed in parallel in different clock domains, and the two do not block each other. Therefore, external device 30 can send the next data without waiting for LTC100 to complete internal processing, effectively eliminating the waiting time of external device 30, improving bus utilization and data transmission efficiency, and significantly shortening the power-on initialization time of memory 10. In addition, the data caching method of the first asynchronous FIFO 1021 can effectively control chip area overhead in scenarios where a large amount of redundant repair information is cached.

[0153] For example, step S11, receiving the first data signal through the interface unit, may include: in response to a built-in self-test command, receiving a test vector as the first data signal through the interface unit 101.

[0154] In this embodiment, the memory 10 may be in the testing phase. The LTC 100 needs to load test vectors from an external device 30 (e.g., a test bench) to perform functional testing and performance verification on the memory 10, ensuring the yield and reliability of the memory 10. After being received by the LTC 100, the test vectors need to be written into the memory array in at least one layer of memory die 12 to complete the testing operation.

[0155] A first asynchronous FIFO 1021 is set in the LTC 100, and the first data signal is buffered in the first asynchronous FIFO 1021. Based on the empty / full state of the first asynchronous FIFO 1021, a first ready signal indicating whether the LTC 100 can receive the first data signal is generated by the control logic unit 103. The speed at which the external device 30 sends test vectors to the LTC 100 is not limited by the internal processing speed of the LTC 100. A non-full state of the first asynchronous FIFO 1021 can trigger PREADY to be active, allowing the external device 30 to continuously send test vectors. Furthermore, the LTC 100 independently reads and processes the buffered data from the first asynchronous FIFO 1021 using its own operating clock. The data writing by the external device 30 and the data processing inside the LTC 100 are performed in parallel in different clock domains, without blocking each other. Therefore, external device 30 can send the next test vector without waiting for LTC 100 to complete internal processing, effectively eliminating the waiting time of external device 30, improving bus utilization and data transmission efficiency, and significantly shortening the test time of memory 10. In addition, the data caching method of the first asynchronous FIFO 1021 can effectively control chip area overhead in scenarios where a large number of test vectors are cached.

[0156] refer to Figures 1 to 3 , Figure 8 In some embodiments of this disclosure, the LTC operation method 2 may further include: reading a second data signal from at least one layer of memory die 12 and providing the second data signal to a second asynchronous FIFO 1022 via a storage interface control unit 200.

[0157] In this embodiment, the storage interface control unit 200 is coupled to at least one layer of memory die 12 and can provide the second data signal read from the at least one layer of memory die 12 to the second asynchronous FIFO 1022. Thus, the second data signal enters the second asynchronous FIFO 1022 from the at least one layer of memory die 12 via the storage interface control unit 200, completing the source acquisition of the outgoing data stream.

[0158] For example, the LTC operation method 2 may further include: in response to a repair data read instruction, reading failure bitmap data as a second data signal from at least one layer of memory die 12 via the storage interface control unit 200, and providing the failure bitmap data to the second asynchronous FIFO 1022. In this embodiment, the second data signal is buffered by the second asynchronous FIFO 1022 and output via the interface unit 101, wherein a second ready signal indicating whether the LTC 100 can output the second data signal is generated by the control logic unit 103 according to the empty / full state of the second asynchronous FIFO 1022.

[0159] Therefore, the speed at which the storage interface control unit 200 provides fault bitmap data to the second asynchronous FIFO 1022 is not limited by the read speed of the GTC 300. The non-empty state of the second asynchronous FIFO 1022 triggers PREADY to be active, allowing the GTC 300 to continuously read fault bitmap data. Furthermore, the storage interface control unit 200 writes data to the second asynchronous FIFO 1022 independently using the internal operating clock of the LTC 100. The data supply from the storage interface control unit 200 and the data reading from the GTC 300 occur in parallel under different clock domains, without blocking each other. Thus, the GTC 300 can read continuously without waiting for the LTC 100 to prepare the next data, effectively eliminating the waiting time of the GTC 300, improving bus utilization and data transmission efficiency, and significantly shortening the read time of fault bitmap data. In addition, the data caching method of the second asynchronous FIFO 1022 can effectively control chip area overhead in scenarios where a large amount of fault bitmap data is cached.

[0160] Furthermore, step S21, which involves generating a second ready signal by the control logic unit 103 to indicate whether the LTC 100 can output the second data signal based on the empty / full state of the second asynchronous FIFO 1022, may include: generating a valid second ready signal based on the second asynchronous FIFO 1022 being in a non-empty state, and outputting it to the GTC 300, wherein the valid second ready signal indicates that the LTC 100 can output the second data signal; and generating an invalid second ready signal based on the second asynchronous FIFO 1022 being in an empty state, and outputting it to the GTC 300, wherein the invalid second ready signal indicates that the LTC 100 cannot output the second data signal.

[0161] Specifically, in this embodiment, "full / empty state" can be understood as the storage state of the second asynchronous FIFO 1022, which may include a non-empty state and an empty state. A non-empty state indicates that there is a cached second data signal in the second asynchronous FIFO 1022, which can be read by the GTC 300; an empty state indicates that no second data signal is cached in the second asynchronous FIFO 1022, and there is no data available for reading.

[0162] When the second asynchronous FIFO 1022 is not empty, a valid second ready signal can be generated and output to GTC 300. This valid second ready signal indicates that LTC 100 can currently output the second data signal, and GTC 300 can read the second data signal from the second asynchronous FIFO 1022. When the second asynchronous FIFO 1022 is empty, an invalid second ready signal can be generated and output to GTC 300. This invalid second ready signal indicates that LTC 100 cannot currently output the second data signal, and GTC 300 must pause reading until the second ready signal becomes valid again.

[0163] Since the valid and invalid states of the second ready signal are determined in real time by the empty / full state of the second asynchronous FIFO 1022, the GTC 300 does not need to wait for the LTC 100 to prepare the next second data signal before initiating a read operation. Instead, it only needs to determine whether the second asynchronous FIFO 1022 is not empty based on the second ready signal. As long as the second ready signal is valid, the GTC 300 can continuously read data, while the storage interface control unit 200 can simultaneously write new second data signals to the second asynchronous FIFO 1022. Therefore, internal data supply and GTC 300 data reading occur in parallel under different clock domains, effectively eliminating the waiting time of the GTC 300 and improving the transmission efficiency of the outgoing data stream.

[0164] Optionally, step S22, which outputs the second data signal through interface unit 101, may include: when the second ready signal is active, reading the second data signal output by interface unit 101 through GTC 300. Thus, the second data signal reaches GTC 300 after passing through the second asynchronous FIFO 1022 and interface unit 101, completing the full transmission path of the outgoing data stream. Therefore, the second data signal travels from at least one layer of memory die 12 through storage interface control unit 200, second asynchronous FIFO 1022, and interface unit 101 to GTC 300.

[0165] It is understood that the above embodiments are described with GTC 300 as the receiver of the outgoing data stream, but this disclosure is not limited thereto. In other embodiments, the receiver of the second data signal can also be an external device 30, such as an off-chip flash memory controller or a test bench. When the external device 30 is the receiver, the interface unit 101 can also output the second data signal to the external device 30 when the second ready signal is valid. Its operation and working principle are similar to those described above with reference to GTC 300, and will not be repeated here. GTC 300 (or external device 30, etc.) initiates reading based on the valid state of the second ready signal without polling or waiting, further improving the reading efficiency of the outgoing data stream of LTC 100.

[0166] Furthermore, step S22, which outputs the second data signal through the interface unit 101, may also include: outputting the current second data signal when the second ready signal is in an active state, wherein the operation of outputting the current second data signal is performed in parallel with the operation of providing the next second data signal to the second asynchronous FIFO 1022 through the storage interface control unit 200.

[0167] While the storage interface control unit 200 continuously provides the second data signal to the second asynchronous FIFO 1022, the interface unit 101 can read the buffered data from the second asynchronous FIFO 1022 in parallel and output it to the external device 30 or GTC 300, thereby ensuring the efficient flow of data outgoing from the LTC 100. Furthermore, since the second asynchronous FIFO 1022 buffers the second data signal provided by the storage interface control unit 200, even if the read speed of the external device 30 or GTC 300 is lower than the supply speed of the storage interface control unit 200 for a period of time, data will not be lost, improving the system's fault tolerance and data reliability.

[0168] For example, the buffer capacity of the first asynchronous FIFO 1021 can be a power of 2, where N is a positive integer; optionally, the buffer capacity of the second asynchronous FIFO 1022 can be a power of 2, where M is a positive integer. Alternatively, the buffer capacity of the first asynchronous FIFO 1021 can be a power of 2, and the buffer capacity of the second asynchronous FIFO 1022 can be a power of 2, where both N and M are positive integers. In this embodiment, as an option, N and M can be equal positive integers; as another option, N and M can be unequal positive integers.

[0169] In the context of FIFO, "buffer capacity" refers to the number of data entries that the FIFO can store simultaneously; in the field of digital circuits, it can also be called "depth." Optionally, the buffer capacity of the first asynchronous FIFO 1021 is a power of 2, such as 2, 4, 8, 16, etc. Optionally, the buffer capacity of the second asynchronous FIFO 1022 is a power of 2, such as 2, 4, 8, 16, etc. Furthermore, the buffer capacity of the first asynchronous FIFO 1021 and the buffer capacity of the second asynchronous FIFO 1022 can be equal, and both can have a buffer capacity of 2.

[0170] This implementation allows the read and write pointers of the FIFOs (e.g., the first asynchronous FIFO 1021 and the second asynchronous FIFO 1022) to be synchronized across clock domains using Gray code, ensuring the accurate generation of empty / full flags. With a cache capacity of 2, the FIFO can promptly respond to external write or read requests when not full, avoiding frequent triggering of full signals and interruption of pipeline transmission when the cache capacity is 1, and also preventing wasted chip area due to excessive depth. Thus, a balance is achieved between chip area overhead and data transmission efficiency while ensuring data transmission reliability.

[0171] Refer again Figures 1 to 3 Some embodiments of this disclosure provide a memory 10 and a memory system 40.

[0172] Exemplarily, the memory 10 may include at least one layer of memory die 12 and a buffer chip 11, wherein the buffer chip 11 includes the LTC 100 provided in any of the above embodiments. By placing the LTC 100 within the buffer chip 11, the memory 10 enables the LTC 100 to directly interact with at least one layer of memory die 12 at high speed via TSV 13, and simultaneously communicates with external devices 30 located outside the memory 10 via a bus, thereby realizing a bidirectional data path between off-chip data loading and on-chip storage, and enabling the memory 10 to independently and efficiently complete operations such as testing, initialization, and repair. Exemplarily, the memory 10 may be DRAM, such as three-dimensional stacked DRAM or HBM, and this disclosure is not limited thereto.

[0173] For example, the memory system 40 may include a memory 10 and a memory controller 20, which is coupled to the memory 10 and used to control the memory 10 to store data. The memory controller 20 can communicate with the LTC 100 via a bus (e.g., APB), and an external device 30 can interact with the LTC 100 via the memory controller 20 or directly via the bus, thereby supporting the control and data interaction needs of the memory 10 at different operating stages (e.g., power-on initialization, factory testing, failure bitmap reading, and hardware repair).

[0174] Exemplarily, system 1 may include memory system 40 and external device 30, with external device 30 coupled to memory system 40. External device 30 may be used to send a first data signal (e.g., test vector or redundancy repair information) to LTC 100 or to receive a second data signal (e.g., test result or failure bitmap data) from LTC 100. During the power-on initialization of memory 10, external device 30 may be an off-chip flash memory controller; during the testing of memory 10, external device 30 may be a test bench; during the failure bitmap reading of memory 10, external device 30 may be a host processor or a test host. This disclosure does not limit this.

[0175] The memory system 40 can be integrated into an electronic device, which may include, but is not limited to, mobile phones, computers, servers, tablets, in-vehicle electronic devices, or wearable devices; this disclosure does not limit this. Through the above configuration, system 1 can configure the communication method between external device 30 and LTC 100 according to actual application requirements, flexibly adapting to different working scenarios.

[0176] It is understood that since memory 10 and memory system 40 include the LTC 100 provided in any of the above embodiments, memory 10 and memory system 40 also possess all the technical features of LTC 100 and can correspondingly achieve all the technical effects of LTC 100, such as independent pipelined processing of bidirectional data streams, decoupling of data transmission from external devices and internal data processing of LTC in different clock domains, improvement of bus utilization and data transmission efficiency, and effective control of chip area overhead by replacing register file with asynchronous FIFO. To avoid redundancy, this disclosure will not elaborate on the above-mentioned identical technical features and effects one by one.

[0177] Various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements of the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0178] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0179] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A test controller, characterized in that, include: An interface unit is used to receive a first data signal and output a second data signal; A first-in-first-out (FIFO) queue group is coupled to the interface unit; as well as The control logic unit is coupled to the interface unit and the FIFO group. The FIFO group includes a first asynchronous FIFO for buffering the first data signal; the control logic unit is used to generate a first ready signal indicating whether the test controller can receive the first data signal based on the empty / full state of the first asynchronous FIFO. and / or The FIFO group includes a second asynchronous FIFO for buffering the second data signal; the control logic unit is used to generate a second ready signal indicating whether the test controller can output the second data signal based on the empty / full state of the second asynchronous FIFO.

2. The test controller according to claim 1, wherein, The test controller is located in the buffer chip of the memory. The test controller is coupled to an external device located outside the memory, and the external device is used to send the first data signal to the test controller.

3. The test controller according to claim 2, wherein, The first asynchronous FIFO includes: The first write clock input is used to receive the first clock signal; and The first clock input is used to receive a second clock signal that is asynchronous with the first clock signal. Wherein, the first clock signal is the clock signal of the clock domain where the external device is located, and the second clock signal is the clock signal of the clock domain where the test controller is located.

4. The test controller according to claim 2, wherein, The second asynchronous FIFO includes: The second clock input is used to receive the second clock signal; and The second clock input is used to receive a first clock signal that is asynchronous with the second clock signal. Wherein, the first clock signal is the clock signal of the clock domain where the external device is located, and the second clock signal is the clock signal of the clock domain where the test controller is located.

5. The test controller according to claim 2, wherein, The control logic unit is also used for: Based on the fact that the first asynchronous FIFO is not in a full state, a first ready signal in a valid state is generated and output to the external device, wherein the first ready signal in a valid state indicates that the test controller can receive the first data signal; as well as Based on the fact that the first asynchronous FIFO is in a full state, a first ready signal in an invalid state is generated and output to the external device. The first ready signal in an invalid state indicates that the test controller cannot receive the first data signal.

6. The test controller according to claim 5, wherein, The buffer chip includes: A storage interface control unit is coupled to at least one layer of the memory die. The test controller further includes: The processing unit is coupled to the first asynchronous FIFO and the storage interface control unit, and is used to read and process the first data signal from the first asynchronous FIFO, and to output the processed first data signal to the storage interface control unit for writing to the at least one layer of memory die. The processing includes converting the first data signal into an instruction format that matches the interface protocol of the at least one layer of memory die.

7. The test controller according to claim 6, wherein, The interface unit is further configured to: receive the next first data signal when the first ready signal is in the valid state. The operation of receiving the next first data signal is performed in parallel with the operation of the processing unit processing the current first data signal.

8. The test controller according to claim 1, wherein, The interface unit is also configured to, in response to a power-on initialization command, receive redundancy repair information as the first data signal; and / or The interface unit is also configured to receive a test vector as the first data signal in response to a built-in self-test command.

9. The test controller according to claim 1, wherein, The test controller is located in a buffer chip of the memory, and the buffer chip includes: A storage interface control unit, coupled to at least one layer of the memory die, is used to read the second data signal from the at least one layer of the memory die and provide the second data signal to the second asynchronous FIFO.

10. The test controller according to claim 9, wherein, The storage interface control unit is also used for: In response to a repair data read command, failure bitmap data, which serves as the second data signal, is read from the at least one layer of memory die, and the failure bitmap data is provided to the second asynchronous FIFO.

11. The test controller according to claim 9, wherein, The buffer chip also includes a test management controller, and the control logic unit is further used for: Based on the fact that the second asynchronous FIFO is in a non-empty state, a second ready signal in a valid state is generated and output to the test management controller, wherein the second ready signal in a valid state indicates that the test controller can output the second data signal; as well as If the second asynchronous FIFO is in an empty state, a second ready signal in an invalid state is generated and output to the test management controller, wherein the second ready signal in an invalid state indicates that the test controller cannot output the second data signal.

12. The test controller according to claim 11, wherein, The test management controller is also used for: When the second ready signal is in the active state, the second data signal output by the interface unit is read.

13. The test controller according to claim 11, wherein, The interface unit is further configured to: output the current second data signal when the second ready signal is in the active state. The operation of outputting the current second data signal is performed in parallel with the operation of the storage interface control unit providing the next second data signal to the second asynchronous FIFO.

14. The test controller according to claim 1, wherein, The buffer capacity of the first asynchronous FIFO is a power of 2, where N is a positive integer; and / or The buffer capacity of the second asynchronous FIFO is a power of 2, where M is a positive integer.

15. A memory, characterized in that, include: At least one layer of bare memory die; as well as A buffer chip, coupled to the at least one layer of memory die, and including a test controller as claimed in any one of claims 1 to 14.

16. A memory system, characterized in that, include: The memory as described in claim 15; as well as A memory controller, coupled to the memory, is used to control the storage of data in the memory.

17. A method for operating a test controller, characterized in that, The test controller includes an interface unit, a first-in-first-out (FIFO) queue group, and a control logic unit. The FIFO group includes at least one of a first asynchronous FIFO and a second asynchronous FIFO. The method includes at least one of the following operations: The interface unit receives the first data signal and buffers the first data signal in the first asynchronous FIFO. The control logic unit generates a first ready signal to indicate whether the test controller can receive the first data signal based on the empty or full state of the first asynchronous FIFO. The second data signal is buffered by the second asynchronous FIFO and output through the interface unit. The control logic unit generates a second ready signal to indicate whether the test controller can output the second data signal based on the empty or full state of the second asynchronous FIFO.

18. The method according to claim 17, wherein, The test controller is disposed in the buffer chip of the memory, and the test controller is coupled to an external device located outside the memory. The method further includes: The external device sends the first data signal to the test controller.

19. The method according to claim 18, wherein, The method further includes: The first asynchronous FIFO receives a first clock signal through its first write clock terminal and a second clock signal asynchronous to the first clock signal through its first read clock terminal. Wherein, the first clock signal is the clock signal of the clock domain where the external device is located, and the second clock signal is the clock signal of the clock domain where the test controller is located.

20. The method according to claim 18, wherein, The method further includes: The second clock signal is received through the second write clock terminal of the second asynchronous FIFO, and a first clock signal asynchronous with the second clock signal is received through the second read clock terminal of the second asynchronous FIFO. Wherein, the first clock signal is the clock signal of the clock domain where the external device is located, and the second clock signal is the clock signal of the clock domain where the test controller is located.

21. The method according to claim 18, wherein, The step of generating a first ready signal, indicating whether the test controller can receive the first data signal, through the control logic unit based on the empty / full state of the first asynchronous FIFO, includes: Based on the first asynchronous FIFO being in a non-full state, a first ready signal in an active state is generated and output to the external device, wherein the active first ready signal indicates that the test controller can receive the first data signal; and Based on the fact that the first asynchronous FIFO is in a full state, a first ready signal in an invalid state is generated and output to the external device, wherein the first ready signal in an invalid state indicates that the test controller cannot receive the first data signal.

22. The method according to claim 21, wherein, The memory includes at least one layer of memory die, the buffer chip includes a memory interface control unit coupled to the at least one layer of memory die, the test controller further includes a processing unit, and the method further includes: The processing unit reads and processes the first data signal from the first asynchronous FIFO, and outputs the processed first data signal to the storage interface control unit to write it into the at least one layer of memory die. The processing includes converting the first data signal into an instruction format that matches the interface protocol of the at least one layer of memory die.

23. The method according to claim 22, wherein, The method further includes: When the first ready signal is in the active state, the next first data signal is received through the interface unit. The operation of receiving the next first data signal is performed in parallel with the operation of processing the current first data signal.

24. The method according to claim 17, wherein, Receiving the first data signal through the interface unit includes: In response to a power-on initialization command, redundancy repair information, which is the first data signal, is received through the interface unit; and / or In response to the built-in self-test command, a test vector, which serves as the first data signal, is received through the interface unit.

25. The method according to claim 17, wherein, The test controller is disposed in a buffer chip of the memory, the memory comprising at least one layer of memory die, and the buffer chip comprising a memory interface control unit coupled to the at least one layer of memory die; the method further comprises: The storage interface control unit reads the second data signal from the at least one layer of memory die and provides the second data signal to the second asynchronous FIFO.

26. The method according to claim 25, wherein, The method further includes: In response to a repair data read command, the failure bitmap data, which serves as the second data signal, is read from the at least one layer of memory die via the storage interface control unit, and the failure bitmap data is provided to the second asynchronous FIFO.

27. The method according to claim 25, wherein, The buffer chip also includes a test management controller, which generates a second ready signal indicating whether the test controller can output the second data signal based on the empty / full state of the second asynchronous FIFO, through the control logic unit. This includes: Based on the second asynchronous FIFO being in a non-empty state, a second ready signal in a valid state is generated and output to the test management controller, wherein the valid second ready signal indicates that the test controller is capable of outputting the second data signal; and If the second asynchronous FIFO is in an empty state, a second ready signal in an invalid state is generated and output to the test management controller, wherein the second ready signal in an invalid state indicates that the test controller cannot output the second data signal.

28. The method according to claim 27, wherein, The step of outputting the second data signal through the interface unit includes: When the second ready signal is in the valid state, the test management controller reads the second data signal output by the interface unit.

29. The method according to claim 27, wherein, The step of outputting the second data signal through the interface unit further includes: When the second ready signal is in the active state, the current second data signal is output. The operation of outputting the current second data signal is performed in parallel with the operation of providing the next second data signal to the second asynchronous FIFO through the storage interface control unit.

30. The method of claim 17, wherein, The buffer capacity of the first asynchronous FIFO is a power of 2, where N is a positive integer; and / or The buffer capacity of the second asynchronous FIFO is a power of 2, where M is a positive integer.

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