Test node, memory test device, and power down method for a memory test device

Abstract

The application discloses a kind of test nodes, memory test equipment and the power-down method of memory test equipment, it is related to computer technical field, including: management board and power board, management board is provided with target controller, power board is provided with power-down control module and power conversion module, power conversion module is used to provide operating voltage to management board;Power-down control module is electrically connected with the enable end of power conversion module and target controller respectively, for when receiving the power-down control signal issued by target controller or not receiving the periodic state signal issued by target controller exceeds preset length of time, at least one output voltage of power conversion module is turned off.Electric arc and electrostatic risk problem caused by low-speed interface after shutdown still with standby electricity in fast plugging scene of test node is solved, while guaranteeing test efficiency, eliminating electric arc and electrostatic discharge risk in the process of plugging, guarantee the reliability and operation safety of equipment.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a test node, a memory testing device, and a power-off method for the memory testing device. Background Technology

[0002] With the rapid development of cloud computing, big data, and artificial intelligence technologies, servers are placing increasingly higher demands on memory performance and reliability. Memory modules must undergo rigorous testing and verification before leaving the factory. Fully automated memory testing equipment based on a rack-mount architecture integrates multiple test nodes within the same rack. Each test node can simultaneously install multiple memory modules for parallel testing, thereby improving testing efficiency.

[0003] In related technologies, test nodes are typically designed to support quick-plug structure: the node power supply uses Power Clip copper busbars that directly plug into the cabinet busbar copper busbars, and external low-speed interfaces are centrally transferred through high-density connectors to achieve one-time quick plug-and-play.

[0004] However, this method has the problem of arcing and electrostatic discharge risks caused by the low-speed interface still carrying standby power after power-off in the case of quick plug-in and unplugging scenarios, which urgently needs to be solved. Summary of the Invention

[0005] This invention provides a test node, a memory testing device, and a power-down method for the memory testing device, in order to at least solve the problem of arcing and electrostatic discharge risks caused by low-speed interfaces still carrying standby power after power-off in fast-plug scenarios in related technologies.

[0006] This invention provides a test node, comprising: A management board, wherein the management board is provided with a target controller, the target controller being configured to output a power-down control signal and / or a periodic status signal; The power board includes a power-down control module and a power conversion module. The input terminal of the power conversion module is electrically connected to an external power source, and the output terminal of the power conversion module is electrically connected to the management board. The power conversion module is configured to provide operating voltage to the management board. The power-down control module is electrically connected to the enable terminal of the power conversion module and the target controller, respectively. The power-down control module is configured to output a shutdown signal to the enable terminal of the power conversion module in response to receiving the power-down control signal and / or not receiving the periodic status signal for a duration longer than a preset duration, so as to shut down at least one output voltage of the power conversion module.

[0007] The present invention also provides a memory testing device, comprising: Server rack; At least one test node as described in the above embodiments, wherein at least one of the test nodes is pluggably installed inside the cabinet.

[0008] The present invention also provides a power-off method for a memory testing device, the method being applied to the memory testing device described in the above embodiments, the method comprising the following steps: In response to receiving a power-down command, a power-down control signal is sent to the power-down control module of the power board; Based on the power-down control signal, the power-down control module is controlled to shut off at least one output voltage of the power conversion module; In response to the power conversion module completing the shutdown action, the status indicator light of the test node is controlled to switch to the safe-to-remove indication state.

[0009] This invention addresses the technical problem of arcing and electrostatic discharge risks caused by low-speed interfaces retaining standby power after power-off in fast-plug scenarios. This is achieved by having the target controller actively send a power-down control signal or the power-down control module autonomously detect a timeout when the target controller malfunctions, triggering the power-down control module to shut down the output voltage of the power conversion module. This cuts off all secondary power supplies, including standby power, ensuring the low-speed interface is completely powered off before the node is unplugged. The goal is to achieve the technical effect of eliminating arcing and electrostatic discharge risks during the fast-plugging and unplugging process while maintaining the efficiency of the test node, thereby improving equipment reliability and operational safety. Attached Figure Description

[0010] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A block diagram illustrating a test node provided in an embodiment of the present invention; Figure 2 A schematic diagram of the power-down control circuit provided in an embodiment of the present invention; Figure 3 A circuit diagram showing the connection between the power input interface and the busbar provided in an embodiment of the present invention; Figure 4 A schematic diagram of a test node provided in an embodiment of the present invention; Figure 5 A schematic diagram of the test node and high-temperature enclosure provided in an embodiment of the present invention; Figure 6 This is a block diagram of a memory testing device provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the internal layout of the entire cabinet provided in an embodiment of the present invention; Figure 8 A schematic diagram of the power supply architecture of the power board provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the signal interconnection architecture between the test node and the cabinet backplane provided in an embodiment of the present invention; Figure 10 A schematic diagram of the interface layout of the cabinet back panel provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the 4-to-1 cable connecting to the back panel of the cabinet, as provided in an embodiment of the present invention. Figure 12 This is a schematic diagram of the structure of a 4-to-1 cable provided in an embodiment of the present invention; Figure 13 A wiring diagram of the test node and the high-temperature shield of the memory provided in an embodiment of the present invention; Figure 14 A schematic diagram of the layout of the rear panel of the test node provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of the control topology of a memory testing device provided in an embodiment of the present invention; Figure 16 This is a flowchart illustrating a power-down method for a memory testing device provided in an embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0013] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0014] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] Figure 1This is a block diagram of a test node according to an embodiment of the present invention.

[0016] Before introducing the test nodes proposed in the embodiments of this application, let's briefly introduce the relevant technical background.

[0017] DDR (Double Data Rate) fully automated testing equipment is mainly used for pre-shipment testing of memory. It typically consists of test nodes and memory high-temperature shields, and operates in a rack configuration. A single rack can accommodate different numbers of test nodes and corresponding memory high-temperature shields depending on the type of DIMM (Dual In-line Memory Module). The rack supports both 21-inch (node ​​+ high-temperature shield) and 21-inch (PDU (Power Distribution Unit), switch, power shelf, CDU (Coolant Distribution Unit)) rack units. It is configured with one 3RU (Rack Unit, 1RU=1U, height unit, 1U=44.45mm) PDU, one 1RU Power Shelf, and one 1RU switch. It supports four 2U test nodes and 2U high-temperature shields, and supports single busbar and two blind-insertion manifolds.

[0018] To address the issue of frequent quick-plugging and unplugging of test nodes in automated testing, this invention employs a special design for the test nodes. The memory slots are located on the back of the motherboard for easy memory insertion / removal and independent temperature control. All interconnects on the node's rear window support blind insertion and quick-release: the node's power supply uses a Power Clip that directly plugs into the rack's busbar copper busbar; the node's internal CPU (Central Processing Unit) uses a cold plate for cooling, and the corresponding water inlet / outlet connectors are designed as blind-plug quick-release structures with the liquid cooling blind-plug structure on the rack; the external low-speed interfaces, originally located on the node's rear window, have been moved from the test node and fixed to the rack, with the test node and rack connected via high-density connectors for quick-plug blind-plug docking.

[0019] However, the aforementioned quick-plug design introduces new technical problems: the multiple low-speed I / O interfaces (including serial ports, Ethernet ports, USB (Universal Serial Bus), VGA (Video Graphics Array), etc.) connected to the test node via high-density terminals are extended by the BMC (Baseboard Management Controller). Even in S5 (State 5, sleep state defined by the ACPI (Advanced Configuration and Power Interface) specification) state, they are still powered by the Standby power supply. When the operator directly unplugs the test node after the test is completed, the low-speed interface will generate arcing and electrostatic discharge when disconnected while energized, which can easily cause hardware failure and safety risks to the Standby power supply chip.

[0020] Based on the above problems, this invention proposes a test node. By improving the power control architecture of the test node, all secondary power supplies, including standby power, are completely cut off before the test node is unplugged, so that the low-speed interface is in a power-free state before being unplugged, thereby eliminating the risk of electric arc and electrostatic discharge and protecting the chip from damage.

[0021] The test nodes proposed in the embodiments of the present invention will be described in detail below.

[0022] For example, such as Figure 1 As shown, the test node 10 includes a management board 100 and a power board 200. The management board 100 is equipped with a target controller 101, which is configured to output a power-down control signal and / or a periodic status signal. The power board 200 is equipped with a power-down control module 201 and a power conversion module 202. The input terminal of the power conversion module 202 is electrically connected to an external power supply, and the output terminal of the power conversion module 202 is electrically connected to the management board 100. The power conversion module 202 is configured to provide operating voltage to the management board 100. The power-down control module 201 is electrically connected to the enable terminal of the power conversion module 202 and the target controller 101, respectively. The power-down control module 201 is configured to output a shutdown signal to the enable terminal of the power conversion module 202 in response to receiving a power-down control signal and / or not receiving a periodic status signal for a duration longer than a preset duration, so as to shut down at least one output voltage of the power conversion module 202.

[0023] Specifically, a target controller 101 is provided on the management board 100. This target controller 101 is a management control chip located on the management board 100, responsible for out-of-band management, status monitoring, and command reception of the test node 10. In this embodiment of the invention, the target controller 101 can be a BMC, serving as the management core of the test node. It is responsible for receiving external power-down commands and outputting power-down control signals, while periodically outputting status signals under normal operating conditions to indicate that it is in normal operating condition. The power board 200 is provided with a power-down control module 201 and a power conversion module 202 (i.e., a power brick). The power-down control module 201 can be a Complex Programmable Logic Device (CPLD) used to control the on / off state of the output voltage of the power conversion module 202. The input terminal of the power conversion module 202 is electrically connected to an external power source, which can receive external power (such as 54V DC input) and convert the external power into the working voltage required by the internal components of the test node 10; the output terminal of the power conversion module 202 is electrically connected to the management board 100 and is used to convert the external power into the working voltage required by the management board 100.

[0024] The power-down control module 201 is electrically connected to the enable pin of the power conversion module 202 and the target controller 101. When the test is completed and the test node 10 needs to be removed, the host computer sends a power-down command to the target controller 101. Upon receiving the power-down command, the target controller 101 outputs a power-down control signal to the power-down control module 201. Responding to this power-down control signal, the power-down control module 201 outputs a shutdown signal to the enable pin of the power conversion module 202 (i.e., pulls down the enable pin of the power conversion module 202) to shut down at least one output voltage of the power conversion module 202. After the output of the power conversion module 202 is shut down, all circuits inside the test node 10 except for the power supply to the power-down control module 201 itself are de-energized, and the low-speed interface no longer has a standby voltage. At this time, the test node 10 can be safely removed.

[0025] During normal operation of the target controller 101, it can periodically output status signals (i.e., dog-feed signals) to the power-down control module 201. When the target controller 101 stops outputting periodic status signals due to hang-up or communication interruption, the power-down control module 201 can determine that the target controller 101 is abnormal if it does not receive the status signal for a duration longer than a preset duration (e.g., 5 seconds). Then, it will automatically output a shutdown signal to the enable terminal of the power conversion module 202 to shut down at least one output voltage of the power conversion module 202, ensuring that the test node 10 can still enter a safe power-off state when the target controller 101 is abnormal.

[0026] Therefore, by having the target controller output a power-down control signal to the power-down control module, and the power-down control module responding to this signal by outputting a shutdown signal to the enable terminal of the power conversion module, at least one output voltage of the power conversion module is completely cut off before the test node is unplugged. This ensures that all circuits inside the test node except for the power supply to the power-down control module itself are de-energized, and the low-speed interface no longer carries a standby voltage. This eliminates the risk of arcing and electrostatic discharge caused by the energized separation of the low-speed interface in fast-plug scenarios, protecting sensitive chips such as the BMC from damage. At the same time, by having the target controller periodically output a status signal, and the power-down control module autonomously outputting a shutdown signal when it does not receive this status signal for a duration longer than a preset duration, a fallback protection is achieved in case of target controller malfunction. This ensures that the test node can enter a safe power-off state under any circumstances, effectively improving the reliability and operational safety of the test node.

[0027] Optionally, in some embodiments, the power-down control module 201 includes: a first power-down control unit and / or a watchdog timer unit, wherein the first power-down control unit is configured to output a shutdown signal to the enable terminal of the power conversion module 202 according to the received power-down control signal; the watchdog timer unit is electrically connected to the status signal output terminal of the target controller 101, and the watchdog timer unit is configured to output a shutdown signal to the enable terminal of the power conversion module 202 if the duration of not receiving a periodic status signal is longer than a preset duration.

[0028] Specifically, the power-down control module 201 may include only a first power-down control unit, only a watchdog timer unit, or both. Preferably, in this embodiment, the power-down control module 201 includes a first power-down control unit and a watchdog timer unit. The first power-down control unit is the functional unit in the power-down control module 201 responsible for the normal power-down path. It receives the power-down control signal output by the target controller 101 and outputs a shutdown signal to the enable terminal of the power conversion module 202 according to the power-down control signal, causing the output voltage of the power conversion module 202 to be turned off. That is, the first power-down control unit corresponds to the controlled power-down scenario after normal testing is completed, actively triggered by the target controller 101. The watchdog timer unit is the functional unit in the power-down control module 201 responsible for the abnormal fallback path. It is electrically connected to the status signal output terminal of the target controller 101 and continuously monitors the periodic status signals issued by the target controller 101. If the target controller 101 stops sending the status signal due to a hang or communication interruption, and the duration exceeds a preset duration (e.g., 5 seconds), the watchdog timer unit determines that the target controller 101 is abnormal and autonomously outputs a shutdown signal to the enable terminal of the power conversion module. In other words, the watchdog timer unit provides an autonomous fallback shutdown scenario for when the target controller 101 is abnormal, and can independently complete the shutdown action without the target controller 101's involvement. The periodic status signal is the signal periodically output by the target controller 101 during normal operation, indicating that the target controller 101 is in normal working condition. After being received by the watchdog timer unit, this signal is used to reset its internal timer, indicating that the target controller 101 is not abnormal.

[0029] In other words, in the normal power-down path, after receiving the power-down control signal from the target controller 101, the first power-down control unit can output a shutdown signal to the enable terminal of the power conversion module 202, causing the enable terminal of the power conversion module 202 to be pulled low, thereby shutting off at least one output voltage of the power conversion module 202. In the fallback path, the watchdog timer unit is electrically connected to the status signal output terminal of the target controller 101. Under normal operating conditions, the target controller 101 periodically outputs a periodic status signal to the watchdog timer unit, and the watchdog timer unit resets its internal timer each time it receives the status signal. When the target controller 101 stops outputting the periodic status signal due to a hangup or communication interruption, if the duration of not receiving the status signal exceeds a preset duration, the watchdog timer unit determines that the target controller 101 has malfunctioned, and then autonomously outputs a shutdown signal to the enable terminal of the power conversion module 202, causing at least one output voltage of the power conversion module 202 to be shut off. The main purpose of introducing the power-down control module 201 is to prevent the target controller 101 from hanging up. The power-down control module 201 can directly shut down the power after the unit detects an abnormality in the target controller 101 through the watchdog timer.

[0030] Therefore, the power-down control module constructs a normal power-down path and an abnormal fallback path through the first power-down control unit and the watchdog timer unit, respectively: when the target controller is working normally, the first power-down control unit responds to the power-down control signal to execute controlled shutdown; when the target controller is stuck or communication is interrupted, the watchdog timer unit autonomously detects the abnormality and executes fallback shutdown. The two paths are independent and complementary, ensuring that the output voltage of the power conversion module can be reliably shut off before the test node is unplugged, regardless of whether the target controller is working normally or not. This eliminates the standby voltage of the low-speed interface, thereby eliminating the risk of arcing and electrostatic discharge caused by the interface being disconnected while energized in fast-plug scenarios, protecting sensitive chips such as the target controller from damage, and improving the safety and reliability of the test node in the rack-mount memory testing equipment.

[0031] Optionally, in some embodiments, the power board 200 further includes: a voltage conversion circuit, the input terminal of which is electrically connected to an external power supply, the output terminal of which is electrically connected to the power supply terminal of the power-down control module 201, and the output terminal of the voltage conversion circuit and the power conversion module 202 are electrically isolated.

[0032] Specifically, the voltage conversion circuit is an independent power conversion circuit set on the power board 200. Its input terminal is electrically connected to the external power supply, and its output terminal is electrically connected to the power supply terminal of the power-down control module 201. Its function is to convert the external power supply (such as 54V DC input) into the operating voltage (such as 3.3V) required by the power-down control module 201, specifically to power the power-down control module 201.

[0033] The voltage conversion circuit draws power from an external power source (such as a 54V DC input), converts it to the operating voltage required by the power-down control module 201 (such as 3.3V), and supplies power to the power supply terminal of the power-down control module 201 through its output terminal. Since the input terminal of the voltage conversion circuit is directly connected to the external power source, while the output terminal of the power conversion module 202 is the converted secondary output, the two are electrically isolated (i.e., there is no direct electrical path between the output terminals of the voltage conversion circuit and the power conversion module, and they belong to different power supply circuits). That is, the power supply path of the voltage conversion circuit does not pass through the power conversion module 202. Therefore, when at least one output voltage of the power conversion module 202 is turned off, the voltage conversion circuit can still obtain power from the external power source and continue to supply power to the power-down control module 201.

[0034] Therefore, by setting up a voltage conversion circuit that is electrically isolated from the output of the power conversion module, the power supply of the power-down control module is directly taken from the external power input rather than the output of the power conversion module. Thus, even after at least one output voltage of the power conversion module is turned off, the power-down control module can still continuously obtain the operating voltage, maintain its control over the enable terminal of the power conversion module, and ensure that both the normal power-down path and the emergency fallback path can be executed reliably. This avoids the situation where the shutdown action cannot be completed due to the power failure of the power-down control module itself, and further improves the reliability of safe power-down.

[0035] Optionally, in some embodiments, the power board 200 further includes a level conversion circuit, which is connected between the power-down control module 201 and the enable terminal of the power conversion module 202. The power-down control module 201 outputs a shutdown signal to the enable terminal of the power conversion module 202 through the level conversion circuit.

[0036] Specifically, the level conversion circuit is a circuit connected between the power-down control module 201 and the enable terminal of the power conversion module 202. It is used to convert the level of the output pin of the power-down control module 201 to the level required by the enable terminal of the power conversion module 202, and enhance the driving capability. The shutdown signal output by the power-down control module 201 is transmitted to the enable terminal of the power conversion module 202 via the level conversion circuit, so that the enable terminal is reliably pulled down to below the shutdown threshold (e.g., 0.8V), thereby stopping the power conversion module 202 from outputting.

[0037] In other words, the power-down control module 201 can generate a shutdown signal on its output pin based on the received power-down control signal (normal path) or the timeout determination of the watchdog timer unit (abnormal path). The level of this shutdown signal is output by the output pin of the power-down control module 201. After receiving the shutdown signal, the level conversion circuit converts its level to the level required by the enable terminal of the power conversion module 202 and transmits it to the enable terminal of the power conversion module 202. After receiving the level-converted shutdown signal, the enable terminal of the power conversion module 202 is pulled low below the shutdown threshold, causing the power conversion module 202 to stop outputting, thereby shutting down at least one output voltage of the power conversion module 202.

[0038] It should be noted that the specific value of the shutdown threshold depends on the electrical characteristics of the enable terminal of the power conversion module 202, i.e., it is determined by the datasheet of the power conversion module 202.

[0039] Therefore, by setting a level conversion circuit between the power-down control module and the enable terminal of the power conversion module, the output level of the power-down control module can match the level required by the enable terminal of the power conversion module and enhance the driving capability. This ensures the reliable transmission of the shutdown signal from the power-down control module to the enable terminal of the power conversion module, and ensures that the enable terminal of the power conversion module can be reliably pulled down below the shutdown threshold, thereby achieving reliable shutdown of the power conversion module. At the same time, the power-down control module does not need to directly bear the electrical characteristics of the enable terminal of the power conversion module, reducing the circuit design difficulty and improving the reliability of safe power-down action.

[0040] Optionally, in some embodiments, the level conversion circuit includes: a first MOS (Metal-Oxide-Semiconductor) transistor, a second MOS transistor, and a pull-up resistor, wherein the gate of the first MOS transistor is electrically connected to the output pin of the power-down control module, the source of the first MOS transistor is grounded, and the drain of the first MOS transistor is electrically connected to the gate of the second MOS transistor; the source of the second MOS transistor is grounded, and the drain of the second MOS transistor is electrically connected to the enable terminal of the power conversion module 202; one end of the pull-up resistor is electrically connected to the gate of the second MOS transistor, and the other end of the pull-up resistor is electrically connected to the power supply terminal of the power-down control module 201.

[0041] Specifically, in this embodiment of the invention, both the first MOS transistor and the second MOS transistor are N-channel enhancement-mode MOS transistors. For example... Figure 2As shown, the P54V input is converted to P3V3_CPLD (i.e., the power supply terminal of the power-down control module 201) via a 54V to 3V3 converter circuit, supplying power to the power-down control module 201 (i.e., CPLD). The output pin of the power-down control module 201 is connected to the gate of the first MOSFET, the gate of the first MOSFET is electrically connected to the output pin of the power-down control module 201, the source of the first MOSFET is grounded, and the drain of the first MOSFET is electrically connected to the gate of the second MOSFET (i.e., the POWER DOWN node, i.e., the power-down control node). The first MOSFET acts as the first-stage inverter, receiving the level signal from the output pin of the power-down control module 201 and generating an inverted level at its drain. The gate of the second MOSFET is electrically connected to the drain of the first MOSFET, the source of the second MOSFET is grounded, and the drain of the second MOSFET is electrically connected to the enable terminal of the power conversion module 202. The second MOSFET acts as a second-stage inverter, receiving the voltage level signal from the drain of the first MOSFET and generating an inverted voltage level at its drain, which ultimately acts on the enable terminal of the power conversion module 202. Additionally, the P54V_PWRGD signal output from the P54VEFUSE (Electronic Fuse) is also connected to the POWER DOWN node. The pull-up resistor is connected between the gate of the second MOSFET and the power supply terminal of the power-down control module. When the first MOSFET is off, the pull-up resistor pulls the gate of the second MOSFET high, turning it on; when the first MOSFET is on, the gate of the second MOSFET is pulled low by the first MOSFET, shorting the pull-up resistor to ground, turning the second MOSFET off.

[0042] In other words, when the power-down control module 201 needs to output a shutdown signal, it pulls its output pin from high to low. Upon receiving this low level, the gate of the first MOSFET is turned off, and the drain of the first MOSFET (i.e., the gate of the second MOSFET) is pulled high through a pull-up resistor to a high level (i.e., the power supply voltage of the power-down control module 201). Upon receiving this high level, the gate of the second MOSFET is turned on, and its drain pulls the enable pin of the power conversion module 202 below the shutdown threshold, causing the power conversion module 202 to stop outputting, and the output P12V drops to 0V, thereby shutting off at least one output voltage of the power conversion module 202.

[0043] Conversely, when the output pin of the power control module 201 is high, the first MOSFET is turned on, its drain is pulled low, the gate of the second MOSFET is pulled low and cut off, the enable pin (i.e. P12V_EN) of the power conversion module 202 is not pulled low, the power conversion module 202 works normally, and the output P12V supplies power to the test node 10.

[0044] Therefore, by using an inverter structure consisting of two cascaded N-channel enhancement-mode MOSFETs and pull-up resistors, the level changes of the output pin of the power-down control module are transmitted step by step and converted into the level required by the enable terminal of the power conversion module. This achieves level matching and enhanced drive capability, ensuring that the enable terminal of the power conversion module can be reliably pulled down below the turn-off threshold, thus guaranteeing the reliable turn-off of the power conversion module. At the same time, this circuit consists of only two MOSFETs and one pull-up resistor, which is simple in structure, requires fewer components, and has high reliability. It does not require an additional level conversion chip, reducing circuit cost and space occupation.

[0045] Optionally, in some embodiments, the test node 10 further includes a power input interface, which is disposed on the rear panel of the test node 10. One end of the power input interface is electrically connected to an external power source, and the other end of the power input interface is electrically connected to the input terminal of the power conversion module 202. The power input interface is configured to connect to an external power source to supply the power provided by the external power source to the power conversion module 202.

[0046] Specifically, the power input interface (Power Clip) is an electrical interface located on the rear panel of test node 10, used to connect external power to the interior of test node 10. One end is electrically connected to the external power source, and the other end is electrically connected to the input terminal of the power conversion module 202, serving as the entry point for external power into the test node. The rear panel is the rear surface of the test node 10 housing, i.e., the side facing inwards when test node 10 is pushed into the rack. Positioning the power input interface on the rear panel allows test node 10 to directly connect to the power supply structure on the rack side when pushed into the rack.

[0047] In other words, an external power source (such as 54V DC power provided by the busbar inside the cabinet) can be connected to the interior of test node 10 through the power input interface on the rear panel of test node 10. The power input interface transmits the power supplied by the external power source to the input terminal of the power conversion module 202, which converts the external power source into the operating voltage required by the various components inside test node 10. Since the power input interface is located on the rear panel, when test node 10 is pushed into the cabinet, the power input interface on the rear panel can be connected to the power supply structure on the cabinet side to realize the access of external power; when test node 10 is pulled out, the power input interface is separated from the cabinet side along with test node 10.

[0048] Therefore, the external power supply can be connected to the power conversion module inside the test node through the power input interface on the rear panel, without the need for additional wiring or adapter structures inside the node. This allows the test node to be connected to the power supply through the rear panel when it is pushed into the rack, facilitating quick plugging and unplugging of the test node. It also provides a power input basis for shutting down the power conversion module output through the power-down control module before the node is unplugged.

[0049] Optionally, in some embodiments, the power input interface includes: a first pin and a second pin, the length of the first pin being greater than the length of the second pin; the first pin is configured to transmit current from an external power source; the second pin is configured to generate an indication signal when the test node 10 is inserted into place, the indication signal being used to trigger the external power source to supply power to the power conversion module 202.

[0050] Specifically, the first pin is the longer pin in the power input interface, used to transmit current from the external power supply. Due to its longer length, during the insertion of test node 10, the first pin contacts the power supply structure on the rack side before the second pin; during the removal process, the first pin separates from the power supply structure on the rack side after the second pin. The second pin is the shorter pin in the power input interface, used to generate an indication signal when test node 10 is fully inserted. Due to its shorter length, during insertion, the second pin contacts the first pin; during removal, the second pin separates from the first pin.

[0051] In other words, the insertion and removal protection of the power input interface mainly utilizes the physical time difference between the contact and disconnection of the long pin (i.e., the first pin, Power PIN) and the short pin (i.e., the second pin, Sense PIN) during insertion and removal to control the power-on and power-off sequence of the power supply, ensuring that the power connection is established and disconnected under no-current or low-current conditions. When test node 10 is inserted into the rack, because the length of the first pin is greater than the length of the second pin, the first pin contacts the power supply structure on the rack side before the second pin. At this time, the second pin has not yet made contact, no indication signal is generated, the path for external power supply to power conversion module 202 is not triggered, and the system is in a power-off state. As test node 10 continues to be inserted, the second pin contacts the power supply structure on the rack side, test node 10 is inserted in place, and the second pin generates an indication signal (i.e., indicating that test node 10 has completed physical insertion). This indication signal triggers external power supply to power conversion module 202, and power conversion module 202 begins to work. Therefore, in the initial stage when the mechanical connection is unstable (i.e., the long needle may bounce and the contact resistance is large), the system is in a de-energized state; only when it is fully inserted and the connection is secure (i.e., the short needle makes contact) is the system allowed to be energized, thus avoiding contact sparks and surge currents generated at the moment of energization.

[0052] When test node 10 is removed from the rack, the second pin separates from the power supply structure on the rack side before the first pin, the indicator signal disappears, the path for external power supply to the power conversion module 202 is cut off, and the power conversion module 202 stops working; subsequently, the first pin separates from the power supply structure on the rack side, completing the removal of test node 10. Because the second pin separates before the first pin, the path for external power supply to the power conversion module 202 is cut off when the second pin separates, and no current flows when the first pin separates, thus avoiding arcing caused by live separation. This protects the connector contacts from electrolytic corrosion and also avoids data corruption caused by sudden power failure.

[0053] like Figure 3 The power input interface shown has multiple pins, including a 54V_Power pin (the first pin) for transmitting 54V current, a 54V_Sense_DP pin (the second pin) for generating a connection detection signal, and ground pins GND and GND_Sense_DN. When the power input interface is inserted into the rack, the long pin of 54V_Power contacts first, followed by the short pin of 54V_Sense_DP. After 54V_Sense_DP contacts, an indication signal is generated. This signal is transmitted to the power board 200, generating a P54V_EFUSE_EN enable signal, which triggers 54V EFUSE to conduct, allowing the 54V input to enter the 54-12V power conversion module 202. The power conversion module 202 converts the 54V to a 12V output voltage to power the components inside test node 10.

[0054] The above-mentioned insertion and removal protection process is completed by the following components in concert, and the roles and cooperative functions of each component are shown in Table 1.

[0055]

[0056] Therefore, by taking advantage of the length difference between the first and second pins, during the insertion of the test node, the indicator signal is generated only after the physical connection is stably established, and the power supply from the external power source to the power conversion module is triggered to conduct only after the connection is reliable, thus avoiding surges and sparks caused by contact bounce or excessive contact resistance during insertion. During the removal process, the indicator signal disappears before the first pin separates, the power supply from the external power source is cut off before physical disconnection, and no current flows when the first pin separates, thereby avoiding arcing during energized separation and improving the safety of quick plug-in / plug-out operations.

[0057] Optionally, in some embodiments, the test node 10 further includes an external interface, which is disposed on the rear panel of the test node 10 and electrically connected to the management board 100. The external interface is configured to establish a signal transmission path between the target controller 101 and the external device.

[0058] Specifically, an external interface is located on the rear panel of test node 10 to establish a signal transmission path between the target controller 101 and external devices. One end is electrically connected to the management board 100, and the other end is used to interface with external devices (such as the docking connector on the back panel of the cabinet). Here, external devices refer to devices outside of test node 10, such as the host computer or other management devices connected to the docking connector on the back panel of the cabinet. The external interface routes the low-speed signals from the target controller 101 to the outside of test node 10 for access by external devices.

[0059] In other words, low-speed signals (such as serial port signals, network port signals, USB signals, VGA signals, etc.) generated by the target controller 101 on the management board 100 can be transmitted to the external interface through the management board 100. The external interface is located on the rear panel of the test node 10. When the test node 10 is pushed into the rack, the external interface on the rear panel mates with the docking connector on the rack side, and the low-speed signals of the target controller 101 can be transmitted to the external device through the external interface. When the test node 10 is pulled out, the external interface is separated from the rack side along with the test node 10. Thus, the target controller 101 establishes a signal transmission path with the external device through the external interface.

[0060] Therefore, the target controller on the management board can interact with external devices through the external interface on the rear panel, enabling the test node to establish a low-speed signal path to the outside through the rear panel after being pushed into the rack, without the need for additional wiring inside the node, facilitating quick plug-and-play. At the same time, the external interface on the rear panel can be separated from the rack along with the test node before it is unplugged, providing a hardware foundation for shutting down the power conversion module output through the power-down control module before unplugging and eliminating the risk of the external interface being live.

[0061] Optionally, in some embodiments, the external interface is a high-density female connector, which is connected to the management board 100 and the power board 200 respectively via cables.

[0062] Understandably, the high-density female connector is a type of high-density connector with multiple signal contacts, enabling simultaneous connection or disconnection of multiple signals within a limited space. As a specific implementation of the external interface, it is located on the rear panel of test node 10 and is used to mate with the high-density male connector on the cabinet back panel.

[0063] Specifically, low-speed signals on the management board 100 (such as serial port signals, network port signals, USB signals, VGA signals, etc.) can be aggregated to the high-density connector female head via cables; relevant signals on the power board 200 can also be aggregated to the high-density connector female head via cables. The high-density connector female head is located on the rear panel of the test node 10. When the test node 10 is pushed into the cabinet, the high-density connector female head engages with the high-density connector male head on the cabinet back panel, and multiple signals from the management board 100 and the power board 200 can be transmitted to the cabinet back panel at once through this high-density connector female head; when the test node 10 is pulled out, the high-density connector female head separates from the high-density connector male head, and multiple signals are disconnected at once.

[0064] After the memory test is completed, test node 10 can send its serial number (SN), memory test log (log), and test completion flag to the host computer via the serial port channel in the high-density connector female connector. The serial number identifies the test node that completed the test, the test log records the detailed process and results of the memory test, and the test completion flag informs the host computer that the memory test for test node 10 has been completed and can proceed to the next step. Once the host computer receives and confirms the above information, it can send a power-down command to trigger test node 10 to execute a safe power-down procedure, preparing for the subsequent removal of test node 10.

[0065] Therefore, the low-speed signals on the management board and the relevant signals on the power board are concentrated on the high-density connector female on the rear panel. The test node only needs to connect or disconnect multiple signals at the same time by inserting the high-density connector female into the mating connector on the back panel of the cabinet once, without having to plug and unplug cables one by one. This significantly improves the convenience of quick plugging and unplugging of the test node and the reliability of the connection. At the same time, since multiple signals are connected and disconnected at the same time on one connector, it also provides a hardware basis for the power-down control module to uniformly shut down the output of the power conversion module before unplugging, thus eliminating the risk of live signal pins.

[0066] Optionally, in some embodiments, the test node 10 further includes a liquid inlet and a liquid outlet, wherein the liquid inlet and the liquid outlet are both disposed on the rear panel of the test node 10, the liquid inlet is configured to allow coolant to flow into the test node 10, and the liquid outlet is configured to allow coolant to flow out of the test node 10, so as to form a coolant passage through the test node 10.

[0067] Specifically, the inlet port is located on the rear panel of test node 10, allowing coolant to flow into the test node 10 for liquid cooling of heat-generating components (such as the CPU) within the test node 10. The outlet port is also located on the rear panel of test node 10, allowing the coolant, after absorbing heat, to flow out of test node 10 and return to the external coolant circulation system.

[0068] In other words, the coolant provided by the external coolant circulation system flows into the test node 10 through the inlet port, absorbs heat from the heat-generating components (such as the CPU) within the test node 10, and then flows out of the test node 10 through the outlet port, returning to the external coolant circulation system for cooling. Thus, a coolant path is formed within the test node 10 from the inlet port to the outlet port, achieving liquid cooling of the heat-generating components inside the test node 10.

[0069] Since both the inlet and outlet ports are located on the rear panel of test node 10, when test node 10 is pushed into the cabinet, the inlet and outlet ports on the rear panel connect with the coolant circulation system on the cabinet side, and a coolant path can be established; when test node 10 is pulled out, the inlet and outlet ports separate from the cabinet side along with test node 10.

[0070] Therefore, the test node can connect to the external coolant circulation system through the liquid inlet and outlet ports on the rear panel. When the test node is pushed into the rack, a liquid cooling path can be established through the rear panel, which facilitates quick plug-and-play of the test node. At the same time, the liquid inlet and outlet ports are both located on the rear panel, so that all external connections (power supply, signal, liquid cooling) of the test node are concentrated on the rear side, eliminating the need to set up additional liquid cooling pipe interfaces on the front or inside of the node, further improving the convenience of quick plug-and-play of the test node in the entire rack.

[0071] Optionally, in some embodiments, the test node 10 further includes: a motherboard and a status indicator light, the motherboard having a memory slot configured to install a memory module to be tested; the status indicator light being configured to indicate the on / off state of the output voltage of the power conversion module 202.

[0072] Specifically, the motherboard is the main circuit board inside test node 10, and it has memory slots for installing the memory modules to be tested and performing memory testing. In this embodiment of the invention, the memory slots are located on the back of the motherboard to facilitate memory insertion and removal and independent temperature control. The motherboard is electrically connected to the power conversion module 202, which provides operating voltage to the motherboard to test the memory modules. A status indicator light is located on the test node to indicate the on / off state of the output voltage of the power conversion module 202. When the output voltage of the power conversion module 202 is turned off, the status indicator light switches to the safe removal indication state; when the power conversion module 202 is outputting normally, the status indicator light is in another indication state.

[0073] In other words, when the power conversion module 202 is outputting normally, the motherboard receives the operating voltage, the memory test proceeds normally, and the status indicator is in the first indication state; when it is necessary to remove the test node 10, the power-down control module 201 outputs a shutdown signal to the enable terminal of the power conversion module 202, the output voltage of the power conversion module 202 is turned off, the motherboard loses power, and the status indicator switches to the safe removal indication state (such as solid green), indicating to the operator that it is safe to remove the test node 10 at this time.

[0074] Therefore, the motherboard installs the memory module to be tested through the memory slot for memory testing. The status indicator light intuitively indicates to the operator the on / off status of the power conversion module's output voltage, allowing the operator to confirm whether the power conversion module's output has been turned off before unplugging the test node, avoiding unplugging the test node while it is powered on, and further improving the safety and reliability of the quick-plug operation.

[0075] Furthermore, the test node used in this embodiment of the invention differs significantly in structural layout from that of a typical server. In a typical server motherboard, the CPU and DIMMs are usually located on the same side (front), while in this embodiment, the test node places the CPU on the front of the motherboard and the DIMMs (Dual In-line Memory Modules) on the back. This design facilitates memory testing, memory insertion and removal, and individual temperature control for the memory modules. Figure 4 As shown, test node 10 features an exposed memory slot structure to facilitate the installation and testing of the memory modules under test. Each test node can support 32 memory modules. During testing, the memory modules under test are installed in the memory slots of test node 10. A high-temperature memory shield can be erected above test node 10 to cover the 32 memory modules under test, providing the necessary constant temperature conditions for memory testing. This high-temperature memory shield needs to achieve stable temperature control at both room temperature and high temperature (e.g., the terminal requires a temperature control accuracy of 40±10℃ at room temperature and 70±7℃ at high temperature). The setup of test node 10 and the high-temperature memory shield can be as follows: Figure 5 As shown.

[0076] It is understood that the power-down protection in this embodiment of the invention can be divided into two levels. The first level of protection is physical layer protection, implemented by the long and short pins of the connector: when pulled out, the long and short pins (i.e., the first and second pins of the power input interface) are triggered first, cutting off P54V_EFUSE_EN and shutting down the main input power. The second level of protection is logic layer protection, implemented by the power-down control module: before the main input power (P54V) ​​is cut off (or the loss of the indication signal is detected), the target controller first sends a power-down command to the power-down control module, which then controls the POWER_DOWN signal to shut down the voltage output by the power board, ensuring that before the test node is pulled out, only the 54V input of the power conversion module is on the test node, and all other power is turned off.

[0077] The collaborative process between the two is as follows: Before the test node is removed, the target controller notifies the power-down control module, which pulls POWER_DOWN low, and the power conversion module shuts down (cuts off secondary outputs such as 12V); then the test node is removed, the short pin (i.e., the second pin) disconnects, the indicator signal disappears, and EFUSE is turned off (cuts off the 54V main input); finally, the long pin (i.e., the first pin) disconnects, and the test node is safely removed.

[0078] According to the test node proposed in the embodiments of the present invention, the power-down control module is triggered to shut down the output voltage of the power conversion module by actively sending a power-down control signal from the target controller or by autonomously detecting a timeout when the target controller is abnormal. This cuts off all secondary power supplies, including the standby power supply, so that the low-speed interface is completely de-energized before the node is unplugged. Therefore, it can solve the technical problem of arcing and electrostatic discharge risks caused by the low-speed interface still carrying standby power after power-off in the test node in the fast plug-in / unplug scenario. It achieves the technical effect of eliminating the risk of arcing and electrostatic discharge during the plug-in / unplugging process while ensuring the fast plug-in / unplugging efficiency of the test node, thereby improving the reliability and operational safety of the equipment.

[0079] Through the above description of the embodiments, those skilled in the art can clearly understand that the system according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0080] Next, the memory testing device proposed according to an embodiment of the present invention is described with reference to the accompanying drawings.

[0081] like Figure 6 As shown, the memory testing device 1 includes at least one test node 10 and a cabinet 20, wherein at least one test node 10 is pluggably installed inside the cabinet 20.

[0082] It is understandable that the rack 20 is the supporting structure for the memory testing equipment 1, and is used to accommodate at least one test node 10.

[0083] Specifically, when test node 10 is pushed into rack 20, the power input interface on the rear panel of test node 10 connects to the power supply structure inside rack 20. External power is connected to the power conversion module 202 inside test node 10 via the power input interface, and the power conversion module 202 provides operating voltage to the management board and other components inside test node 10. After test node 10 completes memory testing inside rack 20, the power-down control module 201 shuts off the output voltage of the power conversion module 202, thus de-energizing all circuits inside test node 10 except for the power supply to the power-down control module 201 itself. The operator can then remove test node 10 from rack 20, completing one rotation of test nodes.

[0084] Therefore, the test nodes can be plugged into the rack, allowing power and signal connections to be completed via the rear panel when the test nodes are pushed into the rack. After the test is completed, the power conversion module can be turned off by the power-down control module, and the test nodes can be safely removed. This achieves efficient rotation and safe quick plugging and unplugging of test nodes in the rack-mount memory testing equipment, improving the automation level and operational safety of memory testing.

[0085] Figure 7 This is a schematic diagram of the internal layout of the entire cabinet provided in an embodiment of the present invention. Figure 7 As shown, the entire rack adopts a 42U standard rack, arranged from bottom to top as follows: the bottom is a 6U CDU, the 7th to 27th U are four sets of test nodes and high temperature shields arranged alternately (specifically: the 8th and 11th U are the lower 2U node 1 and the upper 2U high temperature shield 1, the 13th and 16th U are the lower 2U node 2 and the upper 2U high temperature shield 2, the 18th and 21st U are the lower 2U node 3 and the upper 2U high temperature shield 3, the 23rd and 26th U are the lower 2U node 4 and the upper 2U high temperature shield 4), the 29th to 35th U are the host computer, the 38th U is the Power Shelf, the 39th U is the switch, and the 40th to 42nd U are the PDUs.

[0086] With the above layout, the rack-mount memory testing equipment achieves alternating arrangement of test nodes and high-temperature enclosures, which facilitates independent memory testing and temperature control for each test node. At the same time, the host computer centrally manages all test nodes, the PDU and Power Shelf provide centralized power supply, and the CDU provides liquid cooling for the entire rack, thereby improving the integration and testing efficiency of the rack-mount memory testing equipment.

[0087] Optionally, in some embodiments, the cabinet 20 includes: a busbar and a cabinet back panel disposed inside the cabinet 20, wherein the busbar is pluggably connected to at least one test node 10 via a power input interface, and the busbar is configured to supply power to the power input interface; the cabinet back panel is provided with a high-density connector male, which is pluggably connected to at least one test node 10 via an external interface.

[0088] Specifically, the cabinet 20 contains a busbar and a back panel to provide power and signal transmission for the test nodes 10. The busbar (e.g., a copper busbar) is a power distribution structure located inside the cabinet 20, used to introduce external power and distribute it to the test nodes 10 within the cabinet 20. The back panel is a signal transfer board located inside the cabinet, equipped with high-density male connectors for transferring multiple signals from the test nodes 10 via external interfaces to the cabinet side or external devices. The high-density male connectors are located on the back panel and are used to mate with the high-density female connectors on the rear panel of the test nodes 10, enabling simultaneous connection or disconnection of multiple signals between the test nodes 10 and the back panel.

[0089] For power supply connection, test node 10 can connect to the busbar of the entire rack via a Power Clip (i.e., power input interface) to achieve power input. The Power Clip is fixed to the rear panel of test node 10, using a wire-to-board method, with one end connected to the busbar and the other end connected to the power board 200. During node testing, test node 10 is directly pushed into the rack, and the Power Clip automatically connects to the busbar. The power board 200 draws power from the rack busbar through the Power Clip, obtaining a 54V input. Figure 8 As shown, the 54V input is converted to P54V_SW0, P54V_SW1, and P54V_SW2 via three 54V EFUSE converters. P54V_SW0 and P54V_SW1 are converted to P12V_IN0 and P12V_IN1 via a 2000W power supply (power conversion module 202), and then transmitted to the motherboard via a wire-to-board connector. P54V_SW2 is converted to P12V_IN2 via a 1300W power supply and then transmitted to the fan board via a wire-to-board connector. Additionally, P12V_HDD is converted via EFUSE to power the M.2 (an internal computer expansion interface standard) backplane (the circuit board used to install M.2 storage devices), Riser cards (expansion cards used to expand internal server slots), etc. When test node 10 is removed from rack 20, the power input interface is separated from the busbar.

[0090] The high-density connector male on the back panel of the cabinet is pluggable to at least one test node 10 via the external interface of the test node 10. When the test node 10 is pushed into the cabinet 20, the external interface (such as the high-density connector female) on the rear panel of the test node 10 is plugged into the high-density connector male on the back panel of the cabinet, and multiple signals from the management board and power board inside the test node 10 are transmitted to the back panel of the cabinet through the external interface and the high-density connector male; when the test node 10 is pulled out of the cabinet 20, the external interface is separated from the high-density connector male, and the multiple signals are disconnected at once.

[0091] like Figure 9The diagram illustrates the signal interconnection architecture between test node 10 and the rack backplane. The test node side includes a management board 100, a motherboard, and a power board 200. The three components connect signals to a high-density female connector fixed to the rear window of test node 10 via cables. The high-density male connector on the rack side is fixed to the rack 20. After connecting with the high-density female connector, the signal is transferred to the various interfaces on the rack backplane.Specifically, the BMC (target controller 101) on the management board 100 outputs signals such as BMC_R / G / B (BMC status indicator signals (red / green / blue), used to indicate the operating status of test node 10), BMC_DAT6 / DAT7 (BMC data lines 6 / 7 (the 6th and 7th data signals in the low-speed data lines of the BMC, used to transmit BMC management data)), UART (Universal Asynchronous Receiver / Transmitter, used for serial communication between the BMC and external devices, such as BMC serial port debugging, log output, etc.), I2C (Inter-Integrated Circuit, used for communication between the BMC and I2C devices (such as temperature sensors) on the backplane of the cabinet), and PCIE 2.0 (Peripheral Component Interconnect Express 2.0, used for high-speed data transmission between the management board and external devices), which are then transmitted via Slim SAS (Serial Attached Small Computer System). Interface, a serial connection small computer system interface, is a high-density, small-size high-speed connector standard, commonly used for high-speed signal transmission between the motherboard and backplane, and hard drive backplane within servers. Mini SAS (Mini Serial Attached SCSI, a miniaturized version of the SAS connector, also used for high-speed signal transmission within servers) connectors are combined and then converted to VGA, UART, I2C, and MDI (Medium Dependent Interface) signals, respectively. The CPU outputs USB and PCIE (Peripheral Component Interconnect Express) signals on the motherboard, which are then combined via Conn (Connector) and MCIO (Mini Cool Input / Output) x4 (i.e., 4-channel mini high-speed connectors) connectors and converted to USB, PCIE, and MDI signals. The power board outputs USB and UID (Unit Identification, used to identify and locate indicator lights and buttons of specific test nodes 10 within the rack 20) ​​signals, which are then combined via Conn and PHY (Power over...) connectors. Ethernet (Power over Ethernet) signals are aggregated and converted into USB, UID, and MDI signals.After the above signals are connected via the male and female connectors of the high-density connector, they are respectively transferred on the back panel of the cabinet to the UID button / indicator, VGA interface, SMBus (System Management Bus), I2C level converter, RS232 (Recommended Standard 232) serial port, RJ45 (Registered Jack 45) management network port, USB 2.0 / 3.0 interface, RJ45 data network port, and the header (i.e., connector pin header) for connecting the high-temperature hood MCU (Microcontroller Unit) control board, thereby realizing a one-time quick-plug blind connection of multiple signals between the test node and the back panel of the cabinet.

[0092] Therefore, the cabinet provides power input to the test nodes through the busbar and connects to the external interface of the test nodes through the high-density male connector on the cabinet back panel, realizing simultaneous quick plugging and unplugging of power supply and signal: when the test node is pushed into the cabinet, the busbar connects to the power input interface and the high-density male connector connects to the external interface, and the connection is made simultaneously when the test node is pulled out, eliminating the need to plug and unplug cables one by one; at the same time, the pluggable connection between the busbar and the power input interface and the pluggable connection between the high-density male connector and the external interface provide a hardware foundation for subsequently shutting down the power conversion module output through the power-down control module before the test node is pulled out, thus eliminating the risk of liveness at each interface.

[0093] To facilitate understanding of the interface layout on the rack back panel, the following detailed description of each connector on the rack back panel is provided in conjunction with the tag number and function correspondence table.

[0094] Specifically, the rack back panel is equipped with various external interfaces. The tag numbers and functions of each interface are shown in Table 2. A diagram of the rack back panel tag numbers can be found as follows: Figure 10 As shown.

[0095]

[0096] The back panel of the rack features a UID indicator light, a VGA interface, two serial RJ45 connectors, two USB ports, two MDI signal RJ45 connectors, one RS232 serial port, and one I2C interface. The two MDI signal RJ45 connectors utilize a PHY chip to convert PCIe signals into MDI signals before leading them out. The RS232 serial port and I2C interface are used for communication with the memory high-temperature shield control board. The back panel is fixed to the rack, and its high-density connector male connector mates with the high-density terminal female connector on the rear window of the test node. The high-density terminal female connector on the test node side is fixed to the rear window of the test node and employs a floating tolerance design to ensure reliable mating.

[0097] It should be noted that test node 10 can also be equipped with a 4-to-1 cable. A diagram showing the connection between the 4-to-1 cable and the rack backplane can be seen as follows. Figure 11 As shown. Figure 12 As shown, one end of the cable has four connectors, which connect to the management board 100, the motherboard, and the power board 200 respectively. The other end has a high-density female connector (reference number J1), which is structurally fixed to the rear panel of test node 10 for mating with the high-density male connector on the back panel of the cabinet. The management board 100 has two connectors: J19 for rear I / O VGA expansion (i.e., the VGA-related signals on the management board 100 are led out through the rear I / O interface and expanded into a VGA interface for external display connection) and J3 for rear I / O MDI expansion (i.e., the PCIE signals on the management board 100 are converted into MDI signals by the PHY and led out through the rear I / O interface and expanded into a network interface for management network communication). The motherboard has a connector J50 for expanding the PCIE data network port. The power board has a connector J12 for rear I / O USB expansion (i.e., the USB signals on the power board 200 are led out through the rear I / O interface and expanded into a USB interface for external USB device connection). The signals corresponding to the above four connectors are gathered through cables to the high-density connector female head J1, and then connected to the high-density connector male head on the cabinet back panel via the high-density connector female head, realizing a one-time quick-plug blind connection of multiple signals between test node 10 and the cabinet back panel.

[0098] Through the centralized conversion method of the aforementioned 4-to-1 cable, the expansion of low-speed I / O interfaces on the rack backplane is realized: various scattered interface signals on the management board, motherboard, and power board are first uniformly gathered to the high-density connector female J1, and then led out through the standardized connector on the rack backplane, thus forming a centralized and unified external interface panel. As a result, the previously scattered and complex low-speed interfaces on three boards are integrated into a unified physical interface on the rack backplane. This allows the entire test node to be connected externally only through the standardized quick-connect interface on the backplane, eliminating the need to plug and unplug cables one by one. This significantly improves the modularity, maintenance convenience, and connection reliability of the test system, and enables rapid plugging and unplugging of test nodes.

[0099] Specifically, the low-speed signals collected and transferred to the rack backplane via the high-density connector female head can be divided into three categories according to their functions: management and monitoring signals, data and debugging signals, and power and network signals. Among them, the management and monitoring signals mainly come from the BMC on the management board, including the BMC's serial port (UART), I2C management bus, status indicator signals (R / G / B), and some low-speed data lines (DAT6 / DAT7), etc. After these signals are led out to the rack backplane via the high-density connector female head, they are converted by the backplane into standardized interfaces such as UID buttons / indicator lights, VGA interface, SMBus (SDA / SCL), etc., for the status monitoring, debugging, and out-of-band management of test nodes. Data and debugging signals originate from the motherboard and management board, including the motherboard's general-purpose interfaces such as USB and PCIe, and the management board's UART and PCIe 2.0 interfaces. These signals are led out to the rack backplane via high-density female connectors, where they are centrally converted into multiple easily pluggable standardized interfaces such as USB 2.0 / 3.0 and RS232 serial ports. These interfaces are then routed to areas for connecting to the host computer and the high-temperature hood MCU control board, facilitating the connection of test fixtures or monitoring equipment. Power and network signals primarily originate from the power board, including power control signals, differential signal pairs of the network PHY (such as ETH MDI), and clock (CLK). These signals are also led out to the rack backplane via high-density female connectors, where network connectivity and power communication are achieved through PHY-related connectors and network interfaces, ensuring that test nodes can be remotely controlled and monitored. By centrally transferring the above three types of signals, the test node only needs to connect to the cabinet backplane through the high-density connector female head to simultaneously connect or disconnect multiple signals such as management monitoring, data debugging, and power network, without having to plug and unplug cables one by one, which significantly improves the convenience of quick plugging and unplugging of the test node and the reliability of the connection.

[0100] Furthermore, a side view of test node 10, the memory high-temperature shield, and the host computer placed inside rack 20 is shown below. Figure 13 As shown. The wiring between the memory high-temperature shield and the lower 2U test node mainly consists of two parts: one is the power supply line, as the memory high-temperature shield itself requires a 220V power input; the other is the signal line, which is led out from the target controller 101 of test node 10 and is a serial port cable. It is fixed to the rear panel of test node 10 through a cable and high-density terminals, and achieves blind-plug quick-connection with the high-density terminals on the back panel of the rack. A corresponding serial port terminal is provided on the back panel of the rack. The wiring is connected to the memory high-temperature shield through this serial port terminal to obtain the memory temperature, transmit various information of the high-temperature shield, and send temperature control commands.

[0101] Optionally, in some embodiments, the cabinet 20 further includes a liquid-cooled blind-plug assembly disposed inside the cabinet 20. The liquid-cooled blind-plug assembly is pluggably connected to the liquid inlet interface and the liquid outlet interface, respectively. The liquid-cooled blind-plug assembly is configured to deliver coolant to the liquid inlet interface and receive coolant returned from the liquid outlet interface.

[0102] Specifically, the liquid-cooled blind-plug assembly is a liquid-cooled connection structure located inside the cabinet 20, used to achieve pluggable connection with the liquid inlet and liquid outlet interfaces on the rear panel of the test node 10. When the test node 10 is pushed into the cabinet 20, the liquid-cooled blind-plug assembly automatically mates with the liquid inlet and liquid outlet interfaces, eliminating the need for manual insertion and removal of liquid cooling lines; when the test node 10 is pulled out, the liquid-cooled blind-plug assembly automatically disengages from the liquid inlet and liquid outlet interfaces.

[0103] After the liquid-cooled blind-mount assembly automatically connects to the inlet and outlet ports on the rear side panel of test node 10, the liquid-cooled blind-mount assembly delivers coolant to the inlet port. The coolant flows into the test node 10 through the inlet port, passes through the heat-generating components (such as the CPU) inside the test node 10 to absorb heat, and then flows out of the test node 10 through the outlet port, returning to the liquid-cooled blind-mount assembly, which receives the coolant returning from the outlet port.

[0104] Therefore, the cabinet achieves a coolant circulation path through the liquid-cooled blind-plug assembly and the liquid inlet and outlet interfaces of the test node. When the test node is pushed into the cabinet, the liquid-cooled blind-plug assembly automatically connects with the liquid inlet and outlet interfaces, and disconnects synchronously when the test node is pulled out. There is no need to manually plug and unplug the liquid cooling pipes, which further realizes the synchronous quick plugging and unplugging of the power supply, signal and liquid cooling connections of the test node, improving the maintainability and operation convenience of the entire cabinet memory test equipment.

[0105] The test node 10 has a variety of quick-plug interfaces centrally located on its rear panel, such as... Figure 14 As shown, the liquid inlet and liquid outlet interfaces are used to connect with the liquid-cooled blind-plug structure of the cabinet to provide liquid cooling for the CPU inside the test node; the power input interface is used to connect with the busbar in the cabinet to introduce external power; the external interface (i.e., the high-density connector female head) is used to connect with the high-density connector male head on the back panel of the cabinet to realize one-time quick-plug blind-plug connection of multiple low-speed signals.

[0106] All of the above interfaces are located on the rear panel of the test node, allowing the test node to complete the power supply, signal and liquid cooling connections at once when it is pushed into the rack, thus supporting the quick plugging and unplugging of the test node.

[0107] Optionally, in some embodiments, the memory testing device 1 further includes a host computer, which is communicatively connected to the target controller 101. The host computer is configured to send a power-down command to the target controller 101 and receive test logs and test node serial numbers reported by at least one test node 10.

[0108] Specifically, the host computer is a centralized control device (such as a host computer or industrial computer) located outside or inside the rack 20. As the management and control terminal for the entire rack memory testing equipment, it is responsible for overall test process control, data collection and storage, and issuing test commands and power-down commands. It communicates with the test node 10 through an RS232 interface and receives test completion signals and logs. After the memory test is completed, the host computer receives the test logs and test node serial number reported by the test node 10, confirming that the test data has been properly received and stored for subsequent tracking and analysis. Subsequently, the host computer sends a "deep power-down" command (i.e., a power-down command) to the target controller 101 inside the test node 10. After receiving the power-down command, the target controller 101 outputs a power-down control signal to the power-down control module 201, triggering the test node 10 to execute the safe power-down process. That is, the power-down control module 201 shuts off the output voltage of the power conversion module 202, so that the low-speed interface inside the test node 10 no longer has standby voltage. Once test node 10 has safely powered down, the operator can remove test node 10 from rack 20.

[0109] like Figure 15 As shown, in this process, the test node control layer and the power supply and power-down control layer work together: the host computer communicates with the target controller in the test node through the RS232 interface. The target controller, as the core component of the test node control layer, has the following functions: it acts as the main controller of the high-temperature hood and communicates with the MCU in the high-temperature hood through I2C (the MCU in the high-temperature hood controls the heating, fan, shutter, and motor of the high-temperature hood, thereby realizing the temperature control function of the high-temperature hood); it receives instructions from the host computer and executes the deep power-down process; and it sends test logs and test node serial numbers to the host computer through the BIOS serial port. The power supply and power-down control layer includes a power board (including a power conversion module), a power-down control module, and a power input interface control circuit. Its functions are to provide multiple voltage outputs during normal operation, retain only the 54V input voltage (from the busbar to the power conversion module input) after receiving the deep power-down command, and turn off the output of the power conversion module and other voltages on the board.

[0110] Therefore, the host computer, as the centralized management terminal of the rack-mount memory testing equipment, can receive test logs and serial numbers reported by each test node, realizing centralized test management of multiple test nodes. On the other hand, it can send a power-down command to the target controller after the test is completed, triggering the test node to execute a safe power-down process before being unplugged. This connects test management with the safe power-down process, allowing the operator to send a power-down command to the target controller as soon as the host computer confirms that the test is completed. The node is then unplugged after being powered off, thus achieving automated connection between the test process and the safe plug-in / unplug process in the rack-mount scenario.

[0111] The memory testing equipment proposed in this embodiment of the invention employs pluggable test nodes installed inside the rack. Within each test node are a management board, a power board, and a power-down control module and a power conversion module located on the power board. Upon receiving a power-down command, the target controller outputs a power-down control signal. Alternatively, if the power-down control module fails to receive a periodic status signal for a duration exceeding a preset time, the power-down control module outputs a shutdown signal to the enable terminal of the power conversion module. This completely cuts off at least one output voltage of the power conversion module before the test node is removed, eliminating the standby voltage on the low-speed interface inside the test node. This eliminates the risk of arcing and electrostatic discharge caused by the energized separation of the low-speed interface in fast-plug scenarios, protecting sensitive chips such as the target controller from damage. Furthermore, the dual protection mechanism of active control by the target controller and autonomous fallback by the power-down control module ensures that the test node can reliably and safely power down whether the target controller is operating normally or malfunctioning, thus improving the reliability and operational safety of the entire rack-mounted memory testing equipment.

[0112] The embodiments of the present invention provide a power-down method for a memory testing device, and the method is described in detail in conjunction with the execution flow of the power-down method for the memory testing device.

[0113] like Figure 16 As shown, the power-down method of this memory testing device includes the following steps: In step S1601, in response to receiving a power-down command, a power-down control signal is sent to the power-down control module of the power board; In step S1602, based on the power-down control signal, the power-down control module is controlled to turn off at least one output voltage of the power conversion module; In step S1601, in response to the power conversion module completing the shutdown action, the status indicator light of the control test node is switched to the safe removal indication state.

[0114] In other words, after the test node completes the memory test, the host computer sends a power-down command to the power-down control module. Upon receiving this command, the power-down control module sends a power-down control signal. Upon receiving the power-down control signal, the power-down control module outputs a shutdown signal to the enable pin of the power conversion module, pulling the enable pin down below the shutdown threshold. The power conversion module then stops outputting, and at least one of its output voltages is shut down. Once the power conversion module's output voltage is shut down, the low-speed interface inside the test node no longer has standby voltage. At this point, the status indicator light on the test node switches to the "safe to remove" state, indicating to the operator that it is safe to remove the test node.

[0115] Therefore, after the memory test is completed at the test node, the host computer sends a power-down command to the power-down control module, and the power-down control module outputs a shutdown signal to the enable terminal of the power conversion module, causing the power conversion module to stop outputting and at least one of its output voltages to be turned off. This eliminates the standby voltage on the low-speed interface inside the test node, thus eliminating the risk of arcing and electrostatic discharge caused by the energized separation of the low-speed interface in fast plug-and-play scenarios. At the same time, after the power conversion module is turned off, the control status indicator switches to the safe removal indication state, clearly indicating to the operator when it is safe to remove the test node. This achieves a streamlined connection between safe power-down and safe removal, improving the operational safety and reliability of the whole rack memory testing equipment.

[0116] As one possible implementation, in some embodiments, controlling the power-down control module to shut down at least one output voltage of the power conversion module based on the power-down control signal includes: pulling the output pin of the power-down control module from a high level to a low level to generate a shutdown signal based on the power-down control signal; and using a level conversion circuit to transmit the shutdown signal to the enable terminal of the power conversion module to shut down at least one output voltage of the power conversion module.

[0117] The power-down control module shuts off at least one output voltage of the power conversion module, specifically through the following method: First, based on the received power-down control signal, the power-down control module pulls its output pin from high level to low level, thereby generating a shutdown signal; then, the shutdown signal is transmitted to the enable terminal of the power conversion module via a level conversion circuit connected between the power-down control module and the enable terminal of the power conversion module, causing the enable terminal to be pulled low below the shutdown threshold, thereby stopping the power conversion module from outputting and shutting off at least one output voltage.

[0118] Therefore, by combining the level flipping of the output pin of the power-down control module with the level conversion circuit, the shutdown signal output by the power-down control module can be reliably transmitted to the enable terminal of the power conversion module, ensuring that the enable terminal is pulled down below the shutdown threshold, thereby achieving reliable shutdown of the power conversion module. At the same time, the level conversion circuit, as an intermediate link, eliminates the need for the power-down control module to directly bear the electrical characteristics of the enable terminal of the power conversion module, reducing the difficulty of circuit design and improving the reliability of safe power-down action.

[0119] Optionally, in some embodiments, before responding to receiving a power-down command, the method further includes: generating a test log and a test node serial number in response to a memory test completion command; sending the test log and the test node serial number to a host computer; and generating a power-down command in response to receiving a response signal from the host computer.

[0120] In other words, in response to the memory test completion command, the test node generates a test log and a test node serial number; subsequently, the test node sends the generated test log and test node serial number to the host computer; after receiving the above information, the host computer returns an acknowledgment signal; in response to receiving the acknowledgment signal, the test node generates a power-down command.

[0121] Therefore, the power-down command is not generated immediately after the test is completed. Instead, it is generated by the test node only after the test log and test node serial number have been successfully reported to the host computer and a response signal has been received from the host computer. This ensures that the test data and node information have been properly received and stored by the host computer before the safe power-down process is initiated. This avoids the problem of test logs or serial numbers being lost due to premature power-down and achieves the coordination and unity between test data integrity and the safe power-down process.

[0122] Optionally, in some embodiments, after sending a power-down control signal to the power-down control module of the power board, the method further includes: using a watchdog timer unit to monitor the periodic status signal sent by the target controller to the power-down control module; and in response to the power-down control module not receiving the periodic status signal for a duration longer than a preset duration, outputting a shutdown signal to the enable terminal of the power conversion module to shut down at least one output voltage of the power conversion module.

[0123] Specifically, in the normal power-down path, the target controller actively outputs a power-down control signal, and the power-down control module responds to the signal to perform shutdown. However, in the above-mentioned fallback path, the target controller is no longer working properly. The power-down control module no longer relies on the target controller's instructions, but instead uses a watchdog timer unit to autonomously detect whether the target controller is abnormal. Upon determining that there is an abnormality, it directly performs shutdown as a supplementary protection for the normal power-down path.

[0124] Therefore, when the target controller is unable to send a power-down control signal normally due to hang-up or communication interruption, the power-down control module can autonomously detect the abnormality of the target controller through the watchdog timing unit and actively perform a shutdown action. As a fallback protection for the normal power-down path, it ensures that the test node can still reliably disconnect power before being unplugged in the event of a target controller abnormality, avoiding the low-speed interface being unplugged while energized due to a single point of failure of the target controller, and further improving the reliability and fault tolerance of safe power-down.

[0125] Optionally, in some embodiments, before responding to receiving a power-down command, the method further includes: in response to receiving a power-off command sent by a host computer, controlling at least one test node to enter a standby power-off state.

[0126] Specifically, after the memory test is completed, the host computer first sends a shutdown command to the test node. Upon receiving the shutdown command, the test node performs an orderly shutdown, shutting down the operating system and de-energizing the main circuit, entering a standby power-off state (i.e., a soft shutdown state). At this time, the main power supply inside the test node has been turned off, but components such as the target controller on the management board are still powered by the standby power supply to maintain necessary management functions. After the test node enters the standby power-off state, a subsequent power-down command triggers a complete shutdown of the power conversion module's output, ensuring that the low-speed interface no longer carries standby voltage, thus preparing for the safe removal of the test node.

[0127] Therefore, the safe power-down process is divided into two stages: first, the test node responds to the shutdown command from the host computer and enters a standby power-off state, completing the orderly shutdown of the operating system and ensuring data integrity and system stability; then, the power-down command triggers the complete shutdown of the power conversion module output. This staged power-down method avoids data loss or system anomalies caused by forced power-off before the operating system is fully shut down, further improving the reliability of the safe power-down process.

[0128] For a description of the features of the power-down method of the memory testing device in the corresponding embodiment, please refer to the relevant descriptions of the test node and the memory testing device in the corresponding embodiment, which will not be repeated here.

[0129] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0130] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination thereof. The aforementioned computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0131] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0132] The present invention has provided a detailed description of a test node, a memory testing device, and a power-down method for the memory testing device. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of these embodiments are merely illustrative of the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A test node, characterized in that, include: A management board, wherein the management board is provided with a target controller, the target controller being configured to output a power-down control signal and / or a periodic status signal; The power board includes a power-down control module and a power conversion module. The input terminal of the power conversion module is electrically connected to an external power source, and the output terminal of the power conversion module is electrically connected to the management board. The power conversion module is configured to provide operating voltage to the management board. The power-down control module is electrically connected to the enable terminal of the power conversion module and the target controller, respectively. The power-down control module is configured to output a shutdown signal to the enable terminal of the power conversion module in response to receiving the power-down control signal and / or not receiving the periodic status signal for a duration longer than a preset duration, so as to shut down at least one output voltage of the power conversion module.

2. The test node according to claim 1, characterized in that, The power-down control module includes: a first power-down control unit, which is configured to output the shutdown signal to the enable terminal of the power conversion module according to the received power-down control signal; And / or, a watchdog timer unit, which is electrically connected to the status signal output terminal of the target controller, is configured to output the shutdown signal to the enable terminal of the power conversion module if the duration of the periodic status signal not received exceeds the preset duration.

3. The test node according to claim 1, characterized in that, The power board also includes: A voltage conversion circuit is provided, wherein the input terminal of the voltage conversion circuit is electrically connected to the external power supply, the output terminal of the voltage conversion circuit is electrically connected to the power supply terminal of the power-down control module, and the output terminal of the voltage conversion circuit and the power conversion module are electrically isolated.

4. The test node according to claim 3, characterized in that, The power board also includes: A level conversion circuit is provided, which is connected between the power-down control module and the enable terminal of the power conversion module. The power-down control module outputs the shutdown signal to the enable terminal of the power conversion module through the level conversion circuit.

5. The test node according to claim 4, characterized in that, The level conversion circuit includes: a first MOSFET, a second MOSFET, and a pull-up resistor, wherein, The gate of the first MOS transistor is electrically connected to the output pin of the power-down control module, the source of the first MOS transistor is grounded, and the drain of the first MOS transistor is electrically connected to the gate of the second MOS transistor. The source of the second MOSFET is grounded, and the drain of the second MOSFET is electrically connected to the enable terminal of the power conversion module. One end of the pull-up resistor is electrically connected to the gate of the second MOS transistor, and the other end of the pull-up resistor is electrically connected to the power supply terminal of the power-down control module.

6. The test node according to claim 1, characterized in that, Also includes: A power input interface is provided on the rear panel of the test node. One end of the power input interface is electrically connected to the external power source, and the other end is electrically connected to the input terminal of the power conversion module. The power input interface is configured to connect to the external power source to supply the power provided by the external power source to the power conversion module.

7. The test node according to claim 6, characterized in that, The power input interface includes: a first pin and a second pin, wherein the length of the first pin is greater than the length of the second pin; The first pin is configured to transmit current from the external power supply; The second pin is configured to generate an indication signal when the test node is inserted into place, the indication signal being used to trigger the external power supply to provide power to the power conversion module.

8. The test node according to claim 1, characterized in that, Also includes: An external interface is located on the rear panel of the test node and is electrically connected to the management board. The external interface is configured to establish a signal transmission path between the target controller and the external device.

9. The test node according to claim 8, characterized in that, The external interface is a high-density female connector, which is connected to the management board and the power board respectively via cables.

10. The test node according to claim 1, characterized in that, Also includes: Inlet and outlet ports, among which, Both the inlet and outlet ports are located on the rear panel of the test node. The inlet port is configured to allow coolant to flow into the test node, and the outlet port is configured to allow coolant to flow out of the test node, thereby forming a coolant passage through the test node.

11. The test node according to claim 1, characterized in that, Also includes: A motherboard, wherein the motherboard is provided with memory slots, the memory slots being configured to install the memory module to be tested; Status indicator light, configured to indicate the on / off state of the output voltage of the power conversion module.

12. A memory testing device, characterized in that, include: Server rack; At least one test node as described in any one of claims 1-11, wherein at least one of the test nodes is pluggably installed inside the cabinet.

13. The memory testing device according to claim 12, characterized in that, The server rack includes: a busbar and a server rack back panel disposed inside the server rack, wherein, The busbar is pluggably connected to at least one of the test nodes via a power input interface, and the busbar is configured to supply power to the power input interface; The back panel of the cabinet is equipped with a high-density connector male, which can be plugged into and detached from at least one of the test nodes via an external interface.

14. The memory testing device according to claim 13, characterized in that, The cabinet also includes: The liquid-cooled blind-plug assembly is installed inside the cabinet. The liquid-cooled blind-plug assembly is pluggably connected to the liquid inlet and the liquid outlet respectively. The liquid-cooled blind-plug assembly is configured to deliver coolant to the liquid inlet and receive coolant returned from the liquid outlet.

15. The memory testing device according to claim 12, characterized in that, Also includes: The host computer is communicatively connected to the target controller and is configured to send a power-down command to the target controller and receive test logs and test node serial numbers reported by at least one of the test nodes.

16. A power-down method for a memory testing device, characterized in that, The method is applied to the memory testing device as described in any one of claims 12-15, and the method includes the following steps: In response to receiving a power-down command, a power-down control signal is sent to the power-down control module of the power board; Based on the power-down control signal, the power-down control module is controlled to shut off at least one output voltage of the power conversion module; In response to the power conversion module completing the shutdown action, the status indicator light of the test node is switched to the safe-to-remove indication state.

17. The power-down method of the memory testing device according to claim 16, characterized in that, The step of controlling the power-down control module to shut off at least one output voltage of the power conversion module based on the power-down control signal includes: Based on the power-down control signal, the output pin of the power-down control module is pulled low from high level to low level to generate a shutdown signal; The shutdown signal is transmitted to the enable terminal of the power conversion module using a level conversion circuit, so as to shut down at least one output voltage of the power conversion module.

18. The power-down method of the memory testing device according to claim 16, characterized in that, Prior to receiving the power-down command, the method further includes: In response to the memory test completion command, a test log and test node sequence number are generated; The test log and the test node serial number are sent to the host computer, and in response to receiving the response signal returned by the host computer, the power-down command is generated.

19. The power-down method of the memory testing device according to claim 16, characterized in that, After sending the power-down control signal to the power-down control module of the power board, the method further includes: The watchdog timer unit is used to monitor the periodic status signals sent by the target controller to the power-down control module; In response to the power-down control module not receiving a periodic status signal for a duration longer than a preset duration, a shutdown signal is output to the enable terminal of the power conversion module to shut down at least one output voltage of the power conversion module.

20. The power-down method of the memory testing device according to claim 16, characterized in that, Prior to receiving the power-down command, the method further includes: In response to receiving a power-off command from the host computer, at least one of the test nodes is controlled to enter a standby power-off state.

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