Power-off duration evaluation method, power-on inspection method and flash memory

Abstract

The application discloses a power-off duration evaluation method, a power-on inspection method and a flash memory. The power-off duration evaluation method comprises the following steps: selecting a target physical block, performing one data reading on one physical page in the target physical block by using a preset bias reading voltage, the bias reading voltage being applied to a high-state page of the physical page, wherein the high-state page is a logical page in which the highest programming state of the physical page is located; determining the power-off duration experienced by the target physical block according to the number of bits of the physical page that are flipped under the bias reading voltage; and performing the above steps cyclically until the power-off durations of all physical blocks in the flash memory are obtained. The application only needs one bias reading voltage for one reading, and can complete the evaluation of the flash power-off duration suitable for different power-off scenarios, especially overcoming the defect that the short power-off scenario is easy to misjudge, greatly reducing the reading times, and improving the accuracy and efficiency of the power-off duration evaluation.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a method for evaluating power-off duration, a power-on inspection method, and a flash memory. Background Technology

[0002] After a solid-state drive (SSD) is powered off, the read voltage shifts due to data retention stress, and the system cannot record the power-off duration. Upon power-on, the original read voltage may no longer be applicable. Current power-on recovery (POR) solutions that use multiple Fast OTR (Fast One Time Read) voltage levels for monitoring apply multiple voltage levels to specific physical pages and calculate the power-off duration based on the minimum number of fail bits (FBC). Taking BICS8-TLC-Retail NAND flash memory as an example, this requires at least 7 reads across 7 different power-off scenarios (3H / 24H / 168H / 3M / 6M / 1Y / 5Y).

[0003] The existing technical solutions have the following problems: Low efficiency: Multiple voltage levels are required for multiple reads, which has a significant impact on large-capacity disks and scenarios with frequent power-on and power-off cycles; Discrete judgment is possible: It cannot accurately assess the duration of continuous power outages and can only select settings from preset scenarios; Inaccurate short-term judgment: The number of flipped bits within 3 months is very small and easily affected by noise, which may lead to misjudgment of power outage duration. Summary of the Invention

[0004] This application provides a method for evaluating power-down duration, a power-on inspection method, and a flash memory that only requires a single bias read voltage to complete the evaluation of flash memory power-down duration under different power-down scenarios, significantly reducing the number of reads and improving the accuracy and efficiency of power-down duration evaluation.

[0005] The first aspect of this application provides a method for evaluating power-down duration, applied to a flash memory, the method comprising: selecting a target physical block, performing a data read on a physical page in the target physical block using a preset bias read voltage, wherein the bias read voltage is applied to the high-state page of the physical page, and the high-state page is the logical page in which the highest programming state is located in the physical page; The duration of power loss experienced by the target physical block is determined based on the number of bits that flip under the bias read voltage of the physical page. Repeat the above steps until the power-down duration of all physical blocks in the flash memory is obtained.

[0006] In this embodiment, only one high-level page bias read voltage is needed to complete the assessment of power outage duration. Each physical page only needs to be read once, and the number of reads is independent of the number of power outage scenario levels, fundamentally solving the problem of low inspection efficiency caused by multiple read levels in the prior art. At the same time, this bias read voltage can amplify the FBC difference under different power outage scenarios, making the previously difficult-to-distinguish short-term scenarios significantly different, greatly improving the accuracy of power outage scenario judgment.

[0007] In at least one possible implementation, the power-down duration experienced by the target physical block is calculated using a preset piecewise fitting model based on the number of bits that flip under the bias read voltage of the physical page.

[0008] In at least one possible implementation, the piecewise fitting calculation model is as follows: FBC ≤ first threshold, T = a * FBC^b, [a ∈ [0.1, 1], b ∈ [1, 4]] First threshold < FBC ≤ Second threshold, T = a1 * FBC - b1 [a1 ∈ [1, 10], b1 ∈ [0, 60]] Second threshold < FBC ≤ Third threshold, T = a2 * FBC - b2 [a2 ∈ [10, 20], b2 ∈ [60, 100]] FBC > third threshold, T = a3 * FBC - b3, [a3 ∈ [20, 150], b3 ∈ [100, 1000]] Wherein, FBC is the number of bits that the physical page flips under the bias read voltage, and T is the power-down duration experienced by the target physical block.

[0009] In this embodiment, the power outage duration assessment is upgraded from discrete selection to continuous and accurate calculation. Different fitting formulas (power functions or linear functions) are used for different power outage duration intervals, which can more accurately fit the actual physical relationship between the power outage duration and the FBC, thereby calculating the accurate continuous power outage duration. This overcomes the coarse assessment method in the prior art, which can only "select" from 7 preset discrete scenarios, and provides a reliable basis for the subsequent accurate adjustment of DRC.

[0010] In at least one possible implementation, when the physical page is in TLC mode, the highest programming state is the G state, and the high-level page is the logical page where the G state is located.

[0011] In at least one possible implementation, when the physical page is in QLC mode, the highest programming state is the 0 state, and the high-level page is the logical page where the 0 state is located.

[0012] In at least one possible implementation, when the physical page is in PLC mode, the highest programming state is state 31, and the high-level page is the logical page where the P31 state is located.

[0013] In this practical example, based on the universal rule of reading the page where the highest programming state is located, the technical solution of this application can be adapted to the current and future mainstream flash memory chip types.

[0014] In at least one possible implementation, selecting a target physical block in the flash memory includes: polling the status of all physical blocks in the flash memory, and sequentially selecting the target physical block from the physical blocks in the flash memory that have been programmed and are in a closed state according to a preset polling order.

[0015] In this embodiment, only physical blocks that have been programmed and are in a closed state are selected to avoid interfering with physical blocks that are being read or written. At the same time, empty blocks and other physical blocks that do not need to be inspected are excluded, thereby improving inspection efficiency.

[0016] In at least one possible implementation, after determining the duration of the power outage experienced by the target physical block, the method further includes: Calculate the corresponding data retention compensation value based on the power outage duration experienced by the target physical block; Determine if the data retention compensation value is less than the original data retention compensation value recorded in the flash memory: If yes, maintain the original configuration of the target physical block; otherwise, refresh the data retention compensation value and the corresponding optimal read voltage of the target physical block.

[0017] Adaptive optimization of DRC is achieved based on accurate power-down duration assessment results. Refresh operations are performed only when updates are needed, avoiding unnecessary write operation overhead. When updates are required, the DRC and corresponding optimal read voltage are refreshed promptly, ensuring that subsequent read operations can be executed at the optimal read voltage, significantly reducing the probability of read recovery triggering.

[0018] Secondly, embodiments of this application provide a power-on inspection method applied to a flash memory, characterized in that the method implements the steps described in any of the first aspects.

[0019] Thirdly, embodiments of this application provide a flash memory, which includes a storage chip and a main control chip. The storage chip stores a computer program, and when the computer program is executed by the main control chip, it implements the steps in the method described in any of the first aspects or the steps in the method described in any of the second aspects. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A flowchart illustrating an embodiment of the power outage duration assessment method provided in this application; Figure 2 A comparison chart of experimental data between the power outage duration assessment method provided in this application embodiment and traditional methods; Figure 3 A flowchart illustrating the process after determining the power outage duration experienced by the target physical block in the power outage duration evaluation method embodiment provided in this application; Figure 4 A schematic diagram of Embodiment 2 of the power outage duration evaluation method provided in this application; Figure 5 This is a schematic diagram of the structure of the flash memory in the embodiments of this application.

[0023] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be described in detail below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0025] It should be noted that: throughout the accompanying drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions; in the description of this application, the terms "center," "longitudinal," "lateral," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; in the description of this application, "first," "second," etc., are only used to distinguish each other, and do not indicate their degree of importance or order, etc.

[0026] In the description of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to fixed connections, movable connections, or detachable connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication between two components, etc. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0027] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0028] For non-volatile storage devices such as solid-state drives (SSDs), power outage duration is not a simple calendar time, but rather a weighted integral of "temperature × wear level × power outage time". In simpler terms, it's the total time a non-volatile storage device like an SSD experiences during a power outage.

[0029] Solid-state drives (SSDs) cannot record the power outage time, while the charge in flash memory cells continues to leak over time, causing read voltage shifts that become more severe with prolonged power outages. If the old voltage is used directly after power-on without assessing the power outage duration, it can easily trigger expensive read recovery processes, resulting in soaring I / O latency and a sharp drop in bandwidth. Therefore, it is necessary to assess the power outage duration to calculate the corresponding Data Retention Compensation (DRC) value and the Data Retention Time. The read voltage should be calibrated in one step before power-on to respond to host I / O, thereby avoiding read recovery storms and ensuring the performance and stability of the SSD.

[0030] Data retention time refers to the length of time a flash memory can retain stored data without causing uncorrectable errors when it is completely powered off.

[0031] Power-On Patrol Read is a critical step in the power-on recovery process. It refers to scanning and testing each physical block in the flash memory after power-on to assess its data retention status and determine whether the read voltage needs to be adjusted or data needs to be moved.

[0032] Fail Bit Count (FBC): This refers to the number of bits that are logically flipped (i.e., "0" becomes "1" or "1" becomes "0") when the data read from a flash memory page is compared to the original data written at a specific read voltage.

[0033] Optimum Trim Read (OTR): The actual threshold voltage distribution of the current flash memory cell, which is the reference voltage value that minimizes the raw bit error rate (RBER) when reading.

[0034] A physical page is a collection of multiple storage units arranged together to form a "page". It is the smallest unit in which flash memory performs read and write operations. A physical page typically contains a data area and a spare area (SA area) for storing management information such as error correction codes (ECC).

[0035] A physical block is a collection of multiple physical pages (e.g., 128 or 64). It is the smallest unit in which flash memory performs an erase operation. This "erase before write" mechanism is a key characteristic of flash memory.

[0036] Based on the number of bits that each storage cell can store, NAND flash memory can be divided into different types: SLC (Single-Level Cell): Each storage cell stores 1 bit of information and has two threshold voltage states (P0-P1), namely erase state and programmable state.

[0037] MLC (Multi-Level Cell): In a narrow sense, it refers to a cell that stores 2 bits of information and has 4 threshold voltage states (P0-P3), which are named Erase state and A state to C state by the JEDEC standard.

[0038] TLC (Triple-Level Cell): Each storage cell stores 3 bits of information and has 8 threshold voltage states (P0-P7), which are named Erase state and A state to G state by the JEDEC standard.

[0039] QLC (Quad-Level Cell): Each storage cell stores 4 bits of information and has 16 threshold voltage states (P0-P15), which are named Erase state and A state to O state by the JEDEC standard.

[0040] PLC (Penta-Level Cell): Each storage cell stores 5 bits of information and has 32 threshold voltage states (P0-P31). Currently, the JEDEC standard has not yet released a unified alphabetical naming system.

[0041] This application provides a method for evaluating power-down duration, applied to flash memory (such as solid-state drives, embedded memory, memory cards, etc.), used to evaluate the power-down duration experienced by each physical block in the flash memory due to power-down and the corresponding data retention duration after power-on.

[0042] Flash memory typically consists of three core components: a controller chip, NAND flash memory chips, and firmware. The controller chip is responsible for executing algorithms such as address mapping and wear leveling in the firmware, while the firmware defines specific scheduling strategies. Together, they determine the device's final performance, lifespan, and stability. The duration of power loss—how long data can be retained after a power outage (data retention time)—is primarily determined by the flash memory chips (physical hardware) and the firmware (error correction algorithms).

[0043] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0044] Example of a method for assessing power outage duration: See Figure 1 This application provides a method for evaluating power-down duration, applied to flash memory, the method comprising: Step S10: Poll the status of all physical blocks in the flash memory; In this embodiment, the flash memory comprises several physical blocks, which are composed of multiple physical pages. Physical blocks include free blocks (erased, containing no data, but ready to be written to at any time), open blocks (currently being written to, not yet full or closed), closed blocks (data programming has been completed, all physical pages have been written with valid data, and no new data can be written to them), bad blocks (marked as unusable due to excessive wear), and system blocks (used to store firmware, mapping tables, and other system data).

[0045] The main control chip obtains the current status information of each physical block by reading the status identifier of each physical block. This status identifier is usually stored in the system area of ​​the main control chip's memory or flash memory in the form of a status table or bitmap, and is updated and maintained by the main control chip in real time when the status of the physical block changes.

[0046] Step S20: Select target physical blocks sequentially from the physical blocks that have been programmed in the flash memory and are in a closed state, according to a preset polling order; Physical blocks that have been programmed and are in a closed state are called closed blocks. The threshold voltage distribution of closed blocks has stabilized. Reading the FBC can truly reflect the data retention offset, eliminating bad blocks, idle blocks and other scenarios that do not need to be inspected. This reduces the number of invalid reads from the source. In addition, the preset polling order ensures that all target physical blocks are covered in an orderly manner. Combined with the polling pointer, progress recording and breakpoint resume are realized to avoid repeated inspections and omissions.

[0047] Step S30: Use a preset bias read voltage to perform a data read on a physical page in the target physical block. The bias read voltage is applied to the high-state page of the physical page, where the high-state page is the logical page where the highest programmed state is located in the physical page. The bias read voltage refers to the read voltage obtained by applying a preset offset to the standard read voltage of the flash memory chip. The standard read voltage is a reference voltage value given by the flash memory manufacturer in the chip datasheet to distinguish adjacent threshold voltage states.

[0048] In this embodiment, the bias read voltage is the read voltage obtained by applying a preset offset to the highest standard read voltage corresponding to the highest programming state of the flash physical page. This bias voltage makes the memory cell that was originally at the boundary between two adjacent states more susceptible to read errors, thereby amplifying the threshold voltage drift caused by the data retention effect on the FBC. In this embodiment, one or more physical pages of the target physical block are randomly selected. In practice, the selection can also be made according to the product's power-on time requirements and the physical characteristics of the flash memory.

[0049] The high-level page is the logical page containing the highest programming state in the physical page. In the physical characteristics of flash memory, the bit corresponding to the high-level page usually requires 3 to 4 times longer operation time than the low-level page during programming (i.e., the "slow page" effect). Its threshold voltage distribution is more sensitive to charge leakage, and the read voltage offset phenomenon is the most significant. When the high-level page is used as the target of the bias read voltage, the FBC difference will be even greater.

[0050] The mapping relationship between physical page classes (Lower / Middle / Upper / Top Page) and programmed states may differ depending on the type of flash memory chip (e.g., TLC, QLC) or the wafer manufacturer. In practical engineering applications, those skilled in the art can uniquely determine the logical page class (e.g., high-order page or highest-order page) corresponding to the highest programmed state by consulting JEDEC standard documents or the datasheet and state mapping table provided by the wafer manufacturer.

[0051] In at least one possible implementation, the physical page is in TLC mode. A TLC memory cell has eight threshold voltage states (P0, P1, P2, P3, P4, P5, P6, P7, corresponding to the Erase state and A to G states in the JEDEC standard) and seven read voltages (RL1 to RL7), used to distinguish adjacent threshold voltage states. In TLC mode, the 3 bits of data stored in each physical page are logically mapped to three physical page classes, from lowest to highest: Lower Page, Middle Page, and Upper Page. The highest programming state is P7 (i.e., the G state in the JEDEC standard).

[0052] Reading the highest programming state P7 (G state) depends on the highest read voltage, namely RL7 (used to distinguish between P6 / F state and P7 / G state). In this embodiment, by applying a preset bias voltage to RL7, the failure bit count (FBC) of the high-order page (i.e., the logic page where P7 is located) is read to amplify the FBC difference under different power-down duration scenarios.

[0053] In at least one possible implementation, the physical page is in QLC mode. The QLC memory cell has 16 threshold voltage states (P0, P1, ..., P15 from low to high, corresponding to the Erase state and A to O states in the JEDEC standard) and 15 read voltages (RL1 to RL15) to distinguish adjacent threshold voltage states.

[0054] In QLC mode, the 4 bits of data stored in each physical page are logically mapped to four physical page classes, from lowest to highest: Lower Page, Middle Page, Upper Page, and Top Page (or Extra Page). The highest programming state is P15 (i.e., state 0 in the JEDEC standard), and the upper-state pages are the Top Pages (or Extra Pages).

[0055] Reading the highest programming state P15 (O state) depends on the highest read voltage, namely RL15 (used to distinguish between P14 / N state and P15 / O state). In this embodiment, by applying a preset bias voltage (i.e., the read voltage after biasing) to RL15, the number of failure bits (FBC) of the highest bit page (i.e., the page where P15 is located) is read to amplify the FBC difference under different power-down duration scenarios.

[0056] In at least one possible implementation, the physical page is in PLC mode. The PLC storage unit has 32 threshold voltage states (P0, P1, P2, ..., P30, P31 in ascending order) and 31 read voltages (RL1 to RL31) respectively, which are used to distinguish adjacent threshold voltage states.

[0057] In PLC mode, the 5 bits of data stored in each physical page are logically mapped to five physical page classes. (It should be noted that there is currently no unified alphabetical naming system for the 32 threshold voltage states of the PLC according to the JEDEC standard. The specific page class names vary depending on the manufacturer's bit state mapping design. Those skilled in the art can determine this by consulting the state mapping table provided by the wafer manufacturer.) In the PLC, the highest programming state is P31, and the high-level page is the logical page where P31 is located.

[0058] Reading the highest programming state P31 depends on the highest read voltage, namely RL31 (used to distinguish the second highest state P30 from the highest state P31). In this embodiment, by applying a preset bias voltage (i.e., the read voltage after biasing) to RL31, the number of failure bits (FBC) of the high-level page (i.e., the logic page where P31 is located) is read to amplify the FBC difference under different power-down duration scenarios.

[0059] Step S40: Determine the power-down duration experienced by the target physical block based on the number of bits that flip under the bias read voltage of the physical page; When reading using a preset bias read voltage, the greater the threshold voltage distribution offset, the more the threshold voltage of the memory cell crosses the bias read voltage boundary, resulting in a greater number of data bit flips (FBCs). The longer the power is off, the higher the FBC value.

[0060] In this embodiment, a physical page is randomly selected, and the power outage duration experienced by the target physical block is determined by the number of bits flipped in that physical page. In an optional embodiment, if multiple target physical pages need to be selected according to actual needs, the median of the number of bits flipped in the data of multiple target physical pages is finally counted as the final number of bit flips, and the power outage duration experienced by the target physical block is determined by the final number of bit flips.

[0061] Preferably, a preset piecewise fitting model is used to calculate the power outage duration experienced by the target physical block. The piecewise fitting model is obtained by curve fitting the number of bits that flip under different power outage scenarios.

[0062] In at least one possible implementation, the piecewise fitting calculation model is: FBC≤First threshold, T=a×FBC^b, a∈[0.1,1],b∈[1,4]; First threshold < FBC ≤ second threshold, T = a1 × FBC - b1, [a1 ∈ [1, 10], b1 ∈ [0, 60]; Second threshold < FBC ≤ Third threshold, T = a2 × FBC - b2, a2 ​​∈ [10, 20], b2 ∈ [60, 100]; FBC > third threshold, T = a3 × FBC - b3, a3 ∈ [20, 150], b3 ∈ [100, 1000]; Wherein, FBC is the number of bits of the physical page that flips under the bias read voltage, and T is the power-down duration experienced by the target physical block, in hours.

[0063] The first threshold, the second threshold, and the third threshold are pre-calibrated based on the specific characteristics of the flash memory chip.

[0064] See Figure 2 Taking BICS8-TLC-Retail Particles as an example, the FBC column data obtained by the evaluation method of this application covers 8 power-down scenarios (3 / 24 / 168H / 3M / 6M / 1Y / 5Y). The FBC value monotonically increases from 5 to 542, and there is a sufficiently large difference between adjacent scenarios. There is no FBC crossing or overlap. This means that only one bias read voltage (the voltage value corresponding to the RL3 or RL7 column) is needed. The FBC value obtained by one read can uniquely correspond to each power-down scenario. There is no need to apply 7 Fast OTR voltages to each physical page and perform 7 reads to infer the power-down duration.

[0065] from Figure 2 As shown in the table, the power outage duration predicted by the evaluation method of this application has a high degree of fit with the power outage duration measured by traditional experiments (for example, the power outage duration measured by traditional experiments is 3 hours, and the predicted power outage duration is 3.25 hours; the power outage duration measured by traditional experiments is 4320 hours, and the predicted power outage duration is 4268 hours), thus verifying the prediction accuracy of the evaluation method of this application, especially the prediction accuracy in short-term scenarios (such as 3 hours and 24 hours).

[0066] Step S50: Repeat the above steps until the power-down duration of all physical blocks in the flash memory is obtained.

[0067] After the main control chip completes the power-down duration assessment of the current target physical block, it selects the next target physical block in sequence according to the preset polling order and repeats steps S1-S4 until all physical blocks in the flash memory that have been programmed and are in a closed state are inspected and covered.

[0068] This embodiment requires only one bias read voltage and one read to accurately calculate the power outage duration. The number of reads per physical page is reduced from N times (e.g., 7 times) in the prior art to 1 time, and the efficiency of the whole disk inspection is improved to 1 / N of the original solution. At the same time, by selecting the high-state page that is most sensitive to charge leakage and applying a pull-bias voltage, the FBC discrimination of short-term scenarios (3 hours to 3 months) is improved from less than 10 bits in the original solution to more than 23 bits. This overcomes the defect of easy misjudgment in short-term power outage scenarios, reduces the number of reads, and improves the accuracy and efficiency of power outage duration assessment.

[0069] In at least one possible implementation, see Figure 3 After determining the duration of the power outage experienced by the target physical block, the following operations are performed: Step S31: Calculate the corresponding data retention compensation value based on the power outage duration experienced by the target physical block; In this embodiment, the main control chip has a pre-set mapping table or calculation formula between power-down duration and data retention compensation value. For example, this mapping relationship can be obtained through extensive experimental calibration of flash memory chips. The optimal data retention compensation value is measured under different power-down durations (e.g., 3 hours, 24 hours, 168 hours, 3 months, 6 months, 1 year, 5 years, etc., standard scenarios), and a lookup table is established, or a conversion function is obtained through curve fitting. Based on the calculated power-down duration T, the main control chip obtains the data retention compensation value DRC by looking up the table or substituting it into the conversion formula.

[0070] Step S32: Determine whether the data retention compensation value is less than the original data retention compensation value recorded in the flash memory. Step S33: If yes, then maintain the original configuration of the target physical block; Step S34: If not, refresh the data retention compensation value and the corresponding optimal read voltage of the target physical block.

[0071] Specifically, the flash memory persistently records the data retention compensation value (DRC) stored during the last inspection of the target physical block (e.g., in the reserved storage area of ​​the flash memory chip or in the register / cache of the main control chip), denoted as the original data retention compensation value DRC_old. This original data retention compensation value reflects the data retention status of the physical block during the last power-on inspection.

[0072] The main control chip compares the data retention compensation value DRC_new calculated in step S31 with the original data retention compensation value DRC_old read from the flash memory to determine whether DRC_new is less than DRC_old.

[0073] When the main control chip determines that DRC_new < DRC_old, it means that the data retention compensation level corresponding to the power outage duration calculated at the moment does not exceed the compensation level recorded at the last time (that is, the data retention status of the physical block has not deteriorated significantly, and it may only be a short power outage followed by a power-on). At this time, the data retention compensation value and the optimal read voltage OTR of the target physical block are not updated, and the original configuration remains unchanged.

[0074] When the main control chip determines that DRC_new ≥ DRC_old, it means that the data retention compensation level corresponding to the currently calculated power outage duration has reached or exceeded the compensation level recorded last time (i.e., the physical block has experienced a long power outage, and the data retention effect has caused a significant shift in the read voltage). At this time, it is necessary to update the data retention compensation value of the target physical block to DRC_new, and then obtain the corresponding optimal read voltage OTR_new by looking up a table based on DRC_new or by calculating it through a preset algorithm. The optimal read voltage OTR_new is then configured into the read voltage register corresponding to the target physical block, so that when performing read operations on the physical block in the future, the optimal read voltage OTR_new is used for data reading to adapt to the voltage threshold drift in the current data retention state and reduce the read error rate.

[0075] By following the steps above, the read voltage of each physical block in the flash memory can be adaptively adjusted to ensure that the optimal read voltage can be used for data reading under different power-down durations.

[0076] Example of power-on inspection method: This embodiment provides a power-on inspection method applicable to flash memory (such as solid-state drives, embedded memory, memory cards, etc.). In this embodiment, the flash memory is exemplarily a solid-state drive (SSD), but the present invention is not limited thereto, and is also applicable to other devices that use flash memory as a storage medium (such as embedded memory cards, USB flash drives, etc.).

[0077] The power-on inspection method is executed after each power-on of the solid-state drive and before responding to host I / O. The method includes performing the steps described in the above-described power-down duration evaluation method embodiment.

[0078] Specifically, when the SSD is restored from a power outage, the controller chip first performs firmware initialization, including loading the firmware program, initializing various hardware modules, and reading disk management information. After completing the above initialization operations and before responding to host read / write commands, the controller chip initiates a power-on inspection process. By completing the inspection before responding to host I / O, it ensures that all subsequent host read / write operations are performed under the optimal read voltage configuration, avoiding a large number of read recovery scenarios triggered by uncompensated voltage offsets, thereby ensuring the stability of I / O latency and bandwidth.

[0079] The power-on inspection method includes performing the steps described in the above-mentioned power-down duration evaluation method embodiment to obtain the power-down duration of all physical blocks in the flash memory, and to perform data retention compensation value and optimal read voltage configuration based on the power-down duration of each physical block.

[0080] The following provides a detailed description of this embodiment in conjunction with the specific process.

[0081] Step S41: Start the power-on inspection process; After the solid-state drive (SSD) is powered on, the controller chip completes basic initialization and enters the power-on inspection mode. In this embodiment, the inspection mode is configured as a "full-disk inspection mode," which evaluates the power-down duration of each physical block in the flash memory. This full-disk inspection mode is typically performed upon first power-on or after recovery from an abnormal power outage. In other embodiments, such as in normal frequent power-on / off scenarios, a "sampling inspection mode" is configured, where only a subset of representative physical blocks (e.g., selecting several physical blocks from each die or plane) are evaluated to shorten the inspection time.

[0082] Step S42: Select the target physical block in the flash memory and perform a power-down duration assessment; When performing a power outage duration assessment, the specific steps are as follows: Figure 1 And steps S10 to S50 in the aforementioned power outage duration assessment method embodiment.

[0083] Step S43: Update the data to retain the compensation value and optimal reading voltage based on the power outage duration; The main control chip executes the data retention compensation update process based on the power outage duration T calculated in step S42 (see...). Figure 3 (and steps S31 to S34 in the foregoing embodiments).

[0084] Step S44: Determine whether the full inspection is complete.

[0085] If not, return to step S42; if yes, proceed to step S45.

[0086] Step S45: End the power-on inspection and respond to host I / O.

[0087] After completing the inspection of all physical blocks on the disk, the main control chip exits the power-on inspection mode, sets the disk status to "Ready," returns the command processing status to the host, and begins to respond normally to the host's read / write requests and other I / O commands. It should be noted that the "execution before responding to host I / O" mentioned in this embodiment does not require the inspection process to completely block all host command responses. The main control chip can allow some high-priority host commands (such as Identify, SMART query, and other management commands) during the inspection process, only waiting for read / write I / O commands until the inspection is complete before allowing read / write operations.

[0088] Please refer to Figure 5 This application embodiment also provides a flash memory, including a main control chip 100 and a storage chip 200. The storage chip 200 is coupled to the main control chip 100. The storage chip 200 is used to store computer program code, which includes computer instructions. When the main control chip 100 reads the computer instructions from the storage chip 200, the main control chip 100 executes the steps of the method in any possible implementation of any of the foregoing embodiments.

[0089] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0090] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for evaluating power-down duration, applied to flash memory, characterized in that, The method includes: Select a target physical block, and use a preset bias read voltage to read data from a physical page in the target physical block. The bias read voltage is applied to the high-state page of the physical page, which is the logical page where the highest programmed state is located in the physical page. The power-down duration experienced by the target physical block is determined based on the number of bits that flip under the bias read voltage of the physical page. Repeat the above steps until the power-down duration of all physical blocks in the flash memory is obtained.

2. The power outage duration assessment method according to claim 1, characterized in that, Determining the power outage duration experienced by the target physical block includes: Based on the number of bits that flip under the bias read voltage, the power-down duration experienced by the target physical block is calculated using a preset piecewise fitting model.

3. The power outage duration assessment method according to claim 2, characterized in that... ； The piecewise fitting model is as follows: FBC≤First threshold, T=a×FBC^b, a∈[0.1,1],b∈[1,4]; First threshold < FBC ≤ second threshold, T = a1 × FBC - b1, a1 ∈ [1, 10], b1 ∈ [0, 60]; Second threshold < FBC ≤ Third threshold, T = a2 × FBC - b2, [a2 ∈ [10, 20], b2 ∈ [60, 100]; FBC > third threshold, T = a3 * FBC - b3, a3 ∈ [20, 150], b3 ∈ [100, 1000]; Wherein, FBC is the number of bits that the physical page flips under the bias read voltage, and T is the power-down duration experienced by the target physical block.

4. The power outage duration assessment method according to any one of claims 1 to 3, characterized in that, When the physical page is in TLC mode, the highest programming state is the G state, and the high-level page is the logical page where the G state is located.

5. The power outage duration assessment method according to any one of claims 1 to 3, characterized in that, When the physical page is in QLC mode, the highest programming state is the O state, and the high-level page is the logical page where the O state is located.

6. The power outage duration assessment method according to any one of claims 1 to 3, characterized in that, When the physical page is in PLC mode, the highest programming state is state 31, and the high-level page is the logic page where state P31 is located.

7. The power outage duration assessment method according to any one of claims 1 to 3, characterized in that, The selection of the target physical block in the flash memory includes: polling the status of all physical blocks in the flash memory, and sequentially selecting the target physical block from the physical blocks in the flash memory that have been programmed and are in a closed state according to a preset polling order.

8. The power outage duration assessment method according to any one of claims 1 to 3, characterized in that, After determining the power outage duration experienced by the target physical block, the method further includes: Calculate the corresponding data retention compensation value based on the power outage duration experienced by the target physical block; Determine whether the data retention compensation value is less than the original data retention compensation value recorded in the flash memory: If yes, then maintain the original configuration of the target physical block; otherwise, refresh the data retention compensation value and the corresponding optimal read voltage of the target physical block.

9. A power-on inspection method, applied to a flash memory, characterized in that, The method performs the steps of the power outage duration assessment method according to any one of claims 1 to 8.

10. A flash memory, characterized in that, The flash memory includes a storage chip and a main control chip. The storage chip stores a computer program. When the computer program is executed by the main control chip, it implements the steps of the power-off duration evaluation method according to any one of claims 1 to 8 or the steps of the power-on inspection method according to claim 9.

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