Event-triggered sequential and time-stamped recording device, method and chip

Abstract

The application relates to the technical field of event record, and discloses an event trigger sequence and time recording device. The recording device comprises a cache RAM write data merging module, an event state module and a clock counting module. The cache RAM write data merging module reads event state data from the event state module and reads timestamp data from the clock counting module to generate merging data. A cache RAM write control module outputs a real-time write address to a configuration management module and outputs a write address and a write enable to an information cache RAM, and the write address is equal to the real-time write address. The information cache RAM writes the merging data into the write address. A cache RAM read control module reads data in the information cache RAM according to a read address and feeds back the data to the configuration management module for reading by a bus. The configuration management module resets a recording state of the event state module after the bus reading is completed or when the reading is triggered. The recording device can record the time trigger sequence and time at high speed. The application further discloses an event trigger sequence and time recording method and a chip.

Description

Technical Field

[0001] This application relates to the field of event recording technology, such as an apparatus, method, and chip for recording the sequence and timing of event triggering. Background Technology

[0002] Direct Memory Access (DMA) technology enables data to be transferred directly from one memory to another with minimal or no CPU involvement, thus freeing up CPU resources and making DMA technology widely applicable.

[0003] Even though DMA technology is relatively mature now, it is still undergoing continuous optimization and development. Recording the detailed execution time of each operation in a DMA operation is helpful for analyzing performance bottlenecks and thus guiding the optimization process.

[0004] In the process of implementing the embodiments of this application, at least the following problems were found in the related technology:

[0005] Existing technologies can record the request initiation time, data size, and transfer time of DMA operations, meaning they can only record information about each DMA operation at a relatively macroscopic level. The sequence and time / interval of various hardware actions, such as DMA enabling, descriptor acquisition start / end, data transfer start / end, and interrupt reporting / handling, are also crucial for analyzing DMA performance bottlenecks. Due to the high-speed data transfer characteristic of DMA, existing event recording technologies cannot effectively record these hardware actions. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This application provides an apparatus, method, and chip for recording the sequence and timing of event triggering, so as to record the sequence and timing of events at the level level. When applied in DMA performance bottleneck analysis scenarios, it can analyze DMA performance bottlenecks at a more microscopic level, which is beneficial to the optimization of DMA technology.

[0008] In some embodiments, the recording device for the event triggering sequence and time includes:

[0009] The configuration management module is accessed by the master device via the bus.

[0010] The event status module monitors and records the trigger status of multiple events; these events are at the level level.

[0011] The clock counting module is capable of continuously generating timestamps;

[0012] The cache RAM write data merging module is connected to the event status module and the clock counting module. It reads event status data from the event status module and timestamp data from the clock counting module, and merges the event status data and timestamp data to generate merged data.

[0013] The cache RAM write control module is connected to the configuration management module and the event status module. When the event status module records that an event has been triggered, it outputs the real-time write address to the configuration management module. The configuration management module determines the read address based on the real-time write address.

[0014] The information cache RAM is connected to the cache RAM write data merging module and the cache RAM write control module. When the event status module records that an event has been triggered, the cache RAM write control module outputs a write address and write enable to the information cache RAM. The information cache RAM writes the merged data to the write address, where the write address is equal to the real-time write address. Furthermore, the write address output by the cache RAM write control module is incremented once every time the event status module records that an event has been triggered.

[0015] The cache RAM read control module is connected to the configuration management module and the information cache RAM. It receives the read address output by the configuration management module, reads data from the information cache RAM according to the read address, and feeds back the read data to the configuration management module for access bus reading.

[0016] The configuration management module is connected to the event status module. The configuration management module resets the record status of the event status module after the bus reading is completed or when the reading is triggered.

[0017] Optionally, the device for recording the event triggering sequence and time further includes: an event enabling module connected to the configuration management module;

[0018] The cache RAM write control module is connected to the event status module, including: the cache write control module is connected to the event enable module, and the event enable module is connected to the event status module;

[0019] The configuration management module outputs a configuration mask to the event enable module to set the access rules for multiple event triggering states in the event status module;

[0020] If one or more event trigger states recorded in the event status module indicate that an event has been triggered, and one or more event trigger states meet the pass rules of the configuration mask, then the event enable module outputs an enable signal to the cache RAM write control module. The cache RAM write control module outputs a write address and write enable to the information cache RAM. The information cache RAM writes the merged data to the write address. Furthermore, the cache RAM write control module increments the write address every time it receives an enable signal.

[0021] Otherwise, the event enable module will not output an enable signal to the cache RAM write control module.

[0022] Optionally, when one or more events monitored by the event status module have been triggered, the corresponding historical status position in the event status module is "1";

[0023] The configuration mask in the event enable module consists of several "1"s and "0"s, where "1" indicates that the event trigger state is allowed to pass and "0" indicates that the event trigger state is not allowed to pass.

[0024] Optionally, the configuration management module outputs the write operation mode to the cache RAM write control module.

[0025] Optionally, the cache RAM write control module outputs a write address and write enable to the information cache RAM, including:

[0026] When the write operation mode is stopped at a specified event, when the specified event is triggered, the cache RAM write control module terminates the process of outputting the write address and write enable to the information cache RAM and stops recording subsequent events.

[0027] When the write operation mode is set to stop when the cache is full, the cache RAM write control module terminates the process of outputting the write address and write enable to the information cache RAM when the cache write address reaches the capacity limit, and no longer records subsequent events.

[0028] When the write operation mode is cached circular write, the cache RAM write control module continuously outputs the write address and write enable to the information cache RAM, regardless of whether the cache write address has reached the capacity limit.

[0029] Specifically, when the cache write address reaches its capacity limit, the write address is reset to zero and re-accumulated.

[0030] Optionally, when the cache write address has not reached its capacity limit, the cache RAM write control module increments the write address after each write address is output to the information cache RAM. For example, it increments by 1.

[0031] Specifically, the write enable signal output by the cache RAM write control module to the information cache RAM enables the information cache RAM to be in a write-enabled state. This write enable signal can be in the form of a pulse.

[0032] Furthermore, if the cache write address does not reach the capacity limit after the cache RAM write control module outputs the write address and write enable to the information cache RAM, the cache RAM write control module will increment the write address output next time; if the cache write address reaches the capacity limit after the cache RAM write control module outputs the write address and write enable to the information cache RAM, the cache RAM write control module will reset the write address output next time to zero and increment it again.

[0033] Optionally, the configuration management module outputs a write operation enable status to the cache RAM write control module, and the cache RAM write control module also outputs a write completion status to the configuration management module.

[0034] When the cache RAM write control module terminates the process of outputting the write address and write enable to the information cache RAM, it sets the write completion status to a value indicating that the write is complete.

[0035] When the write operation enable status of the configuration management module is enabled, the write address of the cache write control module remains unchanged;

[0036] When the write operation enable state changes from disabled to enabled, the write address of the cache RAM write control module is cleared to zero, and the write completion status is set to a value indicating incompleteness.

[0037] Optionally, the recording device for the event triggering sequence and time may also include a logic OR module;

[0038] The logic OR module connects to the event status module and the cache RAM write control module; when one or more event trigger states recorded in the event status module are "event triggered past", the logic OR module outputs "enabled", otherwise it outputs "disabled"; or,

[0039] In the case of an event enable module, the logic OR module is connected to the event enable module and the cache RAM write control module; if one or more event trigger states recorded in the event status module indicate that an event has been triggered, and one or more event trigger states meet the pass rules of the configuration mask, the logic OR module outputs enable; otherwise, it outputs disable.

[0040] When the write operation enable state of the configuration management module is enabled and the output of the logical OR module is enabled, the cache RAM write control module is in the write enabled state; otherwise, it is in the write disabled state.

[0041] Optionally, the configuration management module determines the read address based on the real-time write address, including: determining the read address within the range of real-time write addresses.

[0042] Optionally, the cache RAM read control module receives the read address output by the configuration management module, and reads data from the information cache RAM according to the read address, including:

[0043] After receiving the read address output by the configuration management module, if the configuration management module does not output a new read address in the new read cycle, that is, if no updated read address is output before the configuration management module outputs the next read enable, then data is read from the information cache RAM according to the "next read address" in the new read cycle. In each read cycle, the configuration management module sends a read enable to the cache RAM read control module once; the "next read address" can be obtained by incrementing 1 based on the current address.

[0044] If the configuration management module outputs a new read address during a new read cycle, data is read from the cache RAM based on the newly received read address.

[0045] Optionally, when the master device accesses the configuration management module via the bus, the configuration management module and the cache RAM read control module interact cyclically as follows: the configuration management module outputs the read address and read enable to the cache RAM read control module, and receives the data read from the information cache RAM by the cache RAM read control module.

[0046] Optionally, when the master device accesses the configuration management module via the bus, the configuration management module outputs an initial read address to the cache RAM read control module, and the configuration management module then interacts with the RAM read control module in a loop as follows: the configuration management module outputs a read enable to the cache RAM read control module and receives data read from the information cache RAM by the cache RAM read control module.

[0047] In some embodiments, the recording device to which the method for recording the event triggering sequence and time applies includes a configuration management module, an event status module, a clock counting module, a cache RAM write data merging module, a cache RAM write control module, an information cache RAM, and a cache RAM read control module.

[0048] The configuration management module is connected to the event status module, the cache RAM write control module, and the cache RAM read control module, respectively; the cache RAM write data merging module is connected to the event status module, the clock counting module, and the cache RAM write control module, respectively; the cache RAM write control module is also connected to the event status module and the information cache RAM; the cache RAM read control module is also connected to the information cache module.

[0049] The logging method is applied to the configuration management module and is triggered when the master device accesses the device via the bus. The logging method includes:

[0050] Receive the real-time write address sent by the cache RAM write control module, and determine the read address based on the real-time write address;

[0051] Send a read address to the cache RAM read control module so that it can read data from the information cache RAM according to the read address; receive the data read from the information cache RAM by the cache RAM read control module so as to access the bus for reading;

[0052] The recording state of the event status module is reset after the bus read is completed or when a read is triggered;

[0053] The data stored in the information cache RAM is stored in the following manner: the event status module monitors and records the trigger status of multiple events, where the events are level-level events; the clock counting module continuously generates timestamps; the cache RAM write data merging module reads event status data from the event status module and timestamp data from the clock counting module, and merges the event status data and timestamp data to generate merged data; when the event status module records that an event has been triggered, the cache RAM write control module outputs a write address and write enable to the information cache RAM, and the write address is equal to the aforementioned real-time write address; the information cache RAM writes the merged data to the write address.

[0054] Specifically, every time the event status module records that an event has been triggered, the write address output by the cache RAM write control module is incremented once.

[0055] In some embodiments, the event triggering sequence and time recording chip includes the event triggering sequence and time recording device provided in the foregoing embodiments;

[0056] In some embodiments, the recording chip for the event triggering sequence and time includes a storage medium storing computer-executable instructions configured as the event triggering sequence and time recording method provided in the foregoing embodiments.

[0057] The device, method, and chip for recording the event triggering sequence and time provided in the embodiments of this application can achieve the following technical effects:

[0058] The event status module can monitor and record the trigger status of multiple events. For example, if the level corresponding to an event changes from low to high, it is recorded as the event has occurred. Or, if the level corresponding to an event generates a pulse, it is recorded as the event has occurred.

[0059] The event "Event status module records event triggered" will trigger the cache RAM write control module to output the real-time write address to the configuration management module, and simultaneously output the write address and write enable to the information cache RAM. At this moment, the information cache RAM will merge the data and write it to the write address. Furthermore, each time the event "Event status module records event triggered" is triggered, the real-time write address output by the cache RAM write control module to the configuration management module is incremented by one, and the write address output to the information cache RAM is also incremented by one.

[0060] When the event status module does not detect an event trigger, the event status data in the merged data of the cache RAM write data merging module continuously indicates that no event has been triggered. Because the clock counting module continuously generates timestamps, the timestamps in the merged data of the cache RAM write data merging module are constantly updated. When the event "the event status module records that an event has been triggered" occurs, the timestamp in the merged data becomes the latest timestamp, and the event status data in the merged data represents the latest event status where an event has been triggered. The information cache RAM then has a write address and caches the current merged data at that write address.

[0061] In this way, the event triggering sequence and time recording device quickly caches the monitored level-level event triggering state into RAM, where the different addresses where the merged data is written reflect the triggering order of each event.

[0062] During the above process, the configuration management module also determines the read address based on the write address output by the cache RAM write control module, and outputs the read address to the cache RAM read control module. In this way, the cache read control module can read data in the information cache RAM and feed back the read data to the configuration management module for access bus reading.

[0063] The configuration management module resets the recording state of the event status module after the bus read is completed or when a read is triggered, so that the event status module can quickly record the latest event trigger state and continuously and quickly write the latest event status data and timestamp data into the information cache RAM through a series of hardware triggers, so that it can be continuously accessed for reading on the bus.

[0064] The process of writing and reading event status data and timestamps to the information cache RAM described above, from the perspective of the information cache RAM, is the process of reading data from the main memory (information cache RAM) (receiving the write address and merging data) and outputting data (outputting the merging data at the corresponding address to the cache RAM read control module). Its access speed is at the nanosecond (ns) level, which is much faster than the millisecond (ms) level access speed of the disk. Based on this, the technical solution of this application can realize the recording of the sequence and time of events at the level level.

[0065] When the technical solution of this application is applied to the DMA performance bottleneck analysis scenario, it can record the sequence, time / interval of various hardware actions such as DMA enabling, descriptor acquisition start / end, data transfer start / end, interrupt reporting / processing, etc., which is beneficial to the optimization of DMA technology.

[0066] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0067] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrative descriptions and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are considered similar elements, and wherein:

[0068] Figure 1 This is a schematic diagram of an event triggering sequence and time recording device provided in an embodiment of this application;

[0069] Figure 2 This is a schematic diagram of an event triggering sequence and time recording device provided in an embodiment of this application;

[0070] Figure 3 This is a schematic diagram illustrating the interaction between a configuration management module and a cache RAM write control module, provided in an embodiment of this application.

[0071] Figure 4a and Figure 4b This is a schematic diagram of an event triggering sequence and time recording device provided in an embodiment of this application;

[0072] Figure 5 This is a schematic diagram illustrating the interaction between a configuration management module and a cache RAM read control module, as provided in an embodiment of this application.

[0073] Figure 6 This is a flowchart illustrating a method for recording the event triggering sequence and time provided in an embodiment of this application. Detailed Implementation

[0074] To provide a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this application. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0075] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0076] Unless otherwise stated, the term "multiple" means two or more.

[0077] In this embodiment, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0078] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0079] The event triggering sequence and time recording device provided in this application embodiment is a high-speed device for recording event triggering sequence and time. It can be applied to DMA performance bottleneck analysis scenarios, and can also be used to record the state machine transition sequence and time / interval of chip port connection establishment, such as PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard) chips, SRIO (Serial RapidIO, a protocol for high-speed serial communication) chips, Ethernet (Ethernet) network adapter (Network Interface Controller, NIC) chips, etc.

[0080] It should be understood that, since the event triggering sequence and time recording device provided in this application embodiment is a high-speed recording device for event triggering sequence and time, in addition to the above application scenarios, it can also be applied to other scenarios with high-speed recording of event triggering sequence and time at the level level.

[0081] The specific form of the recording device provided in the embodiments of this application can be a chip for various purposes. Here, chip is a broad concept of integrated circuit, which also includes field programmable gate array (FPGA).

[0082] Figure 1 This is a schematic diagram of an event triggering sequence and time recording device provided in an embodiment of this application.

[0083] Combination Figure 1As shown, the device for recording the event triggering sequence and time includes a configuration management module 11, an event status module 12, a clock counting module 13, a cache RAM write data merging module 14, a cache RAM write control module 15, an information cache RAM 16, and a cache RAM read control module 17.

[0084] The configuration management module 11 is accessed by the master device via the bus. The master device refers to any device capable of issuing bus requests and executing data transmission after gaining bus control. It controls the bus's operating mode, startup and shutdown, and performs status acquisition operations via the bus. Buses include, but are not limited to, AMBA (Advanced Microcontroller Bus Architecture). Specifically, AMBA buses include: AXI (Advanced Dextensible Interface), AHB (Advanced High-performance Bus), or APB (Advanced Peripheral Bus).

[0085] The event status module 12 monitors and records the triggering status of multiple events; these events are level-level events. Level-level events are characterized by changes in voltage levels, such as a low voltage when the event is not triggered and a high voltage when the event is triggered, or the generation of a pulse signal. This application does not limit the specific voltage levels for the event triggering and non-triggered states; those skilled in the art can set them according to specific needs and habits.

[0086] The event status module 12 mainly records the historical status of event triggering. For example, when an event is triggered, the event status module 12 will set the historical status position corresponding to the event to "1" or "0" to indicate that the event has been triggered. After the event is triggered, the historical status bit corresponding to the event will no longer be affected by whether the event is triggered or not, but will be cleared by the internal logic of this recording device.

[0087] The event status module 12 includes multiple historical status bits, each of which is used to record an event triggering status.

[0088] The number of events monitored / recorded by the event status module 12 is determined by design requirements.

[0089] The clock counting module 13 continuously generates timestamps. Internally, it uses a Timer that increments by 1 under clock drive, resets to zero when full, and then continues incrementing. The bit width of the Timer is determined by design, and in principle, the interval between two consecutive events should be less than the Timer's period. The value of the Timer output by the clock counting module 13 is the timestamp. After the Timer value is cached in the subsequent information buffer RAM 16, if the Timer is reset, the recording device provided in this embodiment can record the time interval; if the Timer does not reset but continues counting, the recording device provided in this embodiment can record the time.

[0090] The cache RAM write data merging module 14 is connected to the event status module 12 and the clock counting module 13. It reads event status data from the event status module 12 and timestamp data from the clock counting module 13, and merges the event status data and timestamp data to generate merged data. The specific form of the merged data can be {event status, timestamp} or {timestamp, event status}. This merged data is refreshed in real time, and the merged data written to the information cache RAM 16 later is the merged data at the current moment.

[0091] The cache RAM write control module 15 is connected to the configuration management module 11 and the event status module 12. When the event status module 12 records that an event has been triggered, it outputs the real-time write address to the configuration management module 11.

[0092] The real-time write address is used to determine the valid address range in the readable information cache RAM 16. When the cache RAM write control module 15 obtains a new address by accumulating the address, the address of the information cache RAM 16 that is less than the real-time write address has completed the write operation, and its internal data is valid.

[0093] Thus, the configuration management module 11 determines the read address based on the real-time write address, ensuring that the read address is within the valid address range.

[0094] The information cache RAM 16 is connected to the cache RAM write data merging module 14 and the cache RAM write control module 15. When the event status module 12 records that an event has been triggered, the cache RAM write control module 15 outputs a write address and write enable to the information cache RAM 16. The information cache RAM 16 writes the merged data to the write address, where the write address is equal to the real-time write address.

[0095] The address depth of the information cache RAM 16 can be determined based on the number of events in the event state. For example, the address depth can be greater than or equal to the number of events. Alternatively, those skilled in the art can determine it according to design requirements, which will not be elaborated here. The data bus width of the information cache RAM 16 is greater than or equal to the bit width of {event state, timestamp}.

[0096] The cache RAM read control module 17 is connected to the configuration management module 11 and the information cache RAM 16. It receives the read address output by the configuration management module 11, reads data from the information cache RAM 16 according to the read address, and feeds back the read data to the configuration management module 11 for access bus reading.

[0097] The configuration management module 11 is connected to the event status module 12. The configuration management module 11 resets the recording status of the event status module 12 after the bus reading is completed or when a reading is triggered. If the event status module 12 indicates that the event has been triggered by "1", then the configuration management module 11 sets "1" to "0" in this step; if the event status module 12 indicates that the event has been triggered by "0", then the configuration management module 11 sets "0" to "1" in this step.

[0098] In this embodiment of the application, the event status module 12 can monitor and record the triggering status of multiple events. For example, if the level corresponding to an event changes from low to high, it is recorded as the event has occurred. Or, if the level corresponding to an event generates a pulse, it is recorded as the event has occurred.

[0099] The event “Event status module 12 recorded that the event has been triggered” will trigger the cache RAM write control module 15 to output the real-time write address to the configuration management module 11, and at the same time output the write address and write enable to the information cache RAM 16. At this moment, the information cache RAM 16 will write the merged data to the write address.

[0100] When the event status module 12 does not detect an event trigger, the event status data in the merged data of the cache RAM write data merging module 14 continuously indicates that no event has been triggered. Since the clock counting module 13 continuously generates timestamps, the timestamps in the merged data of the cache RAM write data merging module 14 are constantly updated. When the event "event status module 12 recorded that an event has been triggered" occurs, the timestamp in the merged data becomes the latest timestamp, and the event status data in the merged data indicates the latest event status with an event trigger. The information cache RAM 16 then has a write address, and under the action of write enable, it caches the merged data of the current moment at the write address.

[0101] In this way, the event triggering sequence and time recording device quickly caches the monitored level-level event triggering state into RAM, where the different addresses where the merged data is written reflect the triggering order of each event.

[0102] During the above process, the configuration management module 11 also determines the read address based on the write address output by the cache RAM write control module 15, and outputs the read address to the cache RAM read control module 17. In this way, the cache read control module 17 can read data in the information cache RAM 16 and feed back the read data to the configuration management module 11 for access bus reading.

[0103] After the bus reading is completed or when the reading is triggered, the configuration management module 11 resets the recording state of the event state module 12 so that the event state module 12 can quickly record the latest event trigger state and continuously and quickly write the latest event state data and timestamp data into the information cache RAM 16 through a series of hardware triggers, so as to continuously provide access to the bus for reading.

[0104] The process of writing and reading event status data and timestamps to the information cache RAM16 described above, from the perspective of the information cache RAM16, is the process of reading data (receiving the write address and merging data) and outputting data (outputting the merging data at the corresponding address to the cache RAM read control module 17) from the main memory (information cache RAM16). Its access speed is at the nanosecond (ns) level, which is much faster than the millisecond (ms) level access speed of the disk. Based on this, the technical solution of this application can realize the recording of the order and time of events at the level level.

[0105] When the technical solution of this application is applied to the DMA performance bottleneck analysis scenario, it can record the sequence, time / interval of various hardware actions such as DMA enabling, descriptor acquisition start / end, data transfer start / end, interrupt reporting / processing, etc., which is beneficial to the optimization of DMA technology.

[0106] Figure 2 This is a schematic diagram of an event triggering sequence and time recording device provided in an embodiment of this application.

[0107] Combination Figure 2 As shown, the device for recording the event triggering sequence and time also includes an event enabling module 18 connected to the configuration management module 11.

[0108] The cache RAM write control module 15 is connected to the event status module 12, and includes: the cache write control module 15 is connected to the event enable module 18, and the event enable module 18 is connected to the event status module 12.

[0109] The configuration management module 11 outputs a configuration mask to the event enable module 18 to set the access rules for multiple event trigger states in the event status module 12. The event status module 12 monitors or records the trigger states of multiple events. After the access rules for multiple event trigger states in the event status module 12 are set by the configuration mask, the event trigger states that are allowed to pass can continue to trigger subsequent operations, while the event trigger states that are not allowed will no longer affect subsequent operations.

[0110] If one or more event triggering states recorded in the event status module 12 indicate that an event has been triggered, and one or more event triggering states meet the pass rules of the configuration mask, then the event enable module 18 outputs an enable signal to the cache RAM write control module 15, the cache RAM write control module 15 outputs a write address and write enable to the information cache RAM 16, and the information cache RAM 16 writes the merged data to the write address.

[0111] Otherwise, the event enable module 18 will not output an enable signal to the cache RAM write control module 15, the cache RAM write control module 15 will no longer output a write address and write enable to the information cache RAM 16, and the information cache RAM 16 will no longer write the merged data to the write address.

[0112] In the recording device of this application embodiment, an event enable module 18 is added, and a mask is configured through the configuration management module 11. Even if the historical status bit of the event corresponding to the event in the event status module 12 changes, such change will not affect the operation of other subsequent modules, thus enabling the selection of events that need to be recorded.

[0113] Optionally, when one or more events monitored by the event status module 12 have been triggered, the corresponding historical status position in the event status module 12 is set to "1" to indicate that the event has been triggered.

[0114] In this case, the configuration mask in the event enable module 18 consists of several "1"s and "0"s, with "1" indicating that the event triggering state is allowed to pass and "0" indicating that the event triggering state is not allowed to pass.

[0115] Each "1" or "0" represents a specific parameter of an enable bit, and the specific parameter of each enable bit can be independently adjusted by the configuration management module 11. The number of enable bits in the event enable module 18 is the same as the number of historical status bits in the event status module 12, both being the total number of events monitored / recorded by the event status module 12, and both are determined by design requirements.

[0116] The specific working principle of the event status module 12 and the event enable module 18 is as follows: the specific value of the enable bit in the event enable module 18 is bitwise ANDed with the specific value of the historical status bit in the corresponding event status module 12. That is, if the value of "historical status bit & enable bit" is "1", then the bit will continue to trigger the operation of other subsequent modules; if the value of "historical status bit & enable bit" is "0", then the bit will no longer trigger the operation of other subsequent modules.

[0117] Specifically, if one enable bit in the event enable module 18 is turned on (i.e., the value of the enable bit is "1"), then even if the corresponding historical state bit in the event state module 12 changes from "0" to "1", the value of "historical state bit & enable bit" also changes from "0" to "1" when the corresponding historical state bit in the event state module 12 changes from "0" to "1", which will trigger subsequent operations of other modules; if one enable bit in the event enable module 18 is turned off (i.e., the value of the enable bit is "0"), then when the corresponding historical state bit in the event state module 12 changes from "0" to "1", the value of "historical state bit & enable bit" will always remain "0", which will not trigger subsequent operations of other modules.

[0118] Figure 3 This is a schematic diagram illustrating the interaction between a configuration management module and a cache RAM write control module, as provided in an embodiment of this application.

[0119] Combination Figure 3 As shown, the configuration management module 11 outputs the write operation mode to the cache RAM write control module 15. The write operation modes include stop at a specified event, stop when the cache is full, and cache loop write.

[0120] Correspondingly, the cache RAM write control module 15 outputs a write address and write enable to the information cache RAM 16, including:

[0121] When the write operation mode is stopped at a specified event, when the specified event is triggered, the cache RAM write control module 15 terminates the process of outputting the write address and write enable to the information cache RAM 16 and no longer records subsequent events.

[0122] When the write operation mode is "stop when cache is full", when the cache write address reaches the capacity limit, the cache RAM write control module 15 terminates the process of outputting the write address and write enable to the information cache RAM 16 and no longer records subsequent events.

[0123] When the write operation mode is cached circular write, regardless of whether the cache write address has reached the capacity limit, the cache RAM write control module 15 continuously outputs the write address and write enable to the information cache RAM 16.

[0124] Specifically, when the cache write address reaches the capacity limit, the write address output by the cache RAM write control module 15 is reset to zero and re-accumulated.

[0125] This can satisfy a variety of writing needs.

[0126] In some specific application scenarios, when the cache write address reaches the capacity limit, the write address is reset to zero and re-accumulated.

[0127] Optionally, when the cache write address has not reached the capacity limit, the cache RAM write control module 15 increments the write address after each write address is output to the information cache RAM 16. For example, it increments by 1.

[0128] Specifically, the write enable signal output by the cache RAM write control module 15 to the information cache RAM 16 enables the information cache RAM 16 to be in a write-enabled state. The write enable signal output by the cache RAM write control module 15 to the information cache RAM 16 can be in the form of a pulse.

[0129] Furthermore, if the cache write address does not reach the capacity limit after the cache RAM write control module 15 outputs the write address and write enable to the information cache RAM 16, the cache RAM write control module will increment the write address output next time; if the cache write address reaches the capacity limit after the cache RAM write control module 15 outputs the write address and write enable to the information cache RAM 16, the cache RAM write control module 15 will reset the write address output next time to zero and increment it again.

[0130] Recombined Figure 3 As shown, the configuration management module 11 also outputs the write operation enable status to the cache RAM write control module 15, and the cache RAM write control module 15 also outputs the write completion status to the configuration management module 11.

[0131] When the cache RAM write control module 15 terminates the process of outputting the write address and write enable to the information cache RAM 16, that is, when the two write operation modes of specified event stop and cache full stop meet the stop conditions, the write completion status is set to a value indicating completion, such as "1" or "0".

[0132] When the write operation enable state of the configuration management module 11 is disabled, the write address of the cache write control module 15 remains unchanged, and no write operation of the cache RAM write control module 15 will be triggered by any event. For example, "0" can be used to represent that the write operation enable state is disabled.

[0133] When the write operation enable state changes from disabled to enabled, the write address of the cache RAM write control module 15 is cleared to zero, and the write completion status is set to a value indicating incompleteness. For example, the write operation enable state changes from "0" to "1".

[0134] The values ​​indicating incompleteness are determined by the values ​​indicating completeness. If "1" indicates completeness, then "0" indicates incompleteness. When the write operation enable state changes from "0" to "1", the write completion state is set from "1" to "0". If "0" indicates completeness, then "1" indicates incompleteness. When the write operation enable state changes from "0" to "1", the write completion state is set from "0" to "1".

[0135] The term "write operation enable state" in this application embodiment is different from "write enable" in cache RAM write control module 15. Write enable is a specific signal for cache RAM write control module 15 to perform an action. It allows cache RAM write control module 15 to perform the action of outputting write address and write enable to information cache RAM 16. The write operation enable state can be regarded as one of the conditions for write enable. Another condition for write enable is that the event state module 12 records that an event has been triggered.

[0136] The write operation enable state can be viewed as a master switch through which the cache RAM write control module 15 continuously outputs write address and write enable to the information cache RAM 16. Specifically:

[0137] When the write operation enable state is enabled, when the event status module 12 records that an event has been triggered, the cache RAM write control module 15 outputs the write address and write enable to the information cache RAM 16; when the write operation enable state is disabled, even if the event status module 12 records that an event has been triggered, the cache RAM write control module 15 will not output the write address and write enable to the information cache RAM 16.

[0138] When the write operation is enabled and the event status module 12 has recorded that an event has been triggered, the cache RAM write control module 15 increments or decrements the write address by 1 each time it outputs a write address. The condition under which the write address stops changing depends on the specific write operation mode described above.

[0139] The configuration management module effectively controls the cache RAM write control module 15 through the above method, enabling it to write data on demand according to bus access.

[0140] Figure 4a and Figure 4b This is a schematic diagram of an event triggering sequence and time recording device provided in an embodiment of this application.

[0141] Combination Figure 4a and Figure 4b As shown, the recording device for the event triggering sequence and time also includes a logic OR modulo 19.

[0142] Specific combination Figure 4aAs shown, the logic OR module 19 is connected to the event status module 12 and the cache RAM write control module 15; when one or more event triggering states recorded in the event status module 12 are event triggered past, the logic OR module 19 outputs enable, otherwise it outputs disable.

[0143] When the write operation enable state of the configuration management module 11 is enabled and the output of the logic OR module 19 is enabled, the cache RAM write control module 15 is in the write enabled state; otherwise, it is in the write disabled state.

[0144] In the case where the recording device includes the event enable module 18, further specific combinations Figure 4b As shown, the logic OR module 19 is connected to the event enable module 18 and the cache RAM write control module 15; if one or more event triggering states recorded in the event status module 12 indicate that an event has been triggered, and one or more event triggering states meet the pass rules of the configuration mask, the logic OR module 19 outputs enable; otherwise, it outputs disable.

[0145] When the write operation enable state of the configuration management module 11 is enabled and the output of the logic OR module 19 is enabled, the cache RAM write control module 15 is in the write enabled state; otherwise, it is in the write disabled state.

[0146] The number of data bits (i.e., bit width) contained in the logic OR module 19 is equal to the number of data bits contained in the event state module 12 and the event enable module 18, both determined by design requirements.

[0147] exist Figure 4a In this logic OR module 19, the rising edge operation is performed on each historical state bit, and then a bitwise OR operation is performed, that is, the bit corresponding to any event is set, and the logic OR output is set.

[0148] exist Figure 4b In this logic OR module 19, the rising edge operation is performed on the logical result bits of each "historical status bit & enable bit", and then a bitwise OR operation is performed, that is, the bit corresponding to any event is set, and the logical OR output is set.

[0149] The process involves taking the rising edge of the data bit to generate a single-cycle pulse signal. The operation is as follows: a timer operation is performed on data bit A (delayed by one data cycle) to generate A_Delay; the calculation logic for the rising edge pulse signal is A & !A_Delay, where data bit A is any "historical state bit & enable bit".

[0150] The following example, in conjunction with the output of logic OR module 19, illustrates a specific application scenario of write operation enable state and write enable.

[0151] When the write operation enable state is "1", if the logic OR module 19 outputs "1" (i.e., enabled), then the write enable state is "1", indicating that write is enabled; if the logic OR module 19 outputs "0" (i.e. disabled), then the write enable state is "0", indicating that write is disabled.

[0152] Figure 5 This is a schematic diagram illustrating the interaction between a configuration management module and a cache RAM read control module, as provided in an embodiment of this application.

[0153] Combination Figure 5 As shown, the cache RAM read control module 17 receives the read address output by the configuration management module 11, and reads data from the information cache RAM 16 according to the read address, including:

[0154] After receiving the read address output by the configuration management module 11, if the configuration management module 11 does not output a new read address in the new read cycle, that is, if no updated read address is output before the configuration management module outputs the next read enable, then in the new read cycle, data is read from the information cache RAM 16 according to the "next read address", and the "next read address" and the data read from the information cache RAM 16 are fed back to the configuration management module 11. Specifically, in each read cycle, the configuration management module sends a read enable to the cache RAM read control module once; the "next read address" can be obtained by incrementing the current address by 1, and the cache RAM read control module 17 uses this "next read address" as the new read address to read data from the information cache RAM 16.

[0155] In this way, the configuration management module 11 only needs to cyclically set the read enable, for example, by cyclically outputting pulses indicating read enable, so that the cache RAM read control module 17 can read data sequentially from the information cache RAM 16.

[0156] The read address output by the configuration management module 11 to the cache RAM read control module 17 is determined by the configuration management module 11. The configuration management module 11 determines the read address based on the real-time write address, which may include determining the read address within the range of the real-time write address to ensure that the data cached in the information cache RAM 16 at the read address is valid.

[0157] If the configuration management module 11 outputs a new read address during a new read cycle, then data is read from the cache RAM according to the newly received read address.

[0158] The configuration management module 11 outputs the read address in real time and not in real time, which can realize on-demand control of the cache RAM read control module 17.

[0159] Specifically, the configuration management module 11 outputs the read address in real time and does not output the read address in real time, representing two reading modes: specified address mode and address cumulative change mode.

[0160] Recombined Figure 5 The two modes are illustrated by example.

[0161] In the specified address mode, when the master device accesses the configuration management module 11 via the bus, the configuration management module 11 and the cache RAM read control module 17 interact cyclically as follows: the configuration management module 11 outputs a read address and read enable to the cache RAM read control module 17, and receives data read from the information cache RAM 16 by the cache RAM read control module 17. This three-step cycle ensures that data can be read from the information cache RAM 16 according to the bus access requirements.

[0162] In address accumulation mode, when the master device accesses the configuration management module 11 via the bus, the configuration management module 11 outputs an initial read address to the cache RAM read control module 17. The configuration management module 11 then interacts with the RAM read control module 17 in a loop as follows: the configuration management module 11 outputs a read enable to the cache RAM read control module 17 and receives data read from the information cache RAM 16 by the cache RAM read control module 17. This two-step loop enables automatic data reading.

[0163] Figure 6 This is a flowchart illustrating a method for recording the event triggering sequence and time provided in an embodiment of this application.

[0164] The recording device to which the recording method is applicable includes a configuration management module 11, an event status module 12, a clock counting module 13, a cache RAM write data merging module 14, a cache RAM write control module 15, an information cache RAM 16, and a cache RAM read control module 17.

[0165] The configuration management module 11 is connected to the event status module 12, the cache RAM write control module 15, and the cache RAM read control module 17, respectively; the cache RAM write data merging module 14 is connected to the event status module 12, the clock counting module 13, and the cache RAM write control module 17, respectively; the cache RAM write control module 15 is also connected to the event status module 12 and the information cache RAM 16; and the cache RAM read control module 17 is also connected to the information cache module.

[0166] When the recording method is applied to the configuration management module 11, it is triggered when the master device accesses the device via the bus, combined with... Figure 6 As shown, the recording method includes:

[0167] S601: Receive the real-time write address sent by the cache RAM write control module 15, and determine the read address based on the real-time write address.

[0168] S602: Send a read address to the cache RAM read control module 17, so that it reads data from the information cache RAM 16 according to the read address; receive the data read from the information cache RAM 16 by the cache RAM read control module 17 for access bus reading.

[0169] S603. Reset the recording state of the event state module 12 after the bus reading is completed or when the reading is triggered.

[0170] The data stored in the information cache RAM 16 is stored in the following manner: the event status module 12 monitors and records the trigger status of multiple events, wherein the events are level-level events; the clock counting module 13 continuously generates timestamps; the cache RAM write data merging module 14 reads event status data from the event status module 12 and timestamp data from the clock counting module 13, and merges the event status data and timestamp data to generate merged data; when the event status module 12 records that an event has been triggered, the cache RAM write control module 15 outputs a write address and write enable to the information cache RAM 16, and the write address is equal to the above-mentioned real-time write address; the information cache RAM 16 writes the merged data to the write address.

[0171] Figure 6 The order of the steps described is for general illustration only. In specific application scenarios, all steps will be executed, but not necessarily in the following order. Figure 6 The steps shown must be performed strictly in sequence.

[0172] In some embodiments, the event triggering sequence and time recording chip includes the event triggering sequence and time recording device provided in the foregoing embodiments.

[0173] In some embodiments, a chip storage medium for recording the event triggering sequence and time stores computer-executable instructions configured as the event triggering sequence and time recording method provided in the foregoing embodiments.

[0174] This application provides a computer-readable storage medium storing computer-executable instructions, which are configured as a method for recording the event triggering sequence and time provided in the foregoing embodiments.

[0175] This application provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions, which, when executed by a computer, cause the computer to execute the event triggering sequence and time recording method provided in the foregoing embodiments.

[0176] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0177] The technical solutions of this application embodiment can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods in this application embodiment. The aforementioned storage medium can be a non-transitory storage medium, including: USB flash drive, portable hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0178] The foregoing description and accompanying drawings fully illustrate embodiments of this application to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Additionally, when used in this application, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Unless otherwise specified, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes that element. In this document, each embodiment may focus on describing the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referred to the description of the method section.

[0179] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0180] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0181] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A device for recording the sequence and time of event triggering, characterized in that, include: The configuration management module is accessed by the master device via the bus. The event status module monitors and records the trigger status of multiple events; these events are at the level level. The clock counting module is capable of continuously generating timestamps; The cache RAM write data merging module is connected to the event status module and the clock counting module. It reads event status data from the event status module and timestamp data from the clock counting module, and merges the event status data and timestamp data to generate merged data. The cache RAM write control module is connected to the configuration management module and the event status module. When the event status module records that an event has been triggered, it outputs the real-time write address to the configuration management module. The configuration management module determines the read address based on the real-time write address. The information cache RAM is connected to the cache RAM write data merging module and the cache RAM write control module. When the event status module records that an event has been triggered, the cache RAM write control module outputs a write address and write enable to the information cache RAM. The information cache RAM then writes the merged data to the write address, where the write address is equal to the real-time write address. The cache RAM read control module is connected to the configuration management module and the information cache RAM. It receives the read address output by the configuration management module, reads data from the information cache RAM according to the read address, and feeds back the read data to the configuration management module for access bus reading. The configuration management module is connected to the event status module. The configuration management module resets the record status of the event status module after the bus reading is completed or when the reading is triggered.

2. The recording device according to claim 1, characterized in that, Also includes: An event enabling module that connects to the configuration management module; The cache RAM write control module is connected to the event status module, including: the cache write control module is connected to the event enable module, and the event enable module is connected to the event status module; The configuration management module outputs a configuration mask to the event enable module to set the access rules for multiple event triggering states in the event status module; If one or more event triggering states recorded in the event status module indicate that an event has been triggered, and one or more event triggering states meet the pass rules of the configuration mask, then the event enable module outputs an enable signal to the cache RAM write control module, the cache RAM write control module outputs a write address and write enable to the information cache RAM, and the information cache RAM writes the merged data to the write address. Otherwise, the event enable module will not output an enable signal to the cache RAM write control module.

3. The recording device according to claim 2, characterized in that, When one or more events monitored by the event status module have been triggered, the corresponding historical status position in the event status module is "1"; The configuration mask in the event enable module consists of several "1"s and "0"s, where "1" indicates that the event trigger state is allowed to pass and "0" indicates that the event trigger state is not allowed to pass.

4. The recording device according to any one of claims 1 to 3, characterized in that, The configuration management module outputs the write operation mode to the cache RAM write control module; The cache RAM write control module outputs the write address and write enable to the information cache RAM, including: When the write operation mode is stopped at a specified event, when the specified event is triggered, the cache RAM write control module terminates the process of outputting the write address and write enable to the information cache RAM and stops recording subsequent events. When the write operation mode is set to stop when the cache is full, the cache RAM write control module terminates the process of outputting the write address and write enable to the information cache RAM when the cache write address reaches the capacity limit, and no longer records subsequent events. When the write operation mode is cached circular write, the cache RAM write control module continuously outputs the write address and write enable to the information cache RAM, regardless of whether the cache write address has reached the capacity limit.

5. The recording device according to claim 4, characterized in that, The configuration management module outputs the write operation enable status to the cache RAM write control module, and the cache RAM write control module also outputs the write completion status to the configuration management module. When the cache RAM write control module terminates the process of outputting the write address and write enable to the information cache RAM, it sets the write completion status to a value indicating that the write is complete. When the write operation enable status of the configuration management module is disabled, the write address of the cache write control module remains unchanged; When the write operation enable state changes from disabled to enabled, the write address of the cache RAM write control module is cleared to zero, and the write completion status is set to a value indicating incompleteness.

6. The recording device according to claim 5, characterized in that, It also includes logic or modules; The logic OR module connects to the event status module and the cache RAM write control module; when one or more event trigger states recorded in the event status module are "event triggered past", the logic OR module outputs "enabled", otherwise it outputs "disabled"; or, In the case of an event enable module, the logic OR module is connected to the event enable module and the cache RAM write control module; if one or more event trigger states recorded in the event status module indicate that an event has been triggered, and one or more event trigger states meet the pass rules of the configuration mask, the logic OR module outputs enable; otherwise, it outputs disable. When the write operation enable state of the configuration management module is enabled and the output of the logical OR module is enabled, the cache RAM write control module is in the write enabled state; otherwise, it is in the write disabled state.

7. The recording apparatus according to any one of claims 1 to 3, characterized in that, The configuration management module determines the read address based on the real-time write address, including: determining the read address within the range of the real-time write address; The cache RAM read control module receives the read address output by the configuration management module and reads data from the information cache RAM according to the read address, including: After receiving the read address output by the configuration management module, if the configuration management module does not output a new read address in the new read cycle, then data is read from the information cache RAM according to the "next read address" in the new read cycle. If the configuration management module outputs a new read address during a new read cycle, data is read from the cache RAM based on the newly received read address.

8. The recording device according to claim 7, characterized in that, When the master device accesses the configuration management module via the bus, the configuration management module and the cache RAM read control module interact cyclically as follows: the configuration management module outputs the read address and read enable to the cache RAM read control module, and receives the data read from the information cache RAM by the cache RAM read control module. or, When the master device accesses the configuration management module via the bus, the configuration management module outputs the initial read address to the cache RAM read control module. The configuration management module then interacts with the RAM read control module in a loop as follows: the configuration management module outputs read enable to the cache RAM read control module and receives the data read from the information cache RAM by the cache RAM read control module.

9. A method for recording the sequence and time of event triggering, characterized in that, The recording device to which the recording method is applicable includes a configuration management module, an event status module, a clock counting module, a cache RAM write data merging module, a cache RAM write control module, an information cache RAM, and a cache RAM read control module; The configuration management module is connected to the event status module, the cache RAM write control module, and the cache RAM read control module, respectively; the cache RAM write data merging module is connected to the event status module, the clock counting module, and the cache RAM write control module, respectively; the cache RAM write control module is also connected to the event status module and the information cache RAM; The cache RAM read control module is also connected to the information cache module; The logging method is applied to the configuration management module and is triggered when the master device accesses the device via the bus. The logging method includes: Receive the real-time write address sent by the cache RAM write control module, and determine the read address based on the real-time write address; Send a read address to the cache RAM read control module so that it can read data from the information cache RAM according to the read address; receive the data read from the information cache RAM by the cache RAM read control module so as to access the bus for reading; The recording state of the event status module is reset after the bus read is completed or when a read is triggered; The data stored in the information cache RAM is stored in the following manner: the event status module monitors and records the trigger status of multiple events, where the events are level-level events; the clock counting module continuously generates timestamps; the cache RAM write data merging module reads event status data from the event status module and timestamp data from the clock counting module, and merges the event status data and timestamp data to generate merged data; when the event status module records that an event has been triggered, the cache RAM write control module outputs a write address and write enable to the information cache RAM, and the write address is equal to the aforementioned real-time write address; the information cache RAM writes the merged data to the write address.

10. A recording chip for the sequence and timing of event triggering, characterized in that, The device for recording the event triggering sequence and time as described in any one of claims 1 to 8; Or, including: A storage medium storing computer-executable instructions configured as the method for recording the event triggering sequence and time as provided in claim 9.

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