A chip performance verification method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application disclose a chip performance verification method and device, electronic equipment and storage medium, and relate to the technical field of integrated circuits, which can effectively improve the accuracy of chip performance verification. The method comprises the following steps: obtaining a chip performance verification model of a chip to be verified, wherein the chip performance verification model comprises at least one performance verification sub-model, each performance verification sub-model is constructed based on one circuit module in the chip to be verified; each performance verification sub-model is written based on a hardware verification language; and the performance of the chip to be verified is verified based on the chip performance verification model. The present application is suitable for chip performance verification.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method, apparatus, electronic device, and storage medium for verifying the performance of a chip. Background Technology

[0002] The processor is the core component of a computer, and its performance directly affects the computer's overall performance. To ensure that a processor design achieves its expected performance specifications, it is generally necessary to perform performance verification on the designed processor.

[0003] In related technologies, most processors to be verified are modeled using C++ and run on the GEM5 platform to perform performance verification. However, C++ is a software programming language, while processor design typically uses hardware description languages. Hardware description languages ​​and software programming languages ​​have many irreparable differences in detail, leading to significant discrepancies between the model's hierarchical partitioning, pipeline design, and specific implementation and the processor's pre-silicon design. These differences can cause discrepancies in execution order and / or execution results between the model and the design, resulting in significant deviations in performance verification. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a chip performance verification method, apparatus, electronic device, and storage medium, which can effectively improve the accuracy of chip performance verification.

[0005] In a first aspect, embodiments of the present invention provide a chip performance verification method, comprising: obtaining a chip performance verification model of a chip to be verified, the chip performance verification model including at least one performance verification sub-model, wherein each performance verification sub-model is constructed based on a circuit module in the chip to be verified; each performance verification sub-model is written in a hardware verification language; and performing performance verification on the chip to be verified based on the chip performance verification model.

[0006] In one embodiment, obtaining the chip performance verification model of the chip to be verified includes: obtaining the design file of the chip to be verified, the design file including the design code of at least one circuit module in the chip to be verified; selecting one or more first circuit modules from the at least one circuit module according to the performance verification requirements; constructing a corresponding performance verification sub-model for each first circuit module according to the design code of each first circuit module in the design file, wherein each performance verification sub-model carries initial timing information; and constructing the chip performance verification model of the chip to be verified based on each performance verification sub-model.

[0007] In one implementation, constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models includes: determining the interaction relationship between each of the first circuit modules according to the design code of each of the first circuit modules in the design file; establishing a communication path between each of the performance verification sub-models according to the interaction relationship between each of the first circuit modules, wherein the communication path is established based on a preset communication protocol; and constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models and the communication path.

[0008] In one implementation, after obtaining the design file of the chip to be verified and before constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models, the method further includes: selecting one or more second circuit modules from the at least one circuit module according to performance verification requirements, wherein each second circuit module is used to interact with at least one first circuit module; constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models includes: constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models and each of the second circuit modules.

[0009] In one implementation, constructing the chip performance verification model of the chip to be verified based on each performance verification sub-model and each second circuit module includes: determining the interaction relationship between each first circuit module according to the design code of each first circuit module in the design file; establishing a communication path between each performance verification sub-model according to the interaction relationship between each first circuit module, the communication path being established based on a preset communication protocol; searching for a circuit module that has an interaction relationship with any second circuit module from each first circuit module to obtain at least one first target module; generating a signal format conversion interface for each performance verification sub-model of the first target module, so that the performance verification sub-model of each first target module can interact with the corresponding second circuit module through its respective signal format conversion interface; and constructing the chip performance verification model of the chip to be verified based on each performance verification sub-model, the communication path, the signal format conversion interface, and each second circuit module.

[0010] In one implementation, the step of constructing a corresponding performance verification sub-model for each of the first circuit modules based on the design code of each of the first circuit modules in the design file includes: determining the signal timing of each of the first circuit modules based on the design code and interface vector file of each of the first circuit modules; and constructing a performance verification sub-model for each of the first circuit modules based on the classes in the hardware verification language according to the signal timing of each of the first circuit modules, wherein the initial timing information corresponds to the signal timing of each of the first circuit modules.

[0011] In one implementation, after determining the signal timing of each first circuit module based on its design code and interface vector file, and before constructing a performance verification sub-model for each first circuit module based on the signal timing of each first circuit module and classes in the hardware verification language, the method further includes: for each first circuit module, determining whether the timing relationship between its input and output signals meets preset conditions; the step of constructing a performance verification sub-model for each first circuit module based on the signal timing of each first circuit module and classes in the hardware verification language includes: simplifying the first circuit modules whose timing relationship meets the preset conditions to obtain a first simplified module; and constructing the performance verification sub-model for the first simplified module based on classes in the hardware verification language.

[0012] In one embodiment, after constructing corresponding performance verification sub-models for each of the first circuit modules based on the design code of each first circuit module in the design file, the method further includes: obtaining simulation delay information for each of the first circuit modules; updating the initial timing information of the performance verification sub-models corresponding to each of the first circuit modules using the simulation delay information to obtain optimized timing information; and updating the chip performance verification model of the chip to be verified based on each performance verification sub-model carrying the optimized timing information.

[0013] In one embodiment, the performance verification of the chip to be verified based on the chip performance verification model includes: providing a stimulus signal to the chip performance verification model; collecting the output signal of the chip performance verification model in response to the stimulus signal; and determining whether the chip to be verified has passed the performance verification by detecting whether the timing relationship between the output signal and the stimulus signal meets a preset expectation.

[0014] In one embodiment, the chip to be verified includes a general-purpose graphics processing unit (GPU) chip; the GPU chip includes a task control module and an instruction processing module; the instruction processing module includes multiple processing sub-modules; the at least one performance verification sub-model includes a task control verification sub-model of the task control module and an instruction processing verification sub-model of the instruction processing module; wherein, the instruction processing verification sub-model includes multiple model units, each model unit corresponding to one of the processing sub-modules; the task control verification sub-model is used to receive a computation task and split the computation task into multiple sub-tasks and send them to the multiple model units of the instruction processing verification sub-model; the instruction processing verification sub-module is used to compute the multiple sub-tasks in parallel through the multiple model units.

[0015] Secondly, embodiments of the present invention also provide a chip performance verification apparatus, comprising: an acquisition unit for acquiring a chip performance verification model of a chip to be verified, the chip performance verification model including at least one performance verification sub-model, wherein each performance verification sub-model is constructed based on a circuit module in the chip to be verified; each performance verification sub-model is written based on a hardware verification language; and a verification unit for performing performance verification on the chip to be verified based on the chip performance verification model.

[0016] In one embodiment, the acquisition unit includes: a first acquisition module, configured to acquire the design file of the chip to be verified, the design file including design code of at least one circuit module in the chip to be verified; a first selection module, configured to select one or more first circuit modules from the at least one circuit module according to performance verification requirements; a first construction module, configured to construct a corresponding performance verification sub-model for each first circuit module according to the design code of each first circuit module in the design file, wherein each performance verification sub-model carries initial timing information; and a second construction module, configured to construct the chip performance verification model of the chip to be verified based on each performance verification sub-model.

[0017] In one implementation, the second construction module is specifically used for: determining the interaction relationship between each of the first circuit modules according to the design code of each of the first circuit modules in the design file; establishing a communication path between each of the performance verification sub-models according to the interaction relationship between each of the first circuit modules, wherein the communication path is established based on a preset communication protocol; and constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models and the communication path.

[0018] In one embodiment, the acquisition unit further includes: a second selection module, configured to select one or more second circuit modules from the at least one circuit module according to performance verification requirements after acquiring the design file of the chip to be verified and before constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models, wherein each second circuit module is used to interact with at least one first circuit module; and a second construction module, specifically configured to construct the chip performance verification model of the chip to be verified based on each of the performance verification sub-models and each of the second circuit modules.

[0019] In one embodiment, the second construction module includes: a first determining submodule, configured to determine the interaction relationship between each first circuit module based on the design code of each first circuit module in the design file; an establishing submodule, configured to establish a communication path between each performance verification sub-model based on the interaction relationship between each first circuit module, the communication path being established based on a preset communication protocol; a searching submodule, configured to search for a circuit module that has an interaction relationship with any second circuit module from each first circuit module, to obtain at least one first target module; a generating submodule, configured to generate a signal format conversion interface for each performance verification sub-model of the first target module, so that the performance verification sub-model of each first target module interacts with the corresponding second circuit module through its respective signal format conversion interface; and a first construction submodule, configured to construct the chip performance verification model of the chip to be verified based on each performance verification sub-model, the communication path, the signal format conversion interface, and each second circuit module.

[0020] In one implementation, the first construction module includes: a second determining submodule, configured to determine the signal timing of each first circuit module based on the design code and interface vector file of each first circuit module; and a first construction submodule, configured to construct a performance verification sub-model for each first circuit module based on the signal timing of each first circuit module and on classes in the hardware verification language, wherein the initial timing information corresponds to the signal timing of each first circuit module.

[0021] In one embodiment, the first construction module further includes: a third determining submodule, configured to, after determining the signal timing of each first circuit module based on the design code and interface vector file of each first circuit module, and before constructing a performance verification submodel for each first circuit module based on the signal timing of each first circuit module and the classes in the hardware verification language, determine whether the timing relationship between the input and output signals of each first circuit module meets preset conditions; the first construction submodule is specifically configured to: simplify the first circuit modules whose timing relationship meets the preset conditions to obtain a first simplified module; and construct the performance verification submodel for the first simplified module based on the classes in the hardware verification language.

[0022] In one embodiment, the acquisition unit further includes: a second acquisition module, configured to acquire simulation delay information of each first circuit module after constructing a corresponding performance verification sub-model for each first circuit module according to the design code of each first circuit module in the design file; a first update module, configured to update the initial timing information of the performance verification sub-model corresponding to each first circuit module using the simulation delay information to obtain optimized timing information; and a second update module, configured to update the chip performance verification model of the chip to be verified based on each performance verification sub-model carrying the optimized timing information.

[0023] In one embodiment, the verification unit includes: a providing module for providing an excitation signal to the chip performance verification model; a collecting module for collecting the output signal of the chip performance verification model in response to the excitation signal; and a determining module for determining whether the chip to be verified has passed performance verification by detecting whether the timing relationship between the output signal and the excitation signal meets a preset expectation.

[0024] In one embodiment, the chip to be verified includes a general-purpose graphics processing unit (GPU) chip; the GPU chip includes a task control module and an instruction processing module; the instruction processing module includes multiple processing sub-modules; the at least one performance verification sub-model includes a task control verification sub-model of the task control module and an instruction processing verification sub-model of the instruction processing module; wherein, the instruction processing verification sub-model includes multiple model units, each model unit corresponding to one of the processing sub-modules; the task control verification sub-model is used to receive a computation task and split the computation task into multiple sub-tasks and send them to the multiple model units of the instruction processing verification sub-model; the instruction processing verification sub-module is used to compute the multiple sub-tasks in parallel through the multiple model units.

[0025] Thirdly, embodiments of the present invention also provide an electronic device, the electronic device comprising: a processor and a memory, the processor being electrically connected to the memory; the memory being used to store executable program code; the processor running a program corresponding to the executable program code by reading the executable program code stored in the memory, thereby implementing any chip performance verification method provided by embodiments of the present invention.

[0026] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the performance verification method for any chip provided in the embodiments of the present invention.

[0027] The chip performance verification method, apparatus, electronic device, and storage medium provided in the embodiments of the present invention can obtain a chip performance verification model of a chip to be verified. The chip performance verification model includes at least one performance verification sub-model, wherein each performance verification sub-model is constructed based on a circuit module of the chip to be verified; each performance verification sub-model is written in a hardware verification language. Since the performance verification sub-models in the chip performance verification model are written in a hardware verification language, and the hardware verification language can be seamlessly connected to the chip's RTL (Register Transfer Level) design code, it is convenient to port key functional logic from the RTL, thereby enabling more accurate reproduction of the same task execution order and results as the chip logic design code. Therefore, it can effectively improve the accuracy of chip performance verification. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A flowchart of a chip performance verification method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a chip performance verification model for the chip to be verified in an embodiment of the present invention. Figure 3 This is another schematic diagram of the chip performance verification model of the chip to be verified in an embodiment of the present invention; Figure 4 A detailed flowchart of a chip performance verification method provided for embodiments of the present invention; Figure 5 A schematic diagram of a chip performance verification device provided in an embodiment of the present invention; Figure 6 A schematic diagram of an electronic device provided as an embodiment of the present invention. Detailed Implementation

[0030] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0031] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0032] In a first aspect, embodiments of the present invention provide a chip performance verification method that can effectively improve the accuracy of chip performance verification.

[0033] like Figure 1 As shown, an embodiment of the present invention provides a chip performance verification method, including: S11, Obtain the chip performance verification model of the chip to be verified. The chip performance verification model includes at least one performance verification sub-model, wherein each performance verification sub-model is constructed based on a circuit module in the chip to be verified; each performance verification sub-model is written based on a hardware verification language. Chip performance refers to a chip's ability and efficiency in performing specific tasks, which can be reflected in metrics such as frequency, throughput, and latency. Chip performance verification models are established to verify chip performance. Chip performance verification is generally performed after the chip's functional verification has been completed. Unlike functional verification, which focuses on the correctness of the logical relationship between input and output signals, performance verification primarily focuses on the timing relationship between the chip's input and output signals.

[0034] In embodiments of the present invention, the chip to be verified may include one or more circuit modules, and correspondingly, the chip performance verification model may include one or more performance verification sub-models established for these circuit modules. Here, a circuit module can refer to a circuit design with relatively independent functions, and can be defined as needed. The size of a circuit module can be large or small, and the embodiments of the present invention do not limit this.

[0035] The performance verification sub-model can be written using a hardware programming language, such as System Verilog (SV). Hardware programming languages ​​are not only compatible with the circuit's RTL design code, facilitating the transfer of key functional logic from the circuit's RTL design code and accurately reproducing the same task execution order and results as the chip logic design code, but they also provide object-oriented programming capabilities. Therefore, they can effectively improve simulation efficiency while ensuring simulation accuracy.

[0036] S12, Based on the chip performance verification model, the performance of the chip to be verified is verified.

[0037] After obtaining the chip performance verification model, this step can be used to perform performance verification on the chip to be verified based on the chip performance verification model, thereby evaluating whether the performance of the chip to be verified meets the design expectations.

[0038] It should be noted that, in the embodiments of the present invention, the performance verification of the chip to be verified can be either a system-level performance verification of the entire chip or a module-level performance verification of a part of the circuit in the chip to be verified. The embodiments of the present invention do not limit this.

[0039] The chip performance verification method provided in the embodiments of the present invention can obtain a chip performance verification model of the chip to be verified. The chip performance verification model includes at least one performance verification sub-model, wherein each performance verification sub-model is constructed based on a circuit module of the chip to be verified; each performance verification sub-model is written in a hardware verification language. Since the performance verification sub-models in the chip performance verification model are written in a hardware verification language, and the hardware verification language can be seamlessly connected with the chip's RTL design code, it is convenient to port key functional logic from the RTL, thereby enabling more accurate reproduction of the same task execution order and results as the chip logic design code, thus effectively improving the accuracy of chip performance verification.

[0040] In embodiments of the present invention, the chip to be verified may include various types of chips, such as central processing unit chips, graphics processing unit chips, etc. For example, Figure 2As shown, in one embodiment, the chip to be verified may include a general-purpose graphics processing unit (GPGPU) chip; the GPGPU chip includes a task control module and an instruction processing module; the instruction processing module includes multiple processing sub-modules. Based on this, at least one performance verification sub-model may include a task control verification sub-model of the task control module and an instruction processing verification sub-model of the instruction processing module; wherein, the instruction processing verification sub-model includes multiple model units, each model unit corresponding to a processing sub-module; wherein, the task control verification sub-model can be used to receive computation tasks and split the computation tasks into multiple sub-tasks and send them to the multiple model units of the instruction processing verification sub-model; the instruction processing verification sub-module can be used to compute the multiple sub-tasks in parallel through the multiple model units. In this way, the GPGPU can be modeled using the task control verification sub-model and the instruction processing verification sub-model, thereby enabling performance verification of the GPGPU.

[0041] Specifically, in step S11, the chip performance verification model of the chip to be verified can be obtained in various ways. For example, a pre-established chip performance verification model can be loaded, or a chip performance verification model can be generated based on some known information.

[0042] For example, in one embodiment of the present invention, step S11 of obtaining the chip performance verification model of the chip to be verified may include: obtaining the design file of the chip to be verified, the design file including the design code of at least one circuit module in the chip to be verified; selecting one or more first circuit modules from the at least one circuit module according to the performance verification requirements; constructing a corresponding performance verification sub-model for each first circuit module according to the design code of each first circuit module in the design file, wherein each performance verification sub-model carries initial timing information; and constructing the chip performance verification model of the chip to be verified based on each performance verification sub-model.

[0043] In this embodiment, a chip performance verification model can be generated based on the design file of the chip to be verified. Specifically, the design file of the chip to be verified may include the design code of one or more circuit modules. According to the performance verification requirements, one or more circuit modules can be selected as the first circuit module. For example, the circuit module related to this verification can be selected as the first circuit module, and a corresponding performance verification sub-model can be built for each first circuit module. The first circuit module can correspond one-to-one with the performance verification sub-model.

[0044] In one embodiment of the present invention, constructing a corresponding performance verification sub-model for each of the first circuit modules based on the design code of each of the first circuit modules in the design file may include: determining the signal timing of each of the first circuit modules based on the design code and interface vector (vec) file of each of the first circuit modules; constructing a performance verification sub-model for each of the first circuit modules based on the classes in the hardware verification language according to the signal timing of each of the first circuit modules, wherein the initial timing information corresponds to the signal timing of each of the first circuit modules.

[0045] In this embodiment, the performance verification sub-model of the first circuit module can carry initial timing information. This initial timing information can be determined based on the interface vector files accumulated in the previous chip design. The interface vector files record the transition times (i.e., signal timing) of signals at each interface within or between circuit modules of the chip. The difference between the transition times can be used to estimate the transmission delay of signals between the corresponding interfaces, thus obtaining the corresponding initial timing information. The initial timing information estimated using the interface vector files can be roughly consistent with the timing information of the first circuit module. Furthermore, since the hardware verification language includes classes, object-oriented programming can be implemented based on classes, dynamically creating and loading program objects, thereby effectively improving the simulation's running efficiency.

[0046] Further, in one embodiment of the present invention, after determining the signal timing of each first circuit module based on the design code and interface vector file of each first circuit module, and before constructing a performance verification sub-model for each first circuit module based on the classes in the hardware verification language, the chip performance verification method provided by the embodiment of the present invention may further include: for each first circuit module, determining whether the timing relationship between the input signal and the output signal of the first circuit module meets preset conditions. Based on this, constructing a performance verification sub-model for each first circuit module based on the classes in the hardware verification language may specifically include: simplifying the first circuit modules whose timing relationship meets the preset conditions to obtain a first simplified module; and constructing the performance verification sub-model for the first simplified module based on the classes in the hardware verification language.

[0047] In this embodiment, each first circuit module may have one or more input signals and one or more output signals. Different combinations of input signals can form different application scenarios. If the timing relationship between the input and output signals of the first circuit module is determined under various application scenarios, then it can be determined that the timing relationship meets the preset conditions. For example, in one example, when the input signal INPUT of the first circuit module A1 is high, the output signal OUTPUT is delayed by 20 nanoseconds; when the input signal INPUT is low, the output signal OUTPUT is delayed by 30 nanoseconds. It can be determined that the timing relationship between the input and output signals of the first circuit module A1 meets the preset conditions. The first circuit module A1 can be simplified to obtain a first simplified module. The first simplified module can define the timing relationship between the input signal INPUT and the output signal OUTPUT from a higher level of abstraction without constructing specific circuit details. Therefore, the simulation speed can be further accelerated.

[0048] In the above embodiments, each performance verification sub-model carries initial timing information. However, the embodiments of the present invention are not limited to this. In other embodiments of the present invention, the initial timing information can be optimized to make the timing information in the performance verification sub-model more accurate.

[0049] For example, in one embodiment of the present invention, after constructing corresponding performance verification sub-models for each of the first circuit modules according to the design code of each first circuit module in the design file, the chip performance verification method provided by the embodiment of the present invention may further include: obtaining simulation delay information of each first circuit module; updating the initial timing information of the performance verification sub-model corresponding to each first circuit module using the simulation delay information to obtain optimized timing information; and constructing the chip performance verification model of the chip to be verified based on each performance verification sub-model carrying the optimized timing information. In this embodiment, the simulation delay information of the first circuit module is the delay characteristic exhibited by the circuit when the first circuit module is dynamically simulated. Compared with the initial timing information calculated based on the interface vector file, it can more accurately reflect the real delay performance of the first circuit module. Therefore, updating the chip performance verification model based on each performance verification sub-model carrying the optimized timing information can make the chip performance verification more accurate.

[0050] In embodiments of the present invention, after constructing corresponding performance verification sub-models for each first circuit module, the chip performance verification model of the chip to be verified can be constructed based on each performance verification sub-model.

[0051] Specifically, in one implementation, constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models may include: determining the interaction relationship between each of the first circuit modules according to the design code of each of the first circuit modules in the design file; establishing a communication path between each of the performance verification sub-models according to the interaction relationship between each of the first circuit modules, wherein the communication path is established based on a preset communication protocol; and constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models and the communication path.

[0052] In other words, after constructing the performance verification sub-models, communication paths can be further established between them, enabling information exchange for performance verification. For example, the design code of each first circuit module can be used to determine which signals each first circuit module sent to or received from other first circuit modules, thus establishing communication paths between the performance verification sub-models corresponding to these first circuit modules. These communication paths can be established based on a preset communication protocol, such as Transaction Level Modeling (TLM) in one example. TLM is a communication standard for system modeling that simplifies communication between modules and improves the efficiency of hardware and software collaborative development through abstracted transaction operations. After constructing the performance verification sub-models and communication paths, a chip performance verification model for the chip to be verified can be constructed based on these performance verification sub-models and communication paths.

[0053] In the foregoing embodiments, the chip performance verification model may include one or more performance verification sub-models, but the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, in addition to the performance verification sub-models, the chip performance verification model may also include a circuit module. That is to say, in the embodiments of the present invention, the performance verification sub-module can form a chip performance verification model together with the circuit module to complete the performance verification of the chip to be verified. The performance verification sub-module can be written based on a hardware verification language (e.g., System Verilog), and the circuit module can be written based on a hardware description language (e.g., Verilog). The hardware verification language can be compatible with the hardware description language.

[0054] Specifically, in one embodiment, after obtaining the design files of the chip to be verified, and before constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models, the chip performance verification method provided in the embodiments of the present invention may further include: selecting one or more second circuit modules from the at least one circuit module according to performance verification requirements, wherein each second circuit module is used to interact with at least one first circuit module. Based on this, constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models may specifically include: constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models and each of the second circuit modules.

[0055] In this embodiment, one or more second circuit modules can be selected from at least one circuit module in the design file of the chip to be verified, wherein each second circuit module is used to interact with one or more first circuit modules. Unlike the first circuit modules, in this embodiment, a corresponding performance verification sub-model is not constructed for the second circuit modules. Instead, the chip performance verification model of the chip to be verified is constructed based on the performance verification sub-models corresponding to the first circuit modules and the second circuit modules. Thus, the chip performance verification model can include both the performance verification sub-models corresponding to the first circuit modules and the second circuit modules, and the performance verification sub-models can interact with the second circuit modules.

[0056] For example, in one implementation, constructing the chip performance verification model of the chip to be verified based on each performance verification sub-model and each second circuit module may include: determining the interaction relationship between each first circuit module according to the design code of each first circuit module in the design file; establishing a communication path between each performance verification sub-model according to the interaction relationship between each first circuit module, the communication path being established based on a preset communication protocol; searching for a circuit module that has an interaction relationship with any second circuit module from each first circuit module to obtain at least one first target module; generating a signal format conversion interface for each performance verification sub-model of the first target module, so that the performance verification sub-model of each first target module interacts with the corresponding second circuit module through its respective signal format conversion interface; and constructing the chip performance verification model of the chip to be verified based on each performance verification sub-model, the communication path, the signal format conversion interface, and each second circuit module.

[0057] For example, such as Figure 3As shown, in one example, the chip to be verified may include three first circuit modules (A, B, and C) and two second circuit modules (D and F). First circuit module A interacts with first circuit modules B and C, first circuit module B interacts with second circuit module D, and first circuit module C interacts with second circuit module F. Since first circuit module B interacts with second circuit module D, it is a first target module. Similarly, since first circuit module C interacts with second circuit module F, it is also a first target module. Furthermore, signal format conversion interfaces can be generated for the performance verification sub-models B1 and C1 of first target modules B and C, respectively. This allows the performance verification sub-models B1 and C1 of first target modules B and C to interact with their corresponding second circuit modules D and F through these signal format conversion interfaces. Simultaneously, the performance verification sub-models A1, B1, and C1 are all models and can directly interact with each other.

[0058] Since a signal format conversion interface can be generated for the performance verification sub-model of the first target module, the chip performance verification model can be constructed freely by using the design code of the circuit module or by building a performance verification sub-model for the circuit module, depending on the needs of performance verification.

[0059] For example, in one instance, the signal format conversion interface could exist as a shell, with each shell wrapping a corresponding performance verification sub-model.

[0060] Further, after obtaining the chip performance verification model in step S11, performance verification of the chip to be verified can be performed in step S12 based on the chip performance verification model. Specifically, in one embodiment of the present invention, performance verification of the chip to be verified based on the chip performance verification model may include: providing an excitation signal to the chip performance verification model; collecting the output signal of the chip performance verification model in response to the excitation signal; and determining whether the chip to be verified passes the performance verification by detecting whether the timing relationship between the output signal and the excitation signal meets expectations. For example, the expected performance of the chip to be verified is that the delay between the output signal and the excitation signal (i.e., the input signal) is less than or equal to 50 nanoseconds. If the delay between the output signal and the excitation signal is collected as 35 nanoseconds during verification, it meets expectations, and the chip to be verified is determined to have passed the performance verification; if the delay between the output signal and the excitation signal is collected as 62 nanoseconds during verification, it does not meet expectations, and the chip to be verified fails the performance verification.

[0061] The performance verification method for the chip provided by the present invention will be described in detail below through a specific embodiment.

[0062] like Figure 4 As shown, the chip performance verification method provided in the embodiments of the present invention may include: S301. Obtain the design file of the chip to be verified, which includes the design code of at least one circuit module in the chip to be verified. S302. Based on performance verification requirements, select one or more first circuit modules from at least one circuit module; S303. Determine the signal timing of each first circuit module based on the design code and interface vector file of each first circuit module; S304. Based on the signal timing of each first circuit module, and using classes in the hardware verification language, construct performance verification sub-models for each first circuit module, wherein each performance verification sub-model carries initial timing information. Specifically, for each of the first circuit modules, the timing relationship between the input and output signals of the first circuit module can be determined to see if it meets a preset condition; the first circuit modules whose timing relationship meets the preset condition are simplified to obtain a first simplified module; and the performance verification sub-model is constructed for the first simplified module based on the classes in the hardware verification language.

[0063] S305. Based on performance verification requirements, select one or more second circuit modules from at least one circuit module, wherein each second circuit module is used to interact with at least one first circuit module; S306. Determine the interaction relationship between each first circuit module based on the design code of each first circuit module in the design file; S307. Based on the interaction relationship between each first circuit module, establish a communication path between each performance verification sub-model, wherein the communication path is established based on a preset communication protocol; S308. Find the circuit module that has an interaction relationship with any second circuit module from each first circuit module to obtain at least one first target module; S309. Generate signal format conversion interfaces for the performance verification sub-models of each first target module, so that the performance verification sub-models of each first target module can interact with the corresponding second circuit module through their respective signal format conversion interfaces. S310. Based on each performance verification sub-model, communication path, signal format conversion interface and each second circuit module, construct the chip performance verification model of the chip to be verified. S311. Obtain the simulation delay information of each first circuit module; S312. Update the initial timing information of the performance verification sub-model corresponding to each first circuit module using the simulation delay information to obtain optimized timing information; S313. Based on each performance verification sub-model carrying optimized timing information, update the chip performance verification model of the chip to be verified. S314, Provide stimulus signals to the chip performance verification model; S315. Collect the output signal of the chip performance verification model in response to the excitation signal; S316. By detecting whether the timing relationship between the output signal and the excitation signal meets expectations, determine whether the chip to be verified has passed the performance verification.

[0064] Secondly, embodiments of the present invention provide a chip performance verification device that can effectively improve the accuracy of chip performance verification.

[0065] like Figure 5 As shown, embodiments of the present invention also provide a chip performance verification apparatus, comprising: The acquisition unit 41 is used to acquire the chip performance verification model of the chip to be verified. The chip performance verification model includes at least one performance verification sub-model, wherein each performance verification sub-model is constructed based on a circuit module in the chip to be verified; each performance verification sub-model is written based on a hardware verification language. Verification unit 42 is used to perform performance verification on the chip to be verified based on the chip performance verification model.

[0066] The chip performance verification apparatus provided in the embodiments of the present invention can acquire a chip performance verification model of a chip to be verified. The chip performance verification model includes at least one performance verification sub-model, wherein each performance verification sub-model is constructed based on a circuit module of the chip to be verified; each performance verification sub-model is written in a hardware verification language. Since the performance verification sub-models in the chip performance verification model are written in a hardware verification language, and the hardware verification language can be seamlessly connected to the chip's RTL design code, it is convenient to port key functional logic from the RTL, thereby enabling more accurate reproduction of the same task execution order and results as the chip logic design code. Therefore, it can effectively improve the accuracy of chip performance verification.

[0067] In one embodiment, the acquisition unit 41 includes: The first acquisition module is used to acquire the design file of the chip to be verified, wherein the design file includes the design code of at least one circuit module in the chip to be verified. The first selection module is used to select one or more first circuit modules from the at least one circuit module according to performance verification requirements; The first construction module is used to construct a corresponding performance verification sub-model for each of the first circuit modules according to the design code of each of the first circuit modules in the design file, wherein each performance verification sub-model carries initial timing information; The second construction module is used to construct the chip performance verification model of the chip to be verified based on each of the performance verification sub-models.

[0068] In one implementation, the second building module is specifically used for: Based on the design code of each first circuit module in the design file, determine the interaction relationship between each first circuit module; Based on the interaction relationship between each of the first circuit modules, a communication path is established between each of the performance verification sub-models, and the communication path is established based on a preset communication protocol; Based on the performance verification sub-models and the communication path, the chip performance verification model of the chip to be verified is constructed.

[0069] In one embodiment, the acquisition unit 41 further includes: The second selection module is used to select one or more second circuit modules from the at least one circuit module according to the performance verification requirements after obtaining the design file of the chip to be verified and before constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models, wherein each second circuit module is used to interact with at least one first circuit module. The second construction module is specifically used to construct the chip performance verification model of the chip to be verified based on each of the performance verification sub-models and each of the second circuit modules.

[0070] In one implementation, the second building module includes: The first determining submodule is used to determine the interaction relationship between each first circuit module based on the design code of each first circuit module in the design file. A submodule is established to establish a communication path between each performance verification sub-model based on the interaction relationship between each of the first circuit modules. The communication path is established based on a preset communication protocol. A search submodule is used to search for a circuit module that has an interaction relationship with any of the second circuit modules from each of the first circuit modules, so as to obtain at least one first target module; A generation submodule is used to generate a signal format conversion interface for the performance verification sub-model of each first target module, so that the performance verification sub-model of each first target module can interact with the corresponding second circuit module through its respective signal format conversion interface; The first construction submodule is used to construct the chip performance verification model of the chip to be verified based on each of the performance verification sub-models, the communication path, the signal format conversion interface and each of the second circuit modules.

[0071] In one implementation, the first building module includes: The second determining submodule is used to determine the signal timing of each of the first circuit modules based on the design code and interface vector file of each of the first circuit modules. The first construction submodule is used to construct a performance verification sub-model for each of the first circuit modules based on the signal timing of each of the first circuit modules and the classes in the hardware verification language. The initial timing information corresponds to the signal timing of each of the first circuit modules.

[0072] In one embodiment, the first construction module further includes: a third determining submodule, configured to, after determining the signal timing of each first circuit module based on the design code and interface vector file of each first circuit module, and before constructing a performance verification submodel for each first circuit module based on the class in the hardware verification language, determine whether the timing relationship between the input signal and the output signal of each first circuit module meets preset conditions; The first construction submodule is specifically used for: The first circuit module whose timing relationship meets the preset conditions is simplified to obtain a first simplified module; Based on the classes in the hardware verification language, the performance verification sub-model is constructed for the first simplified module.

[0073] In one embodiment, the acquiring unit 41 further includes: The second acquisition module is used to acquire the simulation delay information of each first circuit module after constructing a corresponding performance verification sub-model for each first circuit module according to the design code of each first circuit module in the design file. The first update module is used to update the initial timing information of the performance verification sub-model corresponding to each of the first circuit modules using the simulation delay information, so as to obtain optimized timing information; The second update module is used to update the chip performance verification model of the chip to be verified based on each performance verification sub-model carrying the optimized timing information.

[0074] In one embodiment, the verification unit 42 includes: A module is provided for providing excitation signals to the chip performance verification model; The collection module is used to collect the output signal of the chip performance verification model in response to the excitation signal; The determination module is used to determine whether the chip to be verified has passed performance verification by detecting whether the timing relationship between the output signal and the excitation signal meets the preset expectation.

[0075] In one embodiment, the chip to be verified includes a general-purpose graphics processing unit (GPU) chip; the GPU chip includes a task control module and an instruction processing module; the instruction processing module includes multiple processing sub-modules; the at least one performance verification sub-model includes a task control verification sub-model of the task control module and an instruction processing verification sub-model of the instruction processing module; wherein, the instruction processing verification sub-model includes multiple model units, each model unit corresponding to one of the processing sub-modules; the task control verification sub-model is used to receive a computation task and split the computation task into multiple sub-tasks and send them to the multiple model units of the instruction processing verification sub-model; the instruction processing verification sub-module is used to compute the multiple sub-tasks in parallel through the multiple model units.

[0076] Thirdly, embodiments of the present invention also provide an electronic device that can effectively improve the accuracy of chip performance verification.

[0077] like Figure 6 As shown, the electronic device provided in the embodiments of the present invention may include: a processor 71 and a memory 72, wherein the processor 71 and the memory 72 are electrically connected; the memory 72 is used to store executable program code; the processor 71 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 72, so as to implement the performance verification method of any chip provided in the foregoing embodiments.

[0078] The specific execution process of the above steps by the processor 71, as well as the steps further executed by the processor 71 by running executable program code, can be found in the description of the foregoing embodiments, and will not be repeated here.

[0079] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement the performance verification method for any chip provided in the foregoing embodiments, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.

[0080] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0081] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0082] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0083] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0084] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0085] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for verifying the performance of a chip, characterized in that, include: Obtain a chip performance verification model for the chip to be verified, the chip performance verification model including at least one performance verification sub-model, wherein each performance verification sub-model is constructed based on a circuit module in the chip to be verified; each performance verification sub-model is written based on a hardware verification language; Based on the chip performance verification model, the performance of the chip to be verified is performed.

2. The chip performance verification method according to claim 1, characterized in that, The chip performance verification model for obtaining the chip to be verified includes: Obtain the design file of the chip to be verified, wherein the design file includes the design code of at least one circuit module in the chip to be verified; Based on performance verification requirements, one or more first circuit modules are selected from the at least one circuit module; Based on the design code of each first circuit module in the design file, a corresponding performance verification sub-model is constructed for each first circuit module, wherein each performance verification sub-model carries initial timing information; Based on each of the performance verification sub-models, a chip performance verification model for the chip to be verified is constructed.

3. The chip performance verification method according to claim 2, characterized in that, The process of constructing the chip performance verification model for the chip to be verified based on each of the performance verification sub-models includes: Based on the design code of each first circuit module in the design file, determine the interaction relationship between each first circuit module; Based on the interaction relationship between each of the first circuit modules, a communication path is established between each of the performance verification sub-models, and the communication path is established based on a preset communication protocol; Based on the performance verification sub-models and the communication path, the chip performance verification model of the chip to be verified is constructed.

4. The chip performance verification method according to claim 2, characterized in that, After obtaining the design file of the chip to be verified, and before constructing the chip performance verification model of the chip to be verified based on each of the performance verification sub-models, the method further includes: Based on performance verification requirements, one or more second circuit modules are selected from the at least one circuit module, wherein each second circuit module is used to interact with at least one first circuit module; The process of constructing the chip performance verification model for the chip to be verified based on each of the performance verification sub-models includes: Based on each of the performance verification sub-models and each of the second circuit modules, the chip performance verification model of the chip to be verified is constructed.

5. The chip performance verification method according to claim 4, characterized in that, The construction of the chip performance verification model for the chip to be verified based on each of the performance verification sub-models and each of the second circuit modules includes: Based on the design code of each first circuit module in the design file, determine the interaction relationship between each first circuit module; Based on the interaction relationship between each of the first circuit modules, a communication path is established between each of the performance verification sub-models, and the communication path is established based on a preset communication protocol; Find the circuit module that has an interaction relationship with any of the second circuit modules from each of the first circuit modules to obtain at least one first target module; A signal format conversion interface is generated for each performance verification sub-model of the first target module, so that each performance verification sub-model of the first target module can interact with the corresponding second circuit module through its respective signal format conversion interface; Based on each of the performance verification sub-models, the communication path, the signal format conversion interface, and each of the second circuit modules, the chip performance verification model of the chip to be verified is constructed.

6. The chip performance verification method according to claim 2, characterized in that, The step of constructing a corresponding performance verification sub-model for each of the first circuit modules based on the design code of each of the first circuit modules in the design file includes: Based on the design code and interface vector file of each of the first circuit modules, determine the signal timing of each of the first circuit modules; Based on the signal timing of each of the first circuit modules, and using classes in the hardware verification language, a performance verification sub-model is constructed for each of the first circuit modules, wherein the initial timing information corresponds to the signal timing of each of the first circuit modules.

7. The chip performance verification method according to claim 6, characterized in that, After determining the signal timing of each first circuit module based on its design code and interface vector file, and before constructing a performance verification sub-model for each first circuit module based on the signal timing of each first circuit module and classes in the hardware verification language, the method further includes: For each of the first circuit modules, determine whether the timing relationship between the input signal and the output signal of the first circuit module meets the preset conditions; The step of constructing a performance verification sub-model for each of the first circuit modules based on the signal timing of each of the first circuit modules and on classes in the hardware verification language includes: The first circuit module whose timing relationship meets the preset conditions is simplified to obtain a first simplified module; Based on the classes in the hardware verification language, the performance verification sub-model is constructed for the first simplified module.

8. The chip performance verification method according to any one of claims 2 to 7, characterized in that, After constructing corresponding performance verification sub-models for each of the first circuit modules based on the design code of each first circuit module in the design file, the method further includes: Obtain the simulation delay information of each of the first circuit modules; The initial timing information of the performance verification sub-model corresponding to each of the first circuit modules is updated using the simulation delay information to obtain optimized timing information; Based on each performance verification sub-model carrying the optimized timing information, the chip performance verification model of the chip to be verified is updated.

9. The chip performance verification method according to any one of claims 1 to 7, characterized in that, The performance verification of the chip to be verified based on the chip performance verification model includes: Provide excitation signals to the chip performance verification model; Collect the output signal of the chip performance verification model in response to the excitation signal; By detecting whether the timing relationship between the output signal and the excitation signal meets the preset expectation, it is determined whether the chip to be verified has passed the performance verification.

10. The chip performance verification method according to any one of claims 1 to 7, characterized in that, The chip to be verified includes a general-purpose graphics processor chip; The general-purpose graphics processor chip includes: a task control module and an instruction processing module; the instruction processing module includes multiple processing sub-modules. The at least one performance verification sub-model includes a task control verification sub-model of the task control module and an instruction processing verification sub-model of the instruction processing module; wherein, the instruction processing verification sub-model includes multiple model units, and each model unit corresponds to one of the processing sub-modules; The task control verification sub-model is used to receive a computation task and split the computation task into multiple sub-tasks and send them to multiple model units of the instruction processing verification sub-model. The instruction processing and verification submodule is used to compute the multiple subtasks in parallel using multiple model units.

11. A chip performance verification device, characterized in that, include: An acquisition unit is used to acquire a chip performance verification model of a chip to be verified. The chip performance verification model includes at least one performance verification sub-model, wherein each performance verification sub-model is constructed based on a circuit module in the chip to be verified; each performance verification sub-model is written based on a hardware verification language. The verification unit is used to perform performance verification on the chip to be verified based on the chip performance verification model.

12. An electronic device, characterized in that, The electronic device includes: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the chip performance verification method of any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the performance verification method for the chip according to any one of claims 1 to 10.

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