A method and apparatus for generating a verification use case

Abstract

A verification case generation method, the method comprises: according to the description of the chip and the definition of the function points to be verified on the chip, generating a set of test instructions and the interpretation of each function point through a language model; according to the set of test instructions and the interpretation of each function point, generating the test code corresponding to each function point through a language model, the test code corresponding to each function point corresponds to the combination of one or more of the instruction set; according to the test code corresponding to each function point, generating the first verification case of the chip through a language model. Through the construction of structured knowledge, the details of chip design can be further excavated, and more accurate function coverage effect can be realized. Therefore, the generation efficiency and quality of the verification case can be improved.

Description

Technical Field

[0001] This application relates to the field of chip verification, and in particular to a method and apparatus for generating verification test cases. Background Technology

[0002] In the field of chip design, verification is a crucial step in ensuring chip design quality, involving complex verification processes such as confirming logic and physical design specifications and conducting input / output correspondence testing and analysis. All chip design processes require software functional verification, and the performance of this verification directly impacts whether the chip's performance meets the expected design specifications.

[0003] As chip design complexity increases, the verification space resulting from functional functions and logic combinations expands, leading to a sharp increase in both human and computational costs. Traditional chip functional design verification methods can be categorized into formal solution methods based on Boolean equivalence and black-box optimization methods based on data sampling. Formal solution methods require pre-defining the solution space based on human experience; the time cost increases exponentially with the size of the verification space and demands high-quality solvers. In contrast, while black-box optimization methods can solve directly without mathematical modeling of the verification space, the results are prone to getting trapped in local optima, and the quality of the generated results exhibits a degree of randomness.

[0004] Therefore, there is an urgent need for a more efficient and accurate method for generating verification test cases. Summary of the Invention

[0005] This application provides a method for generating verification test cases, which can improve the efficiency and quality of verification test case generation.

[0006] In a first aspect, this application provides a method for generating verification test cases, the method comprising: generating a set of test instructions and an explanation of each function point based on a description of a chip and a definition of a function point to be verified on the chip, using a language model; generating test code corresponding to each function point based on the set of test instructions and the explanation of each function point, using a language model, wherein the test code corresponding to each function point corresponds to a combination of one or more of the instruction set; and generating a first verification test case for the chip based on the test code corresponding to each function point, using a language model.

[0007] The combination of one or more instructions in the instruction set can be referred to as the function point and instruction combination result. This refers to the pairwise mapping relationship between the function point and its corresponding instruction, indicating the mapping relationship that the function point needs to achieve its specific function through the corresponding instruction combination. The set of test instructions consists of instructions that have not yet been matched with function points. They are related within the same group, that is, they correspond to different specific function sets within the same functional group.

[0008] In this embodiment, firstly, a set of test instructions and an explanation of each function point are obtained through a language model based on the chip description and function point definitions. Then, test code corresponding to each function point is generated through the language model based on the set of test instructions and the explanation of each function point. Finally, the first verification test case of the chip is generated through the language model based on the test code corresponding to each function point. This is equivalent to gradually breaking down the original data information according to a progressive reasoning relationship from explanation to analysis and then to generation, guiding the large model to build high-quality verification test cases. Compared with the prior art, this embodiment, by constructing structured knowledge, can more deeply explore the details of chip design and achieve more accurate functional coverage. This can improve the efficiency and quality of verification test case generation.

[0009] In one possible implementation, the function point to be verified is selected from a plurality of function points that are not covered by the chip's historical verification use cases.

[0010] In one possible implementation, generating test code corresponding to each function point through a language model based on the set of test instructions and the interpretation of each function point includes: generating test code corresponding to each function point through a language model based on the set of test instructions, the interpretation chip of each function point, and the instruction set specification; the set of test instructions is code described in a high-level language, the test code is code described in machine language, and the instruction set specification is used to indicate the conversion rules between code described in a high-level language and code described in machine language.

[0011] In one possible implementation, generating test code corresponding to each function point using a language model based on the set of test instructions and the explanation of each function point includes: generating test code corresponding to each function point and a description of each function point using a language model based on the set of test instructions and the explanation of each function point; generating a first verification test case for the chip using a language model based on the test code corresponding to each function point includes: generating a first verification test case for the chip using a language model based on the test code corresponding to each function point and the description.

[0012] In one possible implementation, the explanation includes a description of the specific variables contained within the function point, while the description is an overall description of the function point. Function point explanation refers to explaining each specific function point within a function group, with a focus on specific details. Function point description refers to representing the overall situation of the function group, with a focus on summarizing the overall situation. Specifically, explanation mainly refers to the description of each specific variable, including inputs and outputs, calculation processes, and data flow processes; description can refer to the overall structure designed to achieve the goals of the overall function.

[0013] In one possible implementation, generating the first verification test case for the chip based on the test code corresponding to each function point using a language model includes: generating the first verification test case for the chip based on the test code corresponding to each function point and indication information using a language model; the indication information is used to indicate the function points covered by the chip's historical verification test cases. The previously covered program information is passed to the generation stage to avoid the language model repeatedly generating identical verification test cases.

[0014] In one possible implementation, generating a first verification test case for the chip based on the test code corresponding to each function point through a language model includes: generating a second verification test case for the chip based on the test code corresponding to each function point through a language model; and generating a first verification test case for the chip based on the test code corresponding to each function point and the error information corresponding to the second verification test case when an error exists in the second verification test case.

[0015] Secondly, this application provides a verification test case generation apparatus, the apparatus comprising:

[0016] An explanation generation module is used to generate a set of test instructions and an explanation of each function point based on the chip description and the definition of the function points to be verified on the chip, using a language model.

[0017] The instruction generation module is used to generate test code corresponding to each function point through a language model based on the set of test instructions and the explanation of each function point. The test code corresponding to each function point corresponds to a combination of one or more of the instructions in the set.

[0018] The verification test case generation module is used to generate the first verification test case for the chip based on the test code corresponding to each of the aforementioned functional points and through a language model.

[0019] In one possible implementation, the function point to be verified is selected from a plurality of function points that are not covered by the chip's historical verification use cases.

[0020] In one possible implementation, the instruction generation module is configured to:

[0021] Based on the set of test instructions, the interpretation chip for each function point, and the instruction set specification, test code corresponding to each function point is generated through a language model; the set of test instructions is code described in a high-level language, the test code is code described in machine language, and the instruction set specification is used to indicate the conversion rules between code described in a high-level language and code described in machine language.

[0022] In one possible implementation, the instruction generation module is configured to:

[0023] Based on the set of test instructions and the explanation of each function point, a language model is used to generate test code corresponding to each function point and a description of each function point.

[0024] The verification test case generation module is used for:

[0025] Based on the test code and description corresponding to each function point, the first verification test case of the chip is generated through a language model.

[0026] In one possible implementation, the explanation includes a description of the specific variables contained in the function point, and the description is a general description of the function point.

[0027] In one possible implementation, the verification test case generation module is used to:

[0028] Based on the test code and instruction information corresponding to each function point, a first verification test case for the chip is generated through a language model; the instruction information is used to indicate the function points that have been covered by the chip's historical verification test cases.

[0029] In one possible implementation, the verification test case generation module is configured to:

[0030] Based on the test code corresponding to each of the aforementioned functional points, a second verification test case for the chip is generated using a language model;

[0031] When an error exists in the second verification test case, a first verification test case for the chip is generated using a language model based on the test code corresponding to each function point and the error information corresponding to the second verification test case.

[0032] Thirdly, this application provides a computing device. The computing device includes at least one processor and at least one memory. The at least one processor and the at least one memory communicate with each other. The at least one processor is used to execute instructions stored in the at least one memory to cause the computing device to perform a method as described in the first aspect or any implementation thereof.

[0033] Fourthly, this application provides a computing device cluster. The computing device cluster includes at least one computing device, and the at least one computing device includes at least one processor and at least one memory. The at least one processor and the at least one memory communicate with each other. The at least one processor is used to execute instructions stored in the at least one memory to cause the computing device or the computing device cluster to perform a method as described in the first aspect or any implementation thereof, or a method as described in the second aspect or any implementation thereof.

[0034] Fifthly, this application provides a computer-readable storage medium storing instructions that instruct a computing device or a cluster of computing devices to perform the method described in the first aspect or any implementation thereof, or the method described in the second aspect or any implementation thereof.

[0035] In a sixth aspect, this application provides a computer program product containing instructions that, when run on a computing device or a cluster of computing devices, causes the computing device or cluster of computing devices to perform the method described in the first aspect or any implementation thereof, or the method described in the second aspect or any implementation thereof.

[0036] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0037] Figure 1 A flowchart illustrating a verification test case generation method provided in an embodiment of this application;

[0038] Figure 2a and Figure 2b A flowchart illustrating a verification test case generation method provided in an embodiment of this application;

[0039] Figure 3 A schematic diagram of the architecture provided in an embodiment of this application;

[0040] Figure 4 A schematic diagram of the architecture provided in an embodiment of this application;

[0041] Figure 5 This is a schematic diagram of an architecture provided in an embodiment of this application. Detailed Implementation

[0042] First, some expressions that may appear in this application will be explained.

[0043] "First" and "second" are used to distinguish different objects or to differentiate different treatments of the same object, rather than to describe a specific order of objects.

[0044] "At least one" means one or more, while "more" means two or more.

[0045] "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone. A and B can be singular or plural.

[0046] The character " / " generally indicates that the objects before and after it are in an "or" relationship. For example, A / B can mean A or B.

[0047] Furthermore, the terms "comprising," "including," and "having" used in the description of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0048] It should be noted that in this application, the terms "exemplary" or "for example" are used to indicate that something is being described or illustrated. Any implementation or design scheme described as "exemplary" or "for example" (such as the embodiments in this application) should not be construed as being more preferred or advantageous than other implementations or design schemes. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0049] In the specification and drawings of this application, the terms "of", "relevant", and "corresponding" may sometimes be used interchangeably. It should be noted that when the distinction is not emphasized, they have the same meaning.

[0050] The embodiments of this application can be applied to the field of chip design, especially in the chip functionality verification stage. Through these embodiments, the efficiency of test case construction can be improved, the testing cycle shortened, and the quality and reliability of chip design enhanced. Simultaneously, the embodiments of this application can also be applied to other fields requiring the generation of a large number of verification test cases, such as software development and hardware logic testing.

[0051] Below is a brief description of some of the terms used in this application.

[0052] Large language models are large-scale neural network models based on deep learning. They are mainly used to understand and generate specific language descriptions. They are usually pre-trained with massive amounts of text data (such as books, web pages, etc.) to learn the grammar, semantics and contextual rules of the language. They also use large-scale computing resources to adjust parameters to optimize language processing capabilities.

[0053] Retrieval-enhanced generation is a technical framework that combines information retrieval and text generation. It aims to improve the accuracy, timeliness, and credibility of content generated by large language models by dynamically introducing external knowledge bases. Its core principle is "first retrieve relevant data, then generate content based on that data," thus overcoming the illusion created by traditional generative models' reliance on internal knowledge.

[0054] Instruction set architecture (ISA) is a core component of a computer system. It defines the set of instructions that a processor can execute and their operating rules, serving as an abstract interface between software and hardware. Its core significance lies in providing a unified programming model for programs and compilers, constraining the specific boundaries of hardware implementation.

[0055] In the field of chip design, verification is a crucial step in ensuring chip design quality, involving complex verification processes such as confirming logic and physical design specifications and conducting input / output correspondence testing and analysis. All chip design processes require software functional verification, and the performance of this verification directly impacts whether the chip's performance meets the expected design specifications.

[0056] As chip design complexity increases, the verification space resulting from functional functions and logic combinations expands, leading to a sharp increase in both human and computational costs. Traditional chip functional design verification methods can be categorized into SAT formal solution methods based on Boolean equivalence and black-box optimization methods based on data sampling. Formal solution methods require pre-defining the solution space based on human experience; the time cost increases exponentially with the size of the verification space and demands high-quality solvers. In contrast, while black-box optimization methods can solve directly without mathematical modeling of the verification space, the results are prone to getting trapped in local optima, and the quality of the generated results exhibits a degree of randomness.

[0057] Therefore, there is an urgent need for a more efficient and accurate method for generating verification test cases.

[0058] This application provides a method for generating verification test cases. The method for generating verification test cases according to this application will be described in detail below with reference to the accompanying drawings.

[0059] Reference Figure 1 , Figure 1This application provides a flowchart illustrating a method for generating verification test cases, as shown in the embodiments below. Figure 1 As shown in the embodiment of this application, a method for generating verification test cases may include steps 201 to 203, which are described in detail below.

[0060] 201. Based on the chip description and the definition of the functional points to be verified on the chip, a set of test instructions and an explanation of each functional point are generated using a language model.

[0061] The chip description can include chip design-related information, such as module design documents. The chip description can describe the overall framework of the chip design, its functionalities, and their corresponding implementation methods, helping the language model understand the basic structure and content of the designed chip.

[0062] Optionally, the chip description can be summarized as an integrated circuit development document centered on modular design. It defines the chip's functional architecture, hardware implementation, and verification process through a systematic framework. Specifically, this includes: the overall framework (dividing core modules such as computing, storage, and communication, and their hierarchical relationships), functional functions (such as CPU instruction execution, GPU graphics processing, and memory data read / write management), implementation methods (such as using hardware description languages ​​to write logic circuits and optimizing placement and routing in physical design), and verification and testing strategies (covering functional simulation, timing analysis, and post-package testing). This type of description provides a multi-dimensional technical context for the language model to analyze the chip's design intent by presenting the chip's hardware resource allocation (such as DSP units and memory capacity), interface protocols (such as the AXI bus), and performance indicators (power consumption, latency).

[0063] In one possible implementation, the chip can be described using natural language.

[0064] Among them, the function point is defined as the meaning of a specific function's function point, corresponding to specific design principles and input / output requirements. Through the definition of the function point, the verification target can be conveyed to the language model.

[0065] Optionally, the definition of a chip function point can be summarized as follows: taking a specific function or module as the core, clearly defining its expected behavior, interface specifications, and verification objectives in the chip design. Specifically, it includes, but is not limited to, the following three meanings:

[0066] Functional meaning: Describe the algorithm logic or hardware behavior of the module (such as the audio encoding and decoding function of the DSP module, the graphics rendering process of the GPU), which must comply with design principles (such as demand-oriented, modular) and reliability constraints (such as anti-interference capability, timing tolerance).

[0067] Input / output requirements: Define signal type (digital / analog), protocol standard (e.g., I2C communication), voltage range (e.g., 3.3V TTL input), etc., which must match the interface specification (e.g., AXI bus timing) and hardware safety requirements (e.g., overcurrent protection pins).

[0068] Verification target mapping: Transform the design into quantifiable test metrics through function points. For example, when verifying the dynamic voltage regulation function of a power management chip, it is necessary to cover the input voltage fluctuation range, output stability threshold, and ensure compliance with low power design principles.

[0069] In one possible implementation, the function point to be verified is selected from a plurality of function points that are not covered by the chip's historical verification test cases. For example, the language model can generate one verification test case in each iteration, but this verification test case cannot completely cover all function points. Therefore, in each iteration, information on function points not covered by historical verification test cases can be selected as input to the language model.

[0070] Step 201 can be the explanation stage, which is the first step in reasoning generation. It is responsible for explaining the correlation information between the chip design document and the target function coverage points. Through natural language understanding technology, the model can understand the information related to the target function in the functional design document and extract the corresponding instruction information and function point explanation content.

[0071] In one possible implementation, the description of the chip and the definition of the functional points to be verified on the chip can be used as the content of the prompt and input into the language model to obtain a set of test instructions and an explanation of each functional point.

[0072] For example, a prompt built based on the chip description and the definition of the functional points to be verified on the chip can be illustrated as follows:

[0073] You are an expert developer of "Instruction Set Architecture Name". In the "Instruction Set Architecture Name" processor, functional coverpoints and its cover-bins are associated with some RISC-V assembly instructions.

[0074] Here is the source code of coverpoint`A_mask`:

[0075] Please explain the source code of coverpoint`cp_dummy_instr_mask`indetail,especially the cover-bin""and other bins,related variables and inputinstructions:

[0076] In one possible implementation, a set of test instructions and an explanation of each function point can be generated using a language model, wherein the explanation includes a description of the specific variables contained in the function point, and the set of test instructions is code described in a high-level language.

[0077] 202. Based on the set of test instructions and the explanation of each function point, generate test code corresponding to each function point through a language model, wherein the test code corresponding to each function point corresponds to a combination of one or more of the instruction set;

[0078] Step 202 can be the analysis stage, where the model can further analyze and interpret the content, determine the relationship between the corresponding specific instructions and function coverage points through comparison and matching, and generate corresponding function point descriptions and combination results.

[0079] In one possible implementation, test code corresponding to each function point can be generated using a language model based on the set of test instructions, the interpretation chip for each function point, and the instruction set specification; the set of test instructions is code described in a high-level language, the test code is code described in machine language, and the instruction set specification is used to indicate the conversion rules between code described in a high-level language and code described in machine language.

[0080] The model can further analyze the relationship between the explanatory content and the corresponding chip instruction set architecture specification document. By comparing and matching, it can determine the relationship between specific instructions and function coverage points, and generate corresponding function point descriptions and combination results.

[0081] The instruction set architecture specification can be a standardized definition of the set of test instructions to be verified, the writing format and the encoding method, which guides the language model to build standardized test cases.

[0082] In this embodiment of the application, by constructing a chip knowledge base, importing the corresponding structured background information requirements, fully mining the logical relationship between chip design documents and corresponding functional designs using a language model, injecting chip domain knowledge into the language model, guiding the language model to transform into a chip design verification scenario identity, and inheriting historical domain knowledge information.

[0083] In one possible implementation, test code corresponding to each function point and a description of each function point can be generated through a language model based on the set of test instructions and the explanation of each function point; and a first verification test case of the chip can be generated through a language model based on the test code corresponding to each function point and the description.

[0084] In one possible implementation, the explanation includes a description of the specific variables contained in the function point, and the description is a general description of the function point.

[0085] In this embodiment, multi-level chip information constructed from natural language, program code, machine instructions, etc., is input into a large language model step by step, thereby defining the standard behavior information in the field of large language model chip design verification.

[0086] 203. Based on the test code corresponding to each of the aforementioned functional points, generate the first verification test case for the chip using a language model.

[0087] Step 203 can be the generation stage, where the model can integrate the relevant descriptions of the functional points to generate corresponding verification test cases.

[0088] In this embodiment, firstly, a set of test instructions and an explanation of each function point are obtained through a language model based on the chip description and function point definitions. Then, test code corresponding to each function point is generated through the language model based on the set of test instructions and the explanation of each function point. Finally, the first verification test case of the chip is generated through the language model based on the test code corresponding to each function point. This is equivalent to gradually breaking down the original data information according to a progressive reasoning relationship from explanation to analysis and then to generation, guiding the large model to build high-quality verification test cases. Compared with the prior art, this embodiment, by constructing structured knowledge, can more deeply explore the details of chip design and achieve more accurate functional coverage. This can improve the efficiency and quality of verification test case generation.

[0089] Reference Figure 2a , Figure 2a This is a flowchart of an embodiment of the present application, which includes an interpretation stage, an analysis stage, and a generation stage. The interpretation stage may correspond to step 201 above, the analysis stage may correspond to step 202 above, and the generation stage may correspond to step 203 above.

[0090] In one possible implementation, a first verification test case for the chip can be generated using a language model based on the test code and instruction information corresponding to each function point; the instruction information is used to indicate the function points that have been covered by the chip's historical verification test cases.

[0091] To enhance the efficiency and quality of verification test case generation, this application proposes a system simulation coverage feedback mechanism. The specific process involves first compiling the generated verification samples into executable files using a compiler, then triggering verification generation via a system simulator. After simulation triggering, the specific coverage of corresponding functional points is collected (including functional coverage rate, covered and uncovered functional points, and corresponding generated test cases). Next, uncovered functional points are passed to the first stage (interpretation stage) as guiding prompts, and historically covered program information is passed to the third stage (generation stage) to avoid the language model repeatedly generating identical verification test cases.

[0092] It should be added that the coverage targets of chip design are usually composed of basic units divided according to functional coverage groups (for example, adders, multipliers and other arithmetic function devices). During the coverage process, a priority strategy can be adopted to guide the generation of verification samples to the targets of lower coverage groups first, based on the specific coverage of each coverage group.

[0093] In one possible implementation, a second verification test case for the chip can be generated using a language model based on the test code corresponding to each function point; if an error exists in the second verification test case, a first verification test case for the chip can be generated using a language model based on the test code corresponding to each function point and the error information corresponding to the second verification test case.

[0094] Optionally, the simulation compiler can be used to determine whether the generated verification code test cases conform to the syntax rules. If they are invalid, the error message will be fed back to the language model, and the language model will be guided to generate valid code.

[0095] Reference Figure 2b , Figure 2b This is a flowchart illustrating the feedback-driven mechanism in an embodiment of this application.

[0096] Reference Figure 3 , Figure 3 This is a schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application, such as... Figure 3 As shown in the embodiment of this application, a data processing apparatus 300 includes:

[0097] The explanation generation module 301 is used to generate a set of test instructions and an explanation of each function point based on the chip description and the definition of the function points to be verified on the chip, using a language model.

[0098] The specific description of the interpretation generation module 301 can be referred to the description of step 201 in the above embodiment, and the similarities will not be repeated.

[0099] The instruction generation module 302 is used to generate test code corresponding to each function point through a language model based on the set of test instructions and the explanation of each function point. The test code corresponding to each function point corresponds to a combination of one or more of the instructions in the set.

[0100] The specific description of the instruction generation module 302 can be referred to the description of step 202 in the above embodiment, and the similarities will not be repeated.

[0101] The verification test case generation module 303 is used to generate the first verification test case of the chip based on the test code corresponding to each of the functional points through a language model.

[0102] The specific description of the verification test case generation module 303 can be found in the description of step 203 in the above embodiment, and the similarities will not be repeated here.

[0103] In one possible implementation, the function point to be verified is selected from a plurality of function points that are not covered by the chip's historical verification use cases.

[0104] In one possible implementation, the instruction generation module is configured to:

[0105] Based on the set of test instructions, the interpretation chip for each function point, and the instruction set specification, test code corresponding to each function point is generated through a language model; the set of test instructions is code described in a high-level language, the test code is code described in machine language, and the instruction set specification is used to indicate the conversion rules between code described in a high-level language and code described in machine language.

[0106] In one possible implementation, the instruction generation module is configured to:

[0107] Based on the set of test instructions and the explanation of each function point, a language model is used to generate test code corresponding to each function point and a description of each function point.

[0108] The verification test case generation module is used for:

[0109] Based on the test code and description corresponding to each function point, the first verification test case of the chip is generated through a language model.

[0110] In one possible implementation, the explanation includes a description of the specific variables contained in the function point, and the description is a general description of the function point.

[0111] In one possible implementation, the verification test case generation module is configured to:

[0112] Based on the test code and instruction information corresponding to each function point, a first verification test case for the chip is generated through a language model; the instruction information is used to indicate the function points that have been covered by the chip's historical verification test cases.

[0113] In one possible implementation, the verification test case generation module is configured to:

[0114] Based on the test code corresponding to each of the aforementioned functional points, a second verification test case for the chip is generated using a language model;

[0115] When an error exists in the second verification test case, a first verification test case for the chip is generated using a language model based on the test code corresponding to each function point and the error information corresponding to the second verification test case.

[0116] It should be noted that the information interaction and implementation process between the modules / units of the above-mentioned device are based on the same concept as the method embodiments of this application, and the resulting technical effects are the same as those of the method embodiments of this application. For details, please refer to the description in the method embodiments shown above in the embodiments of this application, and will not be repeated here.

[0117] Please see Figure 4 , Figure 4 This is a schematic diagram of a computing device provided in an embodiment of this application. Figure 4 As shown, the computing device 400 (which can be used to present the aforementioned cloud management platform) includes: a processor 401, a memory 402, a communication interface 403, and a bus 404. The processor 401, memory 402, and communication interface 403 are coupled via the bus (not shown in the figure). The memory 402 stores instructions. When the instructions in the memory 402 are executed, the computing device 400 executes the verification test case generation method in the above method embodiment.

[0118] The computing device 400 may be one or more integrated circuits configured to implement the methods described above, such as: one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. Furthermore, when the units in the device can be implemented in the form of a processing element scheduler, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor capable of calling programs. Alternatively, these units may be integrated together and implemented as a system-on-a-chip (SOC).

[0119] Processor 401 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0120] Memory 402 can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0121] The memory 402 stores executable program code, and the processor 401 executes the executable program code to implement the functions of the aforementioned transceiver module and scheduling module, thereby implementing the aforementioned verification test case generation method. That is, the memory 402 stores instructions for executing the aforementioned verification test case generation method.

[0122] The communication interface 403 uses transceiver modules such as, but not limited to, network interface cards and transceivers to enable communication between the computing device 400 and other devices or communication networks.

[0123] In addition to the data bus, the 404 bus can also include a power bus, a control bus, and a status signal bus. The bus can be a Peripheral Component Interconnect Express (PCIe) bus, an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL) bus, a Cache Coherent Interconnect for Accelerators (CCIX) bus, etc. The bus can be divided into address bus, data bus, and control bus.

[0124] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of this application. This application also provides a computer-readable storage medium in which, in some embodiments, the methods disclosed above can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of art.

[0125] Figure 5 A conceptual partial view of an example computer-readable storage medium arranged according to at least some of the embodiments shown herein is illustrated schematically. The example computer-readable storage medium includes a computer program for executing computer processes on a computing device.

[0126] In one embodiment, the computer-readable storage medium 500 is provided using a signal carrying medium 501. The signal carrying medium 501 may include one or more program instructions 502, which, when executed by one or more processors, can provide the functions or parts thereof described above with respect to the embodiments. Furthermore, Figure 5 The program instruction 502 in the document also describes example instructions.

[0127] In some examples, the signal carrying medium 501 may include a computer-readable medium 503, such as, but not limited to, a hard disk drive, a compact disc (CD), a digital video disc (DVD), a digital magnetic tape, a memory, ROM, or RAM, etc.

[0128] In some embodiments, the signal-bearing medium 501 may comprise a computer-recordable medium 504, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, and so on. In some embodiments, the signal-bearing medium 501 may comprise a communication medium 505, such as, but not limited to, digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links, and so on). Therefore, for example, the signal-bearing medium 501 may be transmitted by a wireless form of communication medium 505 (e.g., a wireless communication medium conforming to the IEEE 802 standard or other transmission protocols).

[0129] One or more program instructions 502 may be, for example, computer-executable instructions or logical implementation instructions. In some examples, the computing device may be configured to provide various operations, functions, or actions in response to one or more program instructions 502 conveyed to the computing device via a computer-readable medium 503, a computer-recordable medium 504, and / or a communication medium 505.

[0130] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0131] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0132] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0133] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A method for generating verification test cases, characterized in that, The method includes: Based on the chip description and the definition of the functional points to be verified on the chip, a set of test instructions and an explanation of each functional point are generated through a language model. Based on the set of test instructions and the explanation of each function point, test code corresponding to each function point is generated through a language model. The test code corresponding to each function point corresponds to a combination of one or more of the instructions in the set. Based on the test code corresponding to each of the aforementioned functional points, the first verification test case for the chip is generated through a language model.

2. The method according to claim 1, characterized in that, The functional point to be verified is selected from multiple functional points, which are functional points not covered by the chip's historical verification test cases.

3. The method according to claim 1 or 2, characterized in that, The step of generating test code corresponding to each function point through a language model based on the set of test instructions and the interpretation of each function point includes: Based on the set of test instructions, the interpretation chip for each function point, and the instruction set specification, test code corresponding to each function point is generated through a language model; the set of test instructions is code described in a high-level language, the test code is code described in machine language, and the instruction set specification is used to indicate the conversion rules between code described in a high-level language and code described in machine language.

4. The method according to any one of claims 1 to 3, characterized in that, The step of generating test code corresponding to each function point through a language model based on the set of test instructions and the interpretation of each function point includes: Based on the set of test instructions and the explanation of each function point, a language model is used to generate test code corresponding to each function point and a description of each function point. The step of generating the first verification test case for the chip based on the test code corresponding to each function point through a language model includes: Based on the test code and description corresponding to each function point, the first verification test case of the chip is generated through a language model.

5. The method according to claim 4, characterized in that, The explanation includes a description of the specific variables contained in the function point, and the description is a general description of the function point.

6. The method according to any one of claims 1 to 5, characterized in that, The step of generating the first verification test case for the chip based on the test code corresponding to each function point through a language model includes: Based on the test code and instruction information corresponding to each function point, a first verification test case for the chip is generated through a language model; the instruction information is used to indicate the function points that have been covered by the chip's historical verification test cases.

7. The method according to any one of claims 1 to 6, characterized in that, The step of generating the first verification test case for the chip based on the test code corresponding to each function point through a language model includes: Based on the test code corresponding to each of the aforementioned functional points, a second verification test case for the chip is generated using a language model; When an error exists in the second verification test case, a first verification test case for the chip is generated using a language model based on the test code corresponding to each function point and the error information corresponding to the second verification test case.

8. A verification test case generation device, characterized in that, The device includes: An explanation generation module is used to generate a set of test instructions and an explanation of each function point based on the chip description and the definition of the function points to be verified on the chip, using a language model. The instruction generation module is used to generate test code corresponding to each function point through a language model based on the set of test instructions and the explanation of each function point. The test code corresponding to each function point corresponds to a combination of one or more of the instructions in the set. The verification test case generation module is used to generate the first verification test case for the chip based on the test code corresponding to each of the aforementioned functional points and through a language model.

9. The apparatus according to claim 8, characterized in that, The functional point to be verified is selected from multiple functional points, which are functional points not covered by the chip's historical verification test cases.

10. The apparatus according to claim 8 or 9, characterized in that, The instruction generation module is used for: Based on the set of test instructions, the interpretation chip for each function point, and the instruction set specification, test code corresponding to each function point is generated through a language model; the set of test instructions is code described in a high-level language, the test code is code described in machine language, and the instruction set specification is used to indicate the conversion rules between code described in a high-level language and code described in machine language.

11. The apparatus according to any one of claims 8 to 10, characterized in that, The instruction generation module is used for: Based on the set of test instructions and the explanation of each function point, a language model is used to generate test code corresponding to each function point and a description of each function point. The verification test case generation module is used for: Based on the test code and description corresponding to each function point, the first verification test case of the chip is generated through a language model.

12. The apparatus according to claim 11, characterized in that, The explanation includes a description of the specific variables contained in the function point, and the description is a general description of the function point.

13. The apparatus according to any one of claims 8 to 12, characterized in that, The verification test case generation module is used for: Based on the test code and instruction information corresponding to each function point, a first verification test case for the chip is generated through a language model; the instruction information is used to indicate the function points that have been covered by the chip's historical verification test cases.

14. The apparatus according to any one of claims 8 to 13, characterized in that, The verification test case generation module is used for: Based on the test code corresponding to each of the aforementioned functional points, a second verification test case for the chip is generated using a language model; When an error exists in the second verification test case, a first verification test case for the chip is generated using a language model based on the test code corresponding to each function point and the error information corresponding to the second verification test case.

15. A computing device, characterized in that, Including processor and memory; The processor is configured to execute instructions stored in the memory to cause the computing device to perform the method as described in any one of claims 1 to 7.

16. A computer program product containing instructions, characterized in that, When the instruction is executed by the computing device cluster, the computing device cluster causes the computing device cluster to perform the method as described in any one of claims 1 to 7.

17. A computer-readable storage medium, characterized in that, Includes computer program instructions, which, when executed by a cluster of computing devices, perform the method as described in any one of claims 1 to 7.

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