Method and apparatus for detecting instruction scheduling quality

Abstract

The present disclosure provides a method and device for detecting instruction scheduling quality, which comprises: determining an instruction pair with a dependency relationship from an instruction assembly text of a current round detection process, wherein the instruction assembly text is obtained by compiling a test case, an instruction pair comprises a dependent instruction and a dependent instruction, and the dependency relationship is used to represent that, in response to executing the dependent instruction, a memory access task initiated according to the dependent instruction is blocked or released downstream of the dependent instruction; generating a statistical value of a preset index according to the number of target instructions between the dependent instruction and the dependent instruction; and determining a quality detection result of the test case according to a comparison result of the statistical value and a preset statistical value. The method improves the detection efficiency and accuracy of the instruction scheduling quality of the test case.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to a method for detecting instruction scheduling quality, a device for detecting instruction scheduling quality, an electronic device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] The backend of the GPU (Graphics Processing Unit) shader compiler is responsible for converting the intermediate representation (IR) into the target architecture's ISA (Instruction Set Architecture). Instruction scheduling is a key factor directly affecting shader execution efficiency. Unlike modern CPUs (Central Processing Units) that execute out of order, GPU shader processors typically rely on the compiler for static instruction scheduling. This means the compiler must arrange instructions in a reasonable order during code generation to fully utilize pipeline parallelism and hide memory access latency. Summary of the Invention

[0003] This disclosure provides a method for detecting instruction scheduling quality, an apparatus for detecting instruction scheduling quality, an electronic device, a computer-readable storage medium, and a computer program product.

[0004] In a first aspect, embodiments of this disclosure propose a method for detecting instruction scheduling quality, comprising: determining instruction pairs with dependencies from the instruction assembly text of the current round of detection, wherein the instruction assembly text is obtained by compiling test cases, an instruction pair includes a dependent instruction and a dependent instruction, the dependency relationship is used to characterize the response to execution of the dependent instruction, blocking or allowing instructions located downstream of the dependent instruction according to the completion status of the memory access task initiated by the dependent instruction; generating a statistical value of a preset index according to the number of target instructions located between the dependent instruction and the dependent instruction; and determining the quality detection result of the test case according to the comparison result between the statistical value and the preset statistical value.

[0005] Secondly, this disclosure provides an instruction scheduling quality detection device, comprising: an instruction pair determination module, a statistical value generation module, and a detection result determination module. The instruction pair determination module is configured to determine instruction pairs with dependencies from the instruction assembly text of the current round of detection. The instruction assembly text is compiled from test cases. An instruction pair includes a dependent instruction and a dependent instruction. The dependency relationship characterizes whether, in response to execution of the dependent instruction, instructions downstream of the dependent instruction are blocked or allowed based on the completion status of the memory access task initiated by the dependent instruction. The statistical value generation module is configured to generate a statistical value of a preset index based on the number of target instructions located between the dependent instruction and the dependent instruction. The detection result determination module is configured to determine the quality detection result of the test cases based on the comparison result between the statistical value and the preset statistical value.

[0006] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform an instruction scheduling quality detection method as described in any implementation of the first aspect.

[0007] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions that, when executed by a processor, enable a method for detecting instruction scheduling quality as described in any implementation of the first aspect.

[0008] Fifthly, embodiments of this disclosure provide a computer program product including a computer program, which, when executed by a processor, can implement the instruction scheduling quality detection method described in any implementation of the first aspect.

[0009] According to the technical solution provided in this disclosure, firstly, instruction pairs with dependencies are determined from the instruction assembly text of the current round of testing. The instruction assembly text is obtained by compiling test cases. An instruction pair includes a dependent instruction and a dependent instruction. The dependency relationship is used to characterize whether to block or allow instructions downstream of the dependent instruction in response to the execution of the dependent instruction, based on the completion status of the memory access task initiated by the dependent instruction. Then, based on the number of target instructions between the dependent instruction and the dependent instruction, a statistical value of a preset index is generated. Finally, the quality detection result of the test case can be determined based on the comparison result between the statistical value and the preset statistical value.

[0010] Based on the assembly text of the instructions compiled from the test cases, the system automatically identifies dependent instruction pairs consisting of delayed memory access instructions and synchronous wait instructions. This eliminates the need for manual analysis of each assembly instruction, significantly reducing manual parsing costs and improving the automation and consistency of dependency extraction. Then, by statistically analyzing the number of target instructions between dependent and dependent instructions, standardized preset metrics are generated. This allows for the calculation of the interval between instruction pairs without running shaders on a real GPU, eliminating reliance on scarce GPU hardware resources and avoiding biases caused by subjective human judgment. Finally, real-time metric statistics are compared with preset statistical benchmarks. Based on the comparison results, the detection value of test cases can be quickly distinguished, automatically filtering out test cases that expose scheduling defects and eliminating inefficient test cases with insufficient discriminative power. This optimizes the overall quality of the test case set, improves the efficiency of instruction scheduling instruction detection for test cases, and consequently enhances the efficiency of subsequent compiler performance iterations and defect localization.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A flowchart illustrating a method for detecting instruction scheduling quality provided in this embodiment of the disclosure; Figure 2 A flowchart of another method for detecting instruction scheduling quality provided in an embodiment of this disclosure; Figure 3 A flowchart of another method for detecting instruction scheduling quality provided in an embodiment of this disclosure; Figure 4 A flowchart illustrating yet another method for detecting instruction scheduling quality provided in this embodiment of the disclosure; Figure 5 A flowchart illustrating the application of the instruction scheduling quality detection method provided in this embodiment of the disclosure; Figure 6 A structural block diagram of an instruction scheduling quality detection device provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of an electronic device for detecting the quality of execution instruction scheduling, as provided in an embodiment of this disclosure. Detailed Implementation

[0013] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding; these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0014] This disclosure relates to the field of integrated circuit technology, specifically to a method for detecting instruction scheduling quality, a device for detecting instruction scheduling quality, an electronic device, a computer storage medium, and a program product. It is applicable to scenarios such as instruction scheduling of GPU compilers, CI / CD (Continuous Integration / Continuous Delivery) automated testing, and static code analysis.

[0015] In a GPU shader compilation system, the backend of the GPU shader compiler is responsible for converting intermediate representations into the target architecture's ISA. Instruction scheduling is a key factor directly affecting shader execution efficiency. In the GPU rendering pipeline, texture sampling and buffer loading are the most common high-latency operations, typically with latencies ranging from hundreds to thousands of clock cycles. The core strategy of latency hiding is to insert as many valid ALU (Arithmetic Logic Unit) computation instructions as possible, independent of the sampling result, after issuing the sampling instruction (SMP) and before waiting for data return (WAIT), thus ensuring the GPU pipeline does not stall while waiting for memory data. The intuitive measure of scheduling quality is the instruction distance between SMP and WAIT.

[0016] Currently, some instruction scheduling quality assessment schemes use static estimation of instruction sequence throughput and clock cycles through microarchitecture models. This can only estimate the overall number of cycles, without providing a distance metric between instruction pairs, and cannot quantify the most direct indicator of scheduling quality—"how much effective computation (number of instructions or estimated cycles) is inserted between SMP-WAIT sessions." Furthermore, it does not support most GPU microarchitecture models.

[0017] Other instruction scheduling quality testing solutions use performance profiling tools for system-level performance tracking, which can display the GPU kernel timeline and the reasons for pauses. However, these solutions require hardware execution, meaning that shaders must be run on a real GPU. A single analysis can take tens of seconds to several minutes, making them unsuitable for CI processes that are executed with every code commit (GPU resources are scarce and execution time is long). Furthermore, they do not provide instruction pitch measurement.

[0018] Therefore, existing instruction scheduling quality detection schemes lack instruction-level scheduling quality metrics, cannot automatically detect scheduling regressions in CI, rely on hardware execution for performance profiling, and require engineers to manually read ISA assembly and count instruction intervals, which is not scalable and is prone to omissions.

[0019] The following description of several optional embodiments illustrates the technical solutions of this disclosure and the technical effects produced by these solutions. It should be noted that the following embodiments can be referenced, learned from, or combined with each other. Identical terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0020] Please refer to Figure 1 , Figure 1 A flowchart of a method for detecting instruction scheduling quality provided in this disclosure embodiment, wherein process 100 includes the following steps: Step 101: Identify instruction pairs with dependencies from the instruction assembly text of the current round of detection process.

[0021] In this embodiment, the instruction scheduling detection method can execute multiple rounds, which may include the detection process of the current round and the detection process of previous rounds. The detection process of previous rounds is the detection process before the detection process of the current round. For the detection process of the current round, instruction pairs with dependencies are determined from the instruction assembly text of the current round detection process. The instruction assembly text is obtained by compiling test cases. An instruction pair includes a dependent instruction and a dependent instruction. First, after determining the test cases, the test cases are input into the compiler. The compiler will sequentially complete lexical and syntax parsing, generate high-level intermediate representation (IR), execute multiple rounds of low-level pass (steps), assign barrier ID (identity), and perform instruction scheduling processing, finally outputting ISA instruction assembly text T adapted to the target GPU instruction set architecture.

[0022] Then, a lexical scan is performed on the compiled instruction text T to extract each operation instruction line by line and arrange them in order of hardware execution, generating a complete instruction sequence I=[i_1,i_2,...,i_n]. It should be noted that lexical scanning, also called lexical analysis, is the first processing step in compilation / text parsing. Its function is to cut a continuous text string into the smallest meaningful syntactic units.

[0023] In this embodiment, the dependent instructions are delayed instructions, referring to high-latency memory access instructions such as texture sampling (SMP) and memory loading (LOAD). These instructions take longer to execute in hardware and consume barrier resources. Subsequent computation instructions must wait for these instructions to complete before they can run normally, and are the source of the dependency relationship; therefore, they are called dependent instructions. Dependent instructions are instructions that need to wait for the aforementioned delayed instructions to complete before they can be executed. They are divided into two categories: the first category is dedicated DEPBAR (Dependence Barrier) waiting instructions, which actively block the execution flow until all delayed instructions under the corresponding barrier are completed; the second category is ALU operation instructions carrying a non-zero wait bit mask (wait_bar_mask). These instructions automatically wait for all delayed instructions corresponding to the barriers within the mask before computation. Both of these types of instructions rely on the results of the delayed instructions to execute, and are therefore called dependent instructions.

[0024] After generating the complete instruction sequence I, each instruction within the sequence is traversed sequentially to complete type determination. Texture sampling and memory loading deferred instructions are marked as dependent instructions, and their bound barrier numbers are recorded and stored in the matching stack. Additionally, DEPBAR wait instructions and ALU instructions with non-zero wait_bar_mask bitmask values ​​are marked as dependent instructions. All barrier identifiers of the instructions waited for by the dependent instructions are extracted, and deferred instructions with matching barrier numbers are matched from the matching stack. Finally, a successfully matched set of deferred instructions and wait instructions are combined into instruction pairs with synchronization dependencies. After completing the traversal of all instructions, all instruction pairs are summarized.

[0025] Here, dependencies are used to characterize the blocking or allowing of downstream instructions in response to the execution of a dependent instruction, based on the completion status of the memory access task initiated by the dependent instruction. That is, dependent instructions and dependent instructions with memory access synchronization dependencies are identified as instruction pairs. This memory access synchronization dependency means that the dependent instruction must wait for the memory access task initiated by the dependent instruction to meet a preset completion condition before the pipeline can continue; it is not a data read / write dependency in ordinary operations. This dependency does not originate from register data streams but is a hardware scheduling dependency introduced by barriers and wait mechanisms in the GPU ISA.

[0026] Step 102: Generate statistical values ​​for preset metrics based on the number of target instructions located between the dependent instructions and the dependent instructions.

[0027] In this embodiment, all matched instruction pairs are traversed. For each pair containing a delayed instruction and a waiting-type dependent instruction, the index positions of the two instructions within the ordered instruction sequence are located. Then, the difference between their indices is calculated, and the first and last instructions themselves are subtracted to obtain the number of target instructions between the dependent instruction and the dependent instruction.

[0028] In this step, the target instruction count refers to the number of effective ALU instructions. Effective ALU instructions are those purely performing numerical operations, located between dependent delayed instructions (SMP / LOAD) and dependent wait instructions (DEPBAR / masked ALU). They do not contain memory access or synchronization instructions and can be executed in parallel during high-latency memory access wait intervals to mask the clock cycle overhead caused by memory access. They are the core statistical object for evaluating instruction scheduling performance. Therefore, all instructions between the dependent and dependent instructions are first calculated based on their corresponding index positions in the ordered instruction sequence. Then, the instruction type of each instruction is determined, including only regular arithmetic ALU instructions in the statistics. High-latency sampling / loading instructions, synchronization barrier instructions, register transfer instructions, etc., are all excluded, retaining only effective arithmetic instructions that can fill latency gaps and mask memory access time. After filtering, the number of effective ALU instructions between the dependent and dependent instructions is counted. This number represents the number of arithmetic instructions successfully scheduled by the compiler during memory access latency gaps; a higher value indicates better instruction scheduling efficiency and less hardware wait overhead.

[0029] Finally, the number of interval instructions (i.e. the number of target instructions) is used as the basic statistical dimension to generate statistical values ​​of preset indicators. For example, the number of interval instructions in a single group, the average number of interval instructions in all instruction pairs, the number of maximum interval instructions, and the number of minimum interval instructions are counted separately. These are then summarized to obtain the statistical values ​​of preset scheduling indicators used to measure the compactness of instruction arrangement.

[0030] Step 103: Determine the quality inspection results of the test cases based on the comparison results between the statistical values ​​and the preset statistical values.

[0031] In this embodiment, the statistical values ​​corresponding to all current instruction pairs are first summarized. Specifically, the statistical indicators such as the average effective ALU instruction value, the maximum and minimum interval instruction value, and the synchronization wait cycle loss corresponding to all current instruction pairs are summarized. Then, each statistical value of the current indicators is compared with the corresponding historical benchmark statistical values. Based on the comparison results, the quality detection result of the test case is determined. The preset statistical values ​​here can be historical benchmark statistical values ​​or statistical value ranges stored in the same GPU compiler scenario. The historical statistical values ​​are obtained by detecting and statistically analyzing the instruction assembly text of the historical detection process. Specifically, if all overall indicators fall within the preset normal range and the fluctuation range is small, stably reproducing the characteristics of conventional instruction scheduling, then the test case is deemed of acceptable quality and can be used as a regular benchmark test case. If multiple overall indicators significantly deviate from the preset benchmark range, clearly exposing performance deviations related to compiler synchronization scheduling and barrier arrangement, with significant differentiation, then the test case is deemed a high-quality defect detection test case. If all overall indicators are highly similar to historical benchmarks, the instruction dependency structure is simple, and it is impossible to distinguish the merits of different scheduling algorithms, lacking differentiated detection capabilities, then the test case is deemed of poor quality and is not recommended for performance comparison testing. Finally, all indicator comparison differences are summarized, and the final quality detection result corresponding to the test case is output.

[0032] As an example, if the average number of effective ALU instructions is higher than the historical baseline lower limit and the memory access gap filling index is within the historical good range, then the compiler instruction scheduling performance under this test case is considered to be up to standard, and the test case quality is qualified. If the average number of effective ALUs is lower than the historical baseline threshold and the additional cycle overhead caused by synchronous blocking is significantly higher than the historical normal level, it indicates that there is a defect in the current compiler scheduling logic. In this case, the test case is considered to effectively expose performance problems and is marked as a high-quality defect detection test case. If all indicators fall within the historical best range, it is marked as a high-quality standard test case. If the instruction dependency structure is simple and the various statistical indicators have no distinguishing significance and cannot reflect the differences in compiler scheduling, it is judged as a low-quality invalid test case.

[0033] According to the instruction scheduling quality detection method provided in this disclosure, the method automatically identifies dependent instruction pairs consisting of delayed memory access instructions and synchronous wait instructions based on the instruction assembly text generated by compiling test cases. This eliminates the need for manual analysis of each assembly instruction, significantly reducing manual parsing costs and improving the automation and consistency of dependency extraction. Then, a standardized preset index is generated by statistically analyzing the number of target instructions between dependent and dependent instructions. This allows for the calculation of the instruction pair spacing without running shaders on a real GPU, eliminating reliance on scarce GPU hardware resources and avoiding biases caused by subjective human judgment. Finally, the index statistics are compared with preset benchmark values. Based on the comparison results, the detection value of test cases is quickly distinguished, automatically filtering out test cases that expose scheduling defects and eliminating those with insufficient discriminative power. This improves the efficiency of instruction scheduling instruction detection for test cases, optimizes the overall quality of the test case set, and ultimately enhances the efficiency of subsequent compiler performance iterations and defect localization.

[0034] Please refer to Figure 2 , Figure 2 A flowchart of another instruction scheduling quality detection method provided for embodiments of this disclosure, wherein process 200 includes the following steps: Step 201: Parse the instruction assembly text of the current round of detection process, and construct a structured instruction sequence based on the parsing results.

[0035] In this embodiment, the instruction assembly text output by the compiler for the test cases of the current round of detection is read and parsed. Specifically, the parsing method can be lexical scanning, that is, performing lexical scanning on the entire assembly text, removing invalid delimiters such as spaces, newlines, and comments character by character, and identifying various valid words such as instruction mnemonics, barrier numbers, registers, numerical constants, and mask identifiers. The words are then grouped according to the execution order of the text from top to bottom, with each group of words corresponding to a hardware instruction. The instruction type, barrier identifier, wait mask, line index, and other attribute information corresponding to each instruction are extracted. The instructions carrying complete attribute information are arranged in order of execution to construct a structured instruction sequence I containing complete instruction attributes and having a sequential index, I=[i_1,i_2,..., i_n].

[0036] Step 202: In response to determining that the first instruction is a dependent instruction from the instruction sequence, the first instruction is stored in the matching stack.

[0037] In this step, each instruction in the structured instruction sequence I is traversed. When the first instruction being traversed is determined to be a texture sampling or memory loading type of lazy dependent instruction, its own identifier, the bound barrier number, and its position index in the instruction sequence are extracted. This information is then integrated into a complete record and pushed into a pre-created matching stack for temporary storage. This allows for quick retrieval of the corresponding dependent instruction from the matching stack based on the barrier number when a dependent instruction is encountered later. The matching stack is a temporary storage container specifically for storing all identified but not yet matched high-latency dependent instruction records. Each record is a triple: [instruction object, barrier identifier, instruction sequence position index].

[0038] In some optional implementations of the embodiments of this disclosure, the above-mentioned instruction scheduling quality detection method may further include the following: extracting a barrier identifier from the parameter information of the first instruction and updating the value of the counter corresponding to the barrier identifier. Step 202 may be executed as follows: storing the first instruction, the barrier identifier of the first instruction, and the position index of the first instruction in the instruction sequence into the matching stack.

[0039] In this implementation, a global barrier counter container BC is pre-created, covering all available barrier numbers, and the counter for each barrier is initialized to 0, represented as BC = {bar_0:0, bar_1:0, ..., bar_k:0}. Then, each instruction in the structured instruction sequence I is traversed. When the first instruction being traversed is determined to be a texture sampling or memory loading type of lazy-dependent instruction, the corresponding barrier identifier (bar_x) is extracted from the parameter information carried by the first instruction i_j, recorded, and the value of the counter BC[bar_x] corresponding to the barrier identifier is incremented by 1. Subsequently, the triple data [i_j, bar_x, j] composed of the first instruction itself i_j, the extracted barrier identifier bar_x, and the position index j of the first instruction in the instruction sequence is pushed into a pre-initialized matching stack S for cache storage. This provides searchable raw data of dependent instructions, barrier association information, and position information for subsequent matching of waiting dependent instructions, thereby improving the matching accuracy of instruction pairs.

[0040] Step 203: In response to determining that the second instruction is a dependent instruction from the instruction sequence, retrieve the third instruction that the second instruction depends on from the matching stack.

[0041] In this embodiment of the disclosure, in response to determining that the second instruction is a dependent instruction from the instruction sequence, a third instruction that the second instruction depends on is obtained from the matching stack, wherein the second instruction and the third instruction constitute an instruction pair with a dependency relationship.

[0042] When the second instruction being iterated is determined to be a DEPBAR wait instruction or a dependent instruction of type ALU with a non-zero wait_bar_mask, since the second instruction's parameters carry the barrier ID of its matched dependent instruction, the barrier ID is first extracted from the second instruction's parameters. This barrier ID is then used as the search condition to iterate through all cached records in the matching stack S, thereby filtering out the storage record corresponding to the third instruction whose barrier ID matches. Next, the third instruction is extracted as the dependent instruction, and it is combined with the currently iterated second instruction to form a pair of instructions with synchronization dependency (src, i_j, type). Here, src is the dependent instruction (i.e., the third instruction), i_j is the dependent instruction (i.e., the second instruction), and type is the instruction pair type identifier used to distinguish synchronization types, such as regular barrier synchronization, masked ALU synchronization, etc., facilitating subsequent classification and statistical metrics. Finally, this instruction pair is stored in the instruction pair set.

[0043] By parsing assembly text to construct a structured instruction sequence, identifying dependent instructions and storing them in a matching stack, and then matching the corresponding dependent instructions based on the barrier identifiers of the dependent instructions, dependent instruction pairs are automatically generated. This improves the parsing efficiency and recognition accuracy of instruction dependency relationships and reduces the cost of manual sorting.

[0044] In some optional implementations of the embodiments of this disclosure, step 203 may be performed as follows: determining the barrier identifier of the third instruction from the parameter information of the second instruction, and obtaining the current value of the counter corresponding to the barrier identifier of the third instruction and the threshold; in response to determining that the current value is greater than the threshold, obtaining all third instructions from the matching stack according to the barrier identifier of the third instruction, and retrieving a target number of third instructions from all the third instructions according to the instruction storage time, wherein the target number is the difference between the current value and the threshold.

[0045] In this implementation, since the second instruction carries the target barrier ID of its dependent instruction in its parameters, the barrier ID is first extracted from the second instruction's parameters, and the synchronization threshold is obtained simultaneously. The target barrier ID is the barrier ID of the third instruction that the second instruction is waiting for. It should be noted that the threshold refers to the synchronization threshold value carried by the DEPBAR instruction, representing the upper limit of the number of high-latency instructions that the hardware does not need to wait for. The barrier counter records the total number of SMP / LOAD instructions executed under this barrier; only when the count exceeds the threshold will additional memory access instructions need to block and wait.

[0046] After determining the barrier ID of the third instruction that the second instruction is waiting for, the barrier counter corresponding to the barrier ID is queried to obtain the real-time count value (i.e., the current value) of that barrier ID, and then compared with the threshold. If the current count value is greater than the threshold, the stack S to be matched is traversed using the barrier ID as the filtering condition, filtering out all third instructions with the same barrier ID, and sorting all the third instructions according to the order in which they were pushed onto the stack. At the same time, the difference between the current count value and the threshold is used as the target number, and the target number of third instructions are taken from all the sorted third instructions to generate instruction pairs with the second instruction. If the current count value is less than the threshold, then no instructions can be released at this time, and no instruction pairs are generated.

[0047] By extracting barrier counts and synchronization thresholds, blocking memory access instructions that exceed the thresholds are filtered out. Instruction pairs are generated by matching them according to the stack push order, which closely matches the actual synchronization logic of the hardware and ensures the accuracy of gap index statistics. This improves the accuracy of instruction pairing results and, in turn, enhances the realism of compiler scheduling evaluation.

[0048] It should be noted that when encountering DEPBAR bar_x,hreshold, it means "waiting for the unfinished count of bar_x to drop below threshold". At this time, only the earliest BC[bar_x]-threshold unmatched instructions are released, and the remaining instructions wait for subsequent WAIT.

[0049] In other words, at the hardware execution semantic level, the role of DEPBAR bar_x, threshold is to block the pipeline and continuously monitor the uncompleted memory access counter BC[bar_x] corresponding to the barrier bar_x until the counter value drops below the threshold, at which point the hardware will unblock and execute subsequent instructions.

[0050] In the static assembly instruction pairing logic, the current count value and threshold are used as the number of memory access instructions to be released this time: from the instruction stack to be matched corresponding to bar_x, the earliest preset number of memory access source instructions are extracted, and (src, DEPBAR) dependent instruction pairs are constructed with the current DEPBAR instruction respectively, which are used to calculate scheduling metrics such as weighted spacing and fill rate; the paired instructions are popped from the stack, and the remaining unmatched memory access instructions with the same barrier in the stack are kept, waiting for other WAIT / DEPBAR instructions to complete the pairing and binding. The former defines the complete processing flow when the triggering condition is met, and the latter defines the pre-judgment threshold for whether the flow can be executed; the former talks about "what to do after the condition is met", and the latter talks about "under what conditions the flow is allowed to be executed and how to handle it if it is not met". The two are a pairing relationship between pre-verification and post-execution.

[0051] Step 204: Identify all Arithmetic Logic Unit (ALU) instructions located between the dependent instruction and the dependent instruction.

[0052] In this step, the start index of the sequence of the dependent instruction src and the end index of the sequence of the dependent instruction i_j in the paired instruction pair (src, i_j) are read first. Then, the range between the two indices is determined. After that, each structured instruction within the range is traversed, the instruction type identifier stored in each instruction is read, and ALU instructions are filtered out, thereby determining all ALU instructions between the dependent instruction and the dependent instruction.

[0053] Step 205: Filter out the preset type instructions from all ALU instructions, and the resulting valid ALU instructions are the target instructions.

[0054] In this step, the type identifier of each instruction in all ALU instructions is read one by one, and the following types of instructions are removed: NOP (No Operation) instructions, other WAIT / DEPBAR instructions, control flow instructions (branch / jump), and debugging information instructions. The remaining instructions with actual computational function are considered valid ALU instructions (i.e., target instructions). The number of valid ALU instructions is also the instruction pair distance (IPD) between the dependent instructions and the dependent instructions.

[0055] By extracting all ALU instructions between two dependent instructions and filtering out invalid instructions such as NOP, synchronization, control flow, and debugging, the effective ALU instructions with actual computing power can be accurately counted, avoiding interference from invalid instructions and ensuring the true accuracy of the scheduling gap index calculation.

[0056] Step 206: Generate statistical values ​​for preset metrics based on the number of target instructions located between the dependent instructions and the dependent instructions.

[0057] Step 207: Determine the quality inspection results of the test cases based on the comparison results between the statistical values ​​and the preset statistical values.

[0058] Steps 206-207 above are similar to... Figure 1 Steps 102-103 shown are the same. For the same parts, please refer to the corresponding parts of the previous embodiment. They will not be repeated here.

[0059] According to the instruction scheduling quality detection method provided in this disclosure, a structured instruction sequence is constructed by automatically parsing assembly text, and memory access-dependent instructions are stored in the matching stack. Then, the corresponding dependent instructions are accurately matched by combining synchronization threshold rules to generate complete instruction dependency pairs. Afterwards, invalid instructions of a preset type are removed from all ALU instructions in the dependent and dependent instructions. The number of valid operation instructions can be accurately counted and scheduling-related indicators can be output. The entire process does not require manual sorting of assembly code, which greatly reduces labor costs, avoids the bias of manual statistics, improves the accuracy of instruction pair identification and the accuracy of instruction pair statistical indicators, and truly restores the scheduling gap of the hardware pipeline, efficiently completing the automated quality detection of GPU test cases.

[0060] In some optional implementations of the embodiments of this disclosure, step 204 may be performed as follows: in response to determining that the dependent instruction and the dependent instruction are located in the same code block, all ALU instructions are determined according to a first position index and a second position index, wherein the first position index is the position index of the dependent instruction in the instruction sequence, and the second position index is the position index of the dependent instruction in the instruction sequence.

[0061] In a real shader ISA, SMP and WAIT operations may be separated by if-else statements or loops, leading to inaccurate distance calculations with a simple linear scan. Therefore, in this embodiment, the ISA instruction sequence is pre-divided into basic blocks based on control flow jump instructions, and a CFG (Control Flow Graph) is constructed. Then, for each instruction pair (src, i_j), path analysis is performed on the CFG. This involves reading the paired dependent instructions and the code block number markers carried by each dependent instruction, comparing their marker values ​​to determine if they belong to the same code block. If they do, the distance is calculated using a linear scan. This involves retrieving the first position index of the dependent instruction and the second position index of the dependent instruction, using these two indices to define a continuous instruction interval, sequentially traversing each structured instruction within the interval, and filtering out all ALU type instructions based on the instruction type field and saving them.

[0062] The CFG basic block identifier determines whether two instructions belong to the same code block. Only when they are in the same code block are the ALU instructions extracted by extracting the interval through their indices. This avoids the situation of invalid instructions being incorrectly counted due to cross-branch jumps, and ensures that the statistical interval matches the actual execution path of the hardware, effectively improving the accuracy of the calculation of the number of effective ALUs and scheduling indicators.

[0063] In some optional implementations of the embodiments of this disclosure, step 204 may be performed as follows: in response to determining that the dependent instruction and the dependent instruction are located in different code blocks, all candidate paths between the first code block where the dependent instruction is located and the second code block where the dependent instruction is located are determined; based on the number of ALU instructions contained in the candidate paths, a target path is determined from all candidate paths; and the ALU instructions contained in the target path are determined as all ALU instructions.

[0064] In this implementation, if it is determined that the dependent instruction and the dependent instruction are not located in the same code block (i.e., the dependent instruction and the dependent instruction belong to independent first and second code blocks respectively), then based on the complete program control flow graph (CFG), a graph traversal algorithm is used to enumerate all executable branches from the exit of the first code block to the entry of the second code block, generating multiple complete candidate execution paths. The number of valid ALU instructions on each candidate execution path is then calculated.

[0065] Next, the path with the most valid ALUs is selected from all candidate paths as the target path. All filtered valid ALU instructions in this target path are extracted as the set of operation instructions between two dependent instructions in a cross-code block scenario.

[0066] This allows for the traversal of all feasible execution paths in the CFG when crossing code blocks, filtering target paths based on the number of ALUs in each path. This improves the accuracy of the results of effective instructions between instruction pairs in cross-code block scenarios, avoids metric distortion caused by single-path statistics, adapts to complex multi-branch code structures, and ensures that the calculation of pipeline delay hidden metrics closely matches the actual execution logic of the program.

[0067] In some scenarios, if the assembler / CFG includes branch weights, it records the probability of each branch being executed. Then, it calculates the effective ALU count for each path multiplied by the execution probability of that path, and sums all the results to obtain the expected average distance. This expected average distance reflects the average level of latency hiding capability under long-term program execution, closely resembling real-world operating scenarios.

[0068] Furthermore, for SMP-WAIT pairs within a loop, the distance can be calculated using the loop unrolling factor (compiler annotation or default value 1). The calculation logic is: the number of effective ALUs counted in a single loop iteration × the loop unrolling factor, which serves as the final distance. This allows for matching the actual hardware execution, avoiding the underestimation of computational loads that can mask latency during loop iterations by only counting single loop segments.

[0069] Please refer to Figure 3 , Figure 3 A flowchart of another instruction scheduling quality detection method provided in this disclosure embodiment, wherein process 300 includes the following steps: Step 301: Identify instruction pairs with dependencies from the instruction assembly text of the current round of detection process.

[0070] The above steps 301 and as follows Figure 1 The steps shown are the same as 101. For the same parts, please refer to the corresponding parts of the previous embodiment. They will not be repeated here.

[0071] Step 302: Generate the average instruction value based on the number of target instructions between the dependent and dependent instructions in each instruction pair.

[0072] In this embodiment, all matched instruction pairs (src, i_j) are first traversed, and the number of valid target ALU instructions for each pair after interval filtering, invalid instruction filtering, and cross-block path selection is read. Then, the valid ALU values ​​of each instruction pair are summed sequentially to obtain the total number of valid ALUs for all instruction pairs. Next, the total number of valid instruction pairs currently participating in the calculation is counted, excluding invalid instruction pairs with no match or no intermediate ALU. Finally, the total number of valid ALUs is used. Dividing by the total number of valid instruction pairs (TaLU), the global average effective ALU index value is calculated, also known as the average interval AVG_IPD. AVG_IPD = This is used to quantify the overall pipeline delay concealment level.

[0073] Step 303: Determine the minimum value from the number of target instructions in all instruction pairs to obtain the minimum instruction value.

[0074] In this embodiment, all instruction pairs that have completed the statistics are traversed, and the number of effective target ALU instructions corresponding to each instruction pair is extracted in turn to establish a numerical set. Then, the numerical set is traversed again to compare and filter out the smallest value, which is taken as the minimum instruction value, also known as the minimum spacing MIN_IPD. MIN_IPD = min(IPD_i), which represents the number of arithmetic instructions that can be used to mask memory access latency in the worst case, and serves as a performance lower limit evaluation indicator.

[0075] Step 304: Determine the target instruction pairs from multiple instruction pairs whose number of target instructions is less than a preset threshold, and calculate the ratio of the number of target instruction pairs to the number of all instruction pairs to obtain the percentage of instructions below the threshold.

[0076] In this embodiment, a threshold T for the number of effective ALUs for determination is preconfigured. All instruction pairs are traversed, the corresponding target instruction quantity of each group is extracted one by one, the instruction pairs with the target instruction quantity less than a preset threshold A are counted and recorded as the total number of low-performance instruction pairs count(IPD_i<A), and the total quantity Ts of all valid instruction pairs is counted at the same time. Finally, the number of low-performance instruction pairs is divided by the number of all instruction pairs to calculate the proportion value RATIO_BELOW(A), where RATIO_BELOW(A) = count(IPD_i<A) / Ts, which is used to quantify the overall proportion of instruction pairs with insufficient latency hiding. That is, the statistical values in this embodiment include: an average instruction value, a minimum instruction value, and a proportion value of instructions below the threshold.

[0077] Thus, three types of statistical indicators including the average value, the minimum value, and the low threshold proportion are synchronously output, to quantify the latency hiding capability of the pipeline from multiple dimensions such as the overall average level, the worst performance lower limit, and the distribution proportion of defective instructions. The average instruction value reflects the filling level of the overall computing power, the minimum instruction value locates the worst performance scenario, and the proportion value intuitively quantifies the scale of instruction pairs with insufficient latency masking. The combination of multiple indicators can comprehensively and objectively evaluate the scheduling performance of test cases, thereby avoiding the one-sidedness caused by evaluation with a single indicator.

[0078] Step 305: If the decrease amplitude of the average instruction value compared with the historical average instruction value exceeds a first preset amplitude, or the decrease amplitude of the minimum instruction value compared with the historical minimum instruction value exceeds a second preset amplitude, or the increase amplitude of the proportion value of instructions below the threshold compared with the historical proportion value exceeds a third preset amplitude, the quality detection result is determined as an alarm.

[0079] In this step, the preset statistical values are historical statistical values generated in the detection process of historical rounds, and the historical statistical values include: a historical average instruction value, a historical minimum instruction value, and a historical proportion value. Here, the AVG_IPD (average interval), MIN_IPD (minimum interval), and RATIO_BELOW(A) obtained by current statistics are first read, and the historical indicator data stored under the same benchmark and the three preset amplitude thresholds are retrieved at the same time. Then, the change amplitudes of the three groups of indicators are calculated respectively: the decrease amplitude of the current AVG_IPD relative to the historical average value, the decrease amplitude of the current MIN_IPD relative to the historical minimum value, and the increase amplitude of the current RATIO_BELOW(A) relative to the historical proportion. After that, the three groups of amplitudes are respectively compared with the first, second and third preset amplitudes. As long as any group of amplitudes exceeds the corresponding threshold, it is determined that the current test case has scheduling performance degradation, and an alarm-type quality detection result is output, indicating that the memory access latency hiding capability is significantly deteriorated.

[0080] For each monitored shader S: current = compute_metrics(S, current_compiler), baseline = load_baseline(S), where current is the set of metrics for this operation, compute_metrics is the function to calculate the metrics, current_compiler refers to the compiler environment / compilation configuration used by the current shader, which may include: compiler version, compilation parameters, target hardware; baseline is the baseline metric, and load_baseline(S) is the historical baseline data of shader S.

[0081] As an example, if the first threshold is 10%, the second is 20%, and the third is 5%, then if AVG_IPD decreases by more than 10%, or MIN_IPD decreases by more than 20%, or RATIO_BELOW(A) increases by more than 5%, then the quality detection result of the current test case is determined to be an alarm. Of course, the first, second, and third preset thresholds can also be set to other values, and this embodiment does not specifically limit them.

[0082] Performance changes are verified from three dimensions: average, worst, and defect percentage. An alarm is triggered if the degradation of any indicator exceeds a preset range. This can promptly capture the degradation of shader latency hiding capabilities and prevent scheduling performance defects from flowing into the version, thereby achieving automated regression detection.

[0083] According to the instruction scheduling quality detection method provided in this disclosure, memory access-synchronization dependent instruction pairs are extracted by automatically parsing assembly, and multi-dimensional statistical analysis is performed on the relevant indicators of effective ALU filling. At the same time, a quantitative comparison is made with historical baselines. An alarm is triggered as soon as any indicator deteriorates beyond the limit, thereby comprehensively quantifying the pipeline's latency hiding capability, accurately identifying the degradation of shader scheduling performance, automating the regression verification of code quality, and intercepting performance defects in advance.

[0084] Please refer to Figure 4 , Figure 4 A flowchart of another instruction scheduling quality detection method provided in this disclosure embodiment, wherein process 400 includes the following steps: Step 401: Identify instruction pairs with dependencies from the instruction assembly text of the current round of detection process.

[0085] Step 402: Generate statistical values ​​for preset metrics based on the number of target instructions located between the dependent instructions and the dependent instructions.

[0086] The above steps 401-402 and as follows Figure 1The steps 101-102 shown are the same. For the same parts, please refer to the corresponding parts of the previous embodiment. They will not be repeated here.

[0087] Step 403: Perform constraint verification on the instruction assembly text to obtain the target verification result.

[0088] In this embodiment, the complete assembly text of the shader to be tested is read, and a full set of preset constraint verification rules is loaded. These rules may include assembly syntax specifications, restrictions on the use of special instructions, register resource limits, CFG branch weight annotation specifications, loop unrolling identifier formats, and memory access synchronization instruction pairing rules. Then, the assembly instructions are parsed line by line, and multi-dimensional verification is performed sequentially: checking for illegal instructions, undefined registers, and excessive resource usage; verifying whether branch code has a branch weight marker and whether loop instructions are marked with a valid unrolling factor; and checking the writing specifications of dependency instructions such as SMP, WAIT, and DEPBAR. Finally, all verification anomalies are recorded, with the corresponding line number, violation constraint type, and specific problem description. If no violations are found, the verification is marked as passed. All verification information is integrated to form a structured target verification result, which is then used for pre-filtering of illegal assembly input in subsequent indicator calculation processes.

[0089] Step 404: In response to determining that the target verification result is a failure, determine the quality inspection result as an alarm.

[0090] In this embodiment, the target verification result of the assembly constraint verification output is read to determine the verification status. If the result is marked as failing, it indicates that there are syntax, instruction, resource, or annotation violations in the assembly. At this time, the current quality detection result is directly determined as an alarm, and the error line number and violation type details of the verification output are attached simultaneously to block the subsequent performance index calculation process and output an alarm prompt.

[0091] By performing syntax, resource, and annotation rule checks on the assembly text beforehand, an alarm is directly triggered if the assembly text fails the check, thus avoiding the calculation of invalid performance indicators and ensuring the data validity and result reliability of subsequent dependent instructions in the analysis and performance statistics process.

[0092] In some optional implementations of the embodiments of this disclosure, the target verification result includes: distance constraint verification result, interval constraint verification result and / or count constraint verification result; and in response to determining that any one of the distance constraint verification result, interval constraint verification result and count constraint verification result is a failed verification, the target verification result is determined to be a failed verification.

[0093] In this implementation, during the target verification of the instruction assembly text, distance constraint verification, interval constraint verification, and count constraint verification are performed separately, resulting in three categories of verification results: distance constraint verification result, interval constraint verification result, and count constraint verification result. Then, these three categories of verification results are aggregated for judgment. If any one category of verification result indicates a failure, the overall target verification result is directly determined to be a failure; only when all three categories of verification results are successful is the target verification result considered successful. This aggregation logic implements an AND logic verification of multiple static assembly constraints. If any constraint condition is not met, the overall verification fails, ensuring that the instruction assembly text simultaneously meets all constraint requirements of the distance, interval, and count dimensions. Therefore, by jointly verifying the assembly text through multi-dimensional constraints, and ensuring that any constraint failure results in overall verification failure, it can comprehensively detect anomalies in instruction sequence position, interval, and count, improving the completeness and reliability of assembly verification.

[0094] In some optional implementations of the embodiments of this disclosure, when the target verification result includes a distance constraint verification result, step 403 may be performed as follows: taking the dependent instruction in the instruction sequence corresponding to the instruction assembly text as the starting position, and searching the instruction sequence backward from the next valid instruction at the starting position; in response to finding an instruction that matches the preset dependent instruction pattern within a preset distance range, determining that the distance constraint verification result corresponding to the current dependent instruction is verified as passed; in response to all distance constraint verification results corresponding to the dependent instructions in the instruction sequence being verified as passed, determining that the distance constraint verification result corresponding to the instruction assembly text is verified as passed.

[0095] In this implementation, distance constraint check (CHECK-WITHIN-N) is used to constrain the effective instruction distance between memory access instructions and synchronization barrier instructions. Its core function is to limit the number of operation instructions that can be accommodated between smp_tex (texture sampling memory access instruction) and DEPBAR (synchronization barrier), ensuring that the latency hiding capability is controllable.

[0096] The specific verification logic is as follows: scan the assembly and locate the line current_pos where smp_tex is located; traverse from current_pos+1 onwards; only count valid instructions, skip all NOPs, code comments, etc., and do not count them; if DEPBAR is found in the interval, the distance constraint verification passes; if DEPBAR is not matched after counting 20 valid instructions, the distance constraint verification fails.

[0097] In other words, when the target verification result includes the distance constraint verification result, the instruction sequence corresponding to the instruction assembly text is traversed. Each dependent instruction is used as the starting position for the search, and the search proceeds from the next valid instruction following the dependent instruction. For each dependent instruction, if an instruction matching the preset dependent instruction pattern is found within the preset valid instruction search range, the sub-item verification result corresponding to that dependent instruction is determined to be passed. Here, the preset dependent instruction pattern is a pre-configured matching rule used to identify dependent instructions. It uses instruction mnemonics, instruction feature bitmasks, etc., as matching elements to identify dependent instructions that form a dependency pair with the dependent instruction in the instruction sequence. This pattern is a static text matching rule used to locate instructions that match the dependent instruction characteristics from the assembly instruction sequence. It does not directly verify the hardware dependency behavior during the memory access task runtime; it only completes instruction-level pattern recognition.

[0098] If the individual verification results of all dependent instructions within the instruction sequence pass, the overall distance constraint verification result of the instruction assembly text is passed; if any dependent instruction fails to find an instruction matching the dependent instruction pattern within the preset distance range, the distance constraint verification result is failed. This method performs distance matching verification for each dependent instruction one by one, achieving full coverage checking of all dependent pairing positional relationships.

[0099] By searching backwards for matching dependent instruction patterns for each dependent instruction, the positional relationships of instructions are fully verified, ensuring that dependent pairings are within the legal instruction distance, thus improving the accuracy of static assembly verification.

[0100] In some optional implementations of the embodiments of this disclosure, when the target verification result includes the interval constraint verification result, step 403 may be performed as follows: determining the first boundary instruction position and the second boundary instruction position in the instruction sequence corresponding to the instruction assembly text, wherein the first boundary instruction position is the position of the instruction that matches the preset dependent instruction pattern, and the second boundary instruction position is the position of the instruction that matches the preset dependent instruction pattern; determining the target interval formed by the next valid instruction from the first boundary instruction position to the previous valid instruction from the second boundary instruction position; in response to determining that there is no instruction matching the preset prohibited instruction pattern within the target interval, determining that the interval constraint verification result corresponding to the target interval is verified; in response that the interval constraint verification results corresponding to all target intervals in the instruction sequence are verified, determining that the interval constraint verification result corresponding to the instruction assembly text is verified.

[0101] In this implementation, the interval constraint check (CHECK-NOT-BETWEEN) is an interval prohibition constraint syntax used to check the region between two target instructions, prohibiting the occurrence of instructions of a specified type. Since smp_tex memory access has high latency, inserting a branch jump in the middle will disrupt the instruction pipeline and weaken the latency hiding effect. This rule forces that no jump instructions can occur within this interval, avoiding scheduling performance loss.

[0102] The specific verification logic is as follows: First, locate the left boundary smp_tex and record the position prev_match_pos; then match the right boundary DEPBAR and record the position next_match_pos; traverse all valid instructions between the two; if any one of them is a branch instruction, the interval constraint verification fails; only when there is no matching branch throughout the entire process does the verification pass.

[0103] When the target verification result includes the interval constraint verification result, based on the preset dependent instruction pattern and dependent instruction pattern, the first boundary instruction position and the second boundary instruction position are located in the instruction sequence corresponding to the instruction assembly text, respectively, and the target interval between the two boundaries is defined. The system checks whether there is an instruction matching the preset prohibited instruction pattern within this target interval. If no prohibited instruction pattern is detected within the target interval, the sub-item verification result of the target interval is considered passed. The instruction sequence is traversed to obtain all target intervals. Only when the sub-item verification results of all target intervals are passed is the overall interval constraint verification result of the instruction assembly text determined to be passed; if a prohibited instruction pattern appears in any target interval, the interval constraint verification result is considered failed. This achieves a step-by-step screening of the intervals enclosed by each set of boundary instructions, avoiding illegal instructions within specified intervals, and ensuring that the scheduling window of the instruction sequence meets the constraint requirements.

[0104] By screening prohibited instructions one by one within the target intervals defined by each group boundary, and only when all intervals pass the verification, the system is deemed to have passed. This effectively avoids illegal instructions appearing in the scheduling window and ensures that the assembly instruction sequence conforms to scheduling constraints.

[0105] In some optional implementations of the embodiments of this disclosure, when the target verification result includes the counting constraint verification result, step 403 may be performed as follows: count the number of valid instructions that match the preset counting instruction pattern within the target interval; in response to the counted number of instructions being greater than or equal to a preset number threshold, determine that the counting constraint verification result corresponding to the target interval is verified; in response to the counting constraint verification results corresponding to all target intervals in the instruction sequence being verified, determine that the counting constraint verification result corresponding to the instruction assembly text is verified.

[0106] In this implementation, the counting constraint verification (CHECK-COUNT-GE) is a counting lower bound constraint syntax used to verify the minimum number of specified operation instructions between two instruction blocks, ensuring that there are sufficient computation instructions within the memory access latency window to mask the latency. Since smp_tex has high memory access latency, enough floating-point ALU operations must be padded in between. If the number is insufficient, the latency cannot be masked, and performance deteriorates. This rule is used to enforce a minimum computational load.

[0107] The specific verification logic is as follows: match the left boundary smp_tex record prev_match_pos, and match the right boundary wait record next_match_pos; traverse all valid instructions between the two, and count the number of matching fadd (Floating-point Add, floating-point addition instruction) / fmul (Floating-point Multiply, floating-point multiplication instruction) / fma (FusedMultiply-Add, fused multiply-add instruction) floating-point operation instructions; if the count is ≥15, the counting constraint verification passes; if it is less than 15, the verification fails.

[0108] When the target verification result includes the counting constraint verification result, for each target interval in the instruction sequence defined by preceding and following boundary instructions, the number of valid instructions matching the preset counting instruction pattern within the interval is counted. If the counted number of instructions is not less than the preset threshold, the sub-item verification result corresponding to the current target interval is considered passed. All target intervals in the processed instruction sequence are traversed, and the overall counting constraint verification result of the instruction assembly text is considered passed only if the sub-item verification results for all target intervals are passed; otherwise, the counting constraint verification result is considered failed if the number of matching instructions within any target interval does not reach the preset threshold. This process completes the verification of the number of valid instructions within each scheduling window, ensuring that the instruction sequence meets the scheduling fill quantity constraint conditions.

[0109] By counting the number of valid instructions matching the pattern within each target interval, and ensuring that all intervals pass the verification, the instruction filling amount within the scheduling window meets the requirements, thereby improving the verification reliability of the assembly sequence.

[0110] Afterwards, the verification results of the three types of checks will be read uniformly, and logical judgment will be executed: if any one of the distance, interval, or count checks fails, the overall target verification result will be judged as failing; only if all three types of checks pass will the overall verification result be marked as passing.

[0111] Finally, the error line numbers, violation rules, and abnormal values ​​of each of the three types of verifications are all collected and uploaded to the overall target verification result, which will serve as the basis for subsequent quality alarm judgments.

[0112] By performing layered verification of three types of assembly constraints—distance, interval, and count—if any one of the verifications fails, the entire verification is deemed to have failed. This multi-dimensional interception of instruction arrangement, operation filling, and jump violations, along with pre-filtering of unqualified assembly code, ensures the reliability of subsequent performance metric statistics.

[0113] Step 405: In response to the determination that both the comparison result of the statistical value and the preset statistical value and the target verification result are verified as passed, the quality inspection result is determined to be verified as passed.

[0114] In this embodiment, the assembly target verification results are read, and the current statistical values ​​are compared with the historical baseline to obtain the indicator comparison results. Only when the target verification passes and the performance indicator comparison results also pass (without alarms) is the overall quality test result determined to be passed.

[0115] The system double-checks assembly constraints and performance baselines, and only when both are qualified is the test considered passed. This allows for the simultaneous interception of both assembly violations and performance degradation issues, ensuring the compliance of shader code and the stability of scheduling performance.

[0116] According to the instruction scheduling quality detection method provided in this disclosure, three types of constraints—assembly execution distance, interval, and count—are checked. If the check fails, an alarm is directly output. If the assembly is compliant, the current indicators are compared with historical baselines. Only when both the assembly constraint check and the indicator baseline comparison are qualified is the quality detection considered passed. The dual-check mechanism simultaneously intercepts problems such as assembly writing violations, unreasonable instruction arrangement, and scheduling performance degradation, and automatically completes shader quality regression detection.

[0117] In some optional implementations of the embodiments of this disclosure, the above-mentioned method for detecting instruction scheduling quality further includes: determining the execution cycle of the target instruction based on a pre-constructed instruction cost dictionary; calculating the total execution cycle of all target instructions based on the execution cycle of the target instruction, and determining the total execution cycle as the weighted distance of the instruction pairs; and determining the alarm level information based on the weighted distance when the decrease in the average instruction value compared to the historical average instruction value exceeds a first preset range.

[0118] In this implementation, a pre-defined instruction cost dictionary is loaded, which stores the individual execution cycles corresponding to each ALU, memory access, and synchronization instruction. For an instruction pair (src, i_j), all valid instructions between the pair are traversed, and the cycle cost(alu_j) of each target instruction is obtained from the instruction cost dictionary. The execution cycles of all target instructions are then summed, and the total execution cycles obtained are used as the weighted distance WIPD(src, i_j) of the instruction pair. Therefore, WIPD(src, i_j) = WIPD represents the total statically estimated hidden cycles between SMP-WAIT intervals, and it reflects the delay-hiding effect more accurately than a simple count. In this embodiment, IPD and WIPD are calculated simultaneously and used complementarily: IPD is intuitive and easy to understand, while WIPD has higher accuracy.

[0119] The instruction cost dictionary is a configuration mapping table used for weighted distance calculation. It is predefined by the policy configuration file in conjunction with the GPU hardware architecture. Its core function is to assign corresponding hardware execution cycles to different computation instructions. Instead of simply counting the number of instructions, it uses the actual hardware time consumption to quantify the computational fill capability between instruction pairs, making the distance evaluation more in line with the actual hardware performance.

[0120] As an example, the instruction cost dictionary contains the following typical values: (1) Simple instructions such as integer addition, shifting, and data transfer, iadd / ishl / mov, can be completed in a single hardware cycle, with the lowest computational cost. The execution cycle of this type of instruction is 1 cycle.

[0121] (2) Floating-point addition and floating-point multiplication fadd / fmul have a longer pipeline time, with an execution cycle of 2 cycles, meaning that a single operation occupies 2 hardware cycles.

[0122] (3) Multiplication and addition fusion, three-dimensional / four-dimensional dot product complex floating-point operations fma / dp3 / dp4, the calculation link is longer, and its execution cycle is 4 cycles, that is, a single link occupies 4 hardware cycles.

[0123] (4) Transcendental functions such as trigonometric functions and reciprocal square roots sin / cos / rsq have the largest hardware computing unit overhead, and their execution cycle is 8 cycles, that is, a single function consumes 8 cycles.

[0124] Next, the current average weighted distance (WIPD) is compared with the historical baseline. If the decrease does not exceed a first preset threshold, no tiered alarm is triggered. If the decrease exceeds the first preset threshold, the alarm level is determined based on the weighted distance value range of the command pair. Here, multiple weighted distance ranges are pre-defined based on hardware standards, and corresponding alarm levels (e.g., minor / moderate / severe) are bound to them. Then, the current WIPD is retrieved, matched to its corresponding range, and a corresponding alarm level is generated. Finally, the weighted distance value, decrease, corresponding alarm level, and location of the violation command pair are integrated and stored in the alarm details.

[0125] Calculating the weighted distance based on the hardware instruction cycle dictionary can accurately reflect the actual computation time. When the average weighted distance deteriorates beyond a threshold, the weighted distance is classified into alarm levels based on the instructions, thereby differentiating the severity of performance defects and facilitating the priority repair of high-risk shaders, thus improving the efficiency of performance problem investigation and rectification.

[0126] In some optional implementations of the embodiments of this disclosure, the statistical values ​​further include: instruction value standard deviation and fill rate; and step 102 can be performed as follows: generating instruction value standard deviation based on the standard deviation operator and the average instruction value; generating fill rate based on the weighted distance of all instruction pairs and the memory access latency of all dependent instructions.

[0127] In this implementation, the statistical values ​​include two types of indicators: the standard deviation of instruction values ​​and the fill rate. During the indicator generation process, the standard deviation operator is called to combine the calculated average instruction value to generate the instruction value standard deviation STD_IPD. This standard deviation characterizes the degree of discrete fluctuation in the instruction interval. The formula for calculating STD_IPD is: STD_IPD = (IPD_i), STD_IPD reflects the uniformity of scheduling. The smaller the value, the smaller the difference in the number of operation instructions filled between each memory access synchronization instruction pair, the more uniform the pipeline load, and the more stable the latency masking. The larger the value, the more uneven the filling amount between instruction pairs, and the less operation in some windows, which can easily lead to performance bottlenecks.

[0128] Then, based on the weighted sum of distances for all instruction pairs and the memory access latency for all dependent instructions, the fill rate (FILL_RATE) is calculated. The fill rate characterizes the instruction fill level of the memory access scheduling window. The formula for FILL_RATE is: FILL_RATE = / LATENCY_i represents the inherent hardware memory access latency of the i-th memory access instruction. The fill rate is calculated by summing the latency cycles of all memory access instructions. It represents the ratio of the total computation cycle time to the total memory access latency cycle, used to measure the ability of computation to mask memory access latency. The process iterates through all instruction pairs and dependent instructions in the instruction sequence to calculate and output the two types of statistical indicators mentioned above, providing quantitative statistical basis for subsequent test case quality comparison and detection.

[0129] By calculating the standard deviation of instruction values ​​and the fill rate, we can quantitatively characterize the fluctuation of instruction spacing and the filling level of the scheduling window, providing objective and comparable quantitative indicators for the quality evaluation of test cases.

[0130] In some optional implementations of the embodiments of this disclosure, the historical statistical values ​​further include: the standard deviation of historical command values ​​and the historical fill rate; and step 103 can be executed as follows: if the increase in the standard deviation of the command value compared with the standard deviation of the historical command value exceeds a fourth preset range, the quality detection result is determined to be an alarm; or if the decrease in the fill rate compared with the historical fill rate exceeds a fifth preset range, the quality detection result is determined to be an alarm.

[0131] In this implementation, historical statistics include the standard deviation of historical instruction values ​​and the historical fill rate. When conducting test case quality inspection, the standard deviation of the instruction value of the test case is compared with the standard deviation of historical instruction values. If the increase in the standard deviation of the instruction value relative to the standard deviation of historical instruction values ​​exceeds a fourth preset range, an alarm quality inspection result is output. Alternatively, the fill rate of the test case is compared with the historical fill rate. When the decrease in the fill rate relative to the historical fill rate exceeds a fifth preset range, the quality inspection result is also determined to be an alarm. By judging the magnitude deviation of these two indicators, the system can capture situations where the instruction interval dispersion increases abnormally and the scheduling window fill level decreases abnormally, thereby achieving the identification and early warning of test case quality degradation.

[0132] In some implementations, a weighted average spacing AVG_WIPD is also calculated. AVG_WIPD reflects the overall latency hiding capability of the shader (estimated number of cycles), and its calculation formula is: AVG_WIPD = This involves summing the total hardware cycle time for each instruction pair and dividing by the total number of instruction pairs to obtain the global average computation fill time, which measures the shader's overall ability to mask memory access latency. By calculating these metrics, the accuracy of the evaluation results is improved, avoiding misjudgments based on a single indicator.

[0133] In some optional implementations of the embodiments of this disclosure, the above-mentioned method for detecting instruction scheduling quality further includes: in response to determining that the quality detection result is an alarm, determining the cause of the problem and the repair suggestion corresponding to the quality detection result; and generating a regression result report based on the information of the test cases, statistical values, target verification results, quality detection results, cause of the problem and repair suggestions.

[0134] In this implementation, when a quality inspection result is determined to be an alarm, a preset fault knowledge base is first matched based on the quality inspection result. This, combined with abnormal constraint verification items, AVG_WIPD, STD_IPD, FILL_RATE, and other indicators, automatically deduce the corresponding root cause of the problem. Simultaneously, standardized repair suggestions are matched and bound. For example, if the fill rate is low, it is determined that the memory access window computation is insufficient, and an optimization scheme to supplement high-overhead floating-point operations is provided. Subsequently, the test case number, source code path, various performance statistics, distance interval counts, three types of constraint verification details, overall pass or alarm quality conclusion, identified problem causes, and corresponding repair suggestions are integrated. All materials are uniformly summarized, and a complete regression result report is automatically generated according to a fixed template. The report fully retains all dimensions of the inspection data, facilitating developers to locate performance defects and archive version regression records.

[0135] This allows for the identification of performance root causes based on detected anomalies and the output of standardized remediation solutions. It also integrates all data, including test cases, constraint verification, and multi-dimensional performance indicators, to automatically generate regression reports. This achieves integrated problem identification, solution output, and report archiving, reducing manual analysis costs, facilitating rapid rectification by R&D teams, and ensuring complete retention of version regression test data.

[0136] In some optional implementations of the embodiments of this disclosure, the dependent instruction includes a delay instruction, and the dependent instruction includes a wait instruction or an ALU instruction that waits for a non-zero bitmask.

[0137] In this implementation, instructions with hardware latency, such as texture sampling and memory reads, are marked as dependent instructions. Then, wait synchronization instructions and ALU operation instructions with non-zero wait bitmasks that require blocking and waiting for preceding memory accesses to complete are identified as dependent instructions. These are paired to form complete memory access latency instruction pairs, used for subsequent calculations of metrics such as weighted distance and fill rate. This accurately distinguishes memory access latency sources from blocking and waiting instructions, completely identifies all instruction pairs with data dependencies, avoids missing dependencies, and ensures the completeness and accuracy of performance metric calculations such as AVG_WIPD and fill rate.

[0138] Furthermore, it should be noted that the measurement and constraint framework in this embodiment is compatible with hardware synchronization mechanisms of different manufacturers and different generations of GPU architectures. It performs differentiated adaptation for the native memory access wait syntax of various ISAs, uniformly extracts dependent instruction pairs and corrects the indicator calculation logic, thereby solving the problem of evaluation standard failure caused by inconsistent scheduling logic of different GPUs.

[0139] In this embodiment, multi-strategy adaptation capability can be achieved simply by switching configuration files, without rewriting the detection logic for each architecture. Specifically, a scheduling detection strategy configuration file for multi-GPU architecture adaptation can be pre-configured, bound to the target hardware architecture gpu_arch_v2, and uniformly defining the dependency instruction matching rules and lower limit constraints of the three types of synchronization mechanisms for automatically extracting instruction pairs and performing static constraint verification. The configuration file externalizes the matching logic and constraint thresholds of different ISAs, allowing adaptation to new GPU architectures without modifying the detection code; during parsing, corresponding dependency instruction pairs are extracted by strategy group, and their minimum average weighted distance is verified separately, taking into account the scheduling characteristics of different hardware synchronization mechanisms, uniformly completing static constraint verification, and ensuring that the metric standard conforms to the corresponding GPU hardware pipeline capability.

[0140] Please refer to Figure 5 , Figure 5 A flowchart illustrating the application of the instruction scheduling quality detection method provided in this embodiment of the disclosure, wherein process 500 includes the following steps: Step 501: Obtain the shader source code, which includes shader source code in formats such as HLSL, GLSL, and SPIR-V.

[0141] Step 502: Input the Shader source code into the GPU compiler backend so that the GPU compiler backend can compile the source code.

[0142] Step 503: Output the generated ISA assembly.

[0143] Steps 504-506 constitute the performance quantification process, specifically: Step 504: Identify SMP-WAIT instruction pairs using the instruction pair extractor. That is, the instruction pair extractor identifies all instruction pairs consisting of SMP, memory access instructions, and WAIT / DEPBAR wait instructions to obtain the SMP-WAIT instruction pairs.

[0144] Step 505: Calculate the effective ALU instruction count using the spacing metric calculation unit. This involves using the spacing metric calculation unit to calculate the effective ALU instruction count and cycle time, based on the hardware instruction cost, to determine scheduling metrics such as AVG_WIPD, STD_IPD, and FILL_RATE.

[0145] Step 506: Baseline Comparison Engine compares with historical data / thresholds. The calculated scheduling metrics data are input into the baseline comparison engine, which compares them with historical version baselines and architectural thresholds. Based on the comparison results, it determines whether there is scheduling performance degradation and obtains the performance comparison results.

[0146] Steps 507-508 constitute the static constraint verification chain, specifically: Step 507: The declarative constraint verifier verifies each hard constraint, such as assembly synchronization instructions, instruction spacing, and barrier thresholds, based on the extended FileCheck (a text pattern verification tool built into the LLVM compiler suite, used to verify whether the compiler output assembly / IR conforms to the expected format, instruction order, and operand rules) semantics and GPU architecture scheduling rule configuration file.

[0147] Step 508: Output constraint verification results, which are PASS / FAIL results with detailed violation information.

[0148] Step 509: Summarize the performance comparison results output in Step 506 and the constraint verification results output in Step 508 to generate a regression test report. This includes compiling the performance degradation judgment results from the baseline comparison, compliance details of the constraint verification, various scheduling statistics, root causes of problems, and standardized remediation suggestions, generating a unified standardized regression test report.

[0149] Step 510: CI / CD automated access control, that is, the entire detection process is integrated into the CI / CD pipeline. Every time the code is committed, the full-link detection will be automatically and completely executed, and it is divided into two processing branches: if the verification detects regression problems such as scheduling degradation or constraint failure, then step 511 is executed; if all indicators and constraint verifications pass, then step 512 is executed.

[0150] Step 511: Trigger an alarm (meaning scheduling quality has degraded), mark the abnormal instruction pairs and weighted distance changes, and block the code from being merged.

[0151] Step 512: CI access control gives the green light, and the code is committed and merged normally.

[0152] The entire solution does not require GPU hardware to run. It achieves automated control of shader scheduling quality based on static assembly analysis, taking into account both hard syntax constraint verification and hardware scheduling performance quantitative evaluation, thus avoiding the performance degradation problem caused by iteration in advance.

[0153] Further reference Figure 6 As an implementation of the methods shown in the above figures, this disclosure provides an embodiment of an instruction scheduling quality detection device, which is similar to... Figure 1 The illustrated method for detecting instruction scheduling quality corresponds to the example.

[0154] like Figure 6 As shown, the instruction scheduling quality detection device 600 of this embodiment may include: an instruction pair determination module 601, a statistical value generation module 602, and a detection result determination module 603. The instruction pair determination module 601 is configured to determine instruction pairs with dependencies from the instruction assembly text of the current round of detection. The instruction assembly text is obtained by compiling test cases. An instruction pair includes a dependent instruction and a dependent instruction. The dependency relationship is used to characterize whether, in response to the execution of the dependent instruction, instructions downstream of the dependent instruction are blocked or allowed based on the completion status of the memory access task initiated by the dependent instruction. The statistical value generation module 602 is configured to generate a statistical value of a preset index based on the number of target instructions located between the dependent instruction and the dependent instruction. The detection result determination module 603 is configured to determine the quality detection result of the test case based on the comparison result of the statistical value and the preset statistical value.

[0155] In some optional implementations of the embodiments of this disclosure, the specific processing of the determination module 601, the statistical value generation module 602, and the detection result determination module 603, and the resulting technical effects, can be referred to respectively. Figure 1 The relevant descriptions of steps 101-103 in the corresponding embodiments will not be repeated here.

[0156] In some optional implementations of the embodiments of this disclosure, the instruction pair determination module 601 includes: a parsing submodule, configured to parse the instruction assembly text of the current round of detection process and construct a structured instruction sequence based on the parsing result; an instruction storage submodule, configured to store the first instruction into a matching stack in response to determining that the first instruction is a dependent instruction from the instruction sequence; and an instruction acquisition submodule, configured to acquire a third instruction dependent on the second instruction from the matching stack in response to determining that the second instruction is a dependent instruction from the instruction sequence, wherein the second instruction and the third instruction constitute an instruction pair with a dependency relationship.

[0157] In some optional implementations of the embodiments of this disclosure, the instruction scheduling quality detection device 600 may further include: a counting module (not shown in the figure), configured to extract a barrier identifier from the parameter information of the first instruction and update the value of the counter corresponding to the barrier identifier in response to determining that the first instruction is a dependent instruction from the instruction sequence; and an instruction storage submodule is further configured to store the first instruction, the barrier identifier of the first instruction, and the position index of the first instruction in the instruction sequence into the matching stack.

[0158] In some optional implementations of the embodiments of this disclosure, the instruction acquisition submodule is further configured to: determine the barrier identifier of the third instruction from the parameter information of the second instruction, and obtain the current value of the counter corresponding to the barrier identifier of the third instruction and the threshold; in response to determining that the current value is greater than the threshold, obtain all third instructions from the matching stack according to the barrier identifier of the third instruction, and retrieve a target number of third instructions from all the third instructions according to the instruction storage time, wherein the target number is the difference between the current value and the threshold.

[0159] In some optional implementations of the embodiments of this disclosure, the instruction scheduling quality detection device 600 may further include: a first instruction determination module (not shown in the figure), configured to determine all arithmetic logic unit (ALU) instructions located between the dependent instruction and the dependent instruction; and a second instruction determination module (not shown in the figure), configured to filter out instructions of a preset type from all ALU instructions, and the resulting valid ALU instruction is the target instruction.

[0160] In some optional implementations of the embodiments of this disclosure, the first instruction determination module is further configured to: in response to determining that the dependent instruction and the dependent instruction are located in the same code block, determine all ALU instructions according to a first position index and a second position index, wherein the first position index is the position index of the dependent instruction in the instruction sequence, and the second position index is the position index of the dependent instruction in the instruction sequence.

[0161] In some optional implementations of the embodiments of this disclosure, the first instruction determination module is further configured to: in response to determining that the dependent instruction and the dependent instruction are located in different code blocks, determine all candidate paths between the first code block where the dependent instruction is located and the second code block where the dependent instruction is located; determine the target path from all candidate paths according to the number of ALU instructions contained in the candidate paths; and determine the ALU instructions contained in the target path as all ALU instructions.

[0162] In some optional implementations of the embodiments of this disclosure, there are multiple instruction pairs; the statistical values ​​include: average instruction value, minimum instruction value, and percentage of instructions below a threshold; and the statistical value generation module is further configured to: generate an average instruction value based on the number of target instructions between dependent instructions and dependent instructions in each instruction pair; determine the minimum value from the number of target instructions in all instruction pairs to obtain the minimum instruction value; determine target instruction pairs from multiple instruction pairs whose number of target instructions is less than a preset threshold, and calculate the ratio of the number of target instruction pairs to the number of all instruction pairs to obtain the percentage of instructions below a threshold.

[0163] In some optional implementations of the embodiments of this disclosure, the preset statistical value is a historical statistical value generated by the historical round detection process. The historical statistical value includes: historical average instruction value, historical minimum instruction value, and historical percentage value. The detection result determination module is further configured to: determine the quality detection result as an alarm when the decrease in the average instruction value compared to the historical average instruction value exceeds a first preset range; or determine the quality detection result as an alarm when the decrease in the minimum instruction value compared to the historical minimum instruction value exceeds a second preset range; or determine the quality detection result as an alarm when the increase in the percentage value of instructions below the threshold compared to the historical percentage value exceeds a third preset range.

[0164] In some optional implementations of the embodiments of this disclosure, the instruction scheduling quality detection device 600 may further include: a constraint verification module (not shown in the figure), configured to perform constraint verification on the instruction assembly text to obtain a target verification result; and in response to determining that the target verification result is a failure verification, determining the quality detection result as an alarm.

[0165] In some optional implementations of the embodiments of this disclosure, the detection result determination module is further configured to: determine the quality detection result as passed in response to determining that both the comparison result and the target verification result are verified.

[0166] In some optional implementations of the embodiments of this disclosure, the target verification result includes: distance constraint verification result, interval constraint verification result and / or count constraint verification result; and the above-mentioned instruction scheduling quality detection device 600 may further include: a constraint verification result determination module (not shown in the figure), configured to determine the target verification result as failing verification in response to determining that any one of the distance constraint verification result, interval constraint verification result and count constraint verification result is failing verification.

[0167] In some optional implementations of the embodiments of this disclosure, when the target verification result includes a distance constraint verification result, the constraint verification module is further configured to: take the dependent instruction in the instruction sequence corresponding to the instruction assembly text as the starting position, and search the instruction sequence backward from the next valid instruction at the starting position; in response to finding an instruction that matches the preset dependent instruction pattern within a preset distance range, determine that the distance constraint verification result corresponding to the current dependent instruction is verified as passed; in response to all distance constraint verification results corresponding to the dependent instructions in the instruction sequence being verified as passed, determine that the distance constraint verification result corresponding to the instruction assembly text is verified as passed.

[0168] In some optional implementations of the embodiments of this disclosure, when the target verification result includes the interval constraint verification result, the constraint verification module is further configured to: determine the first boundary instruction position and the second boundary instruction position in the instruction sequence corresponding to the instruction assembly text, wherein the first boundary instruction position is the position of the instruction that matches the preset dependent instruction pattern, and the second boundary instruction position is the position of the instruction that matches the preset dependent instruction pattern; determine the target interval formed by the next valid instruction from the first boundary instruction position to the previous valid instruction from the second boundary instruction position; in response to determining that there is no instruction matching the preset prohibited instruction pattern within the target interval, determine that the interval constraint verification result corresponding to the target interval is verified; in response that the interval constraint verification results corresponding to all target intervals in the instruction sequence are verified, determine that the interval constraint verification result corresponding to the instruction assembly text is verified.

[0169] In some optional implementations of the embodiments of this disclosure, when the target verification result includes the counting constraint verification result, the constraint verification module is further configured to: count the number of valid instructions matching a preset counting instruction pattern within the target interval; determine that the counting constraint verification result corresponding to the target interval is passed if the counted number of instructions is greater than or equal to a preset number threshold; and determine that the counting constraint verification result corresponding to the instruction assembly text is passed if the counting constraint verification result corresponding to all target intervals in the instruction sequence is passed.

[0170] In some optional implementations of the embodiments of this disclosure, the instruction scheduling quality detection device 600 may further include: an alarm level determination module (not shown in the figure), configured to determine the execution cycle of a target instruction based on a pre-built instruction cost dictionary; calculate the total execution cycle of all target instructions based on the execution cycle of the target instruction, and determine the total execution cycle as the weighted distance of the instruction pairs; and determine alarm level information based on the weighted distance when the decrease in the average instruction value compared to the historical average instruction value exceeds a first preset range.

[0171] In some optional implementations of the embodiments of this disclosure, the statistical values ​​further include: instruction value standard deviation and fill rate; and the statistical value generation module is further configured to: generate instruction value standard deviation based on the standard deviation operator and the average instruction value; and generate fill rate based on the weighted distance of all instruction pairs and the memory access latency of all dependent instructions.

[0172] In some optional implementations of the embodiments of this disclosure, the historical statistical values ​​further include: the standard deviation of historical command values ​​and the historical fill rate; and the detection result determination module is further configured to: determine the quality detection result as an alarm when the increase of the standard deviation of the command value compared with the standard deviation of the historical command value exceeds a fourth preset range; or determine the quality detection result as an alarm when the decrease of the fill rate compared with the historical fill rate exceeds a fifth preset range.

[0173] In some optional implementations of the embodiments of this disclosure, the above-mentioned instruction scheduling quality detection device 600 may further include: a report generation module (not shown in the figure), configured to, in response to determining that the quality detection result is an alarm, determine the cause of the problem and the repair suggestion corresponding to the quality detection result; and generate a regression result report based on the test case information, statistical values, target verification results, quality detection results, cause of the problem and repair suggestion.

[0174] In some optional implementations of the embodiments of this disclosure, the dependent instruction includes a delay instruction, and the dependent instruction includes a wait instruction or an ALU instruction that waits for a non-zero bitmask.

[0175] This embodiment exists as a device 600 embodiment corresponding to the above method embodiment. The key steps or equivalent technical means that can be implemented by each component of the instruction scheduling quality detection device 600 embodiment provided in this embodiment, as well as the technical effects brought about by this device embodiment, can be referred to the relevant descriptions in the above method embodiments, and will not be repeated here.

[0176] According to embodiments of the present disclosure, the present disclosure also provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform an instruction scheduling quality detection method as described in any implementation of the first aspect.

[0177] According to embodiments of this disclosure, this disclosure also provides a non-transitory computer-readable storage medium storing computer instructions thereon, which, when executed by a processor, can implement the instruction scheduling quality detection method described in any of the above embodiments.

[0178] For example, the computer instructions corresponding to the instruction scheduling quality detection method in this embodiment can be stored on storage media such as optical discs, hard disks, and USB flash drives. When the computer instructions corresponding to the instruction scheduling quality detection method in the storage media are read or executed by a computer, the instruction scheduling quality detection method as described in any of the above embodiments can be implemented.

[0179] According to embodiments of this disclosure, this disclosure also provides a computer program product including a computer program that, when executed by a processor, can implement the instruction scheduling quality detection method described in any of the above embodiments.

[0180] Figure 7 A schematic block diagram of an example electronic device 700 that can be used to implement embodiments of the present disclosure is shown. The electronic device 700 proposed in embodiments of the present disclosure includes a processor 701 and a memory 702 storing an executable computer program. The processor 701, when executing the executable computer program stored in the memory 702, implements the instruction scheduling quality detection method provided in embodiments of the present disclosure.

[0181] In some optional implementations of the embodiments of this disclosure, the electronic device 700 may further include a communication interface 703 and a bus 704 for connecting the processor 701, the memory 702 and the communication interface 703.

[0182] In some optional implementations of the embodiments of this disclosure, bus 704 is used to connect communication interface 703, processor 701 and memory 702 to realize mutual communication between these devices.

[0183] In some optional implementations of the embodiments of this disclosure, the processor 701 may be at least one of the following: Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor. It is understood that, for different devices, the electronic device used to implement the function of the processor 701 may also be other, and the embodiments of this disclosure do not specifically limit it.

[0184] The aforementioned memory 702 is used to store executable computer programs and data. The executable computer program includes computer operation instructions. Memory 702 may include high-speed RAM and may also include non-volatile memory, such as at least two disk drives. In practical applications, the aforementioned memory 702 can be volatile memory, such as random-access memory (RAM); or non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); or a combination of the above types of memory, and provides executable computer programs and data to the processor.

[0185] Furthermore, the functional modules in this embodiment can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional module.

[0186] If the integrated units described above are implemented as software functional modules and not sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure embodiment, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the method of this disclosure embodiment. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0187] According to the technical solution of this disclosure, the dependent instruction pairs consisting of delayed memory access instructions and synchronous wait instructions are automatically identified based on the instruction assembly text generated by compiling test cases. This eliminates the need for manual analysis of each assembly instruction, significantly reducing manual parsing costs and improving the automation and consistency of dependency extraction. Then, standardized preset indicators are generated by statistically analyzing the number of target instructions between dependent and dependent instructions. This allows for the calculation of the interval between instruction pairs without running shaders on a real GPU, eliminating dependence on scarce GPU hardware resources and avoiding biases caused by subjective human judgment. Finally, the real-time indicator statistics are compared with preset statistical benchmarks. Based on the comparison results, the detection value of test cases can be quickly distinguished, automatically filtering out test cases that expose scheduling defects and eliminating inefficient test cases with insufficient discriminative power. This optimizes the overall quality of the test case set, improves the detection efficiency of instruction scheduling instructions for test cases, and consequently improves the efficiency of subsequent compiler performance iterations and defect localization.

[0188] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0189] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this disclosure, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0190] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0191] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for detecting instruction scheduling quality, characterized in that, The method includes: Determine the instruction pairs with dependencies from the instruction assembly text of the current round of detection process. The instruction assembly text is obtained by compiling the test cases. Each instruction pair includes a dependent instruction and a dependent instruction. The dependency relationship is used to characterize the blocking or allowing of instructions downstream of the dependent instruction in response to the execution of the dependent instruction, based on the completion status of the memory access task initiated by the dependent instruction. Based on the number of target instructions located between the dependent instruction and the dependent instruction, a statistical value of a preset indicator is generated. The quality inspection result of the test case is determined based on the comparison between the statistical value and the preset statistical value.

2. The method according to claim 1, characterized in that, The step of identifying dependent instruction pairs from the instruction assembly text of the current round of detection includes: The instruction assembly text of the current round of detection process is parsed, and a structured instruction sequence is constructed based on the parsing results; In response to determining from the instruction sequence that the first instruction is the dependent instruction, the first instruction is stored in the matching stack; In response to determining that the second instruction is the dependent instruction from the instruction sequence, a third instruction that the second instruction depends on is obtained from the matching stack, wherein the second instruction and the third instruction constitute the instruction pair with the dependency relationship.

3. The method according to claim 2, characterized in that, The method further includes: Extract the barrier identifier from the parameter information of the first instruction, and update the value of the counter corresponding to the barrier identifier; and The step of storing the first instruction into the matching stack includes: The first instruction, the barrier identifier of the first instruction, and the position index of the first instruction in the instruction sequence are stored in the matching stack.

4. The method according to claim 3, characterized in that, The step of obtaining the third instruction that the second instruction depends on from the stack to be matched includes: The barrier identifier of the third instruction is determined from the parameter information of the second instruction, and the current value and threshold of the counter corresponding to the barrier identifier of the third instruction are obtained. In response to determining that the current value is greater than the threshold, all third instructions are retrieved from the matching stack according to the barrier identifier of the third instruction, and a target number of third instructions are retrieved from all the third instructions according to the instruction storage time, wherein the target number is the difference between the current value and the threshold.

5. The method according to claim 3, characterized in that, The method further includes: Identify all arithmetic logic unit (ALU) instructions located between the dependent instruction and the dependent instruction; The target instruction is obtained by filtering out the preset type of instructions from all ALU instructions and obtaining the valid ALU instructions.

6. The method according to claim 5, characterized in that, The determination of all arithmetic logic unit (ALU) instructions located between the dependent instruction and the dependent instruction includes: In response to determining that the dependent instruction and the dependent instruction are located in the same code block, all ALU instructions are determined according to a first position index and a second position index, wherein the first position index is the position index of the dependent instruction in the instruction sequence, and the second position index is the position index of the dependent instruction in the instruction sequence.

7. The method according to claim 5, characterized in that, The determination of all arithmetic logic unit (ALU) instructions located between the dependent instruction and the dependent instruction includes: In response to determining that the dependent instruction and the dependent instruction are located in different code blocks, all candidate paths between the first code block where the dependent instruction is located and the second code block where the dependent instruction is located are determined; The target path is determined from all candidate paths based on the number of ALU instructions contained in the candidate paths; The ALU instructions contained in the target path are identified as all ALU instructions.

8. The method according to claim 1, characterized in that, The instruction pairs are multiple; the statistical values ​​include: average instruction value, minimum instruction value, and the percentage of instructions below a threshold; and The step of generating statistical values ​​for a preset metric based on the number of target instructions located between the dependent instruction and the dependent instruction includes: The average instruction value is generated based on the number of target instructions between the dependent and dependent instructions in each instruction pair. The minimum instruction value is obtained by determining the minimum number of target instructions from all instruction pairs; From multiple instruction pairs, determine the target instruction pairs whose number of target instructions is less than a preset threshold, and calculate the ratio of the number of target instruction pairs to the number of all instruction pairs to obtain the percentage of instructions below the threshold.

9. The method according to claim 8, characterized in that, The preset statistical values ​​are historical statistical values ​​generated during the historical rounds of detection. These historical statistical values ​​include: historical average command value, historical minimum command value, and historical percentage value; and The step of determining the quality inspection result of the test case based on the comparison result between the statistical value and the preset statistical value includes: If the decrease in the average command value compared to the historical average command value exceeds a first preset range, the quality detection result is determined to be an alarm; or If the decrease in the minimum instruction value compared to the historical minimum instruction value exceeds a second preset range, the quality detection result is determined to be an alarm; or If the percentage of instructions below the threshold increases by more than a third preset range compared to the historical percentage, the quality detection result is determined to be an alarm.

10. The method according to claim 1, characterized in that, The method further includes: The constraint verification is performed on the instruction assembly text to obtain the target verification result; In response to determining that the target verification result is a failure, the quality inspection result is determined to be an alarm.

11. The method according to claim 10, characterized in that, The step of determining the quality inspection result of the test case based on the comparison result between the statistical value and the preset statistical value includes: In response to determining that both the comparison result and the target verification result have passed verification, the quality inspection result is determined to have passed verification.

12. The method according to claim 10, characterized in that, The target verification results include: distance constraint verification results, interval constraint verification results, and / or count constraint verification results; and The method further includes: In response to determining that any one of the distance constraint verification result, the interval constraint verification result, and the count constraint verification result is a failed verification, the target verification result is determined to be a failed verification.

13. The method according to claim 12, characterized in that, When the target verification result includes the distance constraint verification result, the constraint verification of the instruction assembly text to obtain the target verification result includes: Using the dependent instruction in the instruction sequence corresponding to the instruction assembly text as the starting position, the instruction sequence is retrieved backward from the next valid instruction at the starting position; In response to the discovery of an instruction that matches a preset dependent instruction pattern within a preset distance range, the distance constraint verification result corresponding to the currently dependent instruction is determined to be passed. If the distance constraint verification results for all dependent instructions in the instruction sequence are passed, then the distance constraint verification result for the instruction assembly text is determined to be passed.

14. The method according to claim 12, characterized in that, When the target verification result includes the interval constraint verification result, the constraint verification of the instruction assembly text to obtain the target verification result includes: In the instruction sequence corresponding to the instruction assembly text, a first boundary instruction position and a second boundary instruction position are determined, wherein the first boundary instruction position is the position of the instruction that matches the preset dependent instruction pattern, and the second boundary instruction position is the position of the instruction that matches the preset dependent instruction pattern. Determine the target interval formed by the next valid instruction at the first boundary instruction position and the previous valid instruction at the second boundary instruction position; In response to determining that there is no instruction matching the preset prohibited instruction pattern within the target interval, the interval constraint verification result corresponding to the target interval is determined to be verified as passed; If the interval constraint verification results corresponding to all target intervals in the instruction sequence are all verified as passed, then the interval constraint verification result corresponding to the instruction assembly text is determined to be passed.

15. The method according to claim 14, characterized in that, When the target verification result includes the count constraint verification result, the constraint verification of the instruction assembly text to obtain the target verification result includes: Count the number of valid instructions that match the preset counting instruction pattern within the target interval; If the number of instructions obtained from statistics is greater than or equal to a preset number threshold, the counting constraint verification result corresponding to the target interval is determined to be verified as passed. If the counting constraint verification results for all target intervals in the instruction sequence are verified as passed, the counting constraint verification result for the instruction assembly text is determined to be passed.

16. The method according to claim 9, characterized in that, The method further includes: The execution cycle of the target instruction is determined based on a pre-built instruction cost dictionary; Calculate the total execution cycle of all target instructions based on the execution cycle of the target instruction, and determine the total execution cycle as the weighted distance of the instruction pair; If the decrease in the average command value compared to the historical average command value exceeds the first preset range, the alarm level information is determined based on the weighted distance.

17. The method according to claim 16, characterized in that, The statistical values ​​also include: the standard deviation of the command value and the fill rate; and The step of generating statistical values ​​for a preset metric based on the number of target instructions located between the dependent instruction and the dependent instruction includes: The standard deviation of the instruction value is generated based on the standard deviation operator and the average instruction value; The fill rate is generated based on the weighted distance of all instruction pairs and the memory access latency of all dependent instructions.

18. The method according to claim 17, characterized in that, The historical statistics also include: the standard deviation of historical command values ​​and the historical fill rate; and The step of determining the quality inspection result of the test case based on the comparison result between the statistical value and the preset statistical value includes: If the increase in the standard deviation of the command value compared to the standard deviation of the historical command values ​​exceeds a fourth preset range, the quality inspection result is determined to be an alarm; or If the decrease in the fill rate compared to the historical fill rate exceeds a fifth preset range, the quality inspection result is determined to be an alarm.

19. The method according to claim 10, characterized in that, The method includes: In response to determining that the quality inspection result is the alarm, determine the cause of the problem corresponding to the quality inspection result and the repair suggestions; A regression result report is generated based on the information of the test cases, the statistical values, the target verification results, the quality inspection results, the causes of the problems, and the remediation suggestions.

20. The method according to any one of claims 1-19, characterized in that, The dependent instruction includes a delay instruction, and the dependent instruction includes a wait instruction or an ALU instruction with a non-zero wait bitmask.

21. A device for detecting instruction scheduling quality, characterized in that, The device includes: The instruction pair determination module is configured to determine instruction pairs with dependencies from the instruction assembly text of the current round of detection process. The instruction assembly text is obtained by compiling test cases. An instruction pair includes a dependent instruction and a dependent instruction. The dependency relationship is used to characterize whether to block or allow instructions located downstream of the dependent instruction in response to the execution of the dependent instruction, based on the completion status of the memory access task initiated by the dependent instruction. The statistical value generation module is configured to generate statistical values ​​of a preset index based on the number of instructions of the target instruction located between the dependent instruction and the dependent instruction. The test result determination module is configured to determine the quality test result of the test case based on the comparison result between the statistical value and the preset statistical value.

22. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the instruction scheduling quality detection method according to any one of claims 1-20.

23. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the processor to execute the instruction scheduling quality detection method according to any one of claims 1-20.

24. A computer program product, characterized in that, The method includes a computer program that, when executed by a processor, implements the method for detecting instruction scheduling quality according to any one of claims 1-20.

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