Storage device, processor, apparatus, server cluster and access method

Abstract

The application discloses a storage device, a processor, a device, a server cluster and an access method. The device comprises an allocation unit, a mapping unit and a memory. The allocation unit is configured to receive a thread allocation request corresponding to a first thread; allocate a first storage space and a second storage space in the memory for the first thread based on the thread allocation request; the mapping unit is configured to receive an access request associated with the first thread; in a case where the access request belongs to a first request type, perform an access operation in the first storage space, or in a case where the access request belongs to a second request type, perform an access operation in the second storage space. The memory of the application is dynamically divided into a unique data area and a shared data area by the allocation unit, which avoids the problem that a new thread cannot be received due to the storage space of one of the registers and the shared memory being occupied, and improves the utilization rate of the storage space in the storage device.

Description

Technical Field

[0001] This application relates to the field of processors, and in particular to a storage device, processor, device, server cluster, and access method. Background Technology

[0002] In a multithreaded processor, each thread needs to have its own independent register space and a shared memory space. The independent register space is used to store thread-specific data such as instruction operands and intermediate results, while the shared memory space is used to store shared data among multiple threads.

[0003] In related technologies, registers and shared memory in multi-threaded processors are independent of each other. If the storage space of one of the registers and shared memory is fully or largely occupied, while the other still has remaining storage space, the multi-threaded processor cannot accept new threads, resulting in low overall storage space utilization. Summary of the Invention

[0004] This application provides a storage device, a processor, an equipment, a server cluster, and an access method, the technical solution of which is as follows:

[0005] On one hand, a storage device is provided, the storage device comprising: an allocation unit, a mapping unit, and a memory; the mapping unit is connected to the memory;

[0006] The allocation unit is configured to receive a thread allocation request corresponding to the first thread; and allocate a first storage space and a second storage space in the memory to the first thread based on the thread allocation request; the first storage space is used to store the unique data of the first thread, and the second storage space is used to store the shared data between the first thread and other threads.

[0007] The mapping unit is configured to receive an access request associated with the first thread; if the access request belongs to a first request type, perform an access operation in the first storage space, or if the access request belongs to a second request type, perform the access operation in the second storage space; the first request type represents an access request for the unique data, and the second request type represents an access request for the shared data.

[0008] On the other hand, a processor is provided, the processor including: the storage device as described above.

[0009] On the other hand, a computer device is provided, the computer device comprising: a storage device as described above, or a processor as described above.

[0010] Another approach provides a server cluster comprising at least two computer devices, the computer devices comprising: a storage device as described above, or a processor as described above.

[0011] On the other hand, an access method is provided for a storage device, the storage device including: an allocation unit, a mapping unit, and a memory; the mapping unit is connected to the memory.

[0012] The allocation unit receives a thread allocation request corresponding to the first thread; based on the thread allocation request, it allocates a first storage space and a second storage space in the memory to the first thread; the first storage space is used to store the unique data of the first thread, and the second storage space is used to store the shared data between the first thread and other threads;

[0013] The mapping unit receives an access request associated with the first thread; if the access request belongs to a first request type, it performs an access operation in the first storage space, or if the access request belongs to a second request type, it performs the access operation in the second storage space; the first request type represents an access request for the unique data, and the second request type represents an access request for the shared data.

[0014] On the other hand, a computer device is provided, the computer device including a processor and a storage module, the storage module storing at least one computer program, the computer program being loaded and executed by the processor to implement any of the access methods described above.

[0015] On the other hand, a computer-readable storage medium is provided, wherein at least one computer program is stored therein, the at least one computer program being loaded and executed by a processor to implement any of the access methods described above.

[0016] On the other hand, a computer program is provided that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform any of the access methods described above.

[0017] The beneficial effects of the technical solutions provided in this application include at least the following:

[0018] A storage device is designed in which an allocation unit dynamically allocates a first storage space (for exclusive data) and a second storage space (for shared data) in the memory for each new thread based on the thread allocation request. Unlike related technologies where registers and shared memory are independent, the memory in this application is dynamically divided into an exclusive data area (first storage space) and a shared data area (second storage space) by the allocation unit. This avoids the problem of insufficient free storage space in either the registers or the shared memory, which could prevent the reception of new threads, thus improving the utilization rate of storage space in the storage device. In addition, the mapping unit in the storage device can dynamically distinguish the access target (first storage space or second storage space) based on the request type of the access request, ensuring that the access operation is executed correctly, thereby improving access efficiency. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a structural block diagram of a computer system provided in an exemplary embodiment of this application;

[0021] Figure 2 This is a schematic diagram of a storage device provided in an exemplary embodiment of this application;

[0022] Figure 3 This is a structural block diagram of a storage device provided in an exemplary embodiment of this application;

[0023] Figure 4 This is a structural block diagram of a storage device provided in another exemplary embodiment of this application;

[0024] Figure 5 This is a structural block diagram of a storage device provided in yet another exemplary embodiment of this application;

[0025] Figure 6 This is a structural block diagram of a storage unit provided in an exemplary embodiment of this application;

[0026] Figure 7 This is a structural block diagram of a storage device provided in another exemplary embodiment of this application;

[0027] Figure 8 This is a schematic diagram illustrating an allocation example provided in an exemplary embodiment of this application;

[0028] Figure 9This is a schematic diagram illustrating an allocation example provided by another exemplary embodiment of this application;

[0029] Figure 10 This is a schematic diagram illustrating a mapping example provided in an exemplary embodiment of this application;

[0030] Figure 11 This is a flowchart of an access method provided in an exemplary embodiment of this application;

[0031] Figure 12 This is a schematic block diagram of a processor provided in an exemplary embodiment of this application;

[0032] Figure 13 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application;

[0033] Figure 14 This is a schematic block diagram of a computer device provided in another exemplary embodiment of this application;

[0034] Figure 15 This is a schematic block diagram of a computer device provided in yet another exemplary embodiment of this application;

[0035] Figure 16 This is a schematic block diagram of a computer device provided in another exemplary embodiment of this application. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0037] It should be noted that this application may display prompt interfaces, pop-ups, or output voice prompts before and during the collection of user, processor, and computer device data. These prompt interfaces, pop-ups, or voice prompts are used to inform the user that their data is being collected. This ensures that the application only begins the steps for collecting user data after receiving confirmation from the user regarding the prompt interface or pop-up; otherwise (i.e., without user confirmation), the steps for collecting user data end, meaning no user data is collected. In other words, all user data collected in this application is collected with the user's consent and authorization, and the collection, use, and processing of this user data must comply with the relevant laws, regulations, and standards of the relevant countries and regions.

[0038] Figure 1This is a structural block diagram of a computer system provided in an exemplary embodiment of this application. The computer system can be implemented as a hardware architecture for a storage device, or as a system architecture for an access method applied to a storage device. The computer system includes: a terminal 120 and a server 140.

[0039] In some embodiments, terminal 120 includes a storage device according to this embodiment; or, terminal 120 includes a processor, and the processor includes the storage device according to this embodiment. Terminal 120 may be an electronic device such as a mobile phone, tablet computer, vehicle terminal (vehicle system), wearable device, PC (Personal Computer), unmanned reservation terminal, etc., and this application embodiment does not limit it to this.

[0040] In some embodiments, server 140 includes the storage device of this embodiment; or, server 140 includes a processor, and the processor includes the storage device of this embodiment. Server 140 may be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud servers, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms. Server 140 may be a backend server for terminal 120, used to provide backend services for the data operation and processing of terminal 120. Optionally, server 140 may also be implemented as a node in a blockchain system.

[0041] The terminal 120 and the server 140 can communicate via a communication network, such as a wired or wireless network. The access method for a storage device provided in this application embodiment can have its steps executed by a storage device in a computer device, which includes the terminal 120 and / or the server 140.

[0042] Taking the storage device in server 140 as an example, the storage device in server 140 includes: allocation unit 10, mapping table 20, mapping unit 30, and memory 40, with memory 40 connected to mapping unit 30.

[0043] Schematic illustration: After receiving a thread allocation request corresponding to the first thread (new thread), the allocation unit 10 in the storage device of server 140 first allocates a first storage space and a second storage space to the first thread based on the thread allocation request. The first storage space is used to store the unique data of the first thread, and the second storage space is used to store the shared data between the first thread and other threads. Then, the allocation unit 10 writes a first mapping relationship between the first request type and the first storage space into a mapping table 20, and writes a second mapping relationship between the second request type and the second storage space into the mapping table 20. The first request type represents an access request for unique data, and the second request type represents an access request for shared data.

[0044] Schematic, after receiving an access request associated with the first thread, the mapping unit 30 in the storage device of server 140 first reads the mapping table 20 and determines the access target according to the request type of the access request and the mapping relationship in the mapping table. That is, if the request type of the access request belongs to the first request type, the first mapping relationship is determined in the mapping table 20 according to the first request type, and the access operation is performed in the first storage space based on the first mapping relationship; or, if the request type of the access request belongs to the second request type, the second mapping relationship is determined in the mapping table 20 according to the second request type, and the access operation is performed in the second storage space based on the second mapping relationship.

[0045] In multithreaded processors, each thread needs its own independent register space and shared memory space. The independent register space stores thread-specific data such as instruction operands and intermediate results, while the shared memory space stores shared data across multiple threads. In related technologies, the registers and shared memory in multithreaded processors are independent of each other. If the storage space of one of these registers or shared memory is fully or largely occupied, while the other still has remaining storage space, the multithreaded processor cannot accept new threads, resulting in low overall memory utilization.

[0046] Based on this, this application provides a storage device design. Please refer to... Figure 2 , Figure 2 A schematic diagram of a storage device provided in an exemplary embodiment of this application is shown.

[0047] like Figure 2 As shown, the storage device includes an allocation unit 210, a mapping table 220, a mapping unit 230, a first storage unit 241, and a second storage unit 242, wherein the first storage unit 241 and the second storage unit 242 are also the aforementioned memory. The first storage unit 241 and the second storage unit 242 are respectively connected to the mapping unit 230. Optionally, the aforementioned storage device is a device disposed in a processor.

[0048] The allocation unit 210 is used to receive a thread allocation request corresponding to the first thread. Optionally, the first thread refers to a new thread received by the processor. The thread allocation request is used to request the allocation of storage space for the first thread. Illustratively, the thread allocation request includes the register capacity and shared memory capacity required by the first thread. After receiving the thread allocation request, the allocation unit 210 first queries the free storage space of the first storage unit 241 and the second storage unit 242. If the free storage space capacity is greater than or equal to the register capacity and the shared memory capacity, it means that the processor can receive the first thread.

[0049] If the processor can receive the first thread, the allocation unit 210 will allocate register space (i.e., the first storage space) in the first storage unit 241 and the second storage unit 242 to the first thread. The space capacity of the register space is the register capacity, which is used to store the unique data of the first thread (or private data, which means data used independently by the first thread), such as operands and intermediate results that need to be accessed quickly during the execution of instructions of the first thread. The allocation unit 210 will also allocate shared memory space in the first storage unit 241 and the second storage unit 242 to the first thread. The space capacity of the shared memory space is the shared memory capacity, which is used to store shared data between the first thread and other threads (meaning data that the first thread needs to cooperate or communicate with other threads), such as global data that the first thread and other threads operate on together, intermediate results that the first thread and other threads need to pass between them. Optionally, both the register space and the shared memory space belong to the first storage unit 241; or both the register space and the shared memory space belong to the second storage unit 242; or the register space belongs to the first storage unit 241 and the shared memory space belongs to the second storage unit 242; or the register space belongs to the second storage unit 242 and the shared memory space belongs to the first storage unit 241. Optionally, the allocation unit 210 can allocate register space and shared memory space for the first thread by writing a first mapping relationship between a first request type and the register space into a mapping table 220, and writing a second mapping relationship between a second request type and the shared register space into a mapping table 220, where the first request type represents an access request for unique data and the second request type represents an access request for shared data.

[0050] Mapping unit 230 is used to receive access requests associated with the first thread. Optionally, the access request is for requesting to read or write data. After receiving the access request, mapping unit 230 first determines the request type of the access request, and then queries mapping table 220 according to the request type to determine the access target of this access request. Optionally, if the access request belongs to a first request type, a first mapping relationship corresponding to the first request type is determined in mapping table 220, and an access operation is performed in the register space based on the first mapping relationship; or, if the access request belongs to a second request type, a second mapping relationship corresponding to the second request type is determined in mapping table 220, and an access operation is performed in the shared memory space based on the second mapping relationship. Optionally, if the register space belongs to the first storage unit 241, mapping unit 230 sends a register access request to the first storage unit 241; if the register space belongs to the second storage unit 242, mapping unit 230 sends a register access request to the second storage unit 242. Optionally, if the shared memory space belongs to the first storage unit 241, the mapping unit 230 sends a shared memory access request to the first storage unit 241; if the shared memory space belongs to the second storage unit 242, the mapping unit 230 sends a shared memory access request to the second storage unit 242.

[0051] In summary, this application proposes a storage device that dynamically reuses shared memory and registers, which manages the storage space of shared memory and registers in a unified manner (i.e., manages them as memory). By establishing a mapping table to map different types of requests to storage space, the utilization rate of storage space is maximized, thereby improving the chip's area efficiency.

[0052] Figure 3 This is a structural block diagram of a storage device provided in an exemplary embodiment of this application. The storage device includes: an allocation unit 310, a mapping unit 330, and a memory 340. Optionally, the allocation unit 310 is connected to the mapping unit 330, and the mapping unit 330 is connected to the memory 340.

[0053] Optionally, the storage device may be implemented as part of a processor, which includes at least one of a GPU (Graphics Processing Unit) and a CPU (Central Processing Unit). Optionally, the memory is on-chip memory of the processor, and the memory may be implemented as at least one of Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc.

[0054] The processor's processing of a new thread (such as the first thread) typically includes two core phases: a resource allocation phase and an instruction execution phase. The resource allocation phase allocates the necessary hardware and software resources to the new thread, enabling it to execute. In this application, the resource allocation phase mainly involves the allocation of memory space for the new thread. The instruction execution phase executes the thread's instructions, and the execution of these instructions requires the memory space allocated during the resource allocation phase.

[0055] Optionally, the processor described above can be implemented as a multi-threaded processor, that is, a processor for multi-threaded execution scenarios. Multi-threaded execution scenarios include GPU parallel matrix multiplication, CPU multi-threaded sorting algorithms, real-time data processing pipelines (such as producer threads writing sensor data and consumer threads reading and processing it), etc., which are not limited here.

[0056] The allocation unit 310 is used to receive the thread allocation request corresponding to the first thread, and allocate the first storage space and the second storage space in the memory 340 to the first thread based on the thread allocation request.

[0057] To illustrate, when executing multithreaded tasks, the processor needs to dynamically manage thread creation, scheduling, and resource allocation. When a new thread (such as the first thread) needs to be started, the processor's thread scheduler or the operating system's scheduling module triggers a resource allocation process. Optionally, the processor's thread scheduler is responsible for allocating execution time slices and hardware resources to the new thread. When the thread scheduler decides to activate the first thread, it sends a thread allocation request to the allocation unit to request the memory space required by the first thread. Alternatively, the operating system triggers the creation of the first thread by making a call, in which case the operating system's scheduling module sends a thread allocation request to the processor's allocation unit.

[0058] The first storage space is used to store data unique to the first thread. Illustratively, unique data belongs solely to the first thread and cannot be directly accessed or modified by other threads. Unique data includes the first thread's instruction operands (input data required when the thread executes instructions, such as source operands for arithmetic operations), intermediate results (temporary values ​​generated during thread instruction execution), etc. Optionally, the first storage space can be considered as an independent register space allocated for the first thread.

[0059] The second storage space is used to store shared data between the first thread and other threads. Shared data refers to data that can be accessed and modified by both the first thread and other threads. This shared data includes global data corresponding to the first thread and other threads (such as input or output datasets processed jointly by the first thread and other threads), collaborative intermediate results (such as intermediate calculation results that need to be exchanged or merged between threads), synchronization and communication variables (such as shared variables used to coordinate the execution order or state of threads), etc. Optionally, the second storage space can be considered as the storage space of shared memory allocated for the first thread.

[0060] The aforementioned "other threads" refer to threads that share data with the first thread. Optionally, other threads can share global variables with the first thread; both can read and modify these global variables, such as both threads operating on the same `count` variable. Optionally, other threads can share resources with the first thread; for example, the first thread processes the first pixel block, while other threads process the second pixel block, and texture data is a shared resource, in which case the first thread shares the texture data with the other threads. Optionally, other threads need to exchange or merge intermediate calculation results with the first thread; for example, the first thread's intermediate calculation result is `a`, and other threads' intermediate calculation result is `b`, and `a` and `b` need to be merged, or other threads need to obtain `a` as an operand, or the first thread needs to obtain `b` as an operand. The examples of other threads above are merely illustrative and will not be elaborated upon here.

[0061] In some embodiments, the first thread and other threads belong to the same thread block. A thread block is a logical unit for thread organization in the processor, containing a group of cooperating threads. Illustratively, a thread block can be viewed as a basic unit of execution, where multiple threads can work collaboratively within the same thread block to complete a specific computational task. Within the same thread block, the first thread and other threads (other threads being threads other than the first thread in a group of cooperating threads) share a second storage space, while each thread has its own independent first storage space.

[0062] It should be noted that in a multi-threaded architecture, although the allocation process of the second storage space is triggered by the resource allocation request of the first thread, it is essentially a shared resource of the thread group (such as a thread block or thread bundle), rather than an exclusive space of the first thread. Other threads (such as threads within the same thread block) can access the second storage space.

[0063] In some embodiments, a thread allocation request includes a first space capacity and a second space capacity required by a first thread, wherein the first space capacity represents the storage space capacity used to store unique data and the second space capacity represents the storage space capacity used to store shared data.

[0064] Optionally, the allocation unit 310 is used to allocate a first storage space in the memory 340 that matches the first space capacity and a second storage space that matches the second space capacity to the first thread, provided that the first space capacity and the second space capacity meet the free storage space requirements of the memory 340.

[0065] Schematic, a first storage space matching the first space capacity means that the capacity of the first storage space is greater than or equal to the first space capacity; a second storage space matching the second space capacity means that the capacity of the second storage space is greater than or equal to the second space capacity.

[0066] In the above scheme, by explicitly specifying the space capacity required for unique and shared data in the thread allocation request, the allocation unit can accurately match the actual needs of the thread, avoiding resource waste. Furthermore, by dynamically adjusting space allocation based on thread needs, rather than fixedly allocating registers and shared memory, the problem of rejecting new threads entirely due to insufficient space in a certain type of storage is avoided.

[0067] Optionally, the first space capacity and the second space capacity meeting the free storage space requirements of the memory include at least one of the following:

[0068] Scenario 1 The allocation unit is configured to allocate, when there are first and second consecutive free storage spaces in the memory, a first storage space matching the capacity of the first space in the first consecutive free storage space, and a second storage space matching the capacity of the second space in the second consecutive free storage space, to the first thread.

[0069] Wherein, the capacity of the first contiguous free storage space is greater than or equal to the first space capacity, and the capacity of the second contiguous free storage space is greater than or equal to the second space capacity.

[0070] Alternatively, the allocation unit is configured to, when a first contiguous free storage space and a second contiguous free storage space exist in the memory, allocate a first storage space in the second contiguous free storage space that matches the capacity of the first space, and allocate a second storage space in the first contiguous free storage space that matches the capacity of the second space, to the first thread. Wherein, the capacity of the first contiguous free storage space is greater than or equal to the capacity of the second space, and the capacity of the second contiguous free storage space is greater than or equal to the capacity of the first space.

[0071] Optionally, contiguous free storage space refers to a segment of memory with contiguous addresses that is not occupied. Illustratively, assume the capacity (or size) of the first contiguous free storage space in memory is 256 bits, and the capacity of the second contiguous free storage space is 128 bits. If the first thread requires both 128 bits of space, then the first and second space capacities meet the memory's free storage space requirements. In this case, 128 bits can be allocated from the first contiguous free storage space as the first storage space, and 128 bits from the second contiguous free storage space as the second storage space; or, 128 bits can be allocated from the second contiguous free storage space as the first storage space, and 128 bits from the first contiguous free storage space as the second storage space.

[0072] In the above scheme, the allocation unit allocates the first and second storage spaces only when there is enough contiguous free storage space in the memory. By requiring contiguous space, the fragmentation problem caused by non-contiguous allocation is avoided, and the efficient use of storage space is ensured.

[0073] Scenario 2 The allocation unit is used to allocate a first storage space matching the first space capacity and a second storage space matching the second space capacity to the first thread when the free storage space capacity of the memory is greater than or equal to the sum of the first space capacity and the second space capacity.

[0074] Schematic illustration: If there is no contiguous free storage space in the memory that simultaneously satisfies both the first and second space capacities, but there are multiple scattered free storage blocks whose total capacity exceeds the sum of the first and second space capacities, the first and second storage spaces are allocated to these scattered free storage blocks. The first and second storage spaces are mapped using virtual addresses to form logically contiguous storage regions, such as virtual addresses 0-128 corresponding to free storage blocks with physical addresses 0-63 and free storage blocks with physical addresses 128-191. When a subsequent mapping unit accesses the memory, the access address obtained is a virtual address. After determining the virtual address, it is mapped to a real physical address.

[0075] If there exists only a first contiguous free storage space in the memory with a capacity greater than or equal to the first space capacity and less than the second space capacity, but there are multiple scattered free storage blocks and the total capacity of the first contiguous free storage space is greater than the sum of the first space capacity and the second space capacity, then the first storage space in the first contiguous free storage space is allocated to the first thread, and the second storage space is allocated to the remaining free storage blocks; wherein, the second storage space forms a logically contiguous storage region through virtual address mapping.

[0076] If there exists only a second contiguous free storage space in the memory with a capacity greater than or equal to the second space capacity and less than the first space capacity, but there are multiple scattered free storage blocks and the total capacity of the second contiguous free storage space is greater than the sum of the first space capacity and the second space capacity, then the first thread is allocated the second storage space in the second contiguous free storage space, and the first storage space is allocated to the remaining free storage blocks; wherein, the first storage space forms a logically contiguous storage region through virtual address mapping.

[0077] If there exists only a third contiguous free storage space in the memory with a capacity greater than or equal to the second space capacity and greater than or equal to the first space capacity, but the capacity of the third contiguous free storage space is less than the sum of the second and first space capacities, and there are multiple scattered free storage blocks and the total capacity of the third contiguous free storage space is greater than the sum of the first and second space capacities, the allocation scheme may include one of the following allocation schemes:

[0078] (1) Allocate the second storage space in the third contiguous free storage space to the first thread, and allocate the first storage space to the remaining free storage blocks; wherein, the first storage space forms a logically contiguous storage region through virtual address mapping. Illustratively, in cases where the first storage space (unique data) requires extremely low-latency access (such as registers, thread-private states), the third contiguous space is allocated to the first storage space (unique data) to ensure its physical continuity.

[0079] (2) Allocate the first storage space in the third contiguous free storage space to the first thread, and allocate the second storage space to the remaining free storage blocks; wherein, the second storage space forms a logically contiguous storage region through virtual address mapping. Illustratively, in cases where the second storage space (shared data) requires high-throughput collaboration (such as frequent exchange of intermediate results within a thread block), the third contiguous space is allocated to the second storage space (shared data) to ensure collaboration efficiency.

[0080] In some embodiments, the storage device further includes a mapping table 320.

[0081] Optionally, the mapping table is used to store the mapping relationship between access request types and storage spaces. Optionally, the mapping table is stored inside the mapping unit, or the mapping table is stored separately in a certain storage area of ​​the storage device.

[0082] Optionally, the allocation unit is used to write the first mapping relationship between the first request type and the first storage space and the second mapping relationship between the second request type and the second storage space into the mapping table.

[0083] As an illustration, the allocation unit sends a write command to the storage area where the mapping table is located, and writes the first mapping relationship and the second mapping relationship into the mapping table through the write command.

[0084] The mapping unit 330 is used to receive an access request associated with the first thread; if the access request belongs to a first request type, the access operation is performed in the first storage space, or if the access request belongs to a second request type, the access operation is performed in the second storage space.

[0085] In illustrative terms, an access request refers to an access operation to either the first or second memory space during the execution of the first thread. Taking the first memory space as a register space and the second memory space as a shared memory space as an example, after the issue unit in the processor issues the first instruction of the first thread, if the first instruction is a computational instruction, the mapping unit will receive a register access request and then retrieve the operands of the first instruction from the register space according to the register access request. The operands of the first instruction will be sent to the arithmetic logic unit in the processor to complete the calculation. If the first instruction is a memory access instruction, the memory access instruction will be sent to the load memory unit, which will send a shared memory access request to the mapping unit. The mapping unit will then retrieve or store data from the shared memory space according to the shared memory access request.

[0086] The first request type represents an access request for unique data, while the second request type represents an access request for shared data.

[0087] Optionally, the access operation includes at least one of a read operation and a write operation. Schematic, the access operation performed in the first storage space includes at least one of reading data in the first storage space and writing data (i.e., storing data) in the first storage space.

[0088] In some embodiments, the mapping unit is configured to query the mapping table based on an access request. Illustratively, the mapping unit sends a read command to the storage area where the mapping table resides, and obtains the mapping relationships in the mapping table through the read command.

[0089] Optionally, the mapping unit is configured to, when the access request belongs to a first request type, determine a first mapping relationship corresponding to the first request type in the mapping table, and perform an access operation in the first storage space based on the first mapping relationship. Optionally, the mapping unit is configured to, when the access request belongs to a second request type, determine a second mapping relationship corresponding to the second request type in the mapping table, and perform an access operation in the second storage space based on the second mapping relationship.

[0090] As an illustration, when the access request belongs to the first request type, the mapping unit can obtain the first mapping relationship associated with the first request type in the mapping table, thereby determining that the access target of this access request is the first storage space; when the access request belongs to the second request type, the mapping unit can obtain the second mapping relationship associated with the second request type in the mapping table, thereby determining that the access target of this access request is the second storage space.

[0091] In the above scheme, the mapping unit directly jumps to the corresponding storage space based on the request type, reducing the complexity of the access logic. For example, access to unique data does not require traversing the shared data area, improving access speed. Furthermore, the explicit mapping relationship of the mapping table avoids anomalies caused by accidental access to the wrong storage space, enhancing the stability of the storage system.

[0092] In some embodiments, the first mapping relationship indicates the mapping relationship between the first request type and the storage address range of the first storage space, and the second mapping relationship indicates the mapping relationship between the second request type and the storage address range of the second storage space.

[0093] The storage address range of the first storage space can be a physical address range, such as physically contiguous address blocks in memory; or, the storage address range of the first storage space can be a virtual address range, which is mapped to logical address blocks of physical addresses through virtual memory management, and may correspond to multiple non-contiguous physical blocks.

[0094] Optionally, the mapping unit is configured to determine a first access address based on the storage address range and requested address of the first storage space indicated by the first mapping relationship; and perform an access operation in the first storage space according to the first access address. Optionally, the mapping unit is configured to determine a second access address based on the storage address range and requested address of the second storage space indicated by the second mapping relationship; and perform an access operation in the second storage space according to the second access address.

[0095] The access request includes a request address. The request address is the address value carried in the access request, used to indicate the storage bit that needs to be read / written. In this application, the request address refers to an offset relative to the storage address range. Illustratively, assuming the starting address of the storage address range of the first storage space is "x" and the request address is y, then the first access address is "x+y". Assuming the starting address of the storage address range of the second storage space is "z" and the request address is y, then the second access address is "z+y". If the first and second access addresses are virtual addresses, then the first and second access addresses need to be mapped to real physical addresses. Then, the mapping unit performs an access operation in the first storage space based on the first physical address obtained from the mapping of the first access address; the mapping unit performs an access operation in the second storage space based on the second physical address obtained from the mapping of the second access address.

[0096] In the above scheme, by combining address range mapping and request address, the address of the access target can be accurately determined, ensuring the accuracy of data access.

[0097] In summary, this application designs a storage device in which the allocation unit dynamically allocates a first storage space (for exclusive data) and a second storage space (for shared data) in the memory for each new thread based on the thread allocation request. Unlike related technologies where registers and shared memory are independent, the memory in this application is dynamically divided into an exclusive data area (first storage space) and a shared data area (second storage space) by the allocation unit. This avoids the problem of insufficient free storage space in either the registers or the shared memory, which could prevent the reception of new threads, thus improving the utilization rate of storage space in the storage device. Furthermore, the mapping unit in the storage device can dynamically distinguish the access target (first storage space or second storage space) based on the request type of the access request, ensuring that the access operation is executed correctly, thereby improving access efficiency.

[0098] Figure 4 This is a structural block diagram of a storage device provided in an exemplary embodiment of this application. For example... Figure 4 As shown, the storage device also includes an update unit 350 and an access unit 360.

[0099] Optionally, the allocation unit 310 is connected to the update unit 350, the update unit 350 is connected to the mapping unit 330, the mapping unit 330 is connected to the access unit 360, and the access unit 360 is connected to the memory 340.

[0100] The allocation unit 310 is used to receive the thread allocation request corresponding to the first thread, and allocate the first storage space and the second storage space in the memory 340 to the first thread based on the thread allocation request.

[0101] The first storage space is used to store data unique to the first thread, and the second storage space is used to store data shared between the first thread and other threads.

[0102] In some embodiments, the thread allocation request includes a first space capacity and a second space capacity required by the first thread.

[0103] In some embodiments, the storage device further includes a space management table 370.

[0104] The allocation unit 310 is used to query the space management table 370 to determine the free storage units in the memory 340.

[0105] The space management table stores the space usage information of the memory. Optionally, the space management table is stored within the allocation unit, or it can be stored separately in a specific storage area of ​​the storage device. Optionally, the space management table stores the free status information of the memory, such as recording which storage blocks are free and which are occupied. In some embodiments, the space management table can be implemented using a bitmap, where each storage block (e.g., a 1-bit block) corresponds to a binary bit, with 0 indicating free and 1 indicating occupied.

[0106] In the above scheme, a space management table is introduced to record the usage of the memory. The allocation unit determines the free storage unit by querying the space management table, so that the allocation unit can quickly locate available space, and the space management table is updated in real time to ensure the accuracy of allocation decisions.

[0107] The allocation unit 310 is used to allocate a first storage space in the memory 340 that matches the first space capacity and a second storage space that matches the second space capacity to the first thread, provided that the first space capacity and the second space capacity meet the free storage space requirements of the memory 340.

[0108] Optionally, the allocation unit is configured to allocate, in the case that the memory contains a first contiguous free storage space with a capacity greater than or equal to the first space capacity and a second contiguous free storage space with a capacity greater than or equal to the second space capacity, a first storage space matching the first space capacity in the first contiguous free storage space, and a second storage space matching the second space capacity in the second contiguous free storage space, to the first thread.

[0109] The allocation unit 310 is used to indicate the first storage space and the second storage space to the update unit 350.

[0110] Optionally, the allocation unit is used to indicate to the update unit the storage unit to which the first storage space belongs and the storage address range corresponding to the first storage space; and to indicate to the update unit the storage unit to which the second storage space belongs and the storage address range corresponding to the second storage space.

[0111] In some embodiments, the storage device further includes a mapping table 320.

[0112] Optionally, the mapping table is stored inside the update unit, or the mapping table is stored separately in a storage area of ​​the storage device.

[0113] The update unit 350 is used to write the first mapping relationship between the first request type and the first storage space and the second mapping relationship between the second request type and the second storage space into the mapping table 320.

[0114] Optionally, the update unit sends a write command to the storage area where the mapping table is located, and writes the first mapping relationship and the second mapping relationship into the mapping table through the write command.

[0115] Schematic illustration: The allocation unit indicates to the update unit the first storage space belonging to the first storage unit and the storage address range of the first storage space in the first storage unit; or, the allocation unit indicates to the update unit the first storage space belonging to the second storage unit and the storage address range of the first storage space in the second storage unit. Optionally, after receiving the instruction from the update unit, the allocation unit writes the first mapping relationship into a mapping table. Schematic illustration: The allocation unit writing the first mapping relationship into the mapping table can be specifically implemented as follows: writing the first mapping information corresponding to the first mapping relationship into the mapping table, wherein the first mapping information includes the request type identifier of the first request type, the thread identifier of the first thread, the storage unit identifier (first storage unit identifier or second storage unit identifier), and the address information corresponding to the storage address range of the first storage space. Optionally, if the size of the storage address range of the first storage space is a default size (e.g., 128 bits), the address information can be implemented as the start address or end address of the storage address range of the first storage space.

[0116] Schematic illustration: The allocation unit indicates to the update unit the second storage space belonging to the first storage unit and the storage address range of the second storage space in the first storage unit; or, the allocation unit indicates to the update unit the second storage space belonging to the second storage unit and the storage address range of the second storage space in the second storage unit. Optionally, after receiving the instruction from the update unit, the allocation unit writes the second mapping relationship into a mapping table. Schematic illustration: The allocation unit writing the second mapping relationship into the mapping table can be specifically implemented as follows: writing the second mapping information corresponding to the second mapping relationship into the mapping table, wherein the second mapping information includes the request type identifier of the second request type, the thread identifier of the first thread, the storage unit identifier (first storage unit identifier or second storage unit identifier), and the address information corresponding to the storage address range of the second storage space. Optionally, if the size of the storage address range of the second storage space is a default size (e.g., 128 bits), the address information can be implemented as the start address or end address of the storage address range of the second storage space.

[0117] Optionally, the request type identifier of the first request type, the request type identifier of the second request type, and the thread identifier of the first thread may be information indicated by the allocation unit to the update unit; or, the request type identifier of the first request type, the request type identifier of the second request type, and the thread identifier of the first thread may be information confirmed by the update unit itself. For example, the processor assigns a fixed thread ID to each thread. When the allocation unit indicates storage space to the update unit, the update unit automatically associates it with the corresponding thread ID through the current thread scheduling state (maintained by the thread scheduler). The processor assigns a fixed request type ID to the first request type. When the allocation unit indicates storage space to the update unit, the update unit automatically associates it with the corresponding request type ID. For example, when indicating the first storage space, it automatically associates it with the request type ID of the first request type; when indicating the second storage space, it automatically associates it with the request type ID of the second request type.

[0118] The above scheme introduces a mapping table and an update unit. The mapping table directly associates the request type with the storage space, and the mapping unit can quickly determine the target storage space, improving access efficiency. For example, when a thread requests access to shared data, the mapping table can directly return the corresponding storage address range. The update unit can update the mapping relationship in real time, ensuring that the mapping table is always consistent with the actual storage state.

[0119] In some embodiments, the first thread represents a single thread; in other embodiments, this application allocates storage resources in units of thread bundles, that is, the first thread includes at least two sub-threads, and the at least two sub-threads constitute a thread bundle. The thread bundle identifier is also represented by the thread identifier of the first thread in the aforementioned first mapping information.

[0120] Mapping unit 330 is used to receive access requests associated with the first thread.

[0121] Optionally, the access request associated with the first thread represents a single access request; or the access request associated with the first thread includes at least two sub-access requests, each containing a separate request address.

[0122] The mapping unit 330 is used to indicate a first access address to the access unit 360 when the access request belongs to a first request type.

[0123] The first request type represents a request to access unique data.

[0124] Optionally, the mapping unit, when the access request belongs to the first request type, determines the first mapping relationship corresponding to the first request type in the mapping table, determines the first access address based on the storage address range of the first storage space indicated by the first mapping relationship and the request address, and then indicates the first access address to the access unit.

[0125] To illustrate, the first mapping information is obtained from the mapping table. The storage unit identifier and the storage address range of the first storage space are then retrieved from the first mapping information. Based on the storage unit identifier, address information (taking the address information as the starting address corresponding to the storage address range of the first storage space as an example), and the request address, the first access address is determined. To illustrate, assuming the storage unit identifier is the first storage unit identifier, the starting address in the address information is x, and the request address is y, then the first access address is the storage address "x+y" corresponding to the first storage unit.

[0126] Access unit 360 is used to generate a first access request based on a first access address and to send the first access request to memory 340.

[0127] Optionally, after obtaining the first access address, the access unit generates a first access request based on the first access address. The first access request is used to request access to the first storage space. Then, the access unit sends the first access request to the memory. After receiving the first access request, if the first access request indicates reading data, the memory reads the data according to the first access request and performs read feedback; if the first access request indicates writing data, the memory stores the data according to the first access request and performs write feedback.

[0128] Optionally, the access unit is used to generate physical signals that can be recognized by the memory hardware. Schematic, the access unit is used to convert the first access address (virtual address) into a physical address, and then generate a read signal or a write signal. The read signal is used to control the memory to perform a read operation, and the write signal is used to control the memory to perform a write operation. The physical address indicates the target location in the memory where the read or write operation is actually performed.

[0129] The mapping unit 330 is used to indicate a second access address to the access unit 360 when the access request belongs to the second request type.

[0130] The second request type represents a request to access shared data.

[0131] Optionally, if the access request belongs to the second request type, the second mapping relationship corresponding to the second request type is determined in the mapping table, and the second access address is determined based on the storage address range and request address of the second storage space indicated by the second mapping relationship; the second access address is then indicated to the access unit.

[0132] To illustrate, the second mapping information is retrieved from the mapping table. This includes the storage unit identifier and the storage address range of the second storage space. Based on the storage unit identifier, address information (using the starting address corresponding to the storage address range of the second storage space as an example), and the request address, the second access address is determined. To illustrate, assuming the storage unit identifier is the second storage unit identifier, the starting address in the address information is z, and the request address is y, then the second access address is the storage address "z+y" corresponding to the second storage unit.

[0133] Access unit 360 is used to generate a second access request based on the second access address and to send the second access request to memory 340.

[0134] Optionally, after obtaining the second access address, the access unit generates a second access request based on the second access address. The second access request is used to request access to the second storage space. Then, the second access unit sends the second access request to the memory. After receiving the second access request, if the second access request indicates reading data, the memory reads the data according to the second access request and performs read feedback; if the second access request indicates writing data, the memory stores the data according to the second access request and performs write feedback.

[0135] In the above scheme, the introduction of an access unit decouples access requests from memory control signals. The mapping unit only needs to focus on resolving the mapping relationship. In a multi-memory-unit architecture, the access unit can directly generate parallel signals for different memory units, making full use of hardware resources and improving access efficiency.

[0136] In some embodiments, the storage device further includes a dynamic adjustment unit connected to the space management table and the update unit.

[0137] Optionally, the dynamic adjustment unit is used to generate an expansion request when the difference between the used storage space capacity of the first thread and the first storage space capacity is less than a threshold; query the space management table according to the expansion request to determine the first free storage space in the memory, and the first free storage space and the first storage space form a contiguous storage space; the allocation unit is also used to allocate the first free storage space to the first thread; the update unit is also used to update the storage address range corresponding to the first mapping relationship in the mapping table so that it includes the storage address range of the first free storage space.

[0138] In some embodiments, the memory includes at least two storage cells; the at least two storage cells are respectively connected to a mapping cell; the first storage space and the second storage space belong to the same storage cell; or, the first storage space and the second storage space belong to different storage cells.

[0139] For illustrative purposes, when the first contiguous free storage space and the second contiguous free storage space belong to the same storage unit, the first storage space and the second storage space belong to the same storage unit; when the first contiguous free storage space and the second contiguous free storage space belong to different storage units, the first storage space and the second storage space belong to different storage units.

[0140] In the above scheme, after dividing the memory into at least two storage units, it is possible to support the allocation of unique data and shared data to different storage units, thereby supporting parallel access and improving access efficiency.

[0141] Optionally, at least two storage units correspond to one access unit. Illustratively, at least two storage units are each connected to an access unit; or, at least two storage units each correspond to one access unit, and at least two access units are connected to at least two storage units, where the i-th access unit is connected to the i-th storage unit, and i is a positive integer. The following explanation uses the example of at least two storage units each corresponding to one access unit.

[0142] Figure 5 This is a structural block diagram of a storage device provided in an exemplary embodiment of this application. (See diagram below.) Figure 5 As shown, the memory 340 includes at least two memory cells (i.e., Figure 5 The storage device includes storage units 1 to n (where n is an integer greater than 1); the storage device also includes: access units corresponding to at least two storage units respectively (i.e., Figure 5 Access units 1 to n are shown.

[0143] Optionally, the allocation unit 310 is connected to the update unit 350, the update unit 350 is connected to the mapping unit 330, at least two access units are respectively connected to the mapping unit 330, and at least two access units are correspondingly connected to at least two storage units, wherein the i-th access unit is connected to the i-th storage unit, i is a positive integer and i≤n, such as storage unit 1 is connected to access unit 1, and storage unit n is connected to access unit n.

[0144] In some embodiments, the first storage space belongs to the i-th storage unit, and the second storage space belongs to the j-th storage unit, where i and j are positive integers; the access request includes the requested address. The i-th and j-th storage units can be the same or different storage units.

[0145] The mapping unit, when the access request belongs to the first request type, determines the first mapping relationship corresponding to the first request type in the mapping table, determines the first access address based on the storage address range of the register space indicated by the first mapping relationship and the request address, and indicates the first access address to the i-th access unit. The i-th access unit is used to generate a first access request based on the first access address and send the first access request to the i-th storage unit.

[0146] The mapping unit, when the access request belongs to the second request type, determines the second mapping relationship corresponding to the second request type in the mapping table, determines the second access address based on the storage address range of the shared memory space indicated by the second mapping relationship and the request address, and indicates the second access address to the j-th access unit. The j-th access unit is used to generate a second access request based on the second access address and send the second access request to the j-th storage unit.

[0147] In the above scheme, the memory is divided into at least two storage units (e.g., storage unit 1 to storage unit n), and each storage unit corresponds to an independent access unit (e.g., access unit 1 to access unit n). This allows each access unit to process different storage requests in parallel, avoiding the serialization bottleneck of single-channel access. For example, the unique data of the first thread (first storage space) and the shared data of the second thread (second storage space) can be allocated to different storage units, and access requests can be initiated simultaneously through their respective access units, achieving parallel read and write operations.

[0148] In some embodiments, the storage unit adopts a design of at least two sub-storage units, that is, at least two storage units each contain at least two sub-storage units.

[0149] Figure 6 This is a structural block diagram of a storage unit provided in an exemplary embodiment of this application. For example... Figure 6 As shown, the storage unit 600 includes at least two sub-storage units, that is... Figure 6The sub-storages 1 to m are shown, where m is an integer greater than 1.

[0150] In some embodiments, the first storage space belongs to the i-th storage unit, and the second storage space belongs to the j-th storage unit, where i and j are positive integers; the access request includes the request address.

[0151] Optionally, the mapping unit 330 is used to determine a first access address based on the storage address range and request address in the i-th storage unit of the first storage space when the access request belongs to the first request type; and to send a first access request to the first sub-storage of the i-th storage unit according to the first access address, wherein the first access address points to the first sub-storage.

[0152] Schematic, mapping unit 330 is used to determine the first mapping relationship corresponding to the first request type in mapping table 320, determine the first access address based on the storage address range of the register space indicated by the first mapping relationship and the request address, and indicate the first access address to the i-th access unit. The i-th access unit is used to generate a first access request based on the first access address and send the first access request to the i-th storage unit.

[0153] Optionally, the mapping unit 330 is used to determine a second access address based on the storage address range and request address of the second storage space in the j-th storage unit when the access request belongs to the second request type; and to send a second access request to the second sub-storage of the j-th storage unit according to the second access address, wherein the second access address points to the second sub-storage.

[0154] Schematic, mapping unit 330 is used to determine the second mapping relationship corresponding to the second request type in mapping table 320, determine the second access address based on the storage address range and request address of the shared memory space indicated by the second mapping relationship, and indicate the second access address to the j-th access unit. The j-th access unit is used to generate a second access request based on the second access address and send the second access request to the j-th storage unit.

[0155] In the above scheme, by designing sub-memory blocks within the memory unit, parallel access can be maximized. If a single access request contains multiple address-independent sub-requests, and if these sub-requests are distributed across different sub-memory blocks, they can be processed in parallel. For example, a register access request may contain sub-request 1 and sub-request 2. Sub-request 1 requests access to sub-memory block 0, and sub-request 2 requests access to sub-memory block 1. The two sub-requests can be executed simultaneously, improving access efficiency.

[0156] The following explanation uses at least two storage units as an example, implemented as the first storage unit and the second storage unit. Figure 7This is a structural block diagram of a storage device provided in an exemplary embodiment of this application.

[0157] like Figure 7 As shown, the storage device includes: an allocation unit 310, a space management table 370, an update unit 350, a mapping table 320, a mapping unit 330, a first access unit 361, a second access unit 362, a first storage unit 341, and a second storage unit 342.

[0158] The mapping unit 330 is connected to the first access unit 361, the mapping unit 330 is connected to the second access unit 362, the first access unit 361 is connected to the first storage unit 341, and the second access unit 362 is connected to the second storage unit 342.

[0159] Optionally, the storage device is a device within the processor, where the processor's processing of a new thread (such as the first thread) typically includes two core stages: a resource allocation stage and an instruction execution stage. Illustratively, the processor can be implemented as a multi-threaded processor, which is a processor capable of executing multiple threads simultaneously or alternately. In a multi-threaded processor, to achieve zero-overhead switching between threads, an independent register space and shared memory space need to be deployed for each thread during the resource allocation stage. The storage device provided in this application can be used by a multi-threaded processor to allocate register space and shared memory space for a new thread during the resource allocation stage. The allocation process of register space and shared memory space is described below.

[0160] ●Resource allocation stage

[0161] The allocation unit 310 is used to receive the thread allocation request corresponding to the first thread.

[0162] Optionally, the thread allocation request carries the register space capacity (rf_size, i.e., the first space capacity) and other memory space sizes required by the first thread, such as the shared memory space capacity (sm_size, i.e., the second space capacity). After the thread allocation request enters the allocation unit 310, the allocation unit 310 performs a query operation on the free storage space of the first storage unit 341 and the second storage unit 342.

[0163] Optionally, the space management table 370 maintains the current space usage of the first storage unit 341 and the second storage unit 342, such as maintaining the free status of the first storage unit 341 and the second storage unit 342. Illustratively, the allocation unit 310 obtains the free storage space in the first storage unit 341 and the second storage unit 342 by querying the space management table 370.

[0164] Optionally, if there is a first contiguous free storage space and a second contiguous free storage space in the first storage unit 341 and the second storage unit 342, and the capacity of the first contiguous free storage space is greater than or equal to the capacity of the register space, and the capacity of the second contiguous free storage space is greater than or equal to the capacity of the shared memory space (or, the capacity of the second contiguous free storage space is greater than or equal to the capacity of the register space, and the capacity of the first contiguous free storage space is greater than or equal to the capacity of the shared memory space), then the allocation unit 310 determines that the processor can receive the first thread.

[0165] The allocation unit 310 is used to allocate register space for the first thread in the first storage unit 341 and the second storage unit 342, and to allocate shared memory space for the first thread in the first storage unit 341 and the second storage unit 342.

[0166] The register space (i.e., the first storage space) has a capacity equal to the register space capacity; the shared memory space (i.e., the second storage space) has a capacity equal to the shared memory space capacity. The register space is used to store data unique to the first thread, and the shared memory space is used to store data shared between the first thread and other threads. Optionally, the first thread and other threads belong to the same thread block.

[0167] Depending on the different idle states in the first storage unit 341 and the second storage unit 342, there will be different allocation situations for the first thread. The following is an explanation of each allocation situation.

[0168] (1) Register space and shared memory space belong to different storage units.

[0169] Optionally, the register space belongs to the first storage unit 341, and the shared memory space belongs to the second storage unit 342. Illustratively, if the first storage unit 341 has a first contiguous free storage space, the second storage unit 342 has a second contiguous free storage space, and the capacity of the first contiguous free storage space is greater than or equal to the capacity of the register space, and the capacity of the second contiguous free storage space is greater than or equal to the capacity of the shared memory space, register space is allocated to the first thread in the first contiguous free storage space, and shared memory space is allocated to the first thread in the second contiguous free storage space.

[0170] Alternatively, the shared memory space belongs to the first memory unit 341, and the register space belongs to the second memory unit 342. Illustratively, if the first memory unit 341 contains a first contiguous free memory space, the second memory unit 342 contains a second contiguous free memory space, and the capacity of the first contiguous free memory space is greater than or equal to the capacity of the shared memory space, and the capacity of the second contiguous free memory space is greater than or equal to the capacity of the register space, then the first thread is allocated shared memory space in the first contiguous free memory space, and the first thread is allocated register space in the second contiguous free memory space.

[0171] Figure 8 This is a schematic diagram illustrating an allocation example provided in an exemplary embodiment of this application. For example... Figure 8 As shown, the thread allocation request carries a register space capacity of 128 bits and a shared memory space capacity of 128 bits. The white segment 811 (“128-255”) in the idle status information 810 represents the free storage space in the first memory unit, and the white segment 821 (“0-127”) in the idle status information 820 represents the free storage space in the second memory unit. Figure 8 It can be seen that the white segment 811 represents a first contiguous free memory space with a capacity of 128 bits, and the white segment 821 represents a second contiguous free memory space with a capacity of 128 bits. Therefore, the processor can receive the first thread. It should be noted that in this application, 128 bits can also be 128 bytes, 128kb, etc., that is, the size of each address unit can be 1 bit, 1 byte, or 1kb, etc., without limitation here. The address "128" of the first memory unit means the 128th address unit of the first memory unit.

[0172] like Figure 8 As shown, the memory allocation for the first thread can be as follows: allocating the first contiguous free memory space (i.e., "128-255") in the first memory unit to the first thread as its register space; and allocating the second contiguous free memory space (i.e., "0-127") in the second memory unit to the first thread as its shared memory space. Alternatively, the memory allocation can be as follows: allocating the first contiguous free memory space in the first memory unit to the first thread as its shared memory space; and allocating the second contiguous free memory space in the second memory unit to the first thread as its register space. No limitation is imposed here.

[0173] (2) The register space and the shared memory space belong to the same storage unit.

[0174] Optionally, the register space and the shared memory space both belong to the first storage unit 341. Illustratively, if the first storage unit 341 contains a first contiguous free storage space and a second contiguous free storage space, and the capacity of the first contiguous free storage space is greater than or equal to the capacity of the register space, and the capacity of the second contiguous free storage space is greater than or equal to the capacity of the shared memory space, register space is allocated to the first thread in the first contiguous free storage space, and shared memory space is allocated to the first thread in the second contiguous free storage space. Alternatively, if the first storage unit 341 contains a first contiguous free storage space and a second contiguous free storage space, and the capacity of the first contiguous free storage space is greater than or equal to the capacity of the shared memory space, and the capacity of the second contiguous free storage space is greater than or equal to the capacity of the register space, shared memory space is allocated to the first thread in the first contiguous free storage space, and register space is allocated to the first thread in the second contiguous free storage space.

[0175] Optionally, the register space and the shared memory space both belong to the second storage unit 342. Illustratively, if the second storage unit 342 contains a first contiguous free storage space and a second contiguous free storage space, and the capacity of the first contiguous free storage space is greater than or equal to the capacity of the register space, and the capacity of the second contiguous free storage space is greater than or equal to the capacity of the shared memory space, register space is allocated to the first thread in the first contiguous free storage space, and shared memory space is allocated to the first thread in the second contiguous free storage space. Alternatively, if the second storage unit 342 contains a first contiguous free storage space and a second contiguous free storage space, and the capacity of the first contiguous free storage space is greater than or equal to the capacity of the shared memory space, and the capacity of the second contiguous free storage space is greater than or equal to the capacity of the register space, shared memory space is allocated to the first thread in the first contiguous free storage space, and register space is allocated to the first thread in the second contiguous free storage space.

[0176] Figure 9 This is a schematic diagram illustrating an allocation example provided in an exemplary embodiment of this application. For example... Figure 9 As shown, the thread allocation request carries a register space capacity of 128 bits and a shared memory space capacity of 128 bits. The white segments 821 (“0-127”) and 822 (“256-383”) in the idle status information 820 represent the free storage space in the second memory unit. Figure 9 It can be seen that the white segment 821 represents the first contiguous free memory space with a capacity of 128 bits, and the white segment 822 represents the second contiguous free memory space with a capacity of 128 bits. Therefore, the processor can receive the first thread.

[0177] like Figure 9 As shown, the memory allocation for the first thread can be as follows: Allocate the first contiguous free memory space (i.e., "0-127") in the second memory unit to the first thread as its shared memory space; allocate the second contiguous free memory space (i.e., "256-383") in the second memory unit to the first thread as its register space. Alternatively, the memory allocation can be as follows: Allocate the first contiguous free memory space (i.e., "0-127") in the second memory unit to the first thread as its register space; allocate the second contiguous free memory space (i.e., "256-383") in the second memory unit to the first thread as its shared memory space. No limitation is imposed here.

[0178] The following explanation uses the example of register space belonging to the first memory unit and shared memory space belonging to the second memory unit.

[0179] The allocation unit 310 is used to indicate the register space and the shared memory space to the update unit 350; the update unit 350 is used to write the first mapping relationship between the first request type and the register space and the second mapping relationship between the second request type and the shared memory space into the mapping table 320.

[0180] The first request type represents an access request for unique data, while the second request type represents an access request for shared data.

[0181] Optionally, the allocation unit 310 is used to indicate to the update unit 350 the storage unit to which the register space belongs and the storage address range corresponding to the register space; and to indicate to the update unit 350 the storage unit to which the shared memory space belongs and the storage address range corresponding to the shared memory space.

[0182] Schematic, allocation unit 310 indicates to update unit 350 that the register space belongs to the first storage unit and the storage address range of the register space in the first storage unit; or, allocation unit 310 indicates to update unit 350 that the register space belongs to the second storage unit and the storage address range of the register space in the second storage unit. Optionally, after receiving the instruction from update unit 350, allocation unit 310 writes the first mapping relationship into mapping table 320. Schematic, allocation unit 310 writing the first mapping relationship into mapping table 320 can be specifically implemented as follows: writing the first mapping information corresponding to the first mapping relationship into mapping table 320, wherein the first mapping information includes the request type identifier of the first request type, the thread identifier of the first thread, the storage unit identifier (first storage unit identifier or second storage unit identifier), and the address information corresponding to the storage address range of the register space. Optionally, if the size of the storage address range of the register space is a default size (e.g., 128 bits), the address information can be implemented as the start address or end address of the storage address range of the register space.

[0183] Schematic, the allocation unit 310 indicates to the update unit 350 that the shared memory space belongs to the first memory unit and the storage address range of the shared memory space in the first memory unit; or, the allocation unit 310 indicates to the update unit 350 that the shared memory space belongs to the second memory unit and the storage address range of the shared memory space in the second memory unit. Optionally, after receiving the instruction from the update unit 350, the allocation unit 310 writes the second mapping relationship into the mapping table 320. Schematic, the allocation unit 310 writing the second mapping relationship into the mapping table 320 can be specifically implemented as follows: writing the second mapping information corresponding to the second mapping relationship into the mapping table 320, wherein the second mapping information includes the request type identifier of the second request type, the thread identifier of the first thread, the memory unit identifier (first memory unit identifier or second memory unit identifier), and the address information corresponding to the storage address range of the shared memory space. Optionally, if the size of the storage address range of the shared memory space is a default size (e.g., 128 bits), the address information can be implemented as the start address or end address of the storage address range of the shared memory space.

[0184] ●Instruction execution phase

[0185] Mapping unit 330 is used to receive access requests associated with the first thread.

[0186] Optionally, the access request associated with the first thread refers to the register space access request and / or shared memory access request when the instructions of the first thread are executed, wherein the register space access request is used to request access to the unique data of the first thread, and the shared memory access request is used to request access to the shared data between the first thread and other threads.

[0187] Optionally, the access request may include the request address.

[0188] Mapping unit 330 is used to query mapping table 320 based on access request.

[0189] When the access request belongs to the first request type, the mapping unit 330 determines the first mapping relationship corresponding to the first request type in the mapping table 320, determines the first access address based on the storage address range of the register space indicated by the first mapping relationship and the request address, and indicates the first access address to the first access unit 361.

[0190] The first request type represents a request for access to unique data, that is, a register access request.

[0191] Optionally, if the access request belongs to the first request type, the first mapping information is obtained from the mapping table 320. The storage unit identifier and the storage address range of the register space are obtained from the first mapping information. Based on the storage unit identifier, the address information (taking the address information implemented as the starting address corresponding to the storage address range of the register space as an example), and the request address, the first access address is determined. For example, assuming the storage unit identifier is the first storage unit identifier, the starting address in the address information is x, and the request address is y, then the first access address is the storage address "x+y" corresponding to the first storage unit.

[0192] Optionally, after obtaining the first access address, the mapping unit 330 sends the first access address to the first access unit 361.

[0193] The first access unit 361 is used to generate a first access request based on a first access address and to send the first access request to the first storage unit 341.

[0194] Optionally, after obtaining the first access address, the first access unit 361 generates a first access request based on the first access address. The first access request is used to request access to the register space. Then, the first access unit 361 sends the first access request to the first storage unit 341.

[0195] When the access request belongs to the second request type, the mapping unit 330 determines the second mapping relationship corresponding to the second request type in the mapping table 320, determines the second access address based on the storage address range of the shared memory space indicated by the second mapping relationship and the request address, and indicates the second access address to the second access unit 362.

[0196] The second request type represents an access request for shared data, that is, a shared memory access request.

[0197] Optionally, if the access request belongs to the second request type, the second mapping information is obtained from the mapping table 320. The storage unit identifier and the storage address range of the shared memory space are obtained from the second mapping information. Based on the storage unit identifier, the address information (taking the address information implemented as the starting address corresponding to the storage address range of the shared memory space as an example), and the request address, the second access address is determined. For example, assuming the storage unit identifier is the second storage unit identifier, the starting address in the address information is z, and the request address is y, then the second access address is the storage address "z+y" corresponding to the second storage unit.

[0198] Optionally, after obtaining the second access address, the mapping unit 330 sends the second access address to the second access unit 362.

[0199] The second access unit 362 is used to generate a second access request based on the second access address and to send the second access request to the second storage unit 342.

[0200] Optionally, after obtaining the second access address, the second access unit 362 generates a second access request based on the second access address. The second access request is used to request access to the shared memory space. Then, the second access unit 362 sends the second access request to the second storage unit 342.

[0201] Figure 10 This is a schematic diagram illustrating a mapping example provided in an exemplary embodiment of this application. For example... Figure 10 As shown, mapping table 320 includes mapping information 321 and mapping information 322.

[0202] In the mapping information 321, the request type identifier "0" indicates the first request type, the storage unit identifier "0" indicates the first storage unit, and the address information "128" indicates the starting address, with a corresponding storage address range of 128. Therefore, when a thread with a thread identifier (or thread bundle identifier) ​​of "2" sends a register access request (rf_req) to the mapping unit 330, the mapping unit 330 first determines its corresponding storage address range to be "128-255" in the first storage unit. Assuming the request address in the register access request is 10 (which can be understood as an address offset), the final determined first access address is 10 + 128 = 138. The mapping unit 330 then sends the first access address "138" to the first access unit 361. The first access unit 361 generates a first access request based on the first access address "138," which is used to request access to the register space. Then, the first access unit 361 sends the first access request to the first storage unit 341. In some embodiments, the first storage unit 341 includes at least two sub-memory banks. The first access address points to the first sub-memory bank among at least two sub-memory banks of the first storage unit 341. Optionally, the first access unit 361 is configured to send a first access request to the first sub-memory bank of the first storage unit 361 according to the first access address.

[0203] In the mapping information 322, the request type identifier "1" indicates the second request type, the storage unit identifier "1" indicates the second storage unit, and the address information "0" indicates the starting address, with a corresponding storage address range of 128. When the shared memory access request (sm_req) of the thread with thread identifier (or thread bundle identifier) ​​"2" enters the mapping unit 330, the mapping unit 330 first determines its corresponding storage address range to be "0-127" in the second storage unit. Assuming the request address in the shared memory access request is 20 (which can be understood as an address offset), the final determined second access address is 20 + 0 = 20. The mapping unit 330 then sends the second access address "20" to the second access unit 362. The second access unit 362 generates a second access request based on the second access address "20," which is used to request access to the shared memory space. Then, the second access unit 362 sends the second access request to the second storage unit 342. In some embodiments, the second storage unit 342 includes at least two sub-memory banks. The second access address points to the second sub-memory bank among at least two sub-memory banks of the second storage unit 342. Optionally, the second access unit 362 is configured to send a second access request to the second sub-memory bank of the second storage unit 342 according to the second access address.

[0204] It should be noted that the above description only uses the example of the register space belonging to the first storage unit 341 and the shared memory space belonging to the second storage unit 342. In this application, it can be that: the register space belongs to the second storage unit 342 and the shared memory space belongs to the first storage unit 341; it can also be that: the register space and the shared memory space both belong to the first storage unit 341; or it can be that: the register space and the shared memory space both belong to the second storage unit 342. No limitation is made here.

[0205] Figure 11 This is a flowchart of an access method provided in an exemplary embodiment of this application. The method is applied to the storage device described in any of the above embodiments, and the storage device may be located in a processor or computer device.

[0206] The storage device includes an allocation unit, a mapping unit, and a memory; the mapping unit is connected to the memory. The access method performed in the storage device includes steps 1110 to 1130.

[0207] Step 1110: The allocation unit receives the thread allocation request corresponding to the first thread, and allocates the first storage space and the second storage space in the memory to the first thread based on the thread allocation request.

[0208] The first storage space is used to store data unique to the first thread, and the second storage space is used to store data shared between the first thread and other threads.

[0209] In some embodiments, a thread allocation request includes a first space capacity and a second space capacity required by a first thread, wherein the first space capacity represents the storage space capacity used to store unique data and the second space capacity represents the storage space capacity used to store shared data.

[0210] Optionally, if the first space capacity and the second space capacity meet the free storage space requirements of the memory, the allocation unit allocates a first storage space in the memory that matches the first space capacity and a second storage space that matches the second space capacity to the first thread.

[0211] Indicatively, when the memory contains a first contiguous free storage space with a capacity greater than or equal to the first space capacity, and a second contiguous free storage space with a capacity greater than or equal to the second space capacity, the allocation unit allocates a first storage space matching the first space capacity from the first contiguous free storage space to the first thread, and allocates a second storage space matching the second space capacity from the second contiguous free storage space to the first thread.

[0212] In some embodiments, the storage device includes: a space management table; the space management table is used to store the space usage of the storage device.

[0213] Optionally, the allocation unit queries the space management table to determine free storage units in the memory.

[0214] In some embodiments, the storage device includes a mapping table and an update unit.

[0215] Optionally, the allocation unit indicates the first storage space and the second storage space corresponding to the first thread to the update unit; the update unit writes the first mapping relationship between the first request type and the first storage space and the second mapping relationship between the second request type and the second storage space into the mapping table.

[0216] In some embodiments, the memory includes at least two storage units; the first storage space and the second storage space belong to the same storage unit; or, the first storage space and the second storage space belong to different storage units.

[0217] Step 1120: The mapping unit receives the access request associated with the first thread.

[0218] Optionally, the access request may include a request address.

[0219] In some embodiments, the mapping unit queries the mapping table based on the access request.

[0220] Step 1130: If the access request belongs to the first request type, the mapping unit performs an access operation in the first storage space; if the access request belongs to the second request type, the mapping unit performs an access operation in the second storage space.

[0221] The first request type represents an access request for unique data. The second request type represents an access request for shared data.

[0222] ●First Request Type

[0223] Optionally, if the access request belongs to the first request type, the mapping unit determines the first mapping relationship corresponding to the first request type in the mapping table, and performs the access operation in the first storage space based on the first mapping relationship.

[0224] In some embodiments, the first mapping relationship indicates a mapping relationship between a first request type and a storage address range of a first storage space.

[0225] Optionally, the mapping unit determines the first access address based on the storage address range and the requested address of the first storage space indicated by the first mapping relationship; and performs an access operation in the first storage space according to the first access address.

[0226] In some embodiments, at least two storage units each contain at least two sub-storage units, and the first storage space belongs to the i-th storage unit, where i is a positive integer.

[0227] Optionally, if the access request belongs to the first request type, the mapping unit determines the first access address based on the storage address range of the first storage space in the i-th storage unit and the request address; and sends a first access request to the first sub-storage of the i-th storage unit according to the first access address, wherein the first access address points to the first sub-storage.

[0228] In some embodiments, the storage device includes an access unit.

[0229] Optionally, if the access request belongs to the first request type, the mapping unit indicates the first access address to the access unit; the access unit generates the first access request based on the first access address and sends the first access request to the memory, the first access request being used to request access to the first storage space.

[0230] ●Second Request Type

[0231] Optionally, if the access request belongs to the second request type, the second mapping relationship corresponding to the second request type is determined in the mapping table, and the access operation is performed in the second storage space based on the second mapping relationship.

[0232] In some embodiments, the second mapping relationship indicates the mapping relationship between the second request type and the storage address range of the second storage space.

[0233] Optionally, the mapping unit determines the second access address based on the storage address range and the requested address of the second storage space indicated by the second mapping relationship; and performs an access operation in the second storage space according to the second access address.

[0234] In some embodiments, at least two storage units each contain at least two sub-storage units, and the second storage space belongs to the j-th storage unit, where j is a positive integer.

[0235] Optionally, if the access request belongs to the second request type, the mapping unit determines the second access address based on the storage address range of the second storage space in the j-th storage unit and the request address; and sends a second access request to the second sub-storage of the j-th storage unit according to the second access address, wherein the second access address points to the second sub-storage.

[0236] In some embodiments, the storage device includes an access unit.

[0237] Optionally, if the access request belongs to the second request type, the mapping unit indicates the second access address to the access unit; the access unit generates the second access request based on the second access address and sends the second access request to the memory, the second access request being used to request access to the second storage space.

[0238] In summary, the access method provided in this application allows the allocation unit in the storage device to dynamically allocate a first storage space (for exclusive data) and a second storage space (for shared data) in the memory for each new thread based on the thread allocation request. Unlike related technologies where registers and shared memory are independent, the memory in this application is dynamically divided into an exclusive data area (first storage space) and a shared data area (second storage space) by the allocation unit. This avoids the problem of insufficient free storage space in either the registers or the shared memory, which could prevent the reception of new threads and improves the utilization rate of storage space in the storage device. Furthermore, the mapping unit in the storage device can dynamically distinguish the access target (first storage space or second storage space) based on the request type of the access request, ensuring that the access operation is executed correctly, thereby improving access efficiency.

[0239] This application provides a processor. Figure 12 This is a schematic block diagram of a processor provided in an exemplary embodiment of this application. The processor 1200 includes the storage device provided in the above embodiments. Alternatively, an embodiment of this application provides a processor including programmable logic circuitry and / or program instructions, which, when running on a computer device, implement the access method provided in the above method embodiments.

[0240] Processor 1200 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1200 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). Processor 1200 may also include a main processor and a coprocessor. The main processor, also known as a central processing unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1200 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 1200 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0241] This application provides a computer device, which can be implemented as a terminal or a server. Figure 13 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device 1300 includes the storage device provided in the above embodiment. Alternatively, Figure 14 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device 1400 includes the processor provided in the above embodiments. Optionally, this application also provides a server cluster, which includes at least two computer devices, including: the storage device provided in the above embodiments, or, a processor as provided in the above embodiments.

[0242] This application provides a computer device, comprising: a processor and a storage module, wherein the storage module stores a computer program; and a processor for executing the computer program in the storage module to implement the access methods provided in the above-described method embodiments. Optionally, the storage device described above is a device on the processor, and the storage module is a module outside the processor.

[0243] This application provides a computer-readable storage medium storing a computer program, which is loaded and executed by a processor to implement the access methods provided in the above-described method embodiments.

[0244] This application provides a computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to implement the access methods provided in the above-described method embodiments.

[0245] Figure 15 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. The computer device is a server 1500. Typically, the server 1500 includes a processor 1501 and a storage module 1502.

[0246] Storage module 1502 may include one or more computer-readable storage media, which may be non-transitory. Storage module 1502 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in storage module 1502 is used to store at least one computer program, which is executed by processor 1501 to implement the access method provided in the method embodiments of this application.

[0247] In some embodiments, server 1500 may also optionally include an input interface 1503 and an output interface 1504. Processor 1501, storage module 1502, and input interface 1503 and output interface 1504 can be connected via a bus or signal lines. Various peripheral devices can be connected to input interface 1503 and output interface 1504 via a bus, signal lines, or circuit board. Input interface 1503 and output interface 1504 can be used to connect at least one input / output (I / O) related peripheral device to processor 1501 and storage module 1502. In some embodiments, processor 1501, storage module 1502, and input interface 1503 and output interface 1504 are integrated on the same chip or circuit board; in some other embodiments, any one or two of processor 1501, storage module 1502, and input interface 1503 and output interface 1504 can be implemented on separate chips or circuit boards, and this application embodiment does not limit this.

[0248] Figure 16 This is a schematic block diagram of a computer device provided in an exemplary embodiment of this application. Optionally, the computer device 1600 is a terminal.

[0249] The computer device 1600 may be a portable mobile terminal, also referred to as a mobile terminal in this embodiment. Examples include smartphones, tablets, MP3 players (Moving Picture Experts Group Audio Layer III), and MP4 players (Moving Picture Experts Group Audio Layer IV). The computer device 1600 may also be referred to as user equipment, portable terminal, or other names.

[0250] Typically, computer device 1600 includes a processor 1601 and a storage module 1602.

[0251] Storage module 1602 may include one or more computer-readable storage media, which may be non-transitory. Storage module 1602 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in storage module 1602 is used to store at least one computer program, which is executed by processor 1601 to implement the access method provided in the method embodiments of this application.

[0252] In some embodiments, the computer device 1600 may optionally include a peripheral device interface 1603 and at least one peripheral device. Specifically, the peripheral device includes at least one of a radio frequency circuit 1604, a touch display screen 1605, a camera assembly 1606, an audio circuit 1607, and a power supply 1608. The computer device 1600 also includes one or more sensors 1609. The one or more sensors 1609 include, but are not limited to, an accelerometer 1610, a gyroscope 1611, a pressure sensor 1612, an optical sensor 1613, and a proximity sensor 1614.

[0253] Those skilled in the art will understand that Figure 12 The structure shown does not constitute a limitation on the processor. Figure 13 , Figure 14 , Figure 15 and Figure 16 The structure shown does not constitute a limitation on the computer device and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0254] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0255] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0256] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0257] It should be noted that the collection and processing of relevant data (such as proprietary data, shared data, etc.) in this application should strictly comply with the requirements of relevant national laws and regulations, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing within the scope of laws and regulations and the authorization of the personal information subject.

[0258] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A storage device, characterized in that, The storage device includes: an allocation unit, a mapping unit, and a memory; The allocation unit is configured to receive a thread allocation request corresponding to the first thread; and allocate a first storage space and a second storage space in the memory to the first thread based on the thread allocation request; the first storage space is used to store the unique data of the first thread, and the second storage space is used to store the shared data between the first thread and other threads. The mapping unit is configured to receive an access request associated with the first thread; if the access request belongs to a first request type, perform an access operation in the first storage space, or if the access request belongs to a second request type, perform the access operation in the second storage space; the first request type represents an access request for the unique data, and the second request type represents an access request for the shared data.

2. The apparatus according to claim 1, characterized in that, The thread allocation request includes a first space capacity and a second space capacity required by the first thread. The first space capacity represents the storage space capacity used to store the unique data, and the second space capacity represents the storage space capacity used to store the shared data. The allocation unit is configured to allocate, for the first thread, a first storage space matching the first space capacity and a second storage space matching the second space capacity in the memory, provided that the first space capacity and the second space capacity meet the free storage space requirements of the memory.

3. The apparatus according to claim 2, characterized in that, The allocation unit is configured to, when there are first and second consecutive free storage spaces in the memory, allocate the first storage space matching the first space capacity from the first consecutive free storage space to the first thread, and allocate the second storage space matching the second space capacity from the second consecutive free storage space to the first thread, wherein the space capacity of the first consecutive free storage space is greater than or equal to the first space capacity, and the space capacity of the second consecutive free storage space is greater than or equal to the second space capacity.

4. The apparatus according to claim 2, characterized in that, The storage device includes: a space management table; the space management table is used to store the space usage of the storage device; The allocation unit is used to query the space management table to determine the free storage units in the memory.

5. The apparatus according to any one of claims 1 to 4, characterized in that, The storage device includes: a mapping table and an update unit; the update unit is connected to the allocation unit. The allocation unit is used to indicate the first storage space and the second storage space corresponding to the first thread to the update unit; The update unit is used to write the first mapping relationship between the first request type and the first storage space and the second mapping relationship between the second request type and the second storage space into the mapping table.

6. The apparatus according to claim 5, characterized in that, The mapping unit is used to query the mapping table based on the access request; The mapping unit is configured to, when the access request belongs to the first request type, determine the first mapping relationship corresponding to the first request type in the mapping table, and perform an access operation in the first storage space based on the first mapping relationship; Alternatively, if the access request belongs to the second request type, the second mapping relationship corresponding to the second request type is determined in the mapping table, and the access operation is performed in the second storage space based on the second mapping relationship.

7. The apparatus according to claim 6, characterized in that, The first mapping relationship indicates the mapping relationship between the first request type and the storage address range of the first storage space, and the second mapping relationship indicates the mapping relationship between the second request type and the storage address range of the second storage space; the access request includes a request address; The mapping unit is configured to determine a first access address based on the storage address range of the first storage space indicated by the first mapping relationship and the request address; and to perform an access operation in the first storage space according to the first access address. or, The mapping unit is used to determine a second access address based on the storage address range of the second storage space indicated by the second mapping relationship and the request address; and to perform an access operation in the second storage space according to the second access address.

8. The apparatus according to any one of claims 1 to 4, characterized in that, The memory includes at least two storage units; the at least two storage units are respectively connected to the mapping unit. The first storage space and the second storage space belong to the same storage unit; or, the first storage space and the second storage space belong to different storage units.

9. The apparatus according to claim 8, characterized in that, The at least two storage units each contain at least two sub-storage units, the first storage space belongs to the i-th storage unit, and the second storage space belongs to the j-th storage unit, where i and j are positive integers; the access request includes a request address; The mapping unit is configured to, when the access request belongs to the first request type, determine a first access address based on the storage address range of the first storage space in the i-th storage unit and the request address; and send a first access request to the first sub-storage of the i-th storage unit according to the first access address, wherein the first access address points to the first sub-storage. or, The mapping unit is configured to, when the access request belongs to the second request type, determine a second access address based on the storage address range of the second storage space in the j-th storage unit and the request address; and send a second access request to the second sub-storage of the j-th storage unit according to the second access address, wherein the second access address points to the second sub-storage.

10. The apparatus according to any one of claims 1 to 4, characterized in that, The storage device includes: an access unit, a mapping unit connected to the access unit, and an access unit connected to the memory; The mapping unit is configured to indicate a first access address to the access unit when the access request belongs to the first request type; the access unit is configured to generate a first access request based on the first access address and send the first access request to the memory, the first access request being used to request access to the first storage space; or... The mapping unit is configured to indicate a second access address to the access unit when the access request belongs to the second request type; the access unit is configured to generate a second access request based on the second access address and send the second access request to the memory, the second access request being used to request access to the second storage space.

11. A processor, characterized in that, The processor includes: a storage device as described in any one of claims 1 to 10.

12. A computer device, characterized in that, The computer device includes: a storage device as described in any one of claims 1 to 10, or a processor as described in claim 11.

13. A server cluster, characterized in that, The server cluster includes at least two computer devices, each including: a storage device as described in any one of claims 1 to 10, or a processor as described in claim 11.

14. An access method, characterized in that, Applied to a storage device, the storage device comprising: an allocation unit, a mapping unit, and a memory; The allocation unit receives a thread allocation request corresponding to the first thread; based on the thread allocation request, it allocates a first storage space and a second storage space in the memory to the first thread; the first storage space is used to store the unique data of the first thread, and the second storage space is used to store the shared data between the first thread and other threads; The mapping unit receives an access request associated with the first thread; if the access request belongs to a first request type, it performs an access operation in the first storage space, or if the access request belongs to a second request type, it performs the access operation in the second storage space; the first request type represents an access request for the unique data, and the second request type represents an access request for the shared data.

15. The method according to claim 14, characterized in that, The thread allocation request includes a first space capacity and a second space capacity required by the first thread. The first space capacity represents the storage space capacity used to store the unique data, and the second space capacity represents the storage space capacity used to store the shared data. The allocation unit allocates a first storage space and a second storage space in the memory to the first thread based on the thread allocation request, including: If the first space capacity and the second space capacity meet the free storage space requirements of the memory, the allocation unit allocates the first storage space in the memory that matches the first space capacity and the second storage space that matches the second space capacity to the first thread.

16. The method according to claim 15, characterized in that, The storage device includes: a space management table; the space management table is used to store the space usage of the storage device; The method further includes: The allocation unit queries the space management table to determine the free storage units in the memory.

17. The method according to any one of claims 14 to 16, characterized in that, The storage device includes: a mapping table and an update unit; The method further includes: The allocation unit indicates the first storage space and the second storage space corresponding to the first thread to the update unit; The update unit writes the first mapping relationship between the first request type and the first storage space, and the second mapping relationship between the second request type and the second storage space, into the mapping table.

18. The method according to any one of claims 14 to 16, characterized in that, The memory includes at least two storage units; the first storage space and the second storage space belong to the same storage unit; or, the first storage space and the second storage space belong to different storage units.

19. The method according to claim 18, characterized in that, The at least two storage units each contain at least two sub-storage units, the first storage space belongs to the i-th storage unit, and the second storage space belongs to the j-th storage unit, where i and j are positive integers; the access request includes a request address; The method further includes: When the access request belongs to the first request type, the mapping unit determines a first access address based on the storage address range of the first storage space in the i-th storage unit and the request address; and sends a first access request to the first sub-storage of the i-th storage unit according to the first access address, wherein the first access address points to the first sub-storage; or... When the access request belongs to the second request type, the mapping unit determines the second access address based on the storage address range of the second storage space in the j-th storage unit and the request address; and sends a second access request to the second sub-storage of the j-th storage unit according to the second access address, wherein the second access address points to the second sub-storage.

20. The method according to any one of claims 14 to 16, characterized in that, The storage device includes: an access unit; The method further includes: If the access request belongs to the first request type, the mapping unit indicates a first access address to the access unit; the access unit generates a first access request based on the first access address and sends the first access request to the memory, the first access request being used to request access to the first storage space; or... When the access request belongs to the second request type, the mapping unit indicates a second access address to the access unit; the access unit generates a second access request based on the second access address and sends the second access request to the memory, the second access request being used to request access to the second storage space.

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