Instruction execution method and apparatus, electronic device, and storage medium

Abstract

Embodiments of the present application provide an instruction execution method and device, electronic equipment and storage medium. The method comprises: receiving a control request of a target device, the control request comprising a request file in extensible markup language format; performing parsing processing on the request file according to the control request to obtain a physical address corresponding to the target device; mapping the physical address to a virtual address space through a memory mapping file; and reading the request file from the virtual address space through an engine and executing instructions in the request file. The above scheme stores instructions through a request file in extensible markup language format, the engine directly reads the request file through the virtual address space and executes instructions therein, and a developer does not need to generate coded instructions through manual coding, thereby improving the efficiency of instruction execution.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an instruction execution method, apparatus, electronic device, and storage medium. Background Technology

[0002] During device development, an engine is used to fulfill developers' requirements. The engine can recognize and execute development commands input by developers on the device based on their needs, thereby achieving those requirements. The engine can be used in various application scenarios, including industrial equipment and gaming devices.

[0003] In related technologies, developers generate coded instructions through manual coding, and the engine recognizes and executes the coded instructions.

[0004] However, manual coding is inefficient, resulting in low instruction execution efficiency. Summary of the Invention

[0005] This application provides an instruction execution method, apparatus, electronic device, and storage medium to improve the efficiency of instruction execution.

[0006] In a first aspect, embodiments of this application provide an instruction execution method, comprising: receiving a control request from a target device, the control request including a request file in Extensible Markup Language format; parsing the request file according to the control request to obtain a physical address corresponding to the target device; mapping the physical address to a virtual address space through a memory-mapped file; and reading the request file from the virtual address space through an engine and executing the instructions in the request file.

[0007] In one possible implementation, parsing the request file to obtain the physical address corresponding to the target device includes: parsing the request file to obtain a root node and multiple child nodes; determining a device identifier from the root node; verifying the request file using the device identifier to obtain a verification result, wherein the verification result is either verification passed or verification failed; if the verification result is verification passed, determining a target child node from the multiple child nodes, wherein the target child node is labeled with an address label; and determining the physical address of the target device from the target child node.

[0008] In one possible implementation, mapping the physical address to a virtual address space using a memory-mapped file includes: determining the address attributes of the physical address from the target child nodes; determining a mapping table for the virtual address space, the mapping table including multiple allocated memory address blocks in the virtual address space; determining multiple consecutive target memory address blocks from the virtual address space using the memory-mapped file, based on the address attributes and the mapping table; performing address mapping based on the physical address and the multiple target memory address blocks; and updating the mapping table.

[0009] In one possible implementation, the address attribute includes a data bit width; determining a plurality of consecutive target memory address blocks from the virtual address space based on the address attribute and the mapping table includes: calculating the size of a first memory block in the virtual address space that satisfies the continuity and alignment requirements based on the data bit width and alignment constraints; determining whether there is a consecutive address block matching the size of the first memory block in the free region of the virtual address space; if yes, determining the plurality of target memory address blocks corresponding to the size of the first memory block from the virtual address space; if no, merging the fragmented spaces in the virtual address space and determining the plurality of target memory address blocks corresponding to the size of the first memory block from the merged virtual address space.

[0010] In one possible implementation, updating the mapping table includes: generating a corresponding target identifier based on the historical identifiers in the mapping table and the plurality of target memory address blocks; adding the physical address, the plurality of target memory address blocks, and the target identifier to the mapping table to obtain an updated mapping table; and replacing the mapping table with the updated mapping table through atomic operations to achieve the update process.

[0011] In one possible implementation, executing the instructions in the request file includes: parsing the request file using an engine to obtain input instructions and operation types; determining a target template corresponding to the operation type from a template library; generating a target instruction that the engine can recognize based on the input instructions and the target template; and executing the target instruction using the engine to execute the request file.

[0012] In one possible implementation, the request file further includes: a request priority and / or a timeout duration; the method further includes: determining a target instruction queue corresponding to the target device, the target instruction queue being used to indicate the order in which the engine executes instructions; determining the target position of the target instruction in the target instruction queue according to the request priority and / or the timeout duration; and adding the target instruction to the target instruction queue according to the target position.

[0013] Secondly, embodiments of this application provide an instruction execution apparatus, comprising: a receiving module for receiving a control request from a target device, the control request including a request file in Extensible Markup Language format; a parsing module for parsing the request file according to the control request to obtain a physical address corresponding to the target device; a mapping module for mapping the physical address to a virtual address space through a memory mapping file; and an execution module for reading the request file from the virtual address space through an engine and executing the instructions in the request file.

[0014] In one possible implementation, the parsing module is specifically configured to parse the request file to obtain a root node and multiple child nodes of the request file; the parsing module is further configured to determine a device identifier from the root node; the parsing module is further configured to verify the request file using the device identifier to obtain a verification result, wherein the verification result is either verification passed or verification failed; the parsing module is further configured to, if the verification result is verification passed, determine a target child node from the multiple child nodes, wherein the target child node is labeled with an address label; the parsing module is further configured to determine the physical address of the target device from the target child node.

[0015] In one possible implementation, the apparatus further includes: a processing module, configured to determine the address attributes of the physical address from the target child node; the processing module is further configured to determine a mapping table of the virtual address space, the mapping table including a plurality of allocated memory address blocks in the virtual address space; the processing module is further configured to determine a plurality of consecutive target memory address blocks from the virtual address space using a memory-mapped file, based on the address attributes and the mapping table; the processing module is further configured to perform address mapping based on the physical address and the plurality of target memory address blocks, and update the mapping table.

[0016] In one possible implementation, the address attribute includes a data bit width; the processing module is specifically configured to calculate the size of a first memory block in the virtual address space that satisfies the continuity and alignment requirements based on the data bit width and alignment constraints; the processing module is further configured to determine whether there is a contiguous address block matching the size of the first memory block in the free region of the virtual address space; the processing module is further configured to determine, if yes, the plurality of target memory address blocks corresponding to the size of the first memory block from the virtual address space; the processing module is further configured to, if no, merge the fragmented spaces in the virtual address space and determine the plurality of target memory address blocks corresponding to the size of the first memory block from the merged virtual address space.

[0017] In one possible implementation, the processing module is specifically configured to generate a corresponding target identifier based on the historical identifiers in the mapping table and the plurality of target memory address blocks; the processing module is further configured to add the physical address, the plurality of target memory address blocks, and the target identifier to the mapping table to obtain an updated mapping table; the processing module is further configured to replace the mapping table with the updated mapping table through atomic operations to achieve the update processing.

[0018] In one possible implementation, the apparatus further includes: a generation module, configured to parse the request file using an engine to obtain input instructions and operation types; the generation module is further configured to determine a target template corresponding to the operation type from a template library; the generation module is further configured to generate a target instruction that the engine can recognize based on the input instructions and the target template; the generation module is further configured to execute the target instruction using the engine to execute the request file.

[0019] In one possible implementation, the request file further includes: a request priority and / or a timeout duration; the device further includes: a sorting module, configured to determine a target instruction queue corresponding to the target device, the target instruction queue being used to indicate the order in which the engine executes instructions; the sorting module is further configured to determine the target position of the target instruction in the target instruction queue according to the request priority and / or the timeout duration; the sorting module is further configured to add the target instruction to the target instruction queue according to the target position.

[0020] Thirdly, embodiments of this application provide an instruction execution device, including: a memory and a processor;

[0021] The memory stores computer-executed instructions;

[0022] The processor executes computer execution instructions stored in the memory, causing the processor to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0023] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0024] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0025] The instruction execution method, apparatus, electronic device, and storage medium provided in this application include: receiving a control request from a target device, the control request including a request file in Extensible Markup Language (XML) format; parsing the request file according to the control request to obtain the physical address corresponding to the target device; mapping the physical address to a virtual address space using a memory-mapped file; and reading the request file from the virtual address space using an engine and executing the instructions in the request file. This solution uses an XML-formatted request file to store instructions, and the engine directly reads the request file from the virtual address space and executes the instructions therein. Developers do not need to manually generate coded instructions, thereby improving the efficiency of instruction execution. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0027] Figure 1 This is a schematic diagram illustrating an application scenario of an instruction execution method provided in an embodiment of this application;

[0028] Figure 2 A flowchart illustrating an instruction execution method provided in an embodiment of this application;

[0029] Figure 3 A flowchart illustrating an instruction execution method provided in an embodiment of this application;

[0030] Figure 4 A schematic diagram of the hierarchical structure of the request file provided in this application embodiment;

[0031] Figure 5 A schematic diagram of the virtual address space provided in the embodiments of this application;

[0032] Figure 6 A schematic diagram illustrating the engine application provided in the embodiments of this application;

[0033] Figure 7 A schematic diagram illustrating the execution target instructions provided in an embodiment of this application;

[0034] Figure 8 This is a schematic diagram of the structure of an instruction execution device provided in an embodiment of this application;

[0035] Figure 9 This is a schematic diagram of the structure of an instruction execution device provided in an embodiment of this application;

[0036] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0037] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0038] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0039] It should be noted that the instruction execution method, apparatus, electronic device and storage medium of this application can be used in the field of computer technology, or in any field other than computers. The application field of the instruction execution method, apparatus, electronic device and storage medium of this application is not limited.

[0040] Figure 1 This is a schematic diagram illustrating an application scenario of an instruction execution method provided in an embodiment of this application. An example is given based on the illustrated scenario: the device generates and sends an instruction to the engine; the engine recognizes and executes the instruction, obtaining the execution result.

[0041] In practical applications, developers generate instructions, which are used for device development. The engine can be set up on multiple devices, executing instructions from each device to accomplish development tasks across multiple devices.

[0042] In related technologies, each developer has their own data structure or format, which may differ due to project requirements or developer habits. Developers manually hard-code instructions, which incurs learning costs and coding difficulties. They need to master multiple areas such as hardware registers, communication protocols, and control algorithms, spending a significant amount of time on low-level details (such as address calculation and protocol parsing), leading to low coding efficiency and impacting the overall efficiency of device development. Furthermore, when hardware changes, instructions need to be recompiled, and hardware configuration information is scattered throughout the instructions, resulting in low instruction maintenance efficiency.

[0043] The method for executing instructions provided in this application is intended to solve the above-mentioned technical problems of the prior art.

[0044] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0045] Figure 2 This application provides a flowchart illustrating an instruction execution method, which includes the following steps:

[0046] S201. Receive a control request from the target device. The control request includes a request file in Extensible Markup Language format.

[0047] For example, Extensible Markup Language (XML) is a structured markup language that allows data structures to be defined using tags.

[0048] For example, developers only need to declare the target state in XML, without needing to worry about how it is implemented. The engine can automatically parse the XML configuration into underlying operation instructions and execute them, thereby reducing the amount of coding required by developers and improving the efficiency of instruction execution.

[0049] Optional. Generate request files via a drag-and-drop graphical user interface. The drag-and-drop graphical user interface provides visual operations (such as dragging and dropping components, configuring connections, etc.), allowing developers to quickly generate request files through drag-and-drop operations without the need for coding.

[0050] For example, drag-and-drop graphical user interfaces provide a unified logic that is not affected by different formats, so the engine can accurately identify request files generated by different developers based on drag-and-drop graphical user interfaces.

[0051] S202. Based on the control request, the request file is parsed and processed to obtain the physical address corresponding to the target device.

[0052] For example, the physical address is the actual address where the requested file is stored. The request file includes address information, and the physical address is determined based on this address information.

[0053] Optionally, the address information includes an address identifier, which is used to determine the unique corresponding physical address.

[0054] S203. Map physical addresses to virtual address space using memory-mapped files.

[0055] For example, a memory-mapped file (MMF) is a memory-file interaction mechanism. Its core idea is to directly map file content to the virtual address space of a process, making file operations as efficient as accessing memory.

[0056] In related technologies, sending request files or instructions to the engine via a file interface is inefficient.

[0057] For example, a virtual address space is used to provide a unified address view for multiple devices. Different regions in the virtual address space are used to map different request files. The engine can directly access each request file in the virtual address space, thereby managing multiple request files in a unified manner through the virtual address space.

[0058] Optionally, the virtual address space can be shared by multiple devices, enabling interaction between them. This interaction eliminates the need for industrial bus translation, effectively saving overhead. Therefore, providing a unified virtual address space simplifies the collaboration logic between multiple devices.

[0059] S204. The engine reads the request file from the virtual address space and executes the instructions in the request file.

[0060] For example, the engine can directly access the request file in the virtual address space without first copying the request file to the buffer, thereby improving the efficiency of the engine in executing instructions.

[0061] For example, the instructions in the request file are logically described instructions. The engine can automatically convert the logically described instructions into executable instructions, thereby reducing the developer's operations and improving the execution efficiency of the instructions.

[0062] The instruction execution method provided in this application embodiment receives a control request from a target device, the control request including a request file in Extensible Markup Language (XML) format; based on the control request, the request file is parsed to obtain the physical address corresponding to the target device; the physical address is mapped to a virtual address space through a memory-mapped file; and the engine reads the request file from the virtual address space and executes the instructions in the request file. This solution uses an XML-formatted request file to store instructions, and the engine directly reads the request file from the virtual address space and executes the instructions therein. Developers do not need to manually generate coded instructions, thereby improving the efficiency of instruction execution.

[0063] Based on any of the above embodiments, the following, in conjunction with Figure 3 This section provides a detailed explanation of the instruction execution process.

[0064] Figure 3 This is a flowchart illustrating an instruction execution method provided in an embodiment of this application. Figure 3 As shown, the method includes:

[0065] S301. Receive a control request from the target device. The control request includes a request file in Extensible Markup Language format.

[0066] It should be noted that the execution process of S301 is the same as that of S201, and will not be repeated here.

[0067] S302. Based on the control request, parse the request file to obtain the physical address corresponding to the target device.

[0068] One feasible implementation method involves parsing the request file as follows: parsing the request file to obtain the root node and multiple child nodes; determining the device identifier from the root node; verifying the request file using the device identifier to obtain a verification result, which is either verification passed or verification failed; if the verification result is verification passed, determining the target child node from the multiple child nodes, with the target child node labeled as an address label; and determining the physical address of the target device from the target child node.

[0069] For example, the request file is set up as a hierarchy of root and child nodes.

[0070] Below, in conjunction with Figure 4 Describe the hierarchical structure of the request file.

[0071] Figure 4 This is a schematic diagram illustrating the hierarchical structure of the request file provided in an embodiment of this application. For example... Figure 4 As shown, the root node, when expanded, includes the root node's attributes and its child nodes. Child nodes can be further expanded, each including its own attributes and its own child nodes. The type is used to distinguish different types of nodes.

[0072] Optionally, the device identifier can be determined from the root node attributes. The device identifier is a unique identifier for a device, used to distinguish different devices.

[0073] Optionally, maintain a device identifier library and verify device identifiers using the device identifier library. If the device identifier library contains a device identifier, the verification is successful.

[0074] Optionally, verification can be performed using a checksum. If the checksum in the root node is valid, the verification passes.

[0075] With the help of scenario examples, it can be shown that validation can filter invalid request files, avoid the waste of resources by executing invalid request files, and thus improve the efficiency of instruction execution.

[0076] For example, each child node can store different information, and the type of each child node displays a label of the information stored by the child node. The target child node is determined according to the type, and the address label is displayed in the information of the target child node. The physical address is determined from the target child node.

[0077] Optionally, the target child node stores the address offset, and the physical address is determined based on the offset.

[0078] In this feasible implementation, the layered request file allows for rapid verification and determination of physical addresses, thereby improving the efficiency of instruction execution.

[0079] S303. Determine the address attributes of the physical address from the target child node.

[0080] For example, address attributes can be used to describe the occupancy information of a physical address, such as the size of the space required, the type of space, or the space permissions. Address attributes enable accurate address mapping.

[0081] S304. Determine the mapping table of the virtual address space, which includes multiple allocated memory address blocks in the virtual address space.

[0082] For example, the virtual address space includes multiple memory address blocks. The allocated memory address blocks are memory blocks that have been mapped to other physical addresses. By identifying multiple allocated memory address blocks, address mapping conflicts are avoided, thereby improving the reliability of address mapping.

[0083] Optionally, multiple allocated memory address blocks can be determined based on the real-time status of the mapping table. The real-time status indicates the usage of each memory address block, and unused memory blocks can be cleaned up in a timely manner based on the usage.

[0084] S305. Using a memory-mapped file, determine multiple consecutive target memory address blocks from the virtual address space based on address attributes and a mapping table.

[0085] For example, multiple target memory address blocks meet the address attribute requirements to ensure that the granularity of the physical address matches that of the target memory address block.

[0086] For example, identifying multiple contiguous target memory address blocks can avoid memory fragmentation, thereby improving the memory utilization of the virtual address space.

[0087] One feasible implementation, where the address attribute includes data bit width, can determine multiple consecutive target memory address blocks by: calculating the size of a first memory block in the virtual address space that meets the continuity and alignment requirements based on the data bit width and alignment constraints; determining whether there is a consecutive address block matching the size of the first memory block in the free region of the virtual address space; if so, determining multiple target memory address blocks corresponding to the size of the first memory block from the virtual address space; if not, merging fragmented spaces in the virtual address space and determining multiple target memory address blocks corresponding to the size of the first memory block from the merged virtual address space.

[0088] Below, in conjunction with Figure 5 Explain the virtual address space.

[0089] Figure 5 This is a schematic diagram of the virtual address space provided in an embodiment of this application. Figure 5 As shown, the virtual address space includes multiple memory blocks, which consist of used memory blocks and unused free memory blocks. The target memory address block that meets the requirements is determined from the free memory blocks.

[0090] For example, the size of the first memory block is the size of the memory block required by the requested file. The minimum operation unit (MOU) is determined by the data bit width, and the size of the first memory block is calculated based on the MOU and the required space. For instance, if the MOU calculated based on the data bit width is 4KB, then the size of the first memory block should be an integer multiple of 4KB. If the required memory block size is 5KB, aligning to 4KB, the size of the first memory block can be determined as 5KB rounded up, i.e., 8KB. If there are 8KB contiguous memory blocks in the virtual address space, multiple target memory address blocks are determined. If there are no 8KB contiguous memory blocks in the virtual address space, adjacent memory blocks are merged to obtain a merged virtual address space.

[0091] For example, alignment constraints ensure that the size of the first memory block meets the developer's requirements, avoiding bus errors caused by address misalignment. Fragmentation merging eliminates gaps between free blocks, supporting efficient allocation of large block requests.

[0092] In this feasible implementation, the verification process is performed using the size of the first memory block to improve the accuracy of address mapping.

[0093] S306. Perform address mapping based on physical address and multiple target memory address blocks, and update the mapping table.

[0094] For example, an address mapping relationship is established between a physical address and multiple target memory address blocks, so that the engine can access the physical address through multiple target memory address blocks, thereby enabling the engine to quickly obtain the requested file under the physical address.

[0095] For example, by updating the mapping table, the updated mapping table can accurately reflect the real-time address mapping relationship, thereby improving the accuracy of subsequent address allocation.

[0096] One feasible implementation method is to perform the update process as follows: generate a corresponding target identifier based on the historical identifier in the mapping table and multiple target memory address blocks; add the physical address, multiple target memory address blocks, and target identifier to the mapping table to obtain an updated mapping table; and replace the mapping table with the updated mapping table through atomic operations to achieve the update process.

[0097] For example, the history identifier is a used identifier used to identify allocated memory address blocks. The target identifier is used to identify multiple target memory address blocks, and the target identifier is different from the history identifier.

[0098] For example, the process of generating and updating the mapping table is synchronized with the process of using the current mapping table. That is, while the mapping table is being updated, the current mapping table can still be used normally to read mapping relationships. After the updated mapping table is generated, it is replaced through atomic operations so that the mapping relationship can be read through the updated mapping table, thus achieving a seamless update.

[0099] In this feasible implementation, atomic operations are used to prevent other threads from reading the intermediate state of the mapping table during the update process, ensuring that the mapping table is always in a valid state, thereby improving the reliability of instruction execution.

[0100] S307. The engine parses and processes the request file to obtain the input instructions and operation type.

[0101] For example, input instructions are determined based on development requirements and are used to instruct the engine on the operations that need to be performed. Operation types are used to categorize operations.

[0102] S308. Determine the target template corresponding to the operation type from the template library.

[0103] For example, the templates stored in the template library include general information about the execution instructions, which can be used to explain the instructions and assist the engine in executing them.

[0104] For example, each operation type has a corresponding template to accurately interpret the instructions. Operation types include, but are not limited to, at least one of the following: data reading or data writing.

[0105] Optionally, the template library stores templates corresponding to different application scenarios.

[0106] Below, in conjunction with Figure 6 The engine application is explained.

[0107] Figure 6 This is a schematic diagram illustrating the engine application provided in an embodiment of this application. For example... Figure 6 As shown, the engine can execute instructions for different scenarios, such as communication, process flow, parameter configuration, control, event logs, or data logs. The operations performed in different scenarios are different. Templates can help the engine accurately distinguish between different scenarios, thereby improving the accuracy of execution.

[0108] S309. Based on the input instructions and the target template, generate target instructions that the engine can recognize.

[0109] For example, the target template may include placeholders for general information. By adding input instructions to the positions corresponding to the placeholders in the target template, the target instructions can be obtained.

[0110] For example, target instructions are instructions that the engine can directly recognize, so that the engine can correctly implement the developer's requirements. Generating target instructions can improve the accuracy of instruction execution.

[0111] S310, executes target instructions through the engine to fulfill the execution request file.

[0112] With the example scenario, developers only need to generate a request file. The platform will automatically generate the corresponding target instructions and hand them over to the engine for execution, thereby reducing the developer's workload and improving the efficiency of instruction execution.

[0113] Optionally, during engine execution, the execution status is written to a log, which allows for timely tracking.

[0114] One feasible implementation method includes request priority and / or timeout duration; the instruction execution method further includes: determining the target instruction queue corresponding to the target device, the target instruction queue being used to indicate the order in which the engine executes instructions; determining the target position of the target instruction in the target instruction queue based on the request priority and / or timeout duration; and adding the target instruction to the target instruction queue based on the target position.

[0115] For example, priority indicates the urgency of the requested file; urgent requests have higher priority and are placed earlier in the instruction queue. Timeout indicates the maximum allowed delay for the requested file; for example, a timeout of 10 minutes means the requested file needs to be completed within 10 minutes. The target location determined based on priority and / or timeout matches the priority of the requested file, or guarantees that the requested file will be completed within the timeout period.

[0116] Below, in conjunction with Figure 7 The execution target instructions are explained.

[0117] Figure 7 This is a schematic diagram illustrating the execution target instructions provided in an embodiment of this application. For example... Figure 7 As shown, the user generates a request file, the platform sorts the request files, performs memory mapping according to the sorting, and the engine reads the request file from the virtual address space and executes it.

[0118] In this feasible implementation, the target instructions are sorted through a queue to ensure that the execution order of the target instructions meets the developer's requirements, thereby improving the reliability of instruction execution.

[0119] Figure 8 This is a schematic diagram of the structure of an instruction execution device provided in an embodiment of this application. Figure 8 As shown, the instruction execution device 80 may include: a receiving module 81, a parsing module 82, a mapping module 83, and an execution module 84, wherein,

[0120] The receiving module 81 is used to receive control requests from the target device. The control requests include a request file in Extensible Markup Language format.

[0121] The parsing module 82 is used to parse the request file according to the control request to obtain the physical address corresponding to the target device.

[0122] Mapping module 83 is used to map physical addresses to the virtual address space via memory-mapped files.

[0123] Execution module 84 is used to read the request file from the virtual address space through the engine and execute the instructions in the request file.

[0124] Optionally, the receiving module 81 can perform... Figure 2 S201 in the embodiment.

[0125] Optionally, the parsing module 82 can be executed. Figure 2 S202 in the embodiment.

[0126] Optionally, mapping module 83 can execute Figure 2 S203 in the embodiment.

[0127] Optionally, execution module 84 can execute Figure 2 S204 in the embodiment.

[0128] It should be noted that the instruction execution device shown in the embodiments of this application can execute the technical solutions shown in the above method embodiments, and its implementation principle and beneficial effects are similar, so they will not be described again here.

[0129] In one possible implementation, the parsing module 82 is specifically used for:

[0130] The request file is parsed to obtain the root node and multiple child nodes of the request file;

[0131] Determine the device identifier from the root node;

[0132] The verification result is obtained by verifying the request file using the device identifier. The verification result is either verification passed or verification failed.

[0133] If the verification result is successful, the target child node is determined from multiple child nodes, and the label of the target child node is the address label;

[0134] Determine the physical address of the target device from the target child nodes.

[0135] Figure 9 This is a schematic diagram of the structure of an instruction execution device provided in an embodiment of this application. Figure 8 Based on the illustrated embodiments, as Figure 9 As shown, the instruction execution device 90 further includes: a processing module 85, a generation module 86, and a sorting module 87, wherein,

[0136] Processing module 85 is used for:

[0137] Determine the address attribute of the physical address from the target child node;

[0138] Determine the mapping table of the virtual address space, which includes multiple allocated memory address blocks in the virtual address space;

[0139] Using memory-mapped files, multiple consecutive target memory address blocks are determined from the virtual address space based on address attributes and mapping tables.

[0140] Address mapping is performed based on physical addresses and multiple target memory address blocks, and the mapping table is updated.

[0141] In one possible implementation, the address attribute includes the data bit width; the processing module 85 is specifically used for:

[0142] Based on the data bit width, calculate the size of the first memory block in the virtual address space that satisfies the continuity and alignment requirements through alignment constraints;

[0143] Determine whether there is a contiguous address block in the free region of the virtual address space that matches the size of the first memory block;

[0144] If so, then determine the multiple target memory address blocks corresponding to the size of the first memory block from the virtual address space;

[0145] If not, then the fragmented spaces in the virtual address space are merged, and multiple target memory address blocks corresponding to the first memory block size are determined from the merged virtual address space.

[0146] In one possible implementation, the processing module 85 is specifically used for:

[0147] Based on the historical identifiers in the mapping table and multiple target memory address blocks, generate the corresponding target identifier;

[0148] In the mapping table, add the physical address, multiple target memory address blocks, and target identifier to obtain the updated mapping table;

[0149] The update process is achieved by replacing the existing mapping table with an updated one using atomic operations.

[0150] Module 86 is generated for:

[0151] The engine parses and processes the request file to obtain the input instructions and operation types;

[0152] Determine the target template corresponding to the operation type from the template library;

[0153] Based on the input instructions and the target template, generate target instructions that the engine can recognize;

[0154] The engine executes the target instructions to fulfill the execution request file.

[0155] The request file also includes: request priority and / or timeout duration; sorting module 87, used for:

[0156] Determine the target instruction queue corresponding to the target device. The target instruction queue is used to indicate the order in which the engine executes instructions.

[0157] The target position in the target instruction queue is determined based on the request priority and / or timeout duration.

[0158] Based on the target location, add the target instruction to the target instruction queue.

[0159] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 10 As shown, the electronic device includes:

[0160] The electronic device includes a processor 291 and a memory 292; it may also include a communication interface 293 and a bus 294. The processor 291, memory 292, and communication interface 293 can communicate with each other via the bus 294. The communication interface 293 can be used for information transmission. The processor 291 can invoke logical instructions stored in the memory 292 to execute the methods of the above embodiments.

[0161] Furthermore, the logic instructions in the aforementioned memory 292 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0162] The memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this application. The processor 291 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 292, thereby implementing the methods in the above-described method embodiments.

[0163] The memory 292 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 292 may include high-speed random access memory and may also include non-volatile memory.

[0164] This application provides a non-transitory computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the methods described in the foregoing embodiments.

[0165] This application provides a computer program product, including a computer program that, when executed by a processor, implements the method as described in the foregoing embodiments.

[0166] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0167] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0168] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0169] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0170] When the integrated unit / module is implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, memristors, etc. The processor can be any suitable hardware processor, such as CPU, GPU, FPGA, DSP, and ASIC. The storage unit can be any suitable magnetic or magneto-optical storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.

[0171] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0172] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0173] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0174] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for executing instructions, characterized in that, include: Receive a control request from the target device, the control request including a request file in Extensible Markup Language format; Based on the control request, the request file is parsed to obtain the physical address corresponding to the target device; The physical address is mapped to the virtual address space using a memory-mapped file; The engine reads the request file from the virtual address space and executes the instructions in the request file.

2. The method according to claim 1, characterized in that, The request file is parsed to obtain the physical address corresponding to the target device, including: The request file is parsed to obtain the root node and multiple child nodes of the request file; The device identifier is determined from the root node; The verification result is obtained by verifying the request file using the device identifier, and the verification result is either verification passed or verification failed. If the verification result is successful, then the target child node is determined from the plurality of child nodes, and the label of the target child node is an address label; The physical address of the target device is determined from the target child node.

3. The method according to claim 2, characterized in that, Mapping the physical address to the virtual address space using a memory-mapped file includes: Determine the address attribute of the physical address from the target child node; Determine a mapping table for the virtual address space, the mapping table including multiple allocated memory address blocks in the virtual address space; Using a memory-mapped file, and based on the address attributes and the mapping table, a plurality of consecutive target memory address blocks are determined from the virtual address space. Address mapping is performed based on the physical address and the plurality of target memory address blocks, and the mapping table is updated.

4. The method according to claim 3, characterized in that, The address attribute includes the data bit width; based on the address attribute and the mapping table, determining multiple consecutive target memory address blocks from the virtual address space includes: Based on the data bit width, the size of the first memory block in the virtual address space that satisfies the continuity and alignment requirements is calculated through alignment constraints. Determine whether there is a contiguous address block in the free region of the virtual address space that matches the size of the first memory block; If so, then determine the plurality of target memory address blocks corresponding to the size of the first memory block from the virtual address space; If not, then the fragmented spaces in the virtual address space are merged, and the plurality of target memory address blocks corresponding to the size of the first memory block are determined from the merged virtual address space.

5. The method according to claim 3, characterized in that, The update process for the mapping table includes: Based on the historical identifiers in the mapping table and the multiple target memory address blocks, a corresponding target identifier is generated; The physical address, the plurality of target memory address blocks, and the target identifier are added to the mapping table to obtain an updated mapping table; The update process is achieved by replacing the update mapping table with the update mapping table through atomic operations.

6. The method according to any one of claims 1-5, characterized in that, Executing the instructions in the request file includes: The engine parses and processes the request file to obtain the input instructions and operation types; Determine the target template corresponding to the operation type from the template library; Based on the input instructions and the target template, a target instruction that the engine can recognize is generated; The engine executes the target instructions to execute the requested file.

7. The method according to claim 6, characterized in that, The request file further includes: request priority and / or timeout duration; the method further includes: Determine the target instruction queue corresponding to the target device, wherein the target instruction queue is used to indicate the order in which the engine executes instructions; Based on the request priority and / or the timeout duration, determine the target position of the target instruction in the target instruction queue; Based on the target location, the target instruction is added to the target instruction queue.

8. An instruction execution device, characterized in that, include: A receiving module is used to receive control requests from a target device, wherein the control requests include a request file in Extensible Markup Language format; The parsing module is used to parse the request file according to the control request to obtain the physical address corresponding to the target device; The mapping module is used to map the physical address to the virtual address space through a memory-mapped file; An execution module is used to read the request file from the virtual address space through the engine and execute the instructions in the request file.

9. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-7.

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