Garbage collection methods for NAND Flash storage systems, computer equipment, and storage media.

Abstract

Embodiments of the present application provide a garbage collection method of a NAND Flash storage system, a computer device and a storage medium, and relate to the technical field of flash data. The method comprises: in a write operation execution process, obtaining a mapping relationship between a physical address and a logical address and synchronously writing the mapping relationship into a physical-to-logical mapping page in a current physical block; reading all physical-to-logical mapping pages in a source physical block, and traversing each mapping entry of the physical-to-logical mapping pages; calculating a corresponding mapping table number according to a logical address of each mapping entry, and constructing a mapping table reference bitmap; traversing the mapping table reference bitmap according to an incremental order of the mapping table numbers, determining that a mapping entry is valid data when a physical address recorded by the mapping entry belongs to the source physical block, and adding the valid data to a to-be-moved list; and after moving all valid data in the to-be-moved list to a target physical block, performing an erase operation on the source physical block. The embodiments of the present application can reduce the GC time consumption in a random write scenario.

Description

Technical Field

[0001] This application relates to the field of flash memory data technology, and in particular to a garbage collection method, computer equipment, and storage medium for a NAND Flash storage system. Background Technology

[0002] In related technologies, during garbage collection of solid-state storage devices (such as SSDs, eMMC, and UFS), valid data needs to be located and moved from the source physical block to be reclaimed. One existing optimization is to pre-store an index table during data writing, recording which L1 tables (first-level mapping tables) are involved in the write data within that physical block, so that they can be directly read during garbage collection. However, this method requires a large buffer space to store the index table in random write scenarios. Meanwhile, another common problem is that without a pre-built index mechanism during writes, garbage collection still needs to frequently read the L1 table from the NAND flash memory to determine data validity, resulting in extremely high time overhead due to numerous repeated reads. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a garbage collection method, computer device, and storage medium for a NAND Flash storage system, aiming to reduce GC time in random write scenarios.

[0004] In a first aspect, embodiments of this application provide a garbage collection method for a NAND Flash storage system, the method comprising: During the write operation, the mapping relationship between physical address and logical address is obtained and the mapping relationship is synchronously written into the physical-to-logical mapping page in the current physical block. The physical-to-logical mapping page is interspersed within the current data block at a preset fixed interval. During the execution of the garbage collection task, all the physical-to-logical mapping pages in the source physical block are read, and each mapping entry of the physical-to-logical mapping page is traversed. Calculate the corresponding mapping table number based on the logical address of each mapping entry, and construct a mapping table reference bitmap; The mapping table reference bitmap is traversed in ascending order of the mapping table number. When the physical address recorded by the mapping entry belongs to the source physical block, the mapping entry is determined to be valid data, and the valid data is added to the list to be moved. After moving all valid data from the list to be moved to the target physical block, an erase operation is performed on the source physical block.

[0005] According to some embodiments of this application, obtaining the mapping relationship between physical addresses and logical addresses and synchronously writing the mapping relationship between physical addresses and logical addresses into the physical-to-logical mapping page includes: The pages of the current physical block are divided into fixed-size groups, where each group contains N data pages; After each write operation is completed, the mapping relationship between the written physical address and logical address is obtained, and the mapping relationship is updated to the physical-to-logical mapping buffer in SRAM. Once all mapping entries for the data pages of each group have been filled, the mapping relationship is written into the physical-to-logical mapping page within the current physical block.

[0006] According to some embodiments of this application, updating the mapping relationship to the physical-to-logical mapping buffer in SRAM includes: Obtain the current physical page number of the currently written data page and the starting physical page number of the current group; Calculate the difference between the current physical page number and the starting physical page number to obtain the offset of the currently written data page within the group; Based on each logical address within the currently written physical page, the value of the corresponding logical address is cyclically filled into the position corresponding to the offset in the physical-to-logical mapping buffer in SRAM.

[0007] According to some embodiments of this application, after writing the mapping relationship into the physical-to-logical mapping page within the current physical block, the method further includes: Get the total number of pages in the current physical block; When the write operation is complete, if the current physical page number is less than the total number of pages in the current physical block, the physical-to-logical mapping buffer in the SRAM is cleared, and the starting data page number of the next group is updated.

[0008] According to some embodiments of this application, the construction of the mapping table reference bitmap further includes: When the garbage collection task is started, the contiguous storage space required by the mapping table reference bitmap is dynamically requested from the free memory pool of SRAM; After the garbage collection task is completed, the storage space occupied by the mapping table reference bitmap is released and returned to the free memory pool of SRAM.

[0009] According to some embodiments of this application, the source physical block is obtained through the following steps, including: Get all closed or partially closed physical blocks; The source physical blocks are obtained by filtering all closed or partially closed physical blocks according to a preset strategy algorithm, wherein the preset strategy algorithm includes at least one of the following: wear leveling priority, hot and cold data separation, and high inefficiency priority.

[0010] According to some embodiments of this application, the method further includes: When the garbage collection task is interrupted due to priority preemption or timeout protection, the mapping table reference bitmap is written to a preset designated storage location in the NAND Flash storage system.

[0011] According to some embodiments of this application, it also includes: When the garbage collection task is restarted, it is checked whether there is valid persistent bitmap data in the preset specified storage location; If the valid persistent bitmap data exists, the mapping table reference bitmap is read from the preset specified storage location and restored.

[0012] Secondly, embodiments of this application provide a computer device, including: At least one memory; At least one processor; At least one computer program; The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the garbage collection method for the NAND Flash storage system described in the first aspect above.

[0013] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program for causing a computer to execute the garbage collection method for the NAND Flash storage system described in the first aspect.

[0014] The technical solution according to the embodiments of this application has at least the following beneficial effects: This application synchronously updates the P2L mapping data during the write operation, so that each current data block maintains complete reverse mapping information. During the GC process, only the P2L pages in the source block need to be read to know the logical addresses of all data pages in the block, without relying on the L2P mapping table for page-by-page lookup, which greatly reduces the mapping lookup overhead during the GC process. By constructing a mapping table reference bitmap (L1_bitmap), all L1 tables involved in the source block are pre-deduplicated and compressed into a concise candidate list. In the subsequent validity verification stage, each L1 table only needs to be loaded once, fundamentally eliminating the performance bottleneck of the same L1 table being repeatedly loaded in the traditional method, and significantly reducing the number of NAND reads and cache occupation. By persisting the L1_bitmap to a specified location in the NAND Flash, the interrupted resumption of GC task scanning function is realized. When GC is interrupted due to priority preemption or timeout protection, the previously built L1_bitmap can be directly restored upon restart, without rereading P2L pages and rebuilding the bitmap. This avoids a large amount of redundant calculations and I / O operations, significantly improving the overall efficiency of GC. The storage space requirement of L1_bitmap is extremely small (depending only on the total number of L1 tables), can be efficiently managed in SRAM, has low memory footprint, and is suitable for resource-constrained embedded storage devices.

[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0016] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0017] Figure 1 This is a schematic flowchart of a garbage collection method for a NAND Flash storage system provided in one embodiment of this application; Figure 2 This is a schematic diagram of the process of synchronously writing to a physical-to-logical mapped page according to an embodiment of this application; Figure 3 This is a schematic diagram of the process for updating the mapping relationship provided in one embodiment of this application; Figure 4 This is a schematic diagram of the process after writing the physical-to-logical mapping page within the current physical block, according to one embodiment of this application; Figure 5 This is a schematic diagram of the subsequent process of constructing a mapping table reference bitmap according to one embodiment of this application; Figure 6This is a schematic diagram of the process for obtaining the source physical block provided in one embodiment of this application; Figure 7 This is a schematic diagram of a process for writing a mapping table reference bitmap into a preset specified storage location in a NAND Flash storage system, provided in one embodiment of this application. Figure 8 This is a schematic diagram of the process after writing a mapping table reference bitmap into a preset specified storage location in a NAND Flash storage system, according to one embodiment of this application. Figure 9 This is a schematic diagram of a bitmap for constructing a mapping table provided in one embodiment of this application; Figure 10 This is a schematic diagram of a bitmap for traversing a mapping table provided in one embodiment of this application; Figure 11 This is a schematic diagram of the hardware structure of a computer device provided in one embodiment of this application. Detailed Implementation

[0018] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0019] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0021] To make the objectives, technical methods, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, or the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, and c can represent: the existence of a alone, the existence of b alone, the existence of c alone, the simultaneous existence of a and b, the simultaneous existence of a and c, the simultaneous existence of b and c, or the simultaneous existence of a, b, and c, where a, b, and c can be single or multiple.

[0023] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0024] First, let's analyze some of the terms used in this application: NAND Flash storage array: A NAND Flash storage array is a collection of physical media responsible for persistently storing data in a storage system. It is composed of multiple NAND Flash chips combined in parallel or cascaded manner, forming the final storage location for user data.

[0025] SRAM cache: SRAM cache is a high-speed volatile memory embedded inside or adjacent to the storage controller, used to temporarily store high-frequency access data and temporary calculation variables during FTL firmware runtime.

[0026] FTL firmware is a set of embedded core software / algorithms running on the main control chip (MCU / SoC) of the storage device. It is responsible for shielding the physical limitations of NAND Flash and providing a standard block device read / write interface to the host.

[0027] The garbage collection method for the NAND Flash storage system provided in this application is specifically illustrated through the following embodiments.

[0028] The garbage collection method for NAND Flash storage systems provided in this application relates to the field of flash memory technology. This garbage collection method for NAND Flash storage systems can be applied to terminals, servers, or software running on either the terminal or the server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, etc.; the server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application implementing the garbage collection method for NAND Flash storage systems, but is not limited to the above forms.

[0029] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0030] It should be noted that in all specific embodiments of this application, when processing data related to user identity or characteristics, such as user information, user behavior data, user historical data, and user location information, user permission or consent will be obtained first. Furthermore, the collection, use, and processing of this data will comply with relevant laws, regulations, and standards. In addition, when embodiments of this application require access to sensitive personal information of users, separate permission or consent from the user will be obtained through pop-ups or redirects to confirmation pages. Only after obtaining the user's separate permission or consent will the necessary user-related data for the normal operation of the embodiments of this application be obtained.

[0031] In related technologies, during garbage collection of solid-state storage devices (such as SSDs, eMMC, and UFS), valid data needs to be located and moved from the source physical block to be reclaimed. One existing optimization is to pre-store an index table during data writing, recording which L1 tables (first-level mapping tables) are involved in the write data within that physical block, so that they can be directly read during garbage collection. However, this method requires a large buffer space to store the index table in random write scenarios. Meanwhile, another common problem is that without a pre-built index mechanism during writes, garbage collection still needs to frequently read the L1 table from the NAND flash memory to determine data validity, resulting in extremely high time overhead due to numerous repeated reads.

[0032] Please see Figure 1 , Figure 1 This is a schematic flowchart of a garbage collection method for a NAND Flash storage system provided in one embodiment of this application. The garbage collection method for a NAND Flash storage system provided in this embodiment includes, but is not limited to, steps S110 to S150, which will be described in turn below.

[0033] Step S110: During the write operation, the mapping relationship between physical address and logical address is obtained and the mapping relationship is synchronously written into the physical-to-logical mapping page in the current physical block. The physical-to-logical mapping page is interspersed within the current data block at a preset fixed interval. Step S120: During the execution of the garbage collection task, read all physical-to-logical mapping pages in the source physical block and traverse each mapping entry of the physical-to-logical mapping page; Step S130: Calculate the corresponding mapping table number based on the logical address of each mapping entry, and construct a mapping table reference bitmap; Step S140: Traverse the mapping table reference bitmap according to the ascending order of the mapping table number. When the physical address recorded by the mapping entry belongs to the source physical block, determine that the mapping entry is valid data and add the valid data to the list to be moved. Step S150: After moving all valid data in the list to be moved to the target physical block, perform an erase operation on the source physical block.

[0034] It should be noted that this embodiment provides a garbage collection method. The NAND Flash storage system used in this embodiment includes a NAND Flash storage array, an SRAM cache, and FTL firmware. The NAND Flash storage array contains multiple physical blocks, each physical block contains multiple physical pages, and each physical page can store multiple LBA_4K (i.e., 4KB logical block address units). The SRAM cache is used to store temporary data and mapping table data during FTL operation. The FTL firmware runs on the storage controller and is responsible for managing core functions such as logical address to physical address mapping and garbage collection.

[0035] In one embodiment, this application synchronously updates the P2L mapping data during write operations, ensuring that each current data block maintains complete reverse mapping information. During GC, the logical addresses of all data pages within the block can be obtained simply by reading the P2L pages in the source block, eliminating the need for page-by-page queries based on the L2P mapping table, significantly reducing the mapping query overhead during GC. By constructing a mapping table reference bitmap (L1_bitmap), all L1 tables involved in the source block are pre-deduplicated and compressed into a concise candidate list. In the subsequent validity verification stage, each L1 table only needs to be loaded once, fundamentally eliminating the performance bottleneck of repeatedly loading the same L1 table in traditional methods, significantly reducing NAND read counts and cache usage. By persisting the L1_bitmap to a specified location in the NAND Flash, the interrupted GC task can be resumed. When GC is interrupted due to priority preemption or timeout protection, the previously constructed L1_bitmap can be directly restored upon restart, without rereading P2L pages and rebuilding the bitmap, avoiding a large amount of repetitive calculations and I / O operations, and significantly improving the overall efficiency of GC. The L1 bitmap has very small storage requirements (depending only on the total number of L1 tables), can be efficiently managed in SRAM, has low memory footprint, and is suitable for resource-constrained embedded storage devices.

[0036] Please see Figure 2 , Figure 2 This is a schematic diagram of the process of synchronously writing physical to logical mapping pages according to an embodiment of this application; regarding the above step S110 of obtaining the mapping relationship between physical address and logical address and synchronously writing the mapping relationship between physical address and logical address into physical to logical mapping pages, including but not limited to steps S210 to S230, each step will be described in turn below.

[0037] Step S210: Divide the pages of the current physical block into fixed-size groups, where each group contains N data pages; Step S220: After each write operation is completed, obtain the mapping relationship between the written physical address and the logical address, and update the mapping relationship to the physical-to-logical mapping buffer in SRAM. Step S230: After all the mapping entries of the data pages of each group have been filled, the mapping relationship is written into the physical-to-logical mapping page in the current physical block.

[0038] It should be noted that when the FTL firmware allocates a new physical block as the currently active block, it first logically groups the physical pages of that physical block. Specifically, the firmware divides the pages of the current physical block into multiple fixed-size groups according to preset system parameters. Each group contains N consecutive data pages and one reserved physical page for storing P2L mapping information, meaning each group occupies (N+1) physical pages. Here, N is a positive integer, and its value can be set based on the page capacity, LBA size, and SRAM buffer size of the storage device. For example, in a specific implementation, if the physical page size is 16KB and each LBA_4K is 4KB, then each physical page contains 4 LBA_4Ks, and N can preferably be set to 16 or 32 to achieve a balance between mapping granularity and storage overhead.

[0039] It's important to note that the physical location of a P2L page within a group is fixed. A P2L page is located as the adjacent physical page after N consecutive data pages in the group, allowing the firmware to quickly calculate the physical address and group offset of the corresponding P2L page based on the currently written data page number. The firmware obtains the current physical page number corresponding to this write operation, and simultaneously obtains the starting data page number of the current group. The starting data page number of the current group is recorded in the FTL context structure by the firmware during group initialization. The firmware performs an interpolation operation: offset = current physical page number - starting data page number of the current group. Here, offset is the relative index of the data page being written within the current group. For example, if the starting page number of the current group is 64 and the currently written page number is 66, then offset = 2, indicating that this page is the 3rd data page in the group (index starts from 0).

[0040] In one embodiment, when it is confirmed that all N data pages in the group have been written and the corresponding mapping entries have filled the P2L Buffer (i.e., the buffer stores N×4 valid mapping entries), it indicates that the mapping data of the current group has been accumulated.

[0041] At this point, the FTL firmware automatically triggers a persistence operation (i.e., P2L page write). Specifically, the firmware completely moves the contents of the P2L buffer in SRAM to the P2L page pre-reserved for this group within the currently active physical block. The physical address of this P2L page is determined during grouping, typically being the group's starting page number + N (i.e., immediately following the last data page of the group). The firmware calls the NAND write interface to write the buffer data to this physical page and performs write verification to ensure stable data persistence to disk.

[0042] Please see Figure 3 , Figure 3 This is a schematic diagram of the process of updating the mapping relationship provided in one embodiment of this application; regarding the above step S220 of updating the mapping relationship to the physical to logical mapping buffer in SRAM, including but not limited to steps S310 to S330, each step will be described in turn below.

[0043] Step S310: Obtain the current physical page number of the currently written data page and the starting physical page number of the current group; Step S320: Calculate the difference between the current physical page number and the starting physical page number to obtain the offset of the currently written data page within the group; Step S330: Based on each logical address within the currently written physical page, cyclically fill the corresponding logical address value into the position corresponding to the offset in the physical-to-logical mapping buffer in SRAM.

[0044] In one embodiment, whenever the host issues a write command to write data to the currently active physical block, the FTL firmware performs the following operations to update the P2L buffer after completing the normal write operation: First, it calculates the offset. The FTL firmware calculates the relative index of the physical location to be written within the current P2L group. The offset is calculated as: offset = current data block page number - current group starting data block page number. Second, it cyclically fills the P2L mapping array. Since a physical page of NAND Flash typically contains 4 LBA_4Ks, each LBA_4K needs to be processed cyclically. The FTL firmware fills the logical address value of each LBA_4K into the corresponding position in the P2L buffer in SRAM. After N such write operations (N being the number of data pages in a group), all entries in the mapping array are filled with valid values, indicating that the mapping data for the current group has been accumulated.

[0045] Please see Figure 4 , Figure 4This is a flowchart illustrating the process of writing the physical-to-logical mapping page within the current physical block according to an embodiment of this application. The process of writing the mapping relationship into the physical-to-logical mapping page within the current physical block in step S110 includes, but is not limited to, steps S410 to S420. Each step will be described in turn below.

[0046] Step S410: Obtain the total number of pages in the current physical block; Step S420: When the write operation is complete, if the current physical page number is less than the total number of pages in the current physical block, clear the physical-to-logical mapping buffer in the SRAM and update the starting data page number of the next group.

[0047] In one embodiment, when the P2L mapping data accumulates to a preset threshold (i.e., all data pages in the current group have been written), the system automatically triggers a persistence operation, writing the contents of the P2L buffer in memory completely into a dedicated P2L page of the currently active physical block. After the previous group's P2L pages are successfully written and post-processed, if the current physical block still has remaining blank pages (i.e., the current page number is less than the total page capacity of the block), the working environment needs to be prepared for the next group: the P2L buffer is cleared, and the starting data page number of the next group's P2L is updated to continue receiving subsequent host write requests. In this way, each current data block contains P2L pages distributed at fixed intervals, completely recording the reverse mapping relationship from physical address to logical address for all data pages within the block.

[0048] Please see Figure 5 , Figure 5 This is a schematic diagram of the subsequent process of constructing the mapping table reference bitmap according to an embodiment of this application; after constructing the mapping table reference bitmap in step S130 above, there are steps including but not limited to steps S510 to S520, which will be described in turn below.

[0049] Step S510: When the garbage collection task starts, dynamically request the contiguous storage space required by the mapping table reference bitmap from the free memory pool of SRAM; Step S520: After the garbage collection task is completed, release the storage space occupied by the mapping table reference bitmap and return it to the free memory pool of SRAM.

[0050] In one embodiment, when a garbage collection task is initiated, the FTL firmware dynamically requests the contiguous storage space required by the L1_bitmap from the free memory pool of SRAM. The bitmap size is calculated as follows: number of bytes in the bitmap = (total number of L1 tables + 7) / 8. After the garbage collection task is completed, the FTL firmware releases the storage space occupied by the L1_bitmap and returns it to the free memory pool of SRAM. This dynamic allocation and release method allows SRAM resources to be flexibly reused between different tasks, making it particularly suitable for embedded storage devices with limited SRAM capacity.

[0051] Please see Figure 6 , Figure 6 This is a schematic diagram of the process of obtaining the source physical block according to an embodiment of this application; the source physical block in step S120 is obtained through the following steps, including but not limited to steps S610 to S620, which will be described in turn below.

[0052] Step S610: Obtain all closed or partially closed physical blocks; Step S620: Filter all closed or partially closed physical blocks according to the preset strategy algorithm to obtain the source physical blocks. The preset strategy algorithm includes at least one of the following: wear leveling priority, hot and cold data separation, and high inefficiency priority.

[0053] In one embodiment, all closed or partially closed physical blocks are acquired, and then these physical blocks are filtered according to a preset strategy algorithm to obtain source physical blocks. The wear leveling priority strategy prioritizes physical blocks with fewer erase cycles as source blocks to balance the wear levels of each physical block and extend the lifespan of the storage device. The hot and cold data separation strategy divides data into cold and hot data based on access frequency, prioritizing physical blocks containing more cold data as source blocks because cold data is less likely to be updated and can remain valid for a long time after migration. The high inefficiency priority strategy prioritizes physical blocks with the highest proportion of invalid data as source blocks because these blocks can release the most storage space after reclamation, resulting in the highest GC efficiency.

[0054] It should be noted that the above strategies can be used individually or in combination to meet the performance requirements of different application scenarios.

[0055] Please see Figure 7 , Figure 7 This is a schematic diagram of a process for writing a mapping table reference bitmap into a preset specified storage location in a NAND Flash storage system, according to one embodiment of this application; the embodiment of this application also includes, but is not limited to, step S710, which will be described in turn below.

[0056] Step S710: When the garbage collection task is interrupted due to priority preemption or timeout protection, the mapping table reference bitmap is written to the preset specified storage location of the NAND Flash storage system.

[0057] It should be noted that when a GC task is interrupted due to priority preemption or timeout protection, the FTL firmware will not only write the L1_bitmap to the preset specified storage location of the NAND Flash, but also record the current GC progress information, including the bitmap position that has been processed and the amount of valid data that has been moved.

[0058] Please see Figure 8 , Figure 8 This is a schematic diagram of the process after writing the mapping table reference bitmap into the preset designated storage location of the NAND Flash storage system according to an embodiment of this application; regarding the above step S710, when the garbage collection task is interrupted due to priority preemption or timeout protection, after writing the mapping table reference bitmap into the preset designated storage location of the NAND Flash storage system, including but not limited to steps S810 to S820, each step will be described in turn below.

[0059] Step S810: When the garbage collection task restarts, check whether there is valid persistent bitmap data in the preset specified storage location; Step S820: If valid persistent bitmap data exists, read and restore the mapping table reference bitmap from the preset specified storage location.

[0060] It should be noted that when the GC task restarts, the FTL firmware first checks whether valid persistent bitmap data exists in a preset specified storage location. This check can be performed by reading a specific identifier field or a checksum to verify data integrity. If valid persistent bitmap data exists, the FTL firmware reads and restores the L1_bitmap from the preset specified storage location, simultaneously restoring the previously recorded GC progress information, and then continues the GC task from the point of interruption. If valid persistent bitmap data does not exist (e.g., during the first GC startup, or when persistent data is corrupted), the FTL firmware restarts the complete GC process from phase one. Through this mechanism, this embodiment achieves reliable continuation of the GC task, ensuring the integrity of the GC process and data consistency even in extreme situations such as abnormal power outages.

[0061] Based on the above embodiments, the overall embodiments of this application are proposed.

[0062] See Figure 9 and Figure 10 , Figure 9 This is a schematic diagram of constructing a mapping table reference bitmap provided in one embodiment of this application. Figure 10This is a schematic diagram of a traversal mapping table reference bitmap provided in one embodiment of this application.

[0063] In one embodiment, a P2L (Physical-to-Logical) page is a reverse-mapped data page that records which logical address's data is stored at a physical address. Each P2L contains a fixed number of entries, and each entry records the mapping relationship between a physical address and its corresponding logical address (LBA_4K). P2L pages are distributed within the current data block at fixed intervals, interspersed among ordinary data pages. It occupies a complete physical page, dividing the pages of a data block into fixed-size groups, each containing N data pages. A fixed-size memory is allocated from the cache to store the mapping relationship of all data (LBA_4K) in this group. The P2L mapping data is not generated uniformly at the last moment, but is updated synchronously during each host write operation. Whenever the host issues a write command, writing data to the currently active physical block, the FTL firmware performs the following operations to update the P2L buffer after completing the normal write: Calculate the offset: Based on the physical location to be written, calculate the relative index of that location within the current P2L group: offset = current data block page number - current group starting data block page number. Circularly fill the P2L mapping array. Since a physical page of NAND Flash typically contains 4 LBA_4Ks, each LBA_4K needs to be processed cyclically, repeatedly calculating the offset and cyclically filling the P2L mapping array. Each time the host writes a page of data (4 LBA_4Ks), the P2L buffer is filled with 4 new mapping entries. After N such write operations, all entries in the mapping array are filled with valid values, indicating that the mapping data for the current group has been accumulated. When the P2L mapping data accumulates to a preset threshold, the system automatically triggers a persistence operation, completely writing the contents of the buffer in memory to a dedicated page of the currently active physical block. Initialization and loop continuation for the next group: After the previous group's P2L pages are successfully written and post-processed, if there are still blank pages remaining in the current physical block (i.e., the current page number < the total page capacity of the block), then it is necessary to prepare the working environment for the next group (GroupN+1) in order to continue receiving subsequent host write requests: clear the buffer memory and update the starting data page number of the next group of P2L.

[0064] In one embodiment, the GC scheduling module selects a source physical block (srcblock) from all closed or semi-closed physical blocks as the target object for this garbage collection based on the system's preset strategy algorithm (such as wear leveling priority, hot and cold data separation, high inefficiency priority, etc.). The block stores two types of data: valid data and invalid data. The logical address of valid data still points to its position within the block in the latest mapping table, indicating that it has not been overwritten by subsequent write operations and is truly valuable user data. It must be moved to a new target block for storage before erasure. Invalid data, although still occupying physical storage space, has its logical address remapped to another updated physical location (overwritten by new writes). It is outdated old data and can be directly discarded without being moved. Regarding the acquisition of mapped data, since P2L pages are distributed within the current data block at fixed intervals, the firmware can calculate the theoretical P2L page position sequence. The firmware reads each P2L page in the source block one by one in ascending order of physical page number. For each identified P2L page, the underlying NAND read interface is called to read the data of the P2L page into the SRAM buffer. Before starting the traversal, a sufficiently large contiguous space needs to be temporarily allocated from the SRAM free memory pool to store the L1 table reference bitmap (L1Bitmap) to be constructed. The size of the L1Bitmap depends on the total number of L1 tables in the entire storage device. Assuming the system uses a three-level mapping architecture (L3 to L2 to L1), where the L1 table is the smallest unit directly storing the final mapping relationship, each L1 table manages a fixed number of logical address sectors (denoted as LBA_PER_L1). If the total logical address space of the device is N LBA_4K, then the total number of L1 tables = N / LBA_PER_L1. The number of bytes in the bitmap = (total number of L1 tables + 7) / 8 (rounded up; 1 byte can represent 8 bits). The mapping array of each read P2L page is traversed entry by entry. The logical address value of the current entry is extracted, and its L1 table number l1_idx is obtained through a simple calculation: l1_idx = logical address value of the current entry / LBA_PER_L1. Then, the l1_idx position in the L1_bitmap is set to 1. After traversal, a complete L1_bitmap is obtained. The traversal loop terminates when all P2L pages in the source physical block have been read and processed (or the end of the source block has been reached). At this point, the L1_bitmap buffer in SRAM contains the final result, which records the complete set of L1 tables involved in each logical address of the entire source physical block.

[0065] It should be noted that, first, each p21 of the vblock is traversed to find all L1s that are hit in the vb1ock and record them in the L1bitmap table. In the L1bitmap table, each bit represents an L1. Setting it to 1 means that the vblock has an LBA_4K hit on that L1.

[0066] It should be noted that by utilizing the P2L reverse mapping data generated in Phase 1, this phase successfully pre-compressed the massive L1 table lookup tasks that would otherwise be repeatedly performed during GC into a precise, deduplicated L1 table candidate list with extremely low computational overhead and minimal memory usage. This list ensures that each relevant L1 table will only be accessed once in subsequent phases.

[0067] In one embodiment, the firmware sequentially traverses the L1_bitmap, performing a single load for each set L1 table. Starting from bit 0, the firmware checks the state of each bit in ascending order (0, 1, 2, ..., K, ...) until all bits of the bitmap have been scanned. The processing logic for each bit is as follows: if the value is 0, it means that the Kth L1 table is not associated with any data in the source block, so it is skipped without any operation, and the process continues to check the next bit (K+1). If the value is 1, it means that the Kth L1 table manages the logical address of at least one valid data in the source block. The L1 table is loaded from the NAND Flash into the cache, and its physical storage location is determined within the multi-level mapping architecture. The L1 table itself is also stored in a specific location in the NAND Flash. Its storage address is usually located through the upper-level mapping table (L2 table). The firmware first queries the L2 mapping table (which may already be in the cache or may need to be loaded from the NAND first) to obtain the physical block number and page number coordinates of the Kth L1 table. A NAND read request is initiated, calling the underlying NAND read interface to completely read the data content of the target L1 table into the SRAM cache area. Each entry in the loaded L1 table is traversed, and its validity is determined based on its physical address before being moved: Assuming the Kth L1 table contains M entries (M=LBA_PER_L1), with indices from 0 to M-1, the following operations are performed M times: extracting the physical address of the current entry, determining its ownership, and if it belongs to the same block as the currently reclaimed source physical block, it is considered valid data. The information of this valid data (including logical address and physical address / offset within the source block) is recorded in a list to be moved. This loop continues until the bitmap is completely traversed, and all valid data has been identified and moved: After processing one L1 table, the next set L1 table is processed until every bit of the L1_bitmap is traversed, at which point all valid data in the srcblock has been moved. Once it is confirmed that all valid data has been safely transferred, an erase operation is performed on the source physical block, turning it into a brand new free block, which is then returned to the free block pool for future use.

[0068] See Figure 11 , Figure 11 This is a schematic diagram of the hardware structure of a computer device provided in one embodiment of this application. Figure 11 The computer device 1100 provided in this application embodiment is shown. The computer device 1100 may be a server or a terminal, and its internal structure includes, but is not limited to: Memory 1110 is used to store programs; The processor 1120 is used to execute the program stored in the memory 1110. When the processor 1120 executes the program stored in the memory 1110, the processor 1120 is used to execute the garbage collection method of the NAND Flash storage system described above.

[0069] The processor 1120 and the memory 1110 can be connected via a bus or other means.

[0070] The memory 1110, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs, such as the garbage collection method for the NAND Flash storage system described in any embodiment of this application. The processor 1120 implements the above-described garbage collection method for the NAND Flash storage system by running the non-transitory software program and instructions stored in the memory 1110.

[0071] The memory 1110 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store the garbage collection method for executing the NAND Flash storage system described above. Furthermore, the memory 1110 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 1110 may optionally include memory remotely located relative to the processor 1120, and these remote memories can be connected to the processor 1120 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0072] The non-transitory software program and instructions required to implement the garbage collection method of the NAND Flash storage system described above are stored in the memory 1110. When executed by one or more processors 1120, the garbage collection method of the NAND Flash storage system provided in any embodiment of this application is executed.

[0073] This application also provides a computer-readable storage medium storing computer-executable instructions for executing the garbage collection method of the NAND Flash storage system described above.

[0074] In one embodiment, the storage medium stores computer-executable instructions that are executed by one or more control processors, such as one or more processors 1120 in the computer device 1100, which can cause the one or more processors 1120 to perform the garbage collection method of the NAND Flash storage system provided in any embodiment of this application.

[0075] The embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0076] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0077] The above provides a detailed description of the preferred embodiments of this application, but this application is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and all such equivalent modifications or substitutions should fall within the scope defined by the claims of this application.

Claims

1. A garbage collection method for a NAND Flash storage system, characterized in that, The method includes: During the write operation, the mapping relationship between physical address and logical address is obtained and the mapping relationship is synchronously written into the physical-to-logical mapping page in the current physical block. The physical-to-logical mapping page is interspersed within the current data block at a preset fixed interval. During the execution of the garbage collection task, all the physical-to-logical mapping pages in the source physical block are read, and each mapping entry of the physical-to-logical mapping page is traversed. Calculate the corresponding mapping table number based on the logical address of each mapping entry, and construct a mapping table reference bitmap; The mapping table reference bitmap is traversed in ascending order of the mapping table number. When the physical address recorded by the mapping entry belongs to the source physical block, the mapping entry is determined to be valid data, and the valid data is added to the list to be moved. After moving all valid data from the list to be moved to the target physical block, an erase operation is performed on the source physical block.

2. The method according to claim 1, characterized in that, The step of obtaining the mapping relationship between physical addresses and logical addresses and synchronously writing the mapping relationship between physical addresses and logical addresses into the physical-to-logical mapping page includes: The pages of the current physical block are divided into fixed-size groups, where each group contains N data pages; After each write operation is completed, the mapping relationship between the written physical address and logical address is obtained, and the mapping relationship is updated to the physical-to-logical mapping buffer in SRAM. Once all mapping entries for the data pages of each group have been filled, the mapping relationship is written into the physical-to-logical mapping page within the current physical block.

3. The method according to claim 2, characterized in that, The step of updating the mapping relationship to the physical-to-logical mapping buffer in SRAM includes: Obtain the current physical page number of the currently written data page and the starting physical page number of the current group; Calculate the difference between the current physical page number and the starting physical page number to obtain the offset of the currently written data page within the group; Based on each logical address within the currently written physical page, the value of the corresponding logical address is cyclically filled into the position corresponding to the offset in the physical-to-logical mapping buffer in SRAM.

4. The method according to claim 3, characterized in that, After writing the mapping relationship into the physical-to-logical mapping page within the current physical block, the method further includes: Get the total number of pages in the current physical block; When the write operation is complete, if the current physical page number is less than the total number of pages in the current physical block, the physical-to-logical mapping buffer in the SRAM is cleared, and the starting data page number of the next group is updated.

5. The method according to claim 1, characterized in that, The construction of the mapping table reference bitmap also includes: When the garbage collection task is started, the contiguous storage space required by the mapping table reference bitmap is dynamically requested from the free memory pool of SRAM; After the garbage collection task is completed, the storage space occupied by the mapping table reference bitmap is released and returned to the free memory pool of SRAM.

6. The method according to claim 1, characterized in that, The source physical block is obtained through the following steps: Get all closed or partially closed physical blocks; The source physical blocks are obtained by filtering all closed or partially closed physical blocks according to a preset strategy algorithm, wherein the preset strategy algorithm includes at least one of the following: wear leveling priority, hot and cold data separation, and high inefficiency priority.

7. The method according to claim 1, characterized in that, The method further includes: When the garbage collection task is interrupted due to priority preemption or timeout protection, the mapping table reference bitmap is written to a preset designated storage location in the NAND Flash storage system.

8. The method according to claim 7, characterized in that, Also includes: When the garbage collection task is restarted, it is checked whether there is valid persistent bitmap data in the preset specified storage location; If the valid persistent bitmap data exists, the mapping table reference bitmap is read from the preset specified storage location and restored.

9. A computer device, characterized in that, include: At least one memory; At least one processor; At least one computer program; The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the method as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program for causing a computer to perform the method as described in any one of claims 1 to 8.

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