Memory access circuit, method, electronic device, storage medium, and chip

Abstract

The application discloses a memory access circuit, a method, an electronic device, a storage medium and a program product, and belongs to the technical field of computers.The memory access circuit comprises an address mapping module and a data processing module.The address mapping module comprises a burst transaction merging module, a memory address conversion module and a burst transaction length calculation module.The burst transaction merging module is used for performing burst transaction merging processing on N continuous block data access addresses based on at least two block data access addresses.The memory address conversion module is used for mapping a first block data access address in the N block data access addresses into a memory physical address.The burst transaction length calculation module is used for calculating the total bus data amount corresponding to the N block data access addresses.The data processing module is used for performing editing processing on the received bus data, obtaining N continuous block data, and sending the N block data access addresses and the N block data to a buffer.

Description

Technical Field

[0001] This application belongs to the field of computer technology, specifically relating to a memory access circuit, method, electronic device, storage medium, and program product. Background Technology

[0002] Electronic devices can use an Image Signal Processor (ISP) to perform noise reduction, color correction, and sharpening on images. During this process, the ISP needs to read a large amount of image data from memory. Typically, electronic devices can utilize cache circuits and memory access circuits to read image data from memory in block data format, thus enabling the ISP to obtain the image data it needs.

[0003] For example, electronic devices can use cache circuitry to send the access address of the block of data they need to the memory access circuitry. This allows the memory access circuitry to retrieve a fixed cache line length of data from the bus memory based on that access address. Then, after the memory access circuitry retrieves the corresponding data (rdata), it can send the cache access address and the data back to the cache circuitry. This achieves the data transfer from memory on the bus to the cache line.

[0004] However, in the above method, during some image processing steps, adjacent output pixels may map to non-adjacent areas of the input image. This fragments burst transactions on the bus, resulting in short burst transaction lengths, which further increases the number of bus accesses and reduces bus utilization. Consequently, memory access efficiency is poor. Summary of the Invention

[0005] The purpose of this application is to provide a memory access circuit, method, electronic device, storage medium, and program product that can improve bus utilization and memory access efficiency.

[0006] In a first aspect, embodiments of this application provide a memory access circuit, which includes an address mapping module and a data processing module. The address mapping module includes a burst transaction merging module, a memory address translation module, and a burst transaction length calculation module. The burst transaction merging module is used to receive at least two block data access addresses, and based on the at least two block data access addresses, to perform burst transaction merging processing on N consecutive block data access addresses, and to send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module, where the N block data access addresses are at least a portion of the access addresses in the at least two block data access addresses, and N is an integer greater than 1. The memory address translation module is used to map the first block data access address in the N block data access addresses to a memory physical address. The burst transaction length calculation module is used to calculate the amount of bus data corresponding to the N block data access addresses based on the block data bit width and the bus bit width. The data processing module is used to edit the received bus data when the memory access circuit receives the bus data to obtain N consecutive block data, and to send the N block data access addresses and the N block data to a buffer.

[0007] Secondly, embodiments of this application provide an image processing apparatus, which includes an address mapping module and a data processing module. The address mapping module includes a burst transaction merging module, a memory address translation module, and a burst transaction length calculation module. The burst transaction merging module is used to receive at least two block data access addresses, and based on the at least two block data access addresses, to perform burst transaction merging processing on N consecutive block data access addresses, and to send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module, where the N block data access addresses are at least a portion of the access addresses in the at least two block data access addresses, and N is an integer greater than 1. The memory address translation module is used to map the first block data access address in the N block data access addresses to a memory physical address. The burst transaction length calculation module is used to calculate the amount of bus data corresponding to the N block data access addresses based on the block data bit width and the bus bit width. The data processing module is used to edit the received bus data when the image processing apparatus receives the bus data to obtain N consecutive block data, and to send the N block data access addresses and the N block data to a buffer.

[0008] Thirdly, embodiments of this application provide a memory access method, which is applied to a memory access circuit as described in the first aspect, or an image processing device as described in the second aspect. The memory access circuit includes an address mapping module and a data processing module. The memory access method includes: receiving at least two block data access addresses through a burst transaction merging module in the address mapping module, performing burst transaction merging processing on N consecutive block data access addresses based on the at least two block data access addresses, and sending consecutive flag bits corresponding to the N block data access addresses to a memory address translation module and a burst transaction length calculation module in the address mapping module. For at least two block data access addresses, N is an integer greater than 1. The memory address translation module maps the first block data access address to a physical memory address. The burst transaction length calculation module calculates the bus data volume corresponding to the N block data access addresses based on the block data bit width and bus bit width. The address mapping module transmits the physical memory address and the bus data volume to memory. When the memory access circuit receives the bus data sent from memory, the data processing module performs editing processing based on the bus data to obtain N consecutive block data, and sends the N block data access addresses and N block data to the buffer.

[0009] Fourthly, embodiments of this application provide an electronic device that includes a memory access circuit as described in the first aspect, or an image processing device as described in the second aspect.

[0010] Fifthly, embodiments of this application provide an electronic device including a processor and a memory, the memory storing programs or instructions executable on the processor, the programs or instructions, when executed by the processor, implementing the steps of the method described in the third aspect.

[0011] In a sixth aspect, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the third aspect.

[0012] In a seventh aspect, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method described in the third aspect.

[0013] Eighthly, embodiments of this application provide a computer program / program product stored in a storage medium, which is executed by at least one processor to implement the method as described in the third aspect.

[0014] In this embodiment, the memory access circuit includes an address mapping module and a data processing module. The address mapping module includes a burst transaction merging module, a memory address translation module, and a burst transaction length calculation module. The burst transaction merging module is used to receive at least two block data access addresses, and based on the at least two block data access addresses, perform burst transaction merging processing on N consecutive block data access addresses, and send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module. The N block data access addresses are at least a portion of the access addresses in the at least two block data access addresses, and N is an integer greater than 1. The memory address translation module is used to map the first block data access address in the N block data access addresses to a memory physical address. The burst transaction length calculation module is used to calculate the amount of bus data corresponding to the N block data access addresses based on the block data bit width and the bus bit width. The data processing module is used to edit the received bus data when the memory access circuit receives the bus data to obtain N consecutive block data, and send the N block data access addresses and N block data to the buffer. In this scheme, during the process of reading data from memory via the memory access circuit, the memory access circuit can perform burst transaction merging processing on the N consecutive block data access addresses, and then send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module. Thus, the memory address translation module can map the first block data access address among the N block data access addresses to a physical memory address, allowing the memory access circuit to represent the N block data access addresses using this first address. This eliminates the need for memory address translation for the remaining N-1 block data access addresses, reducing the number of block data access addresses that need to be sent. The burst transaction length calculation module can calculate the bus data volume corresponding to the N consecutive block data access addresses, reducing the repetitive statistics of bus data at boundaries during the process of calculating and adding individual block data access addresses. This reduces the number of times the memory access circuit accesses the bus, reduces repeated readings of bus data, improves bus utilization, and further enhances memory access efficiency. Attached Figure Description

[0015] Figure 1 This is one of the existing schematic diagrams of memory access process;

[0016] Figure 2 This is the second schematic diagram of an existing memory access process;

[0017] Figure 3 This is one of the structural schematic diagrams of a memory access circuit provided in the embodiments of this application;

[0018] Figure 4 This is a second schematic diagram of a memory access circuit provided in an embodiment of this application;

[0019] Figure 5A This is a schematic diagram of a horizontal mapping method provided in an embodiment of this application;

[0020] Figure 5B This is a schematic diagram of a vertical mapping method provided in an embodiment of this application;

[0021] Figure 5C This is a schematic diagram of an N-shaped mapping method provided in an embodiment of this application;

[0022] Figure 5D This is a schematic diagram of a Z-shaped mapping method provided in an embodiment of this application;

[0023] Figure 6 This is one of the schematic diagrams of a method for calculating the length of a burst transaction provided in an embodiment of this application;

[0024] Figure 7 This is a second schematic diagram of a method for calculating the length of a sudden transaction provided in an embodiment of this application;

[0025] Figure 8 This is a timing diagram of a block data access address provided in an embodiment of this application;

[0026] Figure 9 This is the third schematic diagram of a memory access circuit provided in the embodiments of this application;

[0027] Figure 10 This is the fourth schematic diagram of a memory access circuit provided in the embodiments of this application;

[0028] Figure 11 This is the fifth schematic diagram of a memory access circuit provided in the embodiments of this application;

[0029] Figure 12 This is the sixth schematic diagram of a memory access circuit provided in the embodiments of this application;

[0030] Figure 13 This is the seventh schematic diagram of a memory access circuit provided in the embodiments of this application;

[0031] Figure 14 This is a schematic diagram of the offset at the boundary between block data and bus data provided in an embodiment of this application;

[0032] Figure 15 This is the eighth schematic diagram of a memory access circuit provided in the embodiments of this application;

[0033] Figure 16This is a schematic diagram of the structure of an image processing device provided in an embodiment of this application;

[0034] Figure 17 This is a flowchart of a memory access method provided in an embodiment of this application;

[0035] Figure 18 This is a schematic diagram of the structure of a memory access device provided in an embodiment of this application;

[0036] Figure 19 This is one of the hardware structure diagrams of an electronic device provided in the embodiments of this application;

[0037] Figure 20 This is a second schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0039] The terms "first," "second," etc., used in this application's specification are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects. For example, a first object can be one or more, where "more" means at least two. Furthermore, in the specification, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0040] The terms "at least one," "at least one," etc., used in this application's specification refer to any one, any two, or a combination of two or more of the included objects. For example, "at least one of a, b, and c" can mean: "a," "b," "c," "a and b," "a and c," "b and c," and "a, b, and c," where a, b, and c can be single or multiple, and multiple means at least two. Similarly, "at least two" refers to two or more, and its meaning is similar to that of "at least one."

[0041] The following is a definition of the technical terms used in the embodiments of this application:

[0042] An Image Signal Processor (ISP) is a hardware or processing unit specifically designed for processing image signals, widely used in the signal conversion process between image sensors and display devices. The image sensor can be a Complementary Metal Oxide Semiconductor (CMOS) or Charge-coupled Device (CCD) sensor. The core function of an ISP is to extract and optimize image information from the raw data output by the sensor, ultimately outputting an image that can be displayed, stored, or further processed.

[0043] AXI (Advanced Extensible Interface) is a bus protocol.

[0044] The AXI bus protocol (Advanced Extensible Interface Bus, AXI Bus) is a high-performance, high-bandwidth, low-latency on-chip bus protocol widely used in modern System-on-Chip (SoC) designs to connect modules such as processors, memory, and peripherals. It is part of the AMBA (Advanced Microcontroller Bus Architecture) bus protocol.

[0045] Burst transmission refers to the continuous transmission of multiple data items with adjacent addresses within a single transmission transaction. This method significantly reduces transmission management overhead because the master device (such as a CPU or DMA controller) only needs to send address and control information once at the beginning, and the slave device (such as memory or peripherals) then automatically calculates and transmits the remaining data items based on this information.

[0046] Burst length refers to the number of consecutive data transfer cycles between adjacent memory cells in the same row. This concept is primarily used in computer storage, especially in memory-related technologies.

[0047] The memory access circuits, methods, electronic devices, storage media, and program products provided in this application will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0048] The embodiments of this application can be applied to scenarios where an electronic device needs to read a large amount of image data from memory during image processing by an ISP. For example, algorithms can be used to perform affine transformations, Gaussian blurring, and region processing on the image.

[0049] Usually, such as Figure 1As shown, in an ISP, electronic devices can send a command prompt (cmd) indicating the access address of the block data they need to the memory access circuit via the cache circuit, such as Read Direct Memory Access (RDMA). The RDMA circuit then sends the corresponding prompt, such as `burst_cmd`, to the memory via the Axi bus to retrieve image data of a fixed cache line length. The memory then sends the data `rdata` corresponding to `cmd` to the RDMA circuit. Furthermore, the RDMA circuit sends the cache access address and `block_data` to the cache circuit, thus enabling the transfer of data from memory to cache lines on the bus.

[0050] The design of memory access circuits needs to be based on bus protocols. For example, RDMA circuits applied to the Axi bus can utilize burst transaction transfers to achieve memory access and data movement between the memory and cache circuits. Furthermore, this RDMA circuit can rely on continuously incrementing memory addresses (INCR mode), making it suitable for processing consecutive pixel blocks, such as entire lines of image data, to maintain the maximum possible burst length for bus access and maximize the utilization of available bandwidth.

[0051] However, combined Figure 1 ,like Figure 2 As shown, for accessing the image processing cache circuit, the RDMA circuit needs to match the bit width of the read-back data with the bit width of the block data stored in the cache line. If this match fails, some invalid data transmission will occur. Figure 2 In this context, way0 and way1 are two-way linked cache structures.

[0052] Meanwhile, in some image processing processes, adjacent output pixels may be mapped to non-adjacent areas of the input image, which may cause burst transmission transactions on the bus to become fragmented, with short burst transaction lengths, increased bus access frequency, and decreased bus utilization.

[0053] In the memory access circuit, method, electronic device, storage medium, and program product provided in the embodiments of this application, the memory access circuit includes an address mapping module and a data processing module. The address mapping module includes a burst transaction merging module, a memory address translation module, and a burst transaction length calculation module. The burst transaction merging module is used to receive at least two block data access addresses, and based on the at least two block data access addresses, to perform burst transaction merging processing on N consecutive block data access addresses, and to send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module. The data access address is at least a portion of at least two block data access addresses, where N is an integer greater than 1. The memory address translation module maps the first block data access address among the N block data access addresses to a physical memory address. The burst transaction length calculation module calculates the amount of bus data corresponding to the N block data access addresses based on the block data width and the bus width. The data processing module, upon receiving bus data from the memory access circuit, edits the received bus data to obtain N consecutive blocks of data, and sends the N block data access addresses and the N block data to the buffer. In this scheme, during the process of reading data from memory through the memory access circuit, the memory access circuit can perform burst transaction merging processing on the N consecutive block data access addresses, and then send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module. Therefore, the memory address translation module can map the first block data access address out of N block data access addresses to a physical memory address. This allows the memory access circuit to represent all N block data access addresses using this first address, eliminating the need for memory address translation for the remaining N-1 block data access addresses and reducing the number of block data access addresses that need to be sent. The burst transaction length calculation module can calculate the amount of bus data corresponding to the N consecutive block data access addresses, reducing redundant statistics on bus data at boundaries during the process of calculating and adding individual block data access addresses. This reduces the number of times the memory access circuit accesses the bus, decreases redundant readings of bus data, improves bus utilization, and further enhances memory access efficiency.

[0054] This application provides a memory access circuit, such as... Figure 3 As shown, the memory access circuit 20 includes an address mapping module 21 and a data processing module 22.

[0055] The address mapping module 21 includes a burst transaction merging module 211, a memory address translation module 212, and a burst transaction length calculation module 213.

[0056] The burst transaction merging module 211 is used to receive at least two block data access addresses, and based on the at least two block data access addresses, to perform burst transaction merging processing on N consecutive block data access addresses, and to send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module 212 and the burst transaction length calculation module 213. The N block data access addresses are at least a portion of the access addresses in the at least two block data access addresses, and N is an integer greater than 1.

[0057] The memory address translation module 212 is used to map the first block data access address among N block data access addresses to a physical memory address.

[0058] The burst transaction length calculation module 213 is used to calculate the bus data volume corresponding to N block data access addresses based on the block data bit width and the bus bit width.

[0059] The data processing module 22 is used to edit the received bus data when the memory access circuit receives the bus data, to obtain N consecutive blocks of data, and to send the N block data access addresses and N block data to the buffer.

[0060] In some embodiments of this application, the memory access circuit 20 can be in Figure 1 This circuit is an improvement on the RDMA circuit in [the original text], and can also provide electronic devices with [the following text is incomplete and likely refers to a separate topic:] Figure 1 The circuit connecting the cache circuit and the RDMA circuit.

[0061] In some embodiments of this application, the memory access circuit 20 can receive the access address, such as cache_address, sent by the cache circuit, and the valid flag bit corresponding to the access address, such as cache_address_valid.

[0062] It should be noted that the above cache_address can be an access address in the form of two-dimensional coordinates (x, y), where x can be used to represent the number of columns corresponding to the block data; y can be used to represent the number of rows corresponding to the block data; and both x and y are integers.

[0063] For example, when the access address corresponding to a block of data is (0, 0), the block of data is the block of data in the zeroth column and the zeroth row; when the access address corresponding to a block of data is (1, 0), the block of data is the block of data in the first column and the zeroth row; when the access address corresponding to a block of data is (0, 1), the block of data is the block of data in the zeroth column and the first row.

[0064] In some embodiments of this application, the memory access circuit 20 may handshake with cache_address_valid based on a handshake protocol, and then receive the cache address after the handshake is successful.

[0065] It should be noted that if cache_address_valid is high, it means that the access address is valid; if cache_address_valid is low, it means that the access address is invalid.

[0066] In some embodiments of this application, if there is a block data access address among the above at least two block data access addresses that is not continuous with the block data access addresses before and after it, such as block data access address A, then the memory access circuit 20 can directly send block data access address A to the subsequent RDMA module for further processing.

[0067] It should be noted that the processing performed by the RDMA module can be found in the description of the following embodiments, and will not be repeated here.

[0068] In some embodiments of this application, in conjunction with the above... Figure 3 ,like Figure 4 As shown, the above-mentioned sudden event merging module 211 may include: a digital statistics module 2111 and a continuous detection module 2112.

[0069] In some embodiments of this application, the above-mentioned digital statistics module 2111 is used to calculate the number of block data based on the maximum burst length value, the block data bit width and the bus bit width.

[0070] In some embodiments of this application, the above-mentioned block data quantity is used to indicate the maximum number of block data access addresses that are allowed to be sent simultaneously.

[0071] In some embodiments of this application, the memory access circuit 20 can limit the number of bus data corresponding to the above N consecutive block data access addresses by using the above-mentioned number of block data.

[0072] In some embodiments of this application, the maximum burst length value can be a maximum quantity of bus data preset based on the bus protocol. For example, the maximum quantity can include, but is not limited to, any one of the following: 2, 4, 8, 16, 32.

[0073] In some embodiments of this application, a block of data may correspond to one or more bus data. Therefore, the memory access circuit 20 can determine the number of bus data corresponding to a block of data based on the block data bit width and the bus bit width. Then, it can determine the number of block data by combining the above-mentioned maximum burst length value.

[0074] It should be noted that the method for determining the number of bus data corresponding to a block of data based on the block data width and the bus width can be found in the description in the following embodiments, and will not be repeated here in the embodiments of this application.

[0075] In some embodiments of this application, the continuous detection module 2112 is used to determine whether at least two block data access addresses are consecutive, and to perform burst transaction merging processing on N block data access addresses based on the maximum number, and to determine the continuous flag bit corresponding to N consecutive block data access addresses.

[0076] In some embodiments of this application, the continuity detection module 2112 can determine whether at least two block data access addresses are consecutive based on the method of mapping block data to memory.

[0077] In some embodiments of this application, the method of mapping the block data to memory may include, but is not limited to, any of the following: horizontal mapping, vertical mapping, N-shaped mapping, and Z-shaped mapping.

[0078] In some embodiments of this application, when block data is mapped to memory in a horizontal mapping manner, if the continuity detection module 2112 determines that two block data access addresses are in the same row, that is, the two block data access addresses are (i, j) and (i+1, j) respectively, then the continuity detection module 2112 can determine that the two block data access addresses are continuous.

[0079] For example, such as Figure 5A As shown, assuming the two block data access addresses obtained by the continuous detection module 2112 are (0, 0) and (1, 0), the continuous detection module 2112 can determine that the column number i of the two block data access addresses differs by 1 and the row number j is the same. Therefore, the continuous detection module 2112 can determine that the two block data access addresses are continuous. Assuming the two block data access addresses obtained by the continuous detection module 2112 are (0, 0) and (0, 1), the continuous detection module 2112 can determine that the row number j of the two block data access addresses differs by 1 and the column number i is the same. That is, the condition that the column number i differs by 1 and the row number j is the same is not satisfied. Therefore, the continuous detection module 2112 can determine that the two block data access addresses are not continuous.

[0080] In some embodiments of this application, when block data is mapped to memory via a vertical mapping method, if the continuity detection module 2112 determines that two block data access addresses are in the same column, that is, the two block data access addresses are (i, j) and (i, j+1) respectively, then the continuity detection module 2112 can determine that the two block data access addresses are continuous.

[0081] For example, such as Figure 5BAs shown, assuming the two block data access addresses obtained by the continuous detection module 2112 are (0, 0) and (0, 1), the continuous detection module 2112 can determine that the row number j of the two block data access addresses differs by 1 and the column number i is the same. Therefore, the continuous detection module 2112 can determine that the two block data access addresses are continuous. Assuming the two block data access addresses obtained by the continuous detection module 2112 are (0, 0) and (1, 0), the continuous detection module 2112 can determine that the column number i of the two block data access addresses differs by 1 and the row number j is the same. That is, the condition that the row number j differs by 1 and the column number i is the same is not satisfied. Therefore, the continuous detection module 2112 can determine that the two block data access addresses are not continuous.

[0082] In some embodiments of this application, when block data is mapped to memory via an N-shape mapping, the method by which the continuity detection module 2112 determines whether two block data access addresses are consecutive may include:

[0083] (1) If the data access address of a block is (i, j) and the number of rows j is even, then the data access address of the next block is (i, j+1), and the two data access addresses are consecutive.

[0084] (2) If the address of a block data access is (i, j+1) and the number of rows j+1 is odd, then the address of the next block data access is (i+1, j), and the two block data access addresses are consecutive.

[0085] For example, such as Figure 5C As shown, assume that the two block data access addresses obtained by the continuous detection module 2112 are a(0,0), b(0,1), and c(1,0). Based on a(0,0) and b(0,1), the continuous detection module 2112 can determine that the number of rows in the first block data access address is even (0), and the number of columns in the second block data access address remains unchanged while the number of rows increases by 1, thus satisfying the above method (1). Therefore, the continuous detection module 2112 can determine that the two block data access addresses are continuous. Then, based on b(0,1) and c(1,0), the continuous detection module 2112 can determine that the number of rows in the first block data access address is odd (1), and the number of columns in the second block data access address increases by 1 while the number of rows decreases by 1, thus satisfying the above method (2). Therefore, the continuous detection module 2112 can determine that the two block data access addresses are continuous. Thus, the continuous detection module 2112 can determine that the above block data access addresses a, b, and c are continuous.

[0086] In some embodiments of this application, when block data is mapped to memory using a Z-shaped mapping method, the method by which the continuity detection module 2112 determines whether two block data access addresses are consecutive may include:

[0087] (1) If the block data access address is (i, j) and the column number i is even, then the next block data access address is (i+1, j), and the two block data access addresses are consecutive.

[0088] (2) If the address of a block data access is (i+1, j), and the number of columns i+1 is odd and the number of rows j is even, then if the address of the next block data access is (i, j+1), then the two block data access addresses are consecutive.

[0089] (3) If the block data access address is (i+1, j+1) and the number of columns i+1 is odd and the number of rows j+1 is odd, then the next block data access address is (i+2, j), and the two block data access addresses are consecutive.

[0090] For example, such as Figure 5DAs shown, assume that the two block data access addresses obtained by the continuous detection module 2112 are A(0,0), B(1,0), C(0,1), D(1,1) and E(2,0). The continuous detection module 2112 can determine, based on A(0,0) and B(1,0), that the number of columns in the first block data access address is even (0), and the number of columns in the second block data access address increases by 1 while the number of rows remains unchanged, thus satisfying the above method (1). Therefore, the continuous detection module 2112 can determine that the two block data access addresses are continuous. The continuous detection module 2112 can also determine, based on B(1,0) and C(0,1), that the number of columns in the first block data access address is odd (1), the number of rows is even (0), and the number of columns in the second block data access address decreases by 1 while the number of rows increases by 1, thus satisfying the above method (2). Therefore, the continuous detection module 2112 can determine that the two block data access addresses are continuous. The continuity detection module 2112 can determine, based on C(0,1) and D(1,1), that the number of columns in the first block data access address is even (0), and the number of columns in the second block data access address increases by 1 while the number of rows remains unchanged, thus satisfying method (1) above. Therefore, the continuity detection module 2112 can determine that the two block data access addresses are continuous. The continuity detection module 2112 can also determine, based on D(1,1) and E(2,0), that the number of columns in the first block data access address is odd (1), the number of rows is odd (1), and the number of columns in the second block data access address increases by 1 while the number of rows decreases by 1, thus satisfying method (3) above. Therefore, the continuity detection module 2112 can determine that the two block data access addresses are continuous. Thus, the continuity detection module 2112 can determine that the aforementioned block data access addresses A, B, C, D, and E are continuous.

[0091] In some embodiments of this application, the continuous detection module 2112 is further configured to send the continuous flag bits corresponding to N block data access addresses to the memory address translation module 212 and the burst transaction length calculation module 213.

[0092] In some embodiments of this application, the consecutive flag bits corresponding to the above N block data access addresses can be used to indicate the information corresponding to the N block data addresses respectively, and there is continuity between the N block data access addresses.

[0093] In some embodiments of this application, the memory address translation module 212 described above is specifically used for:

[0094] Determine the second address offset based on the access address of the first block of data, the block data bit width, the bus bit width, and the first address offset;

[0095] The physical memory address of the first block of data is calculated based on the frame base address and the second address offset corresponding to the memory space of a frame of image in memory.

[0096] In some embodiments of this application, the aforementioned first address offset is the address offset from the starting address of one row of pixels to the starting address of the next row of pixels when storing an image in memory. That is, it can be understood as the number of blocks of data corresponding to a row of data.

[0097] In some embodiments of this application, when storing image data in memory, the memory can allocate a corresponding address space for a frame of image that needs to be stored, and store the frame of image in the form of block data and row data. This address space can correspond to a frame base address.

[0098] In some embodiments of this application, the memory access circuit 20 can calculate the second address offset by y*line_addr_stride+x*block_width / bus_width.

[0099] Where x represents the column number of the block data in the access address of the first block data; y represents the row number of the block data in the access address of the first block data; line_addr_stride represents the address offset from the starting address of one row of pixels to the starting address of the next row of pixels when storing the image in memory, i.e., the first address offset mentioned above; block_width represents the bit width of the block data; and bus_width represents the bus bit width.

[0100] In some embodiments of this application, the memory access circuit 20 can calculate the physical memory address of the first block of data using the formula rdma_address = frame_base_address + (y * line_addr_stride + x * block_width / bus_width). Here, frame_base_address is the frame base address corresponding to the memory space of a frame of image in the aforementioned memory.

[0101] For example, assuming the access address of the first block data is (0, 0), that is, the first block data is the block data in the zeroth row and zeroth column in the image data, the physical memory address of the block data is: rdma_address=frame_base_address+(0*line_addr_stride+0*block_width / bus_width)=frame_base_address.

[0102] Assuming the access address of the first block of data is (1, 0), that is, the first block of data is the block of data in the first column and the zeroth row in the image data, the physical memory address of the block of data is: rdma_address=frame_base_address+(0*line_addr_stride+1*block_width / bus_width)=frame_base_address+1*block_width / bus_width.

[0103] It should be noted that, apart from x and y, all other data in the above formula can be understood as a set of fixed parameter values. In different application scenarios, the parameter values ​​corresponding to these other data can be different.

[0104] In some embodiments of this application, the memory access circuit 20 can calculate the burst length corresponding to a single command based on the two-dimensional coordinates, the block data bit width, and the bus bit width, and then use the burst length + 1 as the number of bus data corresponding to the block data.

[0105] In some embodiments of this application, since the cache line can store block data and the data bit width of the cache line is usually greater than the bus bit width, it is necessary to concatenate multiple bus data into block data.

[0106] The AXI bus allows for burst transfers, where the burst command can include the bus address and burst length, enabling the transfer of multiple bus data entries within a single burst transaction. However, if the cache line block data width is not divisible by the bus width, a boundary issue arises where one bus data entry spans two data blocks.

[0107] In some embodiments of this application, the above-mentioned burst transaction length calculation module 213 is used to calculate the bus data volume corresponding to N block data access addresses based on the block data bit width and the bus bit width.

[0108] In some embodiments of this application, the burst transaction length calculation module 213 described above can realize the burst_length calculation function for any block data bit width and bus bit width.

[0109] In some embodiments of this application, the above-mentioned burst transaction length calculation module 213 can first calculate the least common multiple parameter value based on the block data bit width (cache_line_size) and the bus data bit width (bus size), and then subtract 1 from the quotient of the least common multiple parameter value and the block data bit width to calculate the number of times the cache line block data is processed across different boundaries of the bus data, which is related to the number of columns in the block data access address.

[0110] For example, such as Figure 6 As shown, assuming the ratio of block data width to bus width is 11:4, taking a block data width of cache_line_size = 11 and a bus width of bus size = 4 as an example, the least common multiple of cache_line_size and bus size is 44, and the quotient of the least common multiple parameter value and the block data width is 4. Therefore, the burst transaction length calculation module 213 can calculate that the number of times the cache line block data crosses different boundaries of the bus data is 4-1 = 3. That is... Figure 6 The third, sixth, and ninth bus data points correspond to a cache line block data cross-bus data.

[0111] In some embodiments of this application, the burst transaction length calculation module 213 can calculate the bus data volume corresponding to each of the above N block data access addresses based on the formula burst_length=ceil((x*B)%1)+ceil(A-(x*B)%1).

[0112] Where A = cache_line_size / bus_size, B = |1-(cache_line_size / bus_size)%1|; x can represent the number of columns in the block data access information, cache_line_size can represent the block data bit width, bus_size can represent the bus bit width, ceil() can represent the rounding up calculation method, and % can represent the remainder calculation method.

[0113] For example, combined Figure 6 With a block data width of 11 and a bus width of 4, A = 2.75 and B = 0.25. Therefore, for the block data access address of column 0, i.e., column0, burst_length = ceil((0*0.25)%1) + ceil(2.75-(0*0.25)%1) = 0 + 3 = 3, which means that the block data access address of column 0 can correspond to 3 bus data.

[0114] For the block data access address in column 1, i.e. column1, burst_length = ceil((1*0.25)%1) + ceil(2.75-(1*0.25)%1) = 1 + 3 = 4, which means that the block data access address in column 1 can be understood as corresponding to 4 bus data.

[0115] For the block data access address in column 2, i.e. column2, burst_length = ceil((2*0.25)%1) + ceil(2.75-(2*0.25)%1) = 1 + 3 = 4, which means that the block data access address in column 2 can be understood as corresponding to 4 bus data.

[0116] For the block data access address in column 3, i.e., column3, burst_length = ceil((3*0.25)%1) + ceil(2.75-(3*0.25)%1) = 1 + 2 = 3, which means that the block data access address in column 3 can be understood as corresponding to 3 bus data.

[0117] It's important to note that when accessing block data in column 0, RDMA needs to retrieve 3 bus data entries from the bus. When the cache accesses block data in column 1, it requires 4 bus data entries, with the third bus data entry being retrieved from memory again. Even though only a portion of the bus data at the boundaries is used, the entire bus block still needs to be retrieved. Therefore, the number of AXI bus data entries required for each cache access will vary depending on the position of different block data entries within a row.

[0118] For example, let's take cache_line_size = 576 bits and bus_size = 256 bits as an example. A = 576 / 256 = 2.25, B = |1-(576 / 256)%1| = |1-2.25%1| = |1-0.25| = 0.75;

[0119] When (x, y) = (0, 0), the number of bus data required for this block data access address is: burst_length = ceil((0*0.75)%1) + ceil(2.25 - (0*0.75)%1) = 0 + 3 = 3;

[0120] When (x, y) = (1, 0), the number of bus data required for this block data access address is: burst_length = ceil((1*0.75)%1) + ceil(2.25-(1*0.75)%1) = 1 + 2 = 3;

[0121] When (x, y) = (2, 0), the number of bus data required for this block data access address is: burst_length = ceil((2*0.75)%1) + ceil(2.25-(2*0.75)%1) = 1 + 2 = 3;

[0122] When (x, y) = (3, 0), the number of bus data required for this block data access address is: burst_length = ceil((3*0.75)%1) + ceil(2.25-(3*0.75)%1) = 1 + 2 = 3.

[0123] In some embodiments of this application, after the memory access circuit 20 determines N consecutive block data access addresses based on the burst transaction merging module 211 and sends the consecutive flag bits corresponding to the N block data access addresses to the burst transaction length calculation module 213, the burst transaction length calculation module 213 can calculate the bus data volume corresponding to the N block data access addresses based on the consecutive flag bits.

[0124] For example, such as Figure 7 As shown, with a block data width of 11 and a bus width of 4, if the continuous flag received by the burst transaction length calculation module 213 indicates that column0 to column3 are three consecutive block data access addresses, then the burst transaction length calculation module 213 can determine that the number of buses corresponding to column0 to column3 is 11 by calculating burst_length = ceil((0*0.25)%1) + ceil(2.75-(0*0.25)%1) + ceil(2.75-(1*0.25)%1) + ceil(2.75-(2*0.25)%1) + ceil(2.75-(3*0.25)%1) = 0 + 3 + 3 + 3 + 2 = 11.

[0125] Thus, for N consecutive block data access addresses, the amount of bus data corresponding to each block data access address is greater than the amount of bus data directly corresponding to the N block data access addresses. This reduces repeated readings of bus data, further improving bus utilization and memory access speed.

[0126] In some embodiments of this application, when the memory access circuit 20 is provided with a maximum burst_length limit, the memory access circuit 20 can use a counter to detect whether the sum of the burst_lengths of the current cache accesses exceeds the maximum burst length supported by RDMA. If it does, the current access command will not be merged.

[0127] For example, let's take a scenario where the cache line block data requires 3 bus data units, and the maximum burst_length is 4 block data units. Figure 8As shown, the memory access circuit 20 can receive 10 block data access addresses, such as addr0, addr1, addr2, addr3, addr4, addr12, addr13, addr22, addr23, and addr14. Since the upper limit of burst_length is 4 blocks of data, the burst transaction merging module 211 can determine addr0, addr1, addr2, and addr3 as a group of consecutive block data access addresses, addr12 and addr13 as a group of consecutive block data access addresses, and addr22 and addr23 as a group of consecutive block data access addresses.

[0128] `cache_req` represents the validity signal of a cache access. A successful handshake with `cache_req_rdy` indicates a successful cache access. At this point, the burst transfer merging module 211 first compares the preceding and following access addresses. If two adjacent block data access addresses are consecutive, the `compare_hit` signal is raised, as shown in the parts corresponding to `addr12` and `addr13`, and `addr22` and `addr23`. If two adjacent block data access addresses are not consecutive, the `compare_hit` signal is lowered, as shown in the parts corresponding to `addr4` and `addr12`, and `addr13` and `addr22`. Simultaneously, if the currently accessed block data access address is the first block data access address, `compare_hit` is also raised, as shown in the part corresponding to `addr0`, to wait for the next cache access address to be compared.

[0129] Since the burst transfer merging module 211 determines that the access from address0 to address3 is continuous, the memory address translation module 212 can map only the first block data access address, i.e., the access address of address0, to the physical memory address. In other words, burst_addr can only be calculated as burst_addr0. Meanwhile, since the memory access circuit 20 provided in this embodiment does not need to consider the boundary processing of block data across bus data, the calculated burst_len does not consider repeatedly read bus data.

[0130] If access to address3 is successful and the continuity comparison is also successful, the burst transfer merging module 211 can interrupt the merging process of address4 because the counter has reached its maximum value. In the next cycle, it will raise the burst_vld signal to send burst_len and burst_addr to the subsequent RDMA module for processing. At this point, for address4, the continuity comparison needs to be restarted. If the next access, address12, is not continuous with address4, burst_addr4 will be sent directly. Then address12 will be compared with the next access.

[0131] In the memory access circuit provided in this embodiment, during the process of reading data from memory, the memory access circuit can perform burst transaction merging processing on the N consecutive block data access addresses, and then send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module. Thus, the memory address translation module can map the first block data access address among the N block data access addresses to a physical memory address, allowing the memory access circuit to represent the N block data access addresses using this first address. This eliminates the need for memory address translation for the remaining N-1 block data access addresses, reducing the number of block data access addresses that need to be sent. The burst transaction length calculation module can calculate the bus data volume corresponding to the N consecutive block data access addresses, reducing the repetitive statistics of bus data at boundaries during the process of calculating and adding individual block data access addresses. This reduces the number of times the memory access circuit accesses the bus, reduces repeated readings of bus data, improves bus utilization, and further enhances memory access efficiency.

[0132] In some embodiments of this application, in conjunction with the above... Figure 3 ,like Figure 9 As shown, the address mapping module 21 may also include a handshake shielding module 214.

[0133] In some embodiments of this application, the handshake shielding module 214 is used to shield the handshake signals corresponding to the first N-1 block data access addresses among the N block data access addresses.

[0134] In this way, the handshake blocking module can block the handshake signals corresponding to the first N-1 block data access addresses, meaning that these N block data access addresses will correspond to one data transmission in the future, thereby reducing the number of transmissions to the N block data access addresses.

[0135] In some embodiments of this application, in conjunction with the above... Figure 3 ,like Figure 10 As shown, the address mapping module 21 may also include a burst command sending module 215.

[0136] In some embodiments of this application, the burst command sending module 215 is used to send the received memory physical address and the bus data volume corresponding to N blocks of data to the RDMA module for processing.

[0137] In some embodiments of this application, the above-mentioned N block data are block data corresponding to N block data addresses.

[0138] In some embodiments of this application, the aforementioned physical memory address may be the address sent by the memory address translation module 212.

[0139] In some embodiments of this application, the aforementioned physical memory address can be the physical memory address converted from the first block data access address among N consecutive block data access addresses.

[0140] In some embodiments of this application, the bus data volume corresponding to the aforementioned N blocks of data can be the burst_length calculated by the burst transaction length calculation module 213. For example, Figure 7 The burst_length corresponding to columns 0 to 3.

[0141] In some embodiments of this application, the aforementioned physical memory address may also be a physical memory address converted from a non-contiguous block data access address.

[0142] It should be noted that the aforementioned non-contiguous block data access addresses can be addresses that are not contiguous with either the preceding or following adjacent block data access addresses. For example, combining... Figure 8 If the address following addr14 is not contiguous with it, then addr14 is the address of that single block of data access; it can also be an address that is contiguous with the preceding block of data access address but not contiguous with the following block of data access address, but cannot be merged with the address of the preceding vector due to reaching the burst_length limit, such as... Figure 8 addr4 in the middle.

[0143] In some embodiments of this application, the burst command sending module 215 is used to send the memory physical address and bus data volume corresponding to the received discontinuous block data access address to the RDMA module for processing.

[0144] In some embodiments of this application, the RDMA module can process the received data using at least one bus function such as 4K boundary alignment and outstanding control in the AXI protocol.

[0145] For example, such as Figure 11 As shown, the address mapping module can receive cache access commands to merge burst transactions based on N consecutive block data access addresses. Then, the memory access circuit can perform command asynchronous first-in-first-out (FIFO) related processing on the output content to perform 4K boundary detection and command splitting, thereby executing the output of burst commands to the AXI bus.

[0146] In some embodiments of this application, in conjunction with the above... Figure 9 ,like Figure 12 As shown, the address mapping module 21 may also include an access address storage module 216.

[0147] In some embodiments of this application, the access address storage module 216 is used to store consecutive flag bits corresponding to N block data access addresses, and at least two block data access addresses.

[0148] In some embodiments of this application, the information stored in the access address storage module 216 can be in First-In-First-Out (FIFO) format.

[0149] In some embodiments of this application, when the subsequent memory access circuit 20 receives bus data sent by the memory, the memory access circuit 20 can edit the bus data based on the information stored in the access address storage module 216 to obtain N consecutive blocks of data.

[0150] In some embodiments of this application, the handshake shielding module 214 can be a pipeline-level module to control the operation of each module in the memory access circuit 20 by the number of cycles. For example, suppose that the cache command transmission of the memory access circuit 20 has two pipeline stages. In the first pipeline stage, the cache address can be entered into the burst transaction merging module 211, the memory address translation module 212, and the burst transaction length calculation module 213 for relevant calculations; in the second pipeline stage, the burst command can be received by the burst command sending module 215, and the continuous flag bit and the cache access address can be stored in the access address storage module 216.

[0151] In some embodiments of this application, the editing processing performed by the data processing module 22 may include, but is not limited to, at least one of the following: splicing processing, offset calculation processing, and alignment processing.

[0152] In some embodiments of this application, the bus data described above may be data transferred from memory to memory access circuit 20, such as bus_data.

[0153] In some embodiments of this application, the above-mentioned N block data access addresses can be data stored by the memory access circuit 20 based on the access address storage module 216. That is, after the data processing module 22 obtains the bus data, the data processing module 22 can read the data stored in the access address storage module 216 so as to edit the connected bus data.

[0154] In some embodiments of this application, during the process of the data processing module 22 sending N block data access addresses and N block data to the buffer, the data needs to be sent sequentially according to the order of the N block data access addresses. At the same time, the correctness of the sent addresses and data also needs to be ensured.

[0155] In some embodiments of this application, in conjunction with the above... Figure 3 ,like Figure 13 As shown, the data processing module 22 includes a data splicing module 221 and a block data generation module 222.

[0156] In some embodiments of this application, the data splicing module 221 described above is used to splice bus data based on N block data access addresses.

[0157] In some embodiments of this application, the block data generation module 222 is used to perform offset trimming processing on the spliced ​​bus data based on the continuous flag bits corresponding to N block data access addresses to obtain N consecutive block data.

[0158] In some embodiments of this application, the data processing module 22 can calculate the offset at the boundary of the bus data based on the x-coordinate in the block data access address, and then determine the cache_line_size data, i.e., the cache line block data, based on the data offset.

[0159] In some embodiments of this application, the data processing module 22 described above can calculate the offset based on the following formula: x*B%1*bus_size=(x*|1-(cache_line_size%bus_size)|)*bus_size, where x can represent the number of columns in the block data access address, cache_line_size can represent the block data bit width, and bus_size can represent the bus bit width. For example, as Figure 14 The B*bus_size is shown.

[0160] For example, let's take cache_line_size = 576 bits and bus_size = 256 bits as an example. B = |1 - (576 / 256) % 1| = 0.75. When (x, y) = (0, 0), the data offset is 0, so 576 bits are taken up; when (x, y) = (1, 0), the data offset is 0.75 * 256 = 192 bits, so 576 bits are taken up.

[0161] In some embodiments of this application, a valid consecutive flag bit can indicate that multiple cache commands are consecutive. Therefore, the offset can be calculated and aligned on the initial bus data. Subsequently, the concatenated data can be converted according to the bit width to obtain the corresponding block data.

[0162] In some embodiments of this application, for non-contiguous block data, the data processing module 22 can perform conversion based on a sufficient amount of bus data, that is, the bus data of the burst_length corresponding to the block data, in order to obtain the converted block data.

[0163] For example, combined Figure 11 After the memory access circuit obtains bus data based on memory, it can first transfer the bus data to the data buffer, and after performing asynchronous FIFO processing on the bus data, it can transfer it to the data processing module to edit the bus data, obtain N consecutive blocks of data, and send the access addresses of the N blocks of data and the N blocks of data to the buffer.

[0164] In some embodiments of this application, the memory access circuit 20 provided in this application can also be applied to other buses that support burst command transmission besides the AXI bus protocol, such as the Advanced High-performance Bus (AHB); or it can also be applied to AI accelerators with irregular memory access characteristics.

[0165] This application provides a memory access circuit 20. Figure 15 A schematic diagram of a memory access circuit 20 provided in an embodiment of this application is shown. The following will use... Figure 15 The memory access circuit 20 shown is used as an example to illustrate the memory access method provided in this application embodiment. For example... Figure 15As shown, the memory access circuit 20 provided in this embodiment includes: an address mapping module 21 and a data processing module 22; the address mapping module 21 includes: a burst transaction merging module 211, a memory address translation module 212, a burst transaction length calculation module 213, a handshake shielding module 214, a burst command sending module 215, and an access address storage module 216; the data processing module 22 includes: a data splicing module 221 and a block data generation module 222.

[0166] The cache command transmission of the aforementioned memory access circuit 20 has a two-stage pipeline: the data corresponding to the address mapping module 21 is transmitted from left to right, and the transmission of bus data returned from memory by the memory access circuit 20 also has a two-stage pipeline: the data corresponding to the data processing module 22 is transmitted from right to left. The pipelines in the memory access circuit 20 transmit data according to a handshake protocol.

[0167] If the memory access circuit 20 successfully hands off the cache_addr_valid connection, the cache_address can be successfully received. In the first pipeline stage, this cache_address is processed by the burst transaction merging module 211, the memory address translation module 212, and the burst transaction length calculation module 213. Then, in the second pipeline stage, the burst command sending module 215 receives the burst command (burst_command), and the access address storage module 216 stores the position continuation flag and the block data access address. Furthermore, the burst command sending module 215 can send the rdmarequest_valid signal and the burst command signal to other modules in the subsequent stages.

[0168] For the data processing module 22, in the first pipeline stage, when the bus returns data `bus_data`, the data concatenation module 221 can read the information stored in the access address storage module 216 to concatenate the bus data. Furthermore, the block data generation module 222 can perform alignment, truncation, and other processing on the data in the first pipeline stage to obtain N consecutive blocks of data. Therefore, the data processing module 22 can return the block data access address `cache_address` and the block data `cache_block_data` to the preceding cache circuit via a handshake.

[0169] This application provides an image processing apparatus, such as... Figure 16 As shown, the memory access circuit 30 includes an address mapping module 31 and a data processing module 32.

[0170] The address mapping module 31 includes a burst transaction merging module 311, a memory address translation module 312, and a burst transaction length calculation module 313.

[0171] The burst transaction merging module 311 is used to receive at least two block data access addresses, and based on the at least two block data access addresses, to perform burst transaction merging processing on N consecutive block data access addresses, and to send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module 312 and the burst transaction length calculation module 313, where N is an integer greater than 1.

[0172] The memory address translation module 312 is used to map the first block data access address among N block data access addresses to a physical memory address.

[0173] The burst transaction length calculation module 313 is used to calculate the bus data volume corresponding to N block data access addresses based on the block data bit width and the bus bit width.

[0174] The data processing module 32 is used to edit the received bus data when the memory access circuit receives the bus data, to obtain N consecutive blocks of data, and to send the N block data access addresses and N block data to the buffer.

[0175] In some embodiments of this application, the above-mentioned sudden event merging module 313 may include: a digital statistics module and a continuous detection module.

[0176] In some embodiments of this application, the aforementioned digital statistics module is used to calculate the number of block data based on the maximum burst length value, the block data bit width, and the bus bit width. The number of block data is used to indicate the maximum number of block data access addresses that are allowed to be sent simultaneously.

[0177] It should be noted that for a detailed description of the method for calculating block data in the above-mentioned digital statistics module, please refer to the relevant description of the digital statistics module in the above embodiments, which will not be repeated here in the embodiments of this application.

[0178] In some embodiments of this application, the above-mentioned continuous detection module is used to determine whether at least two block data access addresses are consecutive, and to perform burst transaction merging processing on N block data access addresses based on the maximum number, and to determine the consecutive flag bits corresponding to the N block data access addresses.

[0179] It should be noted that for a detailed description of the continuous detection module's detection of whether access addresses are continuous and its handling of sudden transaction merging, please refer to the relevant description of the continuous detection module in the above embodiments. This application will not repeat it here.

[0180] In some embodiments of this application, the continuous detection module described above is further configured to send the continuous flag bits corresponding to N block data access addresses to the memory address translation module 312 and the burst transaction merging module 313.

[0181] In some embodiments of this application, the memory address translation module 312 described above is specifically used for:

[0182] Determine the second address offset based on the access address of the first block of data, the block data bit width, the bus bit width, and the first address offset;

[0183] The physical memory address of the first block of data is calculated based on the frame base address and the second address offset corresponding to the memory space of a frame of image in memory.

[0184] In some embodiments of this application, the aforementioned first address offset is the address offset from the starting address of one row of pixels to the starting address of the next row of pixels when storing an image in memory. That is, it can be understood as the number of blocks of data corresponding to a row of data.

[0185] It should be noted that for a detailed description of how the memory address translation module 312 calculates the second address offset and the physical memory address of the first block data, please refer to the relevant description of the memory address translation module 312 in the above embodiments. This application embodiment will not repeat it here.

[0186] In some embodiments of this application, the address mapping module may further include a handshake blocking module; the handshake blocking module is used to block the handshake signals corresponding to the first N-1 block data access addresses among the N block data access addresses.

[0187] It should be noted that for a detailed description of the handshake signals corresponding to the first N-1 block data access addresses blocked by the handshake blocking module, please refer to the relevant description of the handshake blocking module in the above embodiments. This application embodiment will not repeat it here.

[0188] In some embodiments of this application, the address mapping module may further include a burst command sending module; the burst command sending module is used to send the received memory physical address and the bus data corresponding to N blocks of data to the Read Direct Memory Access (RDMA) module for processing.

[0189] In some embodiments of this application, the above-mentioned N block data are block data corresponding to N block data addresses.

[0190] It should be noted that for a detailed description of the above-mentioned burst command sending module, please refer to the relevant description of the burst command sending module in the above embodiments, and this application embodiment will not repeat it here.

[0191] In some embodiments of this application, the address mapping module may further include an access address storage module; the access address storage module is used to store consecutive flag bits corresponding to N block data access addresses, and at least two block data access addresses.

[0192] It should be noted that for a detailed description of the access address storage module, please refer to the relevant description of the access address storage module in the above embodiments, and this application embodiment will not repeat it here.

[0193] In some embodiments of this application, the data processing module 32 may include a data splicing module and a block data generation module; the data splicing module is used to splice bus data based on N block data access addresses; the block data generation module is used to perform offset trimming on the spliced ​​bus data based on the continuous flag bits corresponding to the N block data access addresses to obtain N consecutive block data.

[0194] It should be noted that for a detailed description of the data splicing module and the block data generation module, please refer to the relevant descriptions of the data splicing module and the block data generation module in the above embodiments, and will not be repeated here in the embodiments of this application.

[0195] The execution subject of the memory access method provided in this application embodiment is a memory access circuit or an image processing device. This device can be an electronic device, or a functional module or entity within an electronic device; this application embodiment does not limit this. The following will use an electronic device as an example to executively describe the memory access method provided in this application embodiment.

[0196] This application provides a memory access method. Figure 17 A flowchart illustrating a memory access method provided in an embodiment of this application is shown. This method can be applied to the memory access circuit of an electronic device, which includes an address mapping module and a data processing module. Figure 17 As shown, the memory access method provided in this application embodiment may include the following steps 401 to 405.

[0197] Step 401: The electronic device receives at least two block data access addresses through the burst transaction merging module in the address mapping module, and performs burst transaction merging processing on N consecutive block data access addresses based on the at least two block data access addresses, and sends the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and burst transaction length calculation module in the address mapping module.

[0198] Where N is an integer greater than 1.

[0199] It should be noted that for the detailed description of the sudden transaction merging module sending the consecutive flag bits corresponding to N consecutive block data access addresses to the memory address translation module based on at least two block data access addresses, please refer to the relevant description of the sudden transaction merging module in the above embodiments, and this application embodiment will not repeat it here.

[0200] Step 402: The electronic device maps the first block data access address among N block data access addresses to a physical memory address through the memory address translation module in the address mapping module.

[0201] It should be noted that for the detailed steps of the memory address translation module mapping block data access addresses to memory physical addresses, please refer to the relevant description of the memory address translation module in the above embodiments, which will not be repeated here in the embodiments of this application.

[0202] Step 403: The electronic device calculates the bus data volume corresponding to N block data access addresses based on the block data bit width and bus bit width using the burst transaction length calculation module.

[0203] It should be noted that for the detailed steps of calculating the bus data volume for the burst transaction length calculation module, please refer to the relevant description of the burst transaction length calculation module in the above embodiments, which will not be repeated here in the embodiments of this application.

[0204] Step 404: The electronic device transmits the physical address of the memory and the amount of bus data to the memory through the address mapping module.

[0205] Step 405: When the memory access circuit receives the bus data sent by the memory, the electronic device performs editing processing based on the bus data through the data processing module to obtain N consecutive blocks of data, and sends the N block data access addresses and N block data to the buffer.

[0206] In some embodiments of this application, the above editing processes may include, but are not limited to, at least one of the following: splicing processing, offset calculation processing, and alignment processing.

[0207] It should be noted that for the detailed steps of the data processing module in editing and processing the received bus data, please refer to the relevant description of the data processing module in the above embodiments, which will not be repeated here in the embodiments of this application.

[0208] In the memory access method provided in this application embodiment, during the process of reading data from memory through the memory access circuit, the memory access circuit can perform burst transaction merging processing on the N consecutive block data access addresses, and then send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module. Thus, the memory address translation module can map the first block data access address among the N block data access addresses to a physical memory address, allowing the memory access circuit to represent the N block data access addresses using this first address, thereby eliminating the need for memory address translation for the remaining N-1 block data access addresses and reducing the number of block data access addresses that need to be sent. The burst transaction length calculation module can calculate the bus data volume corresponding to the N consecutive block data access addresses, reducing the repetitive statistics of bus data at the boundaries during the process of calculating and adding individual block data access addresses. This reduces the number of times the memory access circuit accesses the bus, reduces repeated readings of bus data, improves bus utilization, and further enhances memory access efficiency.

[0209] In some embodiments of this application, the "performing burst transaction merging processing on N consecutive block data access addresses based on at least two block data access addresses" in step 401 above can be specifically implemented through steps 501 and 502 below.

[0210] Step 501: The electronic device calculates the number of block data based on the maximum burst length value, block data bit width and bus bit width through the digital statistics module in the burst transaction merging module.

[0211] In some embodiments of this application, the above-mentioned block data quantity is used to indicate the maximum number of block data access addresses that are allowed to be sent simultaneously.

[0212] It should be noted that for the detailed steps of calculating the number of block data in the digital statistics module, please refer to the relevant description of the digital statistics module in the above embodiments, which will not be repeated here in the embodiments of this application.

[0213] Step 502: The electronic device uses the continuity detection module in the burst transaction merging module to determine whether at least two block data access addresses are consecutive, and performs burst transaction merging processing on N consecutive block data access addresses based on the maximum number, and determines the continuity flag bit corresponding to the N consecutive block data access addresses.

[0214] It should be noted that for the detailed steps of the continuous detection module in determining whether the block data access addresses are continuous, please refer to the relevant description of the continuous detection module in the above embodiments, which will not be repeated here in the embodiments of this application.

[0215] In this embodiment, the electronic device can determine N consecutive block data access addresses by detecting at least two block data access addresses. Subsequent modules can then determine the continuity of these N block data access addresses based on their corresponding continuity flags and perform appropriate processing. This reduces the number of block data access address conversions and the number of block data access addresses that need to be sent. Consequently, the number of times the memory access circuit accesses the bus is reduced, improving bus utilization and further enhancing memory access efficiency.

[0216] In some embodiments of this application, the memory access method provided in this application may further include the following steps 601 to 603.

[0217] Step 601: The electronic device sends the physical memory address to the burst command sending module in the address mapping module through the memory address translation module.

[0218] Step 602: The electronic device sends the bus data volume to the burst command sending module through the burst transaction length calculation module.

[0219] In some embodiments of this application, the above-mentioned N block data are block data corresponding to N block data addresses.

[0220] Step 603: The electronic device sends the received memory physical address and the bus data corresponding to N block data access addresses to the RDMA module for processing through the burst command sending module.

[0221] In this embodiment of the application, for N consecutive block data access addresses, the amount of bus data corresponding to each block data access address is greater than the amount of bus data directly corresponding to the N block data access addresses. Therefore, based on the amount of bus data corresponding to the N block data, the repeated reading of bus data can be reduced, which can further improve the bus utilization and improve the memory access speed.

[0222] In some embodiments of this application, the "editing process based on bus data to obtain N consecutive blocks of data" in step 405 above can be specifically achieved through steps 405a and 405b below.

[0223] Step 405a: The electronic device performs splicing processing on the bus data through the data splicing module in the data processing module, based on N block data access addresses.

[0224] Step 405b: The electronic device uses the block data generation module in the data processing module to perform offset trimming on the spliced ​​bus data based on the continuous flag bits corresponding to the N block data access addresses, and obtains N consecutive block data.

[0225] In this embodiment of the application, in scenarios with arbitrary block data bit width and bus data bit width, the electronic device can calculate the alignment offset of the bus data to effectively truncate the bus data, generate cache line block data, and write the cache address and the corresponding block data back to the cache in sequence. In this way, the convenience and universality of accessing memory data can be improved.

[0226] It should be noted that the above-described method embodiments, or the various possible implementations of the method embodiments, can be executed individually, or, provided there are no contradictions, they can be combined with each other. The specific implementation can be determined according to actual usage requirements, and this application embodiment does not impose any restrictions on this.

[0227] It should be noted that the memory access method provided in this application embodiment can be executed by a memory access device. This application embodiment uses the execution of the memory access method by a memory access device as an example to illustrate the memory access device provided in this application embodiment.

[0228] Figure 18 A schematic diagram of a possible structure of the memory access device involved in an embodiment of this application is shown. For example... Figure 18 As shown, the memory access device 70 may include: a receiving unit 71, a sending unit 72, a masking unit 73, and a mapping unit 74;

[0229] The receiving unit 71 is used to receive at least two block data access addresses through the burst transaction merging module in the address mapping module;

[0230] The merging unit 72 is used to perform burst transaction merging processing on N consecutive block data access addresses based on at least two block data access addresses received by the receiving unit 71.

[0231] The sending unit 73 is used to send the consecutive flag bits corresponding to N block data access addresses to the memory address translation module and the burst transaction length calculation module in the address mapping module, where the N block data access addresses are at least a part of the access addresses of at least two block data access addresses, and N is an integer greater than 1.

[0232] The mapping unit 74 is used to map the first block data access address among N block data access addresses to a physical memory address through the memory address translation module in the address mapping module;

[0233] The calculation unit 75 is used to calculate the bus data volume corresponding to N block data access addresses based on the block data bit width and bus bit width through the burst transaction length calculation module.

[0234] The sending unit 73 is also used to transmit the memory physical address output by the mapping unit 74 and the bus data amount calculated by the calculation unit 75 to the memory through the address mapping module;

[0235] The processing unit 76 is used to perform editing processing based on the bus data sent by the memory through the data processing module when the memory access circuit receives the bus data sent by the memory to obtain N consecutive blocks of data.

[0236] The sending unit 73 is also used to send the N block data access addresses and the N block data obtained by the processing unit 76 to the buffer.

[0237] In the memory access device provided in this application embodiment, during the process of reading data from memory through the memory access circuit, the memory access circuit can perform burst transaction merging processing on the N consecutive block data access addresses, and then send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module. Thus, the memory address translation module can map the first block data access address among the N block data access addresses to a physical memory address, allowing the memory access circuit to represent the N block data access addresses using the first block data access address, thereby eliminating the need for memory address translation for the remaining N-1 block data access addresses and reducing the number of block data access addresses that need to be sent. The burst transaction length calculation module can calculate the bus data volume corresponding to the N consecutive block data access addresses, reducing the repetitive statistics of bus data at the boundaries during the process of calculating and adding individual block data access addresses. This reduces the number of times the memory access circuit accesses the bus, reduces repeated readings of bus data, improves bus utilization, and further improves memory access efficiency.

[0238] In one possible implementation, the memory access device 70 provided in this application embodiment further includes: a detection unit; a calculation unit 75, specifically used to calculate the number of block data based on the maximum burst length value, block data bit width, and bus bit width through the digital statistics module in the burst transaction merging module, wherein the number of block data is used to indicate the maximum number of block data access addresses that can be sent simultaneously; a detection unit, used to determine whether at least two block data access addresses are consecutive through the continuity detection module in the burst transaction merging module; and a merging unit 72, specifically used to perform burst transaction merging processing on N consecutive block data access addresses based on the maximum number calculated by the calculation unit, and determine the continuity flag bit corresponding to the N consecutive block data access addresses.

[0239] In one possible implementation, the sending unit 73 is further configured to send the physical memory address to the burst command sending module in the address mapping module via the memory address translation module; and to send the bus data volume to the burst command sending module via the burst transaction length calculation module, wherein N block data are the block data corresponding to N block data addresses; and to send the received physical memory address and bus data volume to the RDMA module for processing via the burst command sending module.

[0240] In one possible implementation, the processing unit 76 is further configured to perform concatenation processing on the bus data based on N block data access addresses by the data concatenation module in the data processing module; and to perform offset trimming processing on the concatenated bus data based on the continuous flag bits corresponding to the N block data access addresses by the block data generation module in the data processing module, so as to obtain N consecutive block data.

[0241] The memory access device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the specific type of device.

[0242] The memory access device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0243] The memory access device provided in this application embodiment can implement the various processes implemented in the above method embodiments, and will not be described again here to avoid repetition.

[0244] Optionally, such as Figure 19As shown, this application embodiment also provides an electronic device 90, including a processor 91 and a memory 92. The memory 92 stores a program or instructions that can run on the processor 91. When the program or instructions are executed by the processor 91, they implement the various steps of the above-described memory access method embodiment and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0245] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0246] Figure 20 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0247] The electronic device 100 includes, but is not limited to, components such as: radio frequency unit 101, network module 102, audio output unit 103, input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, and processor 110.

[0248] Those skilled in the art will understand that the electronic device 100 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 110 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 20 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0249] The processor 110 is configured to receive at least two block data access addresses through the burst transaction merging module in the address mapping module, and perform burst transaction merging processing on N consecutive block data access addresses based on the at least two block data access addresses, and send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module in the address mapping module, where N is an integer greater than 1; through the memory address translation module, map the first block data access address among the N block data access addresses to a memory physical address; through the burst transaction length calculation module, calculate the bus data volume corresponding to the N block data access addresses based on the block data bit width and the bus bit width; through the address mapping module, transmit the memory physical address and the bus data volume to the memory; when the memory access circuit receives the bus data sent by the memory, through the data processing module, perform editing processing based on the bus data to obtain N consecutive block data, and send the N block data access addresses and N block data to the register.

[0250] In the electronic device provided in this application embodiment, during the process of reading data from memory via a memory access circuit, the memory access circuit can perform burst transaction merging processing on the N consecutive block data access addresses, and then send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module. Thus, the memory address translation module can map the first block data access address among the N block data access addresses to a physical memory address, allowing the memory access circuit to represent the N block data access addresses using this first address, thereby eliminating the need for memory address translation for the remaining N-1 block data access addresses and reducing the number of block data access addresses that need to be sent. The burst transaction length calculation module can calculate the bus data volume corresponding to the N consecutive block data access addresses, reducing the repetitive statistics of bus data at boundaries during the process of calculating and adding individual block data access addresses. This reduces the number of times the memory access circuit accesses the bus, reduces repeated readings of bus data, improves bus utilization, and further enhances memory access efficiency.

[0251] Optionally, the processor 110 is specifically used to calculate the number of block data based on the maximum burst length value, block data bit width, and bus bit width through the digital statistics module in the burst transaction merging module. The number of block data is used to indicate the maximum number of block data access addresses that can be sent simultaneously. Through the continuity detection module in the burst transaction merging module, it determines whether at least two block data access addresses are consecutive, and performs burst transaction merging processing on N consecutive block data access addresses based on the maximum number, and determines the continuity flag bit corresponding to the N consecutive block data access addresses.

[0252] Optionally, the processor 110 is also used to send the physical memory address to the burst command sending module in the address mapping module through the memory address translation module; to send the bus data volume to the burst command sending module through the burst transaction length calculation module, where N block data are the block data corresponding to N block data addresses; and to send the received physical memory address and bus data volume to the RDMA module for processing through the burst command sending module.

[0253] Optionally, the processor 110 is specifically configured to, through the data splicing module in the data processing module, splice the bus data based on N block data access addresses; and through the block data generation module in the data processing module, perform offset trimming on the spliced ​​bus data based on the consecutive flag bits corresponding to the N block data access addresses to obtain N consecutive blocks of data.

[0254] The electronic device provided in this application embodiment can implement the various processes implemented in the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0255] The beneficial effects of the various implementation methods in this embodiment can be found in the beneficial effects of the corresponding implementation methods in the above method embodiments. To avoid repetition, they will not be repeated here.

[0256] It should be understood that, in this embodiment, the input unit 104 may include a graphics processing unit (GPU) 1041 and a microphone 1042. The GPU 1041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 106 may include a display panel 1061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also called a touch screen. The touch panel 1071 may include a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (such as volume control buttons, power buttons, etc.), a trackball, a mouse, and a joystick, which will not be described in detail here.

[0257] The memory 109 can be used to store software programs and various data. The memory 109 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 109 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 109 in the embodiments of this application includes, but is not limited to, these and any other suitable types of memory.

[0258] Processor 110 may include one or more processing units; optionally, processor 110 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 110.

[0259] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0260] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0261] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0262] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0263] This application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the above method embodiments and achieve the same technical effects. To avoid repetition, it will not be described again here.

[0264] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0265] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0266] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A memory access circuit, characterized in that, The memory access circuit includes an address mapping module and a data processing module. The address mapping module includes a burst transaction merging module, a memory address translation module, and a burst transaction length calculation module. The burst transaction merging module is used to receive at least two block data access addresses, and based on the at least two block data access addresses, to perform burst transaction merging processing on N consecutive block data access addresses, and to send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module, wherein the N block data access addresses are at least a portion of the access addresses among the at least two block data access addresses, and N is an integer greater than 1; The memory address translation module is used to map the first block data access address among the N block data access addresses to a physical memory address; The burst transaction length calculation module is used to calculate the bus data volume corresponding to the N block data access addresses based on the block data bit width and the bus bit width. The data processing module is used to edit the received bus data when the memory access circuit receives bus data, to obtain N consecutive blocks of data, and to send the access addresses of the N blocks of data and the N blocks of data to the buffer.

2. The memory access circuit according to claim 1, characterized in that, The sudden event merging module includes: a digital statistics module and a continuous detection module; The digital statistics module is used to calculate the number of block data based on the maximum burst length value, block data bit width and bus bit width. The number of block data is used to indicate the maximum number of block data access addresses that can be sent simultaneously. The continuous detection module is used to determine whether the at least two block data access addresses are consecutive, and based on the maximum number, to perform burst transaction merging processing on the N block data access addresses, and to determine the consecutive flag bits corresponding to the N block data access addresses. The continuous detection module is also used to send the continuous flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module.

3. The memory access circuit according to claim 1, characterized in that, The memory address translation module is used for: Based on the access address of the first block data, the block data bit width, the bus bit width, and the first address offset, the second address offset is determined. The first address offset is the address offset from the starting address of one row of pixels to the starting address of the next row of pixels when storing an image in memory. The physical memory address of the first block of data is calculated based on the frame base address corresponding to the memory space of a frame of image in memory and the second address offset.

4. The memory access circuit according to claim 1, characterized in that, The address mapping module also includes a handshake blocking module; The handshake shielding module is used to shield the handshake signals corresponding to the first N-1 block data access addresses among the N block data access addresses.

5. The memory access circuit according to claim 1, characterized in that, The address mapping module also includes a burst command sending module; The burst command sending module is used to send the received memory physical address and the bus data corresponding to N blocks of data to the Read Direct Memory Access (RDMA) module for processing, wherein the N blocks of data are the block data corresponding to the N blocks of data addresses.

6. The memory access circuit according to claim 1, characterized in that, The address mapping module also includes an access address storage module; The access address storage module is used to store consecutive flag bits corresponding to the N block data access addresses, as well as the at least two block data access addresses.

7. The memory access circuit according to claim 1, characterized in that, The data processing module includes a data splicing module and a block data generation module; The data splicing module is used to splice the bus data based on the N block data access addresses; The block data generation module is used to perform offset trimming processing on the spliced ​​bus data based on the continuous flag bits corresponding to the N block data access addresses to obtain the N consecutive block data.

8. An image processing apparatus, characterized in that, Includes the memory access circuitry as described in any one of claims 1 to 7; The image processing device includes an address mapping module and a data processing module. The address mapping module includes a burst transaction merging module, a memory address translation module, and a burst transaction length calculation module. The burst transaction merging module is used to receive at least two block data access addresses, and based on the at least two block data access addresses, to perform burst transaction merging processing on N consecutive block data access addresses, and to send the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module, wherein the N block data access addresses are at least a portion of the access addresses among the at least two block data access addresses, and N is an integer greater than 1; The memory address translation module is used to map the first block data access address among the N block data access addresses to a physical memory address; The burst transaction length calculation module is used to calculate the bus data volume corresponding to the N block data access addresses based on the block data bit width and the bus bit width. The data processing module is used to edit the received bus data when the image processing device receives the bus data, to obtain N consecutive blocks of data, and to send the access addresses of the N blocks of data and the N blocks of data to the buffer.

9. The image processing apparatus according to claim 8, characterized in that, The sudden event merging module includes: a digital statistics module and a continuous detection module; The digital statistics module is used to calculate the number of block data based on the maximum burst length value, block data bit width and bus bit width. The number of block data is used to indicate the maximum number of block data access addresses that can be sent simultaneously. The continuous detection module is used to determine whether the at least two block data access addresses are consecutive, and based on the maximum number, to perform burst transaction merging processing on the N block data access addresses, and to determine the consecutive flag bits corresponding to the N block data access addresses. The continuous detection module is also used to send the continuous flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module.

10. The image processing apparatus according to claim 8, characterized in that, The memory address translation module is used for: Based on the access address of the first block data, the block data bit width, the bus bit width, and the first address offset, the second address offset is determined. The first address offset is the address offset from the starting address of one row of pixels to the starting address of the next row of pixels when storing an image in memory. The physical memory address of the first block of data is calculated based on the frame base address corresponding to the memory space of a frame of image in memory and the second address offset.

11. The image processing apparatus according to claim 8, characterized in that, The address mapping module also includes a handshake blocking module; The handshake shielding module is used to shield the handshake signals corresponding to the first N-1 block data access addresses among the N block data access addresses.

12. The image processing apparatus according to claim 8, characterized in that, The address mapping module also includes a burst command sending module; The burst command sending module is used to send the received memory physical address and the bus data corresponding to N blocks of data to the Read Direct Memory Access (RDMA) module for processing, wherein the N blocks of data are the block data corresponding to the N blocks of data addresses.

13. The image processing apparatus according to claim 8, characterized in that, The address mapping module also includes an access address storage module; The access address storage module is used to store consecutive flag bits corresponding to the N block data access addresses, as well as the at least two block data access addresses.

14. The image processing apparatus according to claim 8, characterized in that, The data processing module includes a data splicing module and a block data generation module; The data splicing module is used to splice the bus data based on the N block data access addresses; The block data generation module is used to perform offset trimming processing on the spliced ​​bus data based on the continuous flag bits corresponding to the N block data access addresses to obtain the N consecutive block data.

15. A memory access method, characterized in that, The method is applied to a memory access circuit according to any one of claims 1 to 7, or an image processing apparatus according to any one of claims 8 to 14, wherein the memory access circuit includes an address mapping module and a data processing module, and the method includes: The burst transaction merging module in the address mapping module receives at least two block data access addresses, and performs burst transaction merging processing on N consecutive block data access addresses based on the at least two block data access addresses. It also sends the consecutive flag bits corresponding to the N block data access addresses to the memory address translation module and the burst transaction length calculation module in the address mapping module. The N block data access addresses are at least a portion of the at least two block data access addresses, and N is an integer greater than 1. The memory address translation module maps the first block data access address among the N block data access addresses to a physical memory address. The burst transaction length calculation module calculates the bus data volume corresponding to the N block data access addresses based on the block data bit width and bus bit width. The address mapping module transmits the physical memory address and the bus data volume to the memory. When the memory access circuit receives the bus data sent by the memory, the data processing module performs editing processing based on the bus data to obtain N consecutive blocks of data, and sends the access addresses of the N blocks of data and the N blocks of data to the cache.

16. The method according to claim 15, characterized in that, The step of performing burst transaction merging processing on N consecutive block data access addresses based on the at least two block data access addresses includes: The number of block data is calculated by the digital statistics module in the burst transaction merging module based on the maximum burst length value, block data bit width and bus bit width. The number of block data is used to indicate the maximum number of block data access addresses that can be sent simultaneously. The continuous detection module in the burst transaction merging module determines whether the at least two block data access addresses are consecutive, and performs burst transaction merging processing on N consecutive block data access addresses based on the maximum number, and determines the consecutive flag bit corresponding to the N consecutive block data access addresses.

17. The method according to claim 15, characterized in that, The method further includes: The memory address translation module sends the physical memory address to the burst command sending module in the address mapping module. The bus data volume is sent to the burst command sending module through the burst transaction length calculation module, and the N block data are the block data corresponding to the N block data addresses; The received memory physical address and bus data volume are sent to the Read Direct Memory Access (RDMA) module for processing via the burst command sending module.

18. The method according to claim 15, characterized in that, The editing process based on the bus data yields N consecutive blocks of data, including: The bus data is spliced ​​based on the N block data access addresses using the data splicing module in the data processing module. The block data generation module in the data processing module performs offset trimming on the spliced ​​bus data based on the continuous flag bits corresponding to the N block data access addresses to obtain the N consecutive block data.

19. An electronic device, characterized in that, It includes the memory access circuitry as described in any one of claims 1 to 7, or the image processing apparatus as described in any one of claims 8 to 14.

20. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the memory access method as described in any one of claims 15 to 18.

21. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the memory access method as described in any one of claims 15 to 18.

22. A chip, characterized in that, The chip includes a processor and a communication interface coupled to the processor, the processor being used to run programs or instructions to implement the steps of the memory access method as described in any one of claims 15 to 18.

Images