Edge collaborative data flow scheduling method and system based on domestic SoC industrial computer

Abstract

The application discloses a kind of based on localization SoC industrial computer's edge end collaborative data flow scheduling method and system.The method is inserted in train marshalling reconstruction when, switching mark is collected in queue in vehicle-mounted end, and switching mark is formed before reconstruction section and reconstruction after section with boundary;According to the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical address of the logical

Description

Technical Field

[0001] This invention relates to the field of onboard data processing technology for rail transit, specifically to an edge-to-edge collaborative data flow scheduling method and system based on a domestically produced SoC industrial computer, and particularly to a scheduling technology that ensures the continuous operation of the onboard acquisition queue, edge computing status, and data processing flow when logical address changes are caused by train formation reconfiguration. Background Technology

[0002] With the increasing digitalization of rail transit equipment, industrial computers are typically installed in onboard networks to collect operational, status, and diagnostic data generated by equipment in different carriages. This data is then transmitted to onboard edge computing nodes for continuous processing. To meet the requirements of independent control, domestically produced SoC industrial computers are increasingly being applied to onboard data acquisition, protocol conversion, and edge computing scenarios. Onboard industrial computers generally obtain logical addresses according to train formation relationships, while edge computing allocates processing tasks and computing resources to the corresponding data streams based on these logical addresses.

[0003] During train coupling, decoupling, carriage replacement, or network failure recovery, the physical topology and logical grouping relationships of the onboard network change. Existing technologies typically restore the network by rediscovering network nodes, reallocating logical addresses, updating communication routes, and caching data frames generated during the reconstruction process. For data that was not processed during reconstruction, methods such as resending cached data, restarting processing tasks, or copying the task state to a new execution location are commonly used to allow the edge devices to continue executing the corresponding data processing tasks.

[0004] However, the logical addresses and computational tasks before and after train network reconstruction do not necessarily maintain a stable correspondence. Data that has entered the acquisition queue but has not yet been processed before reconstruction is still associated with the original logical address and execution location, while data generated after reconstruction may enter another acquisition queue or execution location according to the new logical address. Simply reallocating addresses or retransmitting cached data can only restore data transmission and cannot simultaneously maintain the processing order, computational state attribution, and processing location continuity of data before and after reconstruction. Using task restart or complete state copying may also cause duplicate processing, omission of unprocessed data, or state overwriting, and increase the storage access and state migration overhead of domestic SoC industrial computers.

[0005] Therefore, the technical problem that needs to be solved is: how to ensure the continuous continuation of data that has not been processed before the reconfiguration, the data to be written after the reconfiguration, and the existing computing state at the edge when the train network is reconfigured and causes changes in logical addresses, so as to achieve the orderly continuation of the data stream processing process. Summary of the Invention

[0006] The purpose of this invention is to provide an edge-to-edge collaborative data flow scheduling method and system based on a domestically produced SoC industrial computer, which solves the problem of continuous continuity of data flow, computing state and processing position before and after reconfiguration when logical address changes are caused by train reconfiguration.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: An edge-device collaborative data flow scheduling method based on a domestically produced SoC industrial computer includes: A data acquisition queue is established using a domestically produced SoC industrial computer on the vehicle, and vehicle data frames are written into the acquisition queue. When the train network initiates train formation reconfiguration, the current queue node is sealed, a switching marker is inserted after the current queue node, and writing continues from after the switching marker to form the reconfiguration front segment and the reconfiguration back segment. The address acceptance token is passed level by level according to the physical connection order, and the acceptance relationship from the logical address before reconstruction to the logical address after reconstruction is written into the corresponding switching flag. The address acceptance token is passed backward from the end of the physical connection sequence, and the return pointer is written to the corresponding switching flag to form an acceptance chain; Based on the aforementioned connection chain, at the edge end, the computation state page of the pre-reconstruction logical address index is transferred from the old execution slot to the new execution slot of the post-reconstruction logical address index; Position the processing cursor of the computing status page to the unprocessed position of the reconstruction front section, continue the reconstruction back section through the queue successor pointer of the switching mark, process the vehicle data frame along the continuation of the acquisition queue, and release the old execution slot.

[0008] Preferably, the address acceptance token is passed level by level according to the physical connection order, the connection relationship from the logical address before reconstruction to the logical address after reconstruction is written into the corresponding switching flag, and the address acceptance token is passed in reverse from the end of the physical connection order, and the return pointer is written into the corresponding switching flag to form an acceptance chain, including: Read the corresponding pre-reconstruction logical address and post-reconstruction logical address from the domestically produced SoC industrial computers, and write the pre-reconstruction logical address and post-reconstruction logical address into the corresponding front address entry and back address entry of the switching flag respectively to form an address inheritance entry; A first-level address acceptance token is generated based on the switching flag corresponding to the domestic SoC industrial computer located at the first end of the physical connection sequence. The storage address of the corresponding switching flag is written into the flag reference item of the first-level address acceptance token, and the first-level address acceptance token is passed to the subsequent domestic SoC industrial computer. After the subsequent domestically produced SoC industrial computer receives the previous address acceptance token, it generates a subsequent address acceptance token according to the corresponding switching flag, writes the storage address of the corresponding switching flag into the flag reference item of the subsequent address acceptance token, points the token predecessor pointer of the subsequent address acceptance token to the previous address acceptance token, and points the token successor pointer of the previous address acceptance token to the subsequent address acceptance token. Starting from the end of the physical linking sequence, the last generated subsequent address accepting token is passed backward along the token predecessor pointer. During the backward passing process, the return pointer of the current switching mark is written as an addressable reference of the adjacent subsequent address accepting token, and the return pointer of the switching mark corresponding to the last level is written as a null pointer, until the first address accepting token is obtained, thus forming the accepting chain.

[0009] Preferably, according to the relay chain, at the edge end, the calculation state page of the pre-reconstruction logical address index is transferred from the old execution slot to the new execution slot of the post-reconstruction logical address index, and the processing cursor of the calculation state page is positioned to the unprocessed position of the pre-reconstruction segment. The post-reconstruction segment is continued through the queue successor pointer of the switching mark, the vehicle data frame is processed along the continued acquisition queue, and the old execution slot is released, including: Read the pre-reconstruction logical address and post-reconstruction logical address associated with the same switching flag along the succession chain, and locate the old execution slot, the new execution slot, and the switching flag; Read the page pointer in the old execution slot that points to the computing state page, rewrite the page pointer of the new execution slot to point to the computing state page, and rewrite the page pointer of the old execution slot to point to the transfer pointer of the new execution slot; Write the processing cursor as the queue node reference and node offset corresponding to the first unprocessed position in the reconstruction front section, and confirm that the queue successor pointer of the switching mark points to the first node address of the reconstruction back section; The processing cursor is driven to traverse the pre-reconstruction phase and the post-reconstruction phase in sequence. After the processing cursor enters the post-reconstruction phase, the transfer pointer is cleared and the old execution slot is released.

[0010] Preferably, reading the page pointer in the old execution slot that points to the computation state page, rewriting the page pointer of the new execution slot to point to the computation state page, and rewriting the page pointer of the old execution slot to point to the transition pointer of the new execution slot, includes: An active pointer entry and a spare pointer entry are set in the new execution slot; Read the page pointer of the old execution slot and write the read page pointer into the spare pointer entry; Through a single indivisible write operation, the pointer value of the active pointer entry is rewritten to the page pointer in the spare pointer entry; After the indivisible write operation is completed, the page pointer of the old execution slot is rewritten to the transfer pointer containing the address of the new execution slot.

[0011] Preferably, driving the processing cursor to sequentially traverse the pre-reconstruction phase and the post-reconstruction phase, and clearing the transfer pointer and releasing the old execution slot after the processing cursor enters the post-reconstruction phase, includes: Before the pointer value of the active pointer entry is rewritten to the page pointer in the spare pointer entry, the vehicle data frame to be written to the reconstructed stage is kept in the acquisition queue; After the pointer value of the active pointer entry is rewritten to the page pointer in the spare pointer entry, the computation state page is driven to start processing from the unprocessed position pointed to by the processing cursor; When the processing cursor crosses the switching mark, the queue successor pointer of the switching mark is written into the queue node reference portion of the processing cursor; After the processing cursor enters the reconstructing phase, the transfer pointer in the old execution slot is cleared, the old execution slot is released, and the queue nodes that have been processed in the reconstructing phase are reclaimed.

[0012] Preferably, when the train network initiates train formation reconfiguration, the current queue node is sealed, a switching marker is inserted after the current queue node, and writing continues from after the switching marker to form a pre-reconfiguration segment and a post-reconfiguration segment, including: Read the write pointer of the acquisition queue and take the queue node pointed to by the write pointer as the current queue node; The current write position of the current queue node is fixed as the node end position, a sealing identifier is written into the current queue node, and the writing of the vehicle data frame to the current queue node is stopped. Generate the switching flag, point the queue successor pointer of the current queue node to the switching flag, and point the queue predecessor pointer of the switching flag to the current queue node; Assign the first node of the reconstructed segment, point the queue successor pointer of the switching mark to the first node, and point the queue predecessor pointer of the first node to the switching mark; Switch the write pointer of the acquisition queue from the current queue node to the first node.

[0013] Preferably, switching the write pointer of the acquisition queue from the current queue node to the head node includes: Assign a front-end generation number to the current queue node, and write the front-end generation number to the current queue node and the switching flag; Generate a subsequent generation number based on the preceding generation number, and write the subsequent generation number into the switching flag and the first node; Switch the write pointer to the first node, update the queue generation number carried by the write pointer to the later generation number, and keep the queue generation number carried by the processing cursor as the earlier generation number. After the processing cursor reads the switching flag, the queue generation number carried by the processing cursor is updated to the subsequent generation number, and the processing cursor is driven to enter the reconstructed subsequent stage through the queue successor pointer.

[0014] Preferably, after forming the receiving chain, migrating the receiving chain to the edge end includes: According to the arrangement order of the first-level address accepting token to the last generated subsequent address accepting token in the accepting chain, the accepting tokens at each level are traversed, and the corresponding chain number is written for each level of address accepting token. Based on the tag references of the address acceptance tokens at each level and the address acceptance items, queue successor pointers, front generation numbers, and back generation numbers in the corresponding switching tags, queue continuation information is generated. The chain sequence number, the address acceptance items, the queue continuation information, the token predecessor pointer, and the token successor pointer are encapsulated into a migration record. The queue continuation information includes a switching tag reference, a reconstructed back-end first node reference, a front generation number, and a back generation number. Based on the difference in chain sequence number between two adjacent migration records, the token predecessor pointer and the token successor pointer in each migration record are rewritten as predecessor sequence number offset and successor sequence number offset, respectively, to form a chain map; The chain image is transmitted to the edge end, a continuous chain buffer consisting of equal-length record slots is allocated at the edge end, and each migration record is written into the corresponding record slot according to the chain sequence number. Based on the starting address of the continuous chain buffer and the predecessor sequence number offset and the successor sequence number offset in each migration record, the local token predecessor pointer and local token successor pointer between each migration record are reconstructed to form an edge-connecting chain.

[0015] Preferably, based on the starting address of the continuous chain buffer and the predecessor sequence number offset and the successor sequence number offset in each of the migration records, the local token predecessor pointer and local token successor pointer between each of the migration records are reconstructed to form an edge-connecting chain, including: Based on the starting address of the continuous chain buffer, the length of the record slot, and the chain number of each migration record, the slot address of each migration record is obtained sequentially. Add the chain number of the current migration record to the predecessor chain number offset and the successor chain number offset respectively to obtain the chain number of the predecessor migration record and the chain number of the successor migration record. The chain number of the predecessor migration record and the chain number of the successor migration record are converted into corresponding slot addresses, and the two converted slot addresses are written into the local token predecessor pointer and local token successor pointer of the current migration record, respectively. Write the local token predecessor pointer corresponding to the first-level address accepting token to a null pointer, and write the local token successor pointer corresponding to the last generated subsequent address accepting token to a null pointer, thus forming the edge accepting chain.

[0016] This invention also provides an edge-to-edge collaborative data flow scheduling system based on a domestically produced SoC industrial computer, comprising: The vehicle-mounted terminal and the edge terminal that are communicatively connected to the vehicle-mounted terminal, wherein the vehicle-mounted terminal includes at least two domestically produced SoC industrial computers that are communicatively connected in a physical connection order; The vehicle-mounted terminal includes a data acquisition module, a queue segmentation module, an address forward transmission module, and an address back transmission module; the edge terminal includes a status switching module and a cross-segment continuation module. The data acquisition module is used to establish an acquisition queue through the domestically produced SoC industrial computer on the vehicle side and write the vehicle data frame into the acquisition queue. The queue segmentation module is used to seal the current queue node when the train network starts regrouping and reconfiguring, insert a switching marker after the current queue node, and continue writing from the switching marker to form the reconfiguration front segment and the reconfiguration back segment. The address forwarding module is used to pass the address acceptance token step by step according to the physical connection order, and write the acceptance relationship from the logical address before reconstruction to the logical address after reconstruction into the corresponding switching flag. The address backhaul module is used to transmit the address acceptance token in reverse from the end of the physical connection sequence, write the backhaul pointer to the corresponding switching flag, and form an acceptance chain. The state transfer module is used to transfer the computation state page of the pre-reconstruction logical address index from the old execution slot to the new execution slot of the post-reconstruction logical address index at the edge end, according to the receiving chain. The cross-segment continuation module is used to position the processing cursor of the calculation status page to the unprocessed position of the reconstruction front segment, continue the reconstruction back segment through the queue successor pointer of the switching mark, process the vehicle data frame along the continuation acquisition queue, and release the old execution slot.

[0017] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention combines the logical address connection relationship and the segment boundary of the acquisition queue to the same switching mark, so that the edge end can simultaneously obtain the logical address correspondence before and after reconstruction, the unprocessed data of the front segment of the queue and the continuation entry of the back segment of the queue from the switching mark, thus avoiding the break in the processing order caused by the separation of address recovery and data recovery.

[0018] (2) The present invention transmits and transmits the address of the token according to the physical coupling order of the train. The resulting binding chain retains the actual connection order of the vehicles and can support multiple on-board end nodes to perform state switching according to a unified physical topology in the same train reconfiguration.

[0019] (3) The present invention completes the transfer of the computation state page by rewriting the page pointer of the execution slot, without copying all the state data in the computation state page body; and determines the effective boundary of the new execution slot page pointer by indivisible write operation, thereby reducing intermediate states and memory access overhead during the state transfer process.

[0020] (4) The present invention maintains the front generation number and the back generation number on both sides of the switching mark, so that the write pointer can enter the reconstructed back segment to continue receiving vehicle data frames, while the processing cursor continues to execute from the actual unprocessed position of the reconstructed front segment, thus avoiding data acquisition interruption and data omission.

[0021] (5) The present invention converts the local token pointer of the vehicle end into a chain sequence number offset and rebuilds the local pointer in the continuous chain buffer at the edge end, thereby avoiding the cross-address space pointer failure caused by directly transmitting the absolute address of the vehicle end.

[0022] (6) The present invention ensures that the old execution slot is released only after the cursor enters the reconstructing stage, and the release time of the execution resources is consistent with the data processing boundary, so as to avoid the loss of computational state references for data before reconstruction that has not yet been processed. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a flowchart illustrating an edge-to-edge collaborative data flow scheduling method based on a domestically produced SoC industrial computer, as provided in an embodiment of the present invention.

[0025] Figure 2This is a schematic diagram of the acquisition queue segmentation and switching marker structure for an edge-to-edge collaborative data stream scheduling method based on a domestically produced SoC industrial computer, provided in an embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram illustrating the address acceptance token forwarding and backhauling forming an acceptance chain in an edge-end collaborative data flow scheduling method based on a domestically produced SoC industrial computer, provided as an embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram illustrating the computational state page transfer and processing cursor cross-segment continuation of a method for edge-end collaborative data flow scheduling based on a domestically produced SoC industrial computer, provided in an embodiment of the present invention.

[0028] Figure 5 This is a schematic diagram of the structure of an edge-to-edge collaborative data flow scheduling system based on a domestically produced SoC industrial computer, provided as an embodiment of the present invention. Detailed Implementation

[0029] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0030] Example 1: This embodiment provides an edge-to-edge collaborative data flow scheduling method based on a domestically produced SoC industrial computer, such as... Figure 1 As shown, it includes the following steps: Step S1: Establish a data acquisition queue using the domestically produced SoC industrial computer on the vehicle, and write the vehicle data frame into the data acquisition queue.

[0031] In this embodiment, the train formation includes onboard node A, onboard node B, and onboard node C connected in physical coupling order. All three onboard nodes utilize domestically produced SoC industrial computers. These domestically produced SoC industrial computers can employ domestically produced processor platforms with ARMv8 or RISC-V instruction sets, supporting atomic storage instructions STLR (Store-Release) or atomic swap instructions AMOSWAP, and have a natural word length of 64 bits.

[0032] When each domestically produced SoC industrial computer initiates a data acquisition task, it establishes an acquisition queue in its local memory. The acquisition queue is formed by connecting one or more queue nodes, which are linked by a queue predecessor pointer and a queue successor pointer. Each queue node includes a node header and a frame storage area. The node header stores the queue predecessor pointer, queue successor pointer, node end position, seal identifier, and queue generation number; the frame storage area is used to sequentially store vehicle-mounted data frames. The acquisition queue maintains a queue head pointer and a write pointer, with the write pointer pointing to the queue node currently being written to.

[0033] Taking vehicle-mounted node B as an example, after the data acquisition module obtains the vehicle-mounted data frame from the vehicle network interface, it writes the vehicle-mounted data frame to the next writable position in the frame storage area of ​​the queue node pointed to by the write pointer, and moves the write offset within the frame storage area. The vehicle-mounted data frame includes a frame header, data payload, and checksum tail. When the frame storage area of ​​the current queue node is full, the data acquisition module allocates the next queue node according to the usual queue expansion method, points the successor pointer of the current queue node to the newly allocated node, points the predecessor pointer of the newly allocated node to the current queue node, and moves the write pointer to the newly allocated node.

[0034] When no train reconfiguration occurs, all queue nodes have the same current generation number. The edge terminal communicates with each onboard node via the train's Ethernet backbone, and the edge terminal sets up an execution slot for each logical address. An execution slot is a task binding item indexed by its logical address, and it stores a page pointer that points to the computational state page of the corresponding data stream. The computational state page is a state storage unit maintained for a continuous computation task, containing the task context, cumulative processing status, window status, and a processing cursor. The processing cursor includes a queue node reference, an offset within the node, and the queue generation number, used to determine the actual processing progress of the continuous data stream.

[0035] Before grouping and reconfiguration, the logical addresses of vehicle-mounted nodes A, B, and C are 10, 11, and 12, respectively. At the edge, execution slot E10 is set for logical address 10, with its page pointer pointing to computational state page PA; execution slot E11 is set for logical address 11, with its page pointer pointing to computational state page PB; and execution slot E12 is set for logical address 12, with its page pointer pointing to computational state page PC. The processing cursor in each computational state page retrieves the vehicle-mounted data frame to be processed according to the queue node reference and intra-node offset of the corresponding acquisition queue. After processing the current queue node, it moves along the queue successor pointer and executes the data processing algorithm.

[0036] Step S2: When the train network starts regrouping, seal the current queue node, insert a switching marker after the current queue node, and continue writing from the switching marker to form the regrouping front segment and the regrouping back segment.

[0037] When the train network management unit begins reconfiguration, it sends the same reconfiguration event to all domestically produced SoC industrial computers. The reconfiguration event is sent via broadcast or multicast through the train's Ethernet backbone, and all onboard end nodes receive the reconfiguration event almost simultaneously.

[0038] Taking vehicle-mounted node B as an example, after receiving the reconstruction event, the queue segmentation module reads the write pointer of the acquisition queue and determines the queue node pointed to by the write pointer as the current queue node QB0. The queue segmentation module fixes the current write offset of the frame storage area within QB0 as the node end position, writes the node end position into the node header of QB0, and writes a sealing flag into the node header of QB0. The sealing flag can be implemented using a Boolean flag, set to true to indicate that the node has been sealed. After the data acquisition module detects the sealing flag, it stops writing vehicle-mounted data frames to the frame storage area of ​​QB0. Vehicle-mounted data frames before the node end position belong to the reconstruction pre-segment.

[0039] Subsequently, the queue segmentation module generates a switching marker (MB). The switching marker (MB) is a control node inserted into the acquisition queue. It does not carry ordinary vehicle-mounted data frames and is used to identify group reconfiguration boundaries and store the connection information between preceding and following queue segments and their logical addresses. The switching marker (MB) includes fields for queue predecessor pointer, queue successor pointer, previous address entry, next address entry, return pointer, previous segment generation number, and next segment generation number. The queue segmentation module sets the queue successor pointer of QB0 to the storage address of the switching marker (MB) and sets the queue predecessor pointer of the switching marker (MB) to the storage address of QB0.

[0040] The queue segmentation module reallocates and reconstructs the first node QB1 of the subsequent segment, sets the queue predecessor pointer of QB1 to the switching marker MB, and sets the queue successor pointer of the switching marker MB to QB1. After completing the above connections, the acquisition queue is structurally represented as follows: In this process, QB0 and the nodes preceding it constitute the front segment of reconstruction, QB1 and the nodes following it constitute the back segment of reconstruction, and MB is located between the two segments.

[0041] To distinguish between the data segments occupied by the writing side and the processing side, the queue segmentation module assigns a front-segment generation number to QB0. In this embodiment, the front-segment generation number is 0. The queue segmentation module writes the front-segment generation number 0 into the node header of QB0 and the front-segment generation number field of the switching marker MB. Subsequently, the queue segmentation module generates a back-segment generation number based on the front-segment generation number. In this embodiment, the back-segment generation number is 1, which is the same as the front-segment generation number. The queue segmentation module writes the back-segment generation number 1 into the back-segment generation number field of the switching marker MB and the node header of QB1.

[0042] The queue segmentation module switches the write pointer from QB0 to QB1 and updates the queue generation number carried by the write pointer to the subsequent generation number 1. Afterward, the vehicle data frames received by the data acquisition module are written to the frame storage area of ​​QB1. Once QB1 is full, subsequent nodes are allocated according to the conventional queue expansion method, with each subsequent node having a queue generation number of 1. Simultaneously, the processing cursor in the computation status page PB still carries the previous generation number 0, and continues to retrieve vehicle data frames sequentially from the actual unprocessed position of the reconstructed previous segment according to the queue successor pointer.

[0043] like Figure 2 As shown, the collection queue consists of multiple queue nodes connected sequentially before the reconstruction event. and This indicates a historical queue node that has been allocated and written to the vehicle data frame before the current write node QB0. QB0 represents the current write node pointed to by the write pointer when the reconstruction event occurs. After the reconstruction event, QB0 is sealed as the reconstruction front-end node, the switch flag MB is inserted between QB0 and the reconstruction back-end first node QB1, the write pointer switches to QB1, and the processing cursor continues processing from the unprocessed offset in QB0.

[0044] Therefore, newly received vehicle data frames during the reconfiguration process can continue to enter the later stage of reconfiguration without interruption of vehicle data acquisition; while the edge processing cursor is still processed in the earlier stage of reconfiguration in the original order, and will not skip vehicle data frames that have not yet been processed in the earlier stage of reconfiguration because the write pointer has switched to the later stage of reconfiguration.

[0045] Step S3: Pass the address acceptance token level by level according to the physical connection order, and write the acceptance relationship from the logical address before reconstruction to the logical address after reconstruction into the corresponding switching flag.

[0046] After the group reconfiguration is completed and the logical addresses are reallocated, the logical addresses of vehicle-mounted nodes A, B, and C are adjusted to 21, 22, and 23 respectively. Each domestically produced SoC industrial computer reads the logical addresses before and after reconfiguration from its local network configuration area. Vehicle-mounted node A reads logical address 10 before reconfiguration and logical address 21 after reconfiguration; vehicle-mounted node B reads logical address 11 before reconfiguration and logical address 22 after reconfiguration; and vehicle-mounted node C reads logical address 12 before reconfiguration and logical address 23 after reconfiguration.

[0047] The address forwarding module writes the pre-reconstruction logical address into the forward address entry of the corresponding switching marker, and writes the post-reconstruction logical address into the backward address entry of the corresponding switching marker. The forward and backward address entries together constitute the address receiving entry. Taking the vehicle-mounted node B as an example, the address forwarding module writes the pre-reconstruction logical address 11 into the forward address entry of the switching marker MB, and writes the post-reconstruction logical address 22 into the backward address entry of MB, forming the address receiving entry "". The vehicle-mounted node A forms an address acceptor in its switching marker MA. "The vehicle-mounted node C forms an address acceptor in its switching marker MC." ".

[0048] The physical coupling order can be obtained from the train network topology discovery results. During train formation reconfiguration, the train network management unit performs topology discovery, determining the actual coupling order of each onboard node through the connection table of adjacent car network interfaces or through the round-trip latency of probe messages. In this embodiment, the physical coupling order is as follows: onboard node A, onboard node B, and onboard node C are connected sequentially, with onboard node A at the beginning of the physical coupling order and onboard node C at the end.

[0049] The vehicle-mounted node A, located at the head of the physical connection sequence, generates a first-level address acceptance token TA based on its local handover flag MA. The address acceptance token is a control record passed between domestically produced SoC industrial computers according to the physical connection sequence, storing the handover flag reference and the connection relationship between adjacent tokens. The token TA includes a flag reference field, a token predecessor pointer, and a token successor pointer field. The token TA is stored in the local memory of vehicle-mounted node A. Vehicle-mounted node A writes the storage address of the handover flag MA into the flag reference field of the token TA. The storage address uses an addressable reference consisting of a node identifier and an intra-node offset address. The node identifier is the unique identifier of vehicle-mounted node A, and the intra-node offset address is the offset address of the handover flag MA in the memory of vehicle-mounted node A. Since the token TA is the first-level token, its token predecessor pointer is set to a null pointer.

[0050] Onboard node A transmits a preceding token message containing an addressable reference to token TA to the subsequent domestically produced SoC industrial computer, i.e., onboard node B, via the train Ethernet backbone. Upon receiving the preceding token message, onboard node B generates a subsequent address to inherit token TB based on its local switching flag MB. Onboard node B writes the storage address of the switching flag MB into the flag reference field of token TB and writes the token predecessor pointer of token TB as an addressable reference to token TA. After generating token TB, onboard node B returns a subsequent confirmation message containing an addressable reference to token TB to onboard node A. Based on the subsequent confirmation message, onboard node A rewrites the token successor pointer of token TA locally to point to an addressable reference to token TB.

[0051] Vehicle node B transmits a preceding token message containing an addressable reference to token TB to vehicle node C. Upon receiving the preceding token message, vehicle node C generates a successor address acceptor token TC, writes the storage address of the switching flag MC into the flag reference entry of token TC, and writes the token predecessor pointer of token TC as an addressable reference to token TB. After generating token TC, vehicle node C returns a subsequent confirmation message containing an addressable reference to token TC to vehicle node B. Based on this subsequent confirmation message, vehicle node B rewrites the token successor pointer of token TB locally to point to an addressable reference to token TC. Because vehicle node C is at the end of the physical connection sequence, the token successor pointer of token TC is written as a null pointer.

[0052] After the above forward transmission process, a token forward connection relationship is formed on the vehicle end that is identical to the actual connected arrangement of the tokens on the vehicle: Each token is associated with the switching tokens MA, MB, and MC through a token reference item.

[0053] Step S4: Pass the address acceptance token in reverse from the end of the physical connection sequence, write the return pointer to the corresponding switching flag, and form an acceptance chain.

[0054] After the vehicle-mounted node C at the end of the physical connection sequence generates the final address acceptance token TC, the address backhaul module uses the token TC as the backhaul starting point. Since vehicle-mounted node C has no adjacent downstream nodes, it writes the backhaul pointer of the switching marker MC to a null pointer and reads the token predecessor pointer of the token TC, which points to the token TB. Vehicle-mounted node C generates a backhaul message containing an addressable reference to the token TC and sends the backhaul message to vehicle-mounted node B.

[0055] After receiving the feedback message, vehicle node B writes the feedback pointer in its local handover flag MB as an addressable reference to the token TC. The feedback pointer is an addressable reference composed of the node identifier of vehicle node C and the intra-node offset address of the token TC. Vehicle node B can locate the handover flag MC of vehicle node C through the flag reference entry of the token TC, thereby determining the adjacent subsequent successor of the handover flag MB.

[0056] Subsequently, vehicle node B reads the token predecessor pointer of its local token TB, which points to token TA. Vehicle node B generates a callback message containing an addressable reference to token TB and sends it to vehicle node A. Upon receiving the callback message, vehicle node A writes the callback pointer to token TB into its local handover flag MA. Thus, handover flag MA is associated with handover flag MB through token TB, and handover flag MB is associated with handover flag MC through token TC.

[0057] At this point, each non-last-level switching marker has a return pointer written to the adjacent subsequent address accepting token, while the return pointer of the last-level switching marker is a null pointer, forming an accepting chain. This accepting chain has the following properties: starting from any non-last-level switching marker, the adjacent subsequent address accepting token is first obtained through the return pointer of that switching marker, and then the adjacent subsequent switching marker is located through the marker reference entry of that address accepting token. This allows tracing the subsequent switching markers along the physical connection order; each token is associated with its corresponding switching marker through its marker reference entry, and the switching marker stores the address accepting entry and queue connection relationship.

[0058] like Figure 3As shown, vehicle-mounted nodes A, B, and C form tokens TA, TB, and TC according to their physical connection order. Each token is associated with switching tokens MA, MB, and MC through a tag reference item. The switching tokens store the address inheritance items for "logical address 10 before reconstruction to logical address 21 after reconstruction", "logical address 11 before reconstruction to logical address 22 after reconstruction", and "logical address 12 before reconstruction to logical address 23 after reconstruction", respectively. The subsequent inheritance object is traced along the actual connection order from A to C by the return pointer.

[0059] Step S5: Based on the aforementioned connection chain, at the edge end, transfer the computation state page of the pre-reconstruction logical address index from the old execution slot to the new execution slot of the post-reconstruction logical address index.

[0060] In implementations where the vehicle-mounted and edge-mounted terminals use independent address spaces, chain migration is required after the connection chain is formed. Since the forward connections of each token and the return pointers of each switching marker correspond to the same physical connection order, the address return module or independent chain migration program starts by accepting the first-level address token TA, sequentially traversing tokens TA, TB, and TC through the token successor pointers, and reading the fields in the corresponding switching markers through the marker reference entries of each token, writing the chain sequence number for each token according to the traversal order. In this embodiment, the chain sequence number of token TA is 0, the chain sequence number of token TB is 1, and the chain sequence number of token TC is 2.

[0061] Subsequently, the chain migration procedure locates the corresponding switching token through the token's tag reference, reads the address inheriting item, queue successor pointer, previous generation number, and next generation number from the corresponding switching token, and generates queue continuation information accordingly. The token TA uses its tag reference as the switching token MA reference, and reads the address inheriting item from the switching token MA. The queue continuation information QA is generated from the queue successor pointer, the previous generation number, and the next generation number. The queue continuation information QB and QC are generated for the tokens TB and TC in the same way, respectively. The chain migration program encapsulates the chain number, address inheritor, queue continuation information, token predecessor pointer, and token successor pointer into a migration record.

[0062] The original token pointer is only valid within the on-board address space and will become invalid if directly transmitted to the edge. Therefore, the chain migration procedure converts the token pointer into a sequence offset based on the difference in chain numbers between two adjacent migration records. For token TB with chain number 1, its predecessor pointer points to token TA with chain number 0, with a predecessor sequence offset of 0-1=-1; its successor pointer points to token TC with chain number 2, with a successor sequence offset of 2-1=+1. Similarly, the successor sequence offset for token TA is 1-0=+1, and its predecessor pointer is null; the predecessor sequence offset for token TC is 1-2=-1, and its successor pointer is null.

[0063] The chain migration procedure replaces the token predecessor pointer and token successor pointer in each migration record with the predecessor sequence number offset and successor sequence number offset, respectively, to form a chain map.

[0064] In this embodiment, the chain map contains three migration records of equal length: Migration record 0: Chain number 0, address recipient " "The queue continues the information QA, the predecessor sequence number offset is invalid, and the successor sequence number offset is increased by 1; " Migration record 1: Chain number 1, address recipient " ", queue continuation information QB, predecessor sequence number offset -1, successor sequence number offset +1; Migration record 2: Chain number 2, address recipient " ", queue continuation information QC, predecessor sequence number offset -1, successor sequence number offset is invalid."

[0065] Among them, the queue continuation information QA, QB and QC all include the corresponding switching mark reference, the reconstructed first node reference, the previous generation number and the next generation number.

[0066] The chain migration procedure transmits the chain image to the edge end via the train Ethernet backbone. The edge end allocates a continuous chain buffer based on the number of migration records (3) and the length of a single record slot (L). In this embodiment, the length of a single record slot (L) is determined according to the migration record field length and alignment requirements, and can accommodate the chain sequence number, address inheritance item, queue continuation information, predecessor sequence number offset, successor sequence number offset, local token predecessor pointer, and local token successor pointer. For ease of explanation, the addressable reference consists of a 32-bit node identifier and a 32-bit intra-node offset address. The queue continuation information is stored using two addressable references and two 32-bit generation numbers. Under this compressed field organization, the length of a single record slot (L) is 64 bytes. The edge end allocates a continuous chain buffer starting at address B, with a total length of 3 × 64 = 192 bytes.

[0067] At the edge, each migration record is written to its corresponding record slot according to the chain sequence number. Migration record 0 is written to address B+0×64=B, migration record 1 is written to address B+1×64=B+64, and migration record 2 is written to address B+2×64=B+128.

[0068] Subsequently, the edge device reconstructs the local token predecessor pointer and local token successor pointer based on the starting address B of the contiguous chain buffer and the sequence number offset in each migration record. Taking migration record 1 with chain number 1 as an example, the slot address of this migration record... The predecessor sequence number offset of migration record 1 is -1, so the chain number of the predecessor migration record is 1 + (-1) = 0, and the predecessor slot address is B + 0 × 64 = B. The successor sequence number offset of migration record 1 is +1, so the chain number of the successor migration record is 1 + 1 = 2, and the successor slot address is B + 2 × 64 = B + 128. The edge device writes the predecessor slot address B into the local token predecessor pointer field of migration record 1, and writes the successor slot address B + 128 into the local token successor pointer field of migration record 1.

[0069] Similarly, the local token predecessor pointer of migration record 0 is written as a null pointer (because the first level has no predecessor), and the local token successor pointer is written as B+64; the local token predecessor pointer of migration record 2 is written as B+64, and the local token successor pointer is written as a null pointer (because the last level has no successor). After completing the above reconstruction, an edge connection chain that can be traversed locally at the edge end is formed.

[0070] The status transfer module reads the address acceptor and queue continuation information from each migration record along the edge acceptor chain. Taking migration record 1 as an example, the status transfer module reads the address acceptor... The system obtains the logical address 11 before reconstruction and the logical address 22 after reconstruction, and reads the switching flag MB, the first node QB1 of the reconstructed segment, the generation number 0 of the previous segment, and the generation number 1 of the subsequent segment from the queue continuation information QB. At the edge end, the execution slot index table is retrieved using the logical address 11 before reconstruction to locate the old execution slot E11; the execution slot index table is retrieved using the logical address 22 after reconstruction to locate the new execution slot E22.

[0071] The edge allocates an active pointer entry and a standby pointer entry for the new execution slot E22. Both the active and standby pointer entries are 64-bit pointer variables, aligned to a 64-bit natural word length. The state staking module reads the page pointer of the old execution slot E11, which points to the computation state page PB. The state staking module then writes the value of this page pointer into the standby pointer entry of the new execution slot E22.

[0072] Subsequently, the state transfer module uses the processor-supported atomic storage instruction STLR to rewrite the pointer value of the active pointer entry in the new execution slot E22 to the page pointer value in the standby pointer entry through a single indivisible write operation. This indivisible write operation possesses atomicity and memory ordering semantics, ensuring that the update of the active pointer entry is visible to all processor cores, and that no subsequent read operation of the active pointer entry will access an intermediate state before this write operation is complete. This indivisible write operation marks the effective boundary for the new execution slot E22 to begin referencing the computational state page PB.

[0073] After the indivisible write operation is completed, the status transfer module rewrites the page pointer of the old execution slot E11 into a transfer pointer. The transfer pointer stores the address of the new execution slot E22. The purpose of the transfer pointer is that, while the old execution slot E11 is still being released, if a task retrieves the old execution slot E11 through the pre-reconstruction logical address 11, it can further locate the new execution slot E22 through the transfer pointer, thereby obtaining the computation status page PB.

[0074] The execution slots are task-bound items accessed serially by the edge scheduler, rather than two independent concurrent threads. Therefore, page pointer hopping does not require copying all state data in the compute state page (PB). The serial access is used to limit the update order of task-bound items, and does not exclude different processor cores reading active pointer items. The indivisible write operation is used to limit the effective boundaries of page pointer reference relationships. The compute state page (PB) itself remains in its original memory location; only the page pointer reference relationships of the execution slots change. This avoids the copying and relocation of large amounts of state data, significantly reducing memory access overhead.

[0075] Before the active pointer entry of the new execution slot E22 takes effect, the vehicle data frames written to the reconstructed post-stage QB1 remain in the acquisition queue, and processing based on the new execution slot E22 is not initiated. This is because the processing cursor in the computation status page PB has not yet completed the processing of the reconstructed pre-stage. If processing were to start from the reconstructed post-stage prematurely, the unprocessed vehicle data frames in the reconstructed pre-stage would be skipped.

[0076] Vehicle-mounted node A and vehicle-mounted node C perform the same state transfer process according to their respective address inheritors. The computational state page PA of vehicle-mounted node A is transferred from the old execution slot E10 to the new execution slot E21, and the computational state page PC of vehicle-mounted node C is transferred from the old execution slot E12 to the new execution slot E23.

[0077] Step S6: Position the processing cursor of the calculation status page to the unprocessed position of the reconstruction front section, continue the reconstruction back section through the queue successor pointer of the switching mark, process the vehicle data frame along the continuation of the acquisition queue, and release the old execution slot.

[0078] After the state transition is complete, the cross-segment continuation module reads the last processing position saved in the computational state page PB. The last processing position records the queue node references, intra-node offsets, and queue generation numbers that the processing cursor has processed before the reconstruction event occurred. The cross-segment continuation module reads the end positions of each queue node in the reconstruction phase and positions the processing cursor to the queue node reference and intra-node offset corresponding to the first unprocessed position in the reconstruction phase.

[0079] In this embodiment, it is assumed that when the grouping reconfiguration occurs, the processing cursor of the computation state page PB has already processed the queue nodes. and The current queue node QB0 is being processed before the closure. The end position of QB0 is byte 500 within this node, and the last processing position is byte 320 within QB0. The cross-segment continuation module writes the queue node reference of the processed cursor to the address of QB0, writes the offset within the processed cursor node to the first frame header position after byte 320, and keeps the queue generation number carried by the processed cursor at the previous segment generation number 0.

[0080] In step S2, the successor pointer of the queue marked MB has already pointed to the first node QB1 of the reconstructed segment. The cross-segment continuation module confirms the successor pointer of the queue, verifying that QB1 is a valid queue node and that the queue generation number is the generation number 1 of the segment.

[0081] After the active pointer entry of the new execution slot E22 takes effect, the cross-segment continuation module drives the computation status page PB to begin processing from the unprocessed position pointed to by the processing cursor. The processing cursor first starts processing from the first unprocessed frame corresponding to the offset within the node in QB0, until it reaches the end position of the node in QB0. After the data in QB0 is processed, the processing cursor obtains the switching mark MB along the queue successor pointer of QB0. The switching mark MB is located between the pre-reconstruction segment and the post-reconstruction segment.

[0082] When the processing cursor reads the switching marker MB, the cross-segment continuation module performs the following operations: reads the subsequent generation number 1 from the switching marker MB, updates the queue generation number carried by the processing cursor from the previous generation number 0 to the subsequent generation number 1; reads the queue successor pointer of the switching marker MB, which points to the reconstructed subsequent segment first node QB1, writes this pointer value into the queue node reference part of the processing cursor, and sets the node offset of the processing cursor to the position of the first unprocessed frame in QB1. The processing cursor thus crosses the switching marker MB and enters the reconstructed subsequent segment first node QB1.

[0083] like Figure 4 As shown, during the state transition process, the edge terminal locates the old execution slot E11 and the new execution slot E22 based on address inheriting entries "11 to 22," where the page pointer of the old execution slot E11 points to the computation state page PB. The state transition module reads the page pointer value from the old execution slot E11 and writes it into the spare pointer entry of the new execution slot E22. Subsequently, through an STLR atomic storage operation, the active pointer entry of the new execution slot E22 is updated to this page pointer value, causing the new execution slot E22 to begin referencing the computation state page PB. This process does not copy the computation state page PB itself; it only changes the reference relationship between the execution slot and the computation state page. After the above update is completed, the page pointer of the old execution slot E11 is rewritten as a transition pointer, which stores the address of the new execution slot E22 so that the computation state page PB can still be located while the old execution slot E11 is still being released.

[0084] When resuming across segments, the last processing position saved in the computation status page PB still corresponds to the reconstructed previous segment. Taking QB0's node end position as byte 500 and last processing position as byte 320 as an example, the cross-segment continuation module positions the processing cursor to the first unprocessed frame after byte 320 in QB0, while maintaining the previous segment generation number 0. The processing cursor continues to process the unprocessed data frames in QB0 until it reaches the node end position of QB0; then, it reads the switching flag MB along the queue successor pointer of QB0, and reads the subsequent segment generation number 1 and the queue successor pointer pointing to QB1 from the MB, updates the queue node reference of the processing cursor to QB1, sets the node offset to the position of the first unprocessed frame in QB1, and updates the queue generation number to 1. Therefore, the data processing sequence starts from the unprocessed position in the pre-reconstruction stage, passes through the switching marker MB, and continuously enters the first node QB1 of the post-reconstruction stage. After the cursor enters the post-reconstruction stage and there are no active read tasks in the old execution slot E11, the transfer pointer in E11 is cleared and the old execution slot is released.

[0085] After the processing cursor enters the reconstruction phase, it continues to acquire vehicle data frames sequentially and execute data processing algorithms according to the queue successor pointers of each queue node in the reconstruction phase. Since the queue generation number in the reconstruction phase is 1, which is consistent with the queue generation number updated by the processing cursor, the processing cursor can normally traverse each queue node in the reconstruction phase.

[0086] After the cursor has entered the reconstructed segment QB1 and there are no active read tasks in the old execution slot E11, the cross-segment continuation module clears the transfer pointer in the old execution slot E11, restores the page pointer field of the old execution slot E11 to an invalid value or a null pointer, and terminates the transfer relationship between logical address 11 and the new execution slot E22 before reconstruction. Subsequently, the cross-segment continuation module releases the old execution slot E11, marks E11 as reclaimable, and the edge resource manager can reallocate the execution slot for other logical addresses.

[0087] Simultaneously, the cross-segment continuation module reclaims queue nodes that were located before the processing cursor and had already been processed, starting from the beginning of the reconstructed front-end. In this embodiment, queue nodes... and Once processing is complete and the processing cursor has moved past the current node, the memory space of these nodes is released and returned to the memory manager of the on-board node B. The current queue node QB0, after being sealed, is also reclaimed after all its content has been processed. The switching flag MB can also be released after all data has been reclaimed in the corresponding reconstruction phase, or it can be retained until the current reconstruction transaction is completed for fault tracing purposes.

[0088] Thus far, onboard data acquisition continues during the group reconstruction. The same computing state page PB at the edge continues to process onboard data frames in the order of "unprocessed position before reconstruction → switching marker → subsequent reconstruction," forming a complete data flow scheduling closed loop. The data flow scheduling process of onboard node A and onboard node C is similar to that of onboard node B, completing the cross-segment continuation of computing state pages PA and PC, respectively.

[0089] Example 2: This embodiment, based on Embodiment 1, further illustrates the specific calculation process of the transfer chain migration and edge reconstruction.

[0090] The starting address of the contiguous linked buffer allocated at the edge (In hexadecimal representation), the length L of a single record slot is determined according to the migration record field length and alignment requirements. In this embodiment, queue continuation information is stored using a compressed reference field, and L is 64 bytes. The edge receives three migration records with chain numbers 0, 1, and 2.

[0091] Based on the slot address calculation formula The slot addresses for each migration record are: Migration record 0: ; Migration record 1: ; Migration record 2: .

[0092] The edge writes migration record 0 to the address. Write migration record 1 to address Write migration record 2 to address .

[0093] For migration record 1 with chain number 1, the edge performs the following calculations: 1. The chain number i of the current migration record is 1, and the slot address is... 2. Predecessor serial number offset The chain number of the predecessor migration record 3. According to Front drive slot address 4. Successor sequence number offset The chain number of the subsequent migration record 5. According to Subsequent slot address 6. Set the front drive slot address Write the local token predecessor pointer field to migration record 1. 7. Set the successor slot address. Write the local token successor pointer field to migration record 1. 8. Retain the queue continuation information QB in migration record 1, which includes the switching flag MB, the reconstructed back-end first node QB1, the front-end generation number 0, and the back-end generation number 1.

[0094] Similarly, for migration record 0: Chain number i=0, slot address ; The predecessor sequence number offset is invalid (no predecessor at the primary level), and the local token predecessor pointer is written as... (Null pointer); Successor sequence number offset Successor chain number Subsequent slot address ; The local token successor pointer is written as ; The queue continuation information QA retains the switching flag MA reference, the reconstructed first node reference, the previous generation number, and the next generation number.

[0095] For migration record 2: Chain number i=2, slot address ; Pre-drive serial number offset Precursor chain number Front drive slot address ; The local token predecessor pointer is written as ; The successor sequence number offset is invalid (no successor at the last level), and the local token successor pointer is written as... (Null pointer); The queue continuation information QC retains the switching flag MC reference, the reconstructed first node reference, the previous generation number, and the next generation number.

[0096] After completing the above calculations, the edge connection chain forms the following local pointer connection relationship: Migration record 0 (address) ): Previous pointer = NULL, successor pointer = Save queue continuation information (QA); Migration record 1 (address) ): Predecessor pointer = Successor pointer = Save the queue continuation information QB; Migration record 2 (address) ): Predecessor pointer = The successor pointer is NULL, which stores the queue continuation information (QC).

[0097] Status transfer module from address Initially, each migration record is traversed sequentially through the local token successor pointer, and the address acceptance item and queue continuation information are read. The transfer operation of the calculation status pages PA, PB and PC are executed respectively, and the corresponding switching mark reference and reconstruction back segment first node reference are provided for subsequent cursor cross-segment continuation.

[0098] Example 3: This embodiment illustrates the boundary case handling when the group contains only one domestically produced SoC industrial computer.

[0099] Assume the train formation only contains onboard node A, with a logical address of 10 before formation reconfiguration and 21 after reconfiguration. During formation reconfiguration, onboard node A executes steps S1 to S2, inserting a switching flag MA into the acquisition queue, thus forming the pre-reconfiguration segment and the post-reconfiguration segment.

[0100] Vehicle-mounted node A writes the address acceptor in the handover flag MA. Since the vehicle-mounted node A is both the first and last physical connection in the chain, it generates a first-level address accepting token TA. The token predecessor and successor pointers for token TA are both set to null. Because there are no adjacent subsequent addresses accepting tokens, the vehicle-mounted node A sets the return pointer in the switching flag MA to null, forming an accepting chain containing only one token and one switching flag.

[0101] The chain migration procedure assigns chain number 0 to the token TA and generates a migration record, which includes the address carry-over field " The migration record is continuation information and the predecessor and successor sequence number offsets of the migration record are invalid. The edge allocates a continuous chain buffer with a starting address of B and a length of 1×L, and writes the migration record to address B. The edge writes the local token predecessor pointer and local token successor pointer of the migration record to null pointers, forming an edge continuation chain containing only one migration record.

[0102] The status transfer module reads the address inheritance item from the migration record. The queue continuation information is used to transfer the computation status page PA from the old execution slot E10 to the new execution slot E21. The cross-segment continuation module drives the processing cursor from the unprocessed position of the reconstruction front segment to the reconstruction back segment by switching the queue successor pointer marked MA, thus completing the data flow scheduling.

[0103] This embodiment demonstrates that even if the group contains only one domestically produced SoC industrial computer, the method of the present invention can still perform state transfer and cross-segment continuation.

[0104] Example 4: This embodiment illustrates the protection mechanism when the transfer of the receiving chain is not yet complete.

[0105] After step S4 is completed but before the relay migration is completed in step S5, the write pointer on the vehicle end continues to move in the later stage of reconstruction, and the processing cursor can continue to process the earlier stage of reconstruction. However, the edge end has not yet obtained the address relay relationship, cannot determine the correspondence between the logical address before reconstruction and the logical address after reconstruction, and cannot perform state transition.

[0106] To avoid prematurely entering the reconstruction phase before the address connection is available, the cross-segment continuation module checks whether the edge end has already received and rebuilt the edge connection chain when the processing cursor reaches the switching mark. If the edge connection chain is not yet ready, the cross-segment continuation module does not allow the processing cursor to cross the switching mark, but instead pauses the processing cursor at the switching mark, keeping the reconstruction phase data in the acquisition queue.

[0107] In practice, after receiving the chain image and completing the edge connection chain reconstruction, the edge end sets a connection chain ready flag. When the cross-segment continuation module processes the cursor to reach the switching mark, it checks the connection chain ready flag. If the flag is true, the cursor moves past the switching mark in step S6; if the flag is false, the cursor remains at the switching mark, waiting for the connection chain ready flag to become true before continuing.

[0108] The protection mechanism in this embodiment ensures that the processing of the front-end of the reconstruction is not interrupted due to the delay in the transfer chain, and at the same time avoids data flow processing chaos caused by entering the back-end of the reconstruction before the state transition is completed.

[0109] Example 5: This example illustrates the exception handling when the chain sequence number is not consecutive or the address is out of bounds.

[0110] After receiving the chain image, the edge device checks the continuity of the chain numbers for each migration record. If a discontinuity in the chain numbers is found, such as receiving chain numbers 0, 1, and 3 but missing chain number 2, or if the predecessor or successor chain number calculated based on the chain number offset exceeds the range of the actually received chain numbers, then the chain image is determined to be incomplete or corrupted.

[0111] When the edge device detects a discontinuous chain sequence number or a slot address calculated based on the sequence number offset that exceeds the range of the continuous chain buffer, it suspends the corresponding calculation status page transfer operation. The edge device sends a chain image retransmission request to the vehicle-mounted terminal, requesting the vehicle-mounted terminal to regenerate and transmit the chain image. After receiving the retransmission request, the vehicle-mounted terminal retraces the inherited chain, generates the chain image, and transmits it to the edge device.

[0112] During chain image retransmission, the reconstructed backend data remains in the acquisition queue, and the processing cursor remains at the switching marker. Once the edge receives a complete and valid chain image, it re-executes the takeover chain reconstruction and state transition operations, and then continues with step S6.

[0113] The exception handling mechanism in this embodiment ensures that the system can recover through retransmission when data is lost or damaged during chain image transmission, thus avoiding state transition failure due to chain image errors.

[0114] Example 6: This example illustrates the case where the reconstruction process has been completed before the state transition.

[0115] Assuming that during the group reconfiguration, the processing cursor of the computational state page PB of the vehicle-side node B has already processed all queue nodes in the pre-reconfiguration phase, and the processing cursor reaches the end position of the current queue node QB0 after closure. After inserting the switching flag MB in step S2, the queue node reference of the processing cursor still points to QB0, with the node offset being the end position of QB0.

[0116] After the active pointer entry of the new execution slot E22 in step S5 takes effect, the cross-segment continuation module determines that the intra-node offset of the processing cursor has reached the end position of the node in QB0, and therefore reads the switching flag MB along the queue successor pointer of QB0. Since the reconstruction front-end has been completed, the processing cursor does not need to process the vehicle data frames in the reconstruction front-end. The cross-segment continuation module reads the queue successor pointer of the switching flag MB, which points to the first node QB1 of the reconstruction back-end, writes the queue node reference of the processing cursor to the address of QB1, sets the intra-node offset to the position of the first frame to be processed in QB1, and updates the queue generation number carried by the processing cursor to the back-end generation number 1. The processing cursor then directly enters the reconstruction back-end and continues to process the vehicle data frames in the reconstruction back-end.

[0117] This embodiment shows that the method of the present invention can adapt to different situations of the progress of the pre-reconstruction processing; even if the pre-reconstruction process has been completed before the state transition, the processing cursor can still enter the post-reconstruction process by switching the marker.

[0118] Example 7: This embodiment provides an edge-to-edge collaborative data flow scheduling system based on a domestically produced SoC industrial computer, such as... Figure 5 As shown, it includes the vehicle-mounted end and the edge end.

[0119] The onboard unit comprises onboard node A, onboard node B, and onboard node C, which are connected in a physical coupling order. All three onboard nodes utilize domestically produced SoC industrial computers. These domestically produced SoC industrial computers can employ domestically produced processor platforms based on ARMv8 or RISC-V instruction sets, featuring processor cores, memory controllers, network interfaces, and atomic memory instruction support. The three onboard nodes are connected via the train's Ethernet backbone network, which can adopt the Gigabit Ethernet standard and support broadcast, multicast, and unicast communication methods.

[0120] The edge terminal is an edge server located in the driver's cab. The edge server communicates with each onboard node via the train's Ethernet backbone. The edge server uses an x86 or ARM architecture processor, with multi-core processing capabilities and sufficient memory capacity for allocating contiguous linked buffers and computing status pages.

[0121] The vehicle-mounted terminal includes a data acquisition module, a queue segmentation module, an address forwarding module, and an address backhaul module. These four modules run in software on domestically produced SoC industrial computers, and communicate with each other through local function calls or message queues.

[0122] The data acquisition module establishes an acquisition queue via a domestically produced SoC industrial computer on the vehicle, and writes vehicle data frames into the acquisition queue. The data acquisition module receives vehicle data frames from the vehicle network interface, which includes a CAN bus interface, an MVB interface, and an Ethernet interface, for accessing operational data, status data, and diagnostic data generated by the vehicle equipment. The data acquisition module writes the received vehicle data frames into the current queue node of the acquisition queue in the order of arrival, maintains a write pointer, and allocates a new queue node when the current queue node is full.

[0123] The queue segmentation module is used to seal the current queue node when the train network initiates a train formation reconfiguration, insert a switching marker after the current queue node, and continue writing from the switching marker to form a pre-reconfiguration segment and a post-reconfiguration segment. The queue segmentation module receives a reconfiguration event sent by the train network management unit, reads the write pointer of the acquisition queue, determines the queue node pointed to by the write pointer as the current queue node, fixes the node's end position and writes a sealing identifier, generates a switching marker and establishes queue connection relationships, allocates the first node of the post-reconfiguration segment, switches the write pointer, and updates the queue generation number.

[0124] The address fronthaul module is used to pass address acceptance tokens level by level according to the physical connection order, and writes the acceptance relationship from the pre-reconstruction logical address to the post-reconstruction logical address into the corresponding switching flag. The address fronthaul module reads the pre-reconstruction logical address and the post-reconstruction logical address from the local network configuration area, writes the address acceptance item into the switching flag, generates an address acceptance token and writes it into the flag reference item, and transmits the front-level token message and the subsequent confirmation message containing the token addressable reference through the train Ethernet backbone. It receives the front-level token message and establishes the connection between the token predecessor pointer and the token successor pointer.

[0125] The address backhaul module is used to reverse the address acceptance token from the end of the physical connection sequence, writing the backhaul pointer to the corresponding switching flag to form an acceptance chain. After generating the last-level token at the end of the physical connection sequence, the address backhaul module reverses the token's predecessor pointer, passing back a message containing the token's addressable reference. During the reverse transmission, the backhaul pointer of the current switching flag is written as the addressable reference of the adjacent subsequent address acceptance token, until the first-level token. The address backhaul module also includes a chain migration function, used to traverse the acceptance chain and assign a chain sequence number to each token, convert the token pointer to a sequence number offset, generate queue continuation information based on the token's tag reference item and the corresponding switching flag field, generate a chain image, and transmit it to the edge end through the train Ethernet backbone.

[0126] The edge component includes a status transfer module and a cross-segment continuation module. These two modules run as software on the edge server, and communicate with each other through local function calls.

[0127] The state transfer module is used to transfer the computation state page of the pre-reconstruction logical address index from the old execution slot to the new execution slot of the post-reconstruction logical address index at the edge end, based on the aforementioned transfer chain. The state transfer module receives the chain image transmitted from the vehicle-mounted terminal, allocates a continuous chain buffer, writes each migration record according to the chain sequence number, and reconstructs the local token predecessor pointer and local token successor pointer based on the sequence number offset, forming the edge transfer chain. The state transfer module reads the address transfer item and queue continuation information along the edge transfer chain, locates the old execution slot, the new execution slot, the switching flag reference, and the reconstructed post-segment first node reference. It sets an active pointer item and a spare pointer item in the new execution slot, writes the page pointer of the old execution slot into the spare pointer item, rewrites the active pointer item to the page pointer in the spare pointer item through an indivisible write operation, and then rewrites the page pointer of the old execution slot into a transfer pointer.

[0128] The cross-segment continuation module is used to position the processing cursor of the computing status page to the unprocessed position of the reconstruction front segment, continue the reconstruction back segment through the queue successor pointer of the switching mark, process the vehicle data frame along the continuation acquisition queue, and release the old execution slot. The cross-segment continuation module reads the last processing position in the computing status page, positions the processing cursor to the queue node reference and node offset corresponding to the first unprocessed position of the reconstruction front segment, drives the processing cursor to traverse each queue node of the reconstruction front segment in sequence, reads the queue successor pointer and updates the queue generation number when the processing cursor reaches the switching mark, so that the processing cursor enters the reconstruction back segment, and after the processing cursor enters the reconstruction back segment and there are no active reading tasks in the old execution slot, clears the switching pointer in the old execution slot and releases the old execution slot, and reclaims the queue nodes that have been processed in the reconstruction front segment.

[0129] The edge-to-edge collaborative data flow scheduling system in this embodiment forms acquisition queue segments, address succession chains, and chain images during group reconstruction through the collaborative work of various modules on the vehicle end; and completes succession chain reconstruction, computation status page transfer, and cross-segment continuation of processing cursors through the collaborative work of various modules on the edge end, so as to realize the continuous succession of data flow, computation status, and processing position before and after reconstruction.

[0130] The foregoing has provided a detailed description of the edge-to-edge collaborative data flow scheduling method and system based on a domestically produced SoC industrial computer provided by this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A method for edge-device collaborative data flow scheduling based on a domestically produced SoC industrial computer, characterized in that, include: A data acquisition queue is established using a domestically produced SoC industrial computer on the vehicle, and vehicle data frames are written into the acquisition queue. When the train network initiates train formation reconfiguration, the current queue node is sealed, a switching marker is inserted after the current queue node, and writing continues from after the switching marker to form the reconfiguration front segment and the reconfiguration back segment. The address acceptance token is passed level by level according to the physical connection order, and the acceptance relationship from the logical address before reconstruction to the logical address after reconstruction is written into the corresponding switching flag. The address acceptance token is passed backward from the end of the physical connection sequence, and the return pointer is written to the corresponding switching flag to form an acceptance chain; Based on the aforementioned connection chain, at the edge end, the computation state page of the pre-reconstruction logical address index is transferred from the old execution slot to the new execution slot of the post-reconstruction logical address index; Position the processing cursor of the computing status page to the unprocessed position of the reconstruction front section, continue the reconstruction back section through the queue successor pointer of the switching mark, process the vehicle data frame along the continuation of the acquisition queue, and release the old execution slot.

2. The edge-to-edge collaborative data flow scheduling method based on a domestically produced SoC industrial computer according to claim 1, characterized in that, Address acceptance tokens are passed level by level according to the physical connection order. The connection relationship from the pre-reconstruction logical address to the post-reconstruction logical address is written into the corresponding switching flag. The address acceptance tokens are then passed in reverse from the end of the physical connection order, and the return pointer is written into the corresponding switching flag, forming an acceptance chain, including: Read the corresponding pre-reconstruction logical address and post-reconstruction logical address from the domestically produced SoC industrial computers, and write the pre-reconstruction logical address and post-reconstruction logical address into the corresponding front address entry and back address entry of the switching flag respectively to form an address inheritance entry; A first-level address acceptance token is generated based on the switching flag corresponding to the domestic SoC industrial computer located at the first end of the physical connection sequence. The storage address of the corresponding switching flag is written into the flag reference item of the first-level address acceptance token, and the first-level address acceptance token is passed to the subsequent domestic SoC industrial computer. After the subsequent domestically produced SoC industrial computer receives the previous address acceptance token, it generates a subsequent address acceptance token according to the corresponding switching flag, writes the storage address of the corresponding switching flag into the flag reference item of the subsequent address acceptance token, points the token predecessor pointer of the subsequent address acceptance token to the previous address acceptance token, and points the token successor pointer of the previous address acceptance token to the subsequent address acceptance token. Starting from the end of the physical linking sequence, the last generated subsequent address accepting token is passed backward along the token predecessor pointer. During the backward passing process, the return pointer of the current switching mark is written as an addressable reference of the adjacent subsequent address accepting token, and the return pointer of the switching mark corresponding to the last level is written as a null pointer, until the first address accepting token is obtained, thus forming the accepting chain.

3. The edge-to-edge collaborative data flow scheduling method based on a domestically produced SoC industrial computer according to claim 2, characterized in that, According to the aforementioned connection chain, at the edge end, the computational state page of the pre-reconstruction logical address index is transferred from the old execution slot to the new execution slot of the post-reconstruction logical address index, and the processing cursor of the computational state page is positioned at the unprocessed position of the pre-reconstruction segment. The post-reconstruction segment is continued through the queue successor pointer of the switching marker, and the vehicle data frame is processed along the continued acquisition queue. The old execution slot is then released. This includes: Read the pre-reconstruction logical address and post-reconstruction logical address associated with the same switching flag along the succession chain, and locate the old execution slot, the new execution slot, and the switching flag; Read the page pointer in the old execution slot that points to the computing state page, rewrite the page pointer of the new execution slot to point to the computing state page, and rewrite the page pointer of the old execution slot to point to the transfer pointer of the new execution slot; Write the processing cursor as the queue node reference and node offset corresponding to the first unprocessed position in the reconstruction front section, and confirm that the queue successor pointer of the switching mark points to the first node address of the reconstruction back section; The processing cursor is driven to traverse the pre-reconstruction phase and the post-reconstruction phase in sequence. After the processing cursor enters the post-reconstruction phase, the transfer pointer is cleared and the old execution slot is released.

4. The edge-to-edge collaborative data flow scheduling method based on a domestically produced SoC industrial computer according to claim 3, characterized in that, Reading the page pointer in the old execution slot that points to the computation state page, rewriting the page pointer of the new execution slot to point to the computation state page, and rewriting the page pointer of the old execution slot to point to the transfer pointer of the new execution slot, includes: An active pointer entry and a spare pointer entry are set in the new execution slot; Read the page pointer of the old execution slot and write the read page pointer into the spare pointer entry; Through a single indivisible write operation, the pointer value of the active pointer entry is rewritten to the page pointer in the spare pointer entry; After the indivisible write operation is completed, the page pointer of the old execution slot is rewritten to the transfer pointer containing the address of the new execution slot.

5. The edge-to-edge collaborative data flow scheduling method based on a domestically produced SoC industrial computer according to claim 4, characterized in that, The process cursor is driven to traverse the pre-reconstruction phase and the post-reconstruction phase sequentially. After the process cursor enters the post-reconstruction phase, the transfer pointer is cleared and the old execution slot is released, including: Before the pointer value of the active pointer entry is rewritten to the page pointer in the spare pointer entry, the vehicle data frame to be written to the reconstructed stage is kept in the acquisition queue; After the pointer value of the active pointer entry is rewritten to the page pointer in the spare pointer entry, the computation state page is driven to start processing from the unprocessed position pointed to by the processing cursor; When the processing cursor crosses the switching mark, the queue successor pointer of the switching mark is written into the queue node reference portion of the processing cursor; After the processing cursor enters the reconstructing phase, the transfer pointer in the old execution slot is cleared, the old execution slot is released, and the queue nodes that have been processed in the reconstructing phase are reclaimed.

6. The edge-to-edge collaborative data flow scheduling method based on a domestically produced SoC industrial computer according to claim 1, characterized in that, When the train network initiates train formation reconfiguration, the current queue node is sealed, a switching marker is inserted after the current queue node, and writing continues from the switching marker, forming the pre-reconfiguration segment and the post-reconfiguration segment, including: Read the write pointer of the acquisition queue and take the queue node pointed to by the write pointer as the current queue node; The current write position of the current queue node is fixed as the node end position, a sealing identifier is written into the current queue node, and the writing of the vehicle data frame to the current queue node is stopped. Generate the switching flag, point the queue successor pointer of the current queue node to the switching flag, and point the queue predecessor pointer of the switching flag to the current queue node; Assign the first node of the reconstructed segment, point the queue successor pointer of the switching mark to the first node, and point the queue predecessor pointer of the first node to the switching mark; Switch the write pointer of the acquisition queue from the current queue node to the first node.

7. The edge-to-edge collaborative data flow scheduling method based on a domestically produced SoC industrial computer according to claim 6, characterized in that, Switching the write pointer of the acquisition queue from the current queue node to the head node includes: Assign a front-end generation number to the current queue node, and write the front-end generation number to the current queue node and the switching flag; Generate a subsequent generation number based on the preceding generation number, and write the subsequent generation number into the switching flag and the first node; Switch the write pointer to the first node, update the queue generation number carried by the write pointer to the later generation number, and keep the queue generation number carried by the processing cursor as the earlier generation number. After the processing cursor reads the switching flag, the queue generation number carried by the processing cursor is updated to the subsequent generation number, and the processing cursor is driven to enter the reconstructed subsequent stage through the queue successor pointer.

8. The edge-to-edge collaborative data flow scheduling method based on a domestically produced SoC industrial computer according to claim 2, characterized in that, After the receiving chain is formed, migrating the receiving chain to the edge end includes: According to the arrangement order of the first-level address accepting token to the last generated subsequent address accepting token in the accepting chain, the accepting tokens at each level are traversed, and the corresponding chain number is written for each level of address accepting token. Based on the tag references of the address acceptance tokens at each level and the address acceptance items, queue successor pointers, front generation numbers, and back generation numbers in the corresponding switching tags, queue continuation information is generated. The chain sequence number, the address acceptance items, the queue continuation information, the token predecessor pointer, and the token successor pointer are encapsulated into a migration record. The queue continuation information includes a switching tag reference, a reconstructed back-end first node reference, a front generation number, and a back generation number. Based on the difference in chain sequence number between two adjacent migration records, the token predecessor pointer and the token successor pointer in each migration record are rewritten as predecessor sequence number offset and successor sequence number offset, respectively, to form a chain map; The chain image is transmitted to the edge end, a continuous chain buffer consisting of equal-length record slots is allocated at the edge end, and each migration record is written into the corresponding record slot according to the chain sequence number. Based on the starting address of the continuous chain buffer and the predecessor sequence number offset and the successor sequence number offset in each migration record, the local token predecessor pointer and local token successor pointer between each migration record are reconstructed to form an edge-connecting chain.

9. The edge-to-edge collaborative data flow scheduling method based on a domestically produced SoC industrial computer according to claim 8, characterized in that, Based on the starting address of the continuous chain buffer and the predecessor and successor sequence number offsets in each migration record, the local token predecessor and successor pointers between each migration record are reconstructed to form an edge-connecting chain, including: Based on the starting address of the continuous chain buffer, the length of the record slot, and the chain number of each migration record, the slot address of each migration record is obtained sequentially. Add the chain number of the current migration record to the predecessor chain number offset and the successor chain number offset respectively to obtain the chain number of the predecessor migration record and the chain number of the successor migration record. The chain number of the predecessor migration record and the chain number of the successor migration record are converted into corresponding slot addresses, and the two converted slot addresses are written into the local token predecessor pointer and local token successor pointer of the current migration record, respectively. Write the local token predecessor pointer corresponding to the first-level address accepting token to a null pointer, and write the local token successor pointer corresponding to the last generated subsequent address accepting token to a null pointer, thus forming the edge accepting chain.

10. An edge-to-edge collaborative data flow scheduling system based on a domestically produced SoC industrial computer, characterized in that, include: The vehicle-mounted terminal and the edge terminal that are communicatively connected to the vehicle-mounted terminal, wherein the vehicle-mounted terminal includes at least two domestically produced SoC industrial computers that are communicatively connected in a physical connection order; The vehicle-mounted terminal includes a data acquisition module, a queue segmentation module, an address forward transmission module, and an address back transmission module; the edge terminal includes a status switching module and a cross-segment continuation module. The data acquisition module is used to establish an acquisition queue through the domestically produced SoC industrial computer on the vehicle side and write the vehicle data frame into the acquisition queue. The queue segmentation module is used to seal the current queue node when the train network starts regrouping and reconfiguring, insert a switching marker after the current queue node, and continue writing from the switching marker to form the reconfiguration front segment and the reconfiguration back segment. The address forwarding module is used to pass the address acceptance token step by step according to the physical connection order, and write the acceptance relationship from the logical address before reconstruction to the logical address after reconstruction into the corresponding switching flag. The address backhaul module is used to transmit the address acceptance token in reverse from the end of the physical connection sequence, write the backhaul pointer to the corresponding switching flag, and form an acceptance chain. The state transfer module is used to transfer the computation state page of the pre-reconstruction logical address index from the old execution slot to the new execution slot of the post-reconstruction logical address index at the edge end, according to the receiving chain. The cross-segment continuation module is used to position the processing cursor of the calculation status page to the unprocessed position of the reconstruction front segment, continue the reconstruction back segment through the queue successor pointer of the switching mark, process the vehicle data frame along the continuation acquisition queue, and release the old execution slot.

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