A microcontroller chip processing method based on internet of things hardware

Abstract

The application discloses a microcontroller chip processing method based on Internet of Things hardware, and relates to the technical field of microcontroller chip design, which continuously monitors the voltage change trend of an energy storage capacitor through a hardware circuit, generates a hibernation signal before the voltage breaks through a maintenance threshold voltage, a processor decoding stage identifies semantic boundary instructions in a calculation flow and marks an atomic barrier label, a frozen control logic controls a flow pipeline to continue to execute to an instruction corresponding to the label to complete write back after receiving the hibernation signal, and then gradually closes the clock, and a snapshot write control logic writes the values of key registers into a non-volatile storage circuit in parallel, and the values are restored in parallel after power-on and continue to be executed, so that the microcontroller can be used for breakpoint continuation calculation in an intermittent power supply scene, and the task can be completed without being interrupted by repeated power-off.

Description

Technical Field

[0001] This invention relates to the field of microcontroller chip design technology, specifically to a microcontroller chip processing method based on Internet of Things (IoT) hardware. Background Technology

[0002] Environmental micro-energy harvesting devices are widely used in IoT edge nodes to power microcontrollers. Because these devices have weak output current and are used in conjunction with small-capacity energy storage capacitors, the microcontroller needs to accumulate power over a long period of time to obtain enough power to support a short calculation, thus forming an intermittent calculation operation mode.

[0003] The closest prior art to this invention employs a pure software checkpoint mechanism: the software periodically samples the power supply voltage through the analog-to-digital converter and compares it with a preset threshold. When the sampled value is lower than the threshold, a software interrupt service routine is triggered, and the key variables, register group contents and program counter value in the SRAM are written to the on-chip Flash memory via the system bus. After power is restored, the boot program reads the state data stored in the Flash and restores the operating environment.

[0004] The aforementioned existing technologies have the following shortcomings: the software sampling cycle is limited by the millisecond-level scheduling granularity, and there is not enough time to complete sampling and judgment when the voltage drops sharply, resulting in the backup process failing to start;

[0005] Flash writing requires a high programming voltage and a large transient current. Performing a write operation when the voltage is low will further lower the residual voltage, causing the backup process itself to be interrupted.

[0006] The existing clock gating mechanism does not recognize the semantic stage of the pipeline currently being executed. When the voltage drops suddenly, the pipeline may be forcibly interrupted in the middle of the operation. After recovery, the data is incomplete and inconsistent, and it can only be recalculated from the beginning of the task, which means there is room for improvement. Summary of the Invention

[0007] The technical problem to be solved by this invention is that in the existing software checkpointing scheme for intermittent calculation, the voltage sampling response lags behind the voltage drop rate, resulting in the backup process not having enough time to start.

[0008] Backup operations rely on high-power Flash writing, which will further consume the already insufficient remaining power.

[0009] Furthermore, existing clock gating mechanisms lack computational semantic awareness capabilities, and the frozen moment may be in an intermediate state of computation, resulting in incomplete and inconsistent data after recovery. To solve the above problems, this invention provides a microcontroller chip processing method based on Internet of Things hardware.

[0010] The technical solution of the present invention is as follows: continuously collect the voltage value across the energy storage capacitor of the microcontroller, and generate a sleep signal before the voltage drops below the maintenance threshold voltage based on the voltage's decreasing trend;

[0011] The decoding stage of the processor core pipeline identifies semantic boundary instructions in the computation flow based on predefined instruction characteristics and marks atomic barrier tags in the pipeline control word of the corresponding instruction;

[0012] Upon receiving the impending hibernation signal, the pipeline freeze control logic does not immediately interrupt the pipeline. Instead, it controls the pipeline to continue executing at its original pace until it detects that an instruction carrying the atomic barrier tag has completed a write-back operation at the write-back stage. At this point, it sends a freeze confirmation signal to the clock gating controller.

[0013] After receiving the freeze confirmation signal, the clock gating controller disables the corresponding clock enable signals in the order of instruction fetch stage, decode stage, execution stage, memory access stage, and write-back stage, so that the pipeline completely stops stepping at the instruction corresponding to the atomic barrier tag.

[0014] After detecting the freeze confirmation signal, the snapshot write control logic writes the current values ​​in the processor core's general-purpose register file, program counter, status register, and atomic barrier tag register into the non-volatile memory circuit in parallel. After the write is completed, it sends a snapshot completion signal back to the power management unit, which then allows the microcontroller's main power supply voltage to continue to drop until power is cut off.

[0015] When the ambient energy accumulates again, the microcontroller is powered on again, and the voltage stabilizes, a recovery enable signal is generated, which drives the non-volatile storage circuit to write the stored value back to the corresponding register in parallel. After the write-back is completed, pipeline control is returned to the instruction pointed to by the program counter, and the pipeline continues to execute from that instruction.

[0016] Compared with the prior art, the beneficial effects of the present invention by adopting the above technical solution are as follows:

[0017] 1. This invention generates an imminent sleep signal directly based on the voltage drop trend through hardware circuitry, reducing the energy sensing response time from milliseconds to nanoseconds, thus avoiding the backup process failing to start due to response lag;

[0018] 2. This invention uses a non-volatile storage circuit tightly coupled to the register to achieve parallel snapshot writing, reducing the power consumption of breakpoint saving from the peak power consumption of milliamperes to the picojoule level, and avoiding the consumption of residual power during the backup process itself;

[0019] 3. This invention ensures that the freeze point is located at the boundary of computational semantic integrity through atomic barrier tags, so that the restored register data has complete consistency and avoids the task from being recalculated from the starting point;

[0020] 4. The recovery process of this invention is directly written back to the register in reverse parallel by the hardware circuit, without the need to load and run the software boot program, so that the recovery delay is compressed to the microsecond level, thereby enabling large computing tasks that span multiple charge and discharge cycles to be completed cumulatively. Attached Figure Description

[0021] Figure 1 This is a flowchart illustrating the hardware voltage tracking and early warning triggering process in an embodiment of the present invention;

[0022] Figure 2 This is a flowchart of the task semantic boundary freezing process in an embodiment of the present invention;

[0023] Figure 3 This is a flowchart of the overall processing of the three modules in an embodiment of the present invention. Detailed Implementation

[0024] The following is in conjunction with the appendix Figure 1-3 The specific embodiments of the present invention will be further described below. It should be noted that the description of these embodiments is for the purpose of helping to understand the present invention, but does not constitute a limitation of the present invention.

[0025] To make the technical solution and advantages of the present invention clearer, the present invention will be further described in detail below with reference to embodiments. It should be noted that the following embodiments are only used to explain the present invention and are not intended to limit the scope of protection of the present invention.

[0026] I. Overall Architecture

[0027] The microcontroller chip provided in this embodiment includes an ambient energy harvesting interface, an energy storage capacitor, a power management unit, a processor core pipeline, a clock tree and clock gating controller, a critical register group, non-volatile memory circuitry, an on-chip system bus, and static random access memory and flash memory connected via the on-chip system bus.

[0028] The environmental energy harvesting interface receives micro-energy inputs from the environment, such as piezoelectric, radio frequency, or solar energy, and stores the harvested energy in an energy storage capacitor. The power management unit embeds a voltage tracking state machine module to continuously monitor the voltage across the energy storage capacitor and generate an impending sleep signal before the voltage drops below the maintenance threshold voltage.

[0029] The processor core pipeline consists of a fetch stage, a decode stage, an execute stage, a memory access stage, and a write-back stage connected in sequence. The decode stage embeds atomic barrier tag generation logic to identify semantic boundary instructions in the current computation flow and tag them with atomic barrier tags. The clock tree and clock gating controller are controlled by a freeze confirmation signal output from the pipeline freeze control logic, used to sequentially disable the clock enable signals of each stage of the pipeline.

[0030] The critical register set includes a general-purpose register file, a program counter, a status register, and an atomic barrier tag register, each connected to a corresponding memory cell in the non-volatile memory circuit via an independent parallel data bypass bus. Snapshot write control logic synchronously drives the write enable pin of the aforementioned parallel data bypass bus upon the arrival of a freeze confirmation signal. A power-on recovery detection circuit generates a recovery enable signal after the voltage stabilizes, driving the non-volatile memory circuit to write the saved data back to the critical register set in reverse parallel.

[0031] The upcoming sleep signal generated by the voltage tracking state machine module is transmitted to the pipeline freeze control logic where the atomic barrier tag generation logic is located, as well as the clock tree and clock gating controller, through hardware signal lines, forming a hardware-level linkage closed loop.

[0032] II. Hardware-level low-power energy prediction module

[0033] This module consists of a low-power analog comparator array, a voltage slope digitization circuit, and an adaptive threshold judgment logic. The specific processing procedure is as follows.

[0034] First, the hardware comparator circuit samples the voltage across the energy storage capacitor at a fixed hardware sampling period. Perform continuous sampling to obtain values ​​from two consecutive samples. and The sampling period is triggered autonomously by the hardware comparator circuit and does not depend on software scheduling.

[0035] Secondly, based on the two sampled values ​​and the sampling time interval mentioned above, the digital circuit calculates the current voltage drop slope using the following formula:

[0036] ;

[0037] in, This indicates the voltage drop slope at the current moment, measured in volts per second.

[0038] and They represent the sampling times respectively. and The voltage across the energy storage capacitor measured at that time;

[0039] This indicates the time interval between two hardware samples.

[0040] Furthermore, based on the current voltage drop slope, the hardware state machine further predicts the remaining time required for the voltage to drop below the maintenance threshold voltage using the following formula:

[0041] ;

[0042] in, Indicates the predicted remaining available time;

[0043] This represents the threshold voltage, which is the voltage value required for the core logic circuit of the microcontroller to function properly.

[0044] This represents the absolute value of the voltage drop slope.

[0045] Then, to ensure that the voltage actually drops below... Prior to this, time was allocated for completing the freeze and snapshot operations. The state machine sets the adaptive warning threshold as follows:

[0046] ;

[0047] in, This indicates the warning voltage value that will trigger the sleep mode signal.

[0048] This represents the safety margin required to complete an instruction freeze and non-volatile memory circuit snapshot operation. This value is pre-calibrated based on the pipeline depth and snapshot bus bandwidth and written into a hardware register.

[0049] The adaptive threshold judgment logic will determine the current sampled voltage. and Comparison:

[0050] when Greater than If the current energy is sufficient, continue sampling for the next cycle.

[0051] when Not greater than When the system detects that the system is about to enter a low-energy state, the hardware circuit directly sets the sleep signal line and simultaneously starts a timer to record the status. The countdown, which is about to trigger the sleep signal, is synchronously transmitted in the form of a hardware level signal to the pipeline freeze control logic, clock tree and clock gating controller where the atomic barrier tag generation logic is located at the decoding level, triggering the subsequent semantic boundary freeze process. The entire process does not go through any software interrupt or operating system scheduling.

[0052] For example, if the threshold voltage is maintained Calibrated to 1.6 volts, with a safety time margin. The calibration is set to 20 microseconds. When the voltage tracking state machine measures two sampled voltages of 2.1 volts and 2.0 volts respectively, with a sampling interval of 10 microseconds, the absolute value of the voltage drop slope is calculated to be approximately 10,000 volts per second. Based on this, the calculated warning voltage value is approximately 1.8 volts.

[0053] When the capacitor voltage drops below 1.8 volts, a sleep signal is triggered. At this point, there is still a safe time margin of about 20 microseconds before the voltage actually falls below the maintenance threshold voltage, which is sufficient to complete the subsequent semantic boundary freezing and snapshot writing operations.

[0054] III. Task Semantic Boundary Awareness Instruction Microcode Freezing Module

[0055] This module adds atomic barrier tag generation logic to the decoding stage of the processor pipeline to identify the semantic boundaries of the currently executing computation flow. The specific processing procedure is as follows.

[0056] First, while decoding each instruction, the decoding level identifies whether the instruction is a semantic boundary instruction based on a predefined instruction feature table. The semantic boundary instructions include at least one of the following: loop back instruction, accumulation result write-back instruction, and cryptographic round function end flag instruction.

[0057] If a semantic boundary instruction is identified, the atomic barrier tag bit is set in the pipeline control word corresponding to that instruction.

[0058] Secondly, the pipeline freeze control logic continuously monitors the status of the signal line that is about to go into hibernation. When it detects that the signal line is about to go into hibernation is set, it enters the waiting state for freezing, but does not immediately execute the freezing action. Instead, it continues to drive the instructions to flow through each stage of the pipeline at the original rhythm.

[0059] Furthermore, the pipeline freeze control logic checks cycle by cycle whether the instruction currently being written back carries the atomic barrier tag bit while in the waiting state for freeze.

[0060] When the atomic barrier tag bit of an instruction is set and the instruction has completed the write-back operation, the pipeline freeze control logic immediately sends a freeze confirmation signal to the clock tree and clock gating controller.

[0061] Finally, after receiving the freeze confirmation signal, the clock tree and clock gating controller sequentially disable the corresponding clock enable signals at each stage—fetch stage, decode stage, execution stage, memory access stage, and write-back stage—causing the pipeline to completely stop at the atomic barrier point. Since the pipeline is frozen only after completing a full semantic unit write-back operation, there are no incomplete half-operations within the pipeline at this point, and the computational semantics are in a complete and consistent state, triggering the snapshot write process of the non-volatile memory circuitry.

[0062] For example, in the computation flow of a matrix multiply-accumulate loop, when the last accumulated result write-back instruction of the loop body completes the write-back operation, it is considered that a complete semantic unit has been completed, and the atomic barrier tag is set in the pipeline control word corresponding to the instruction.

[0063] Even if the impending sleep signal arrives in advance, the pipeline freeze control logic still allows the pipeline to continue executing the accumulation operation of the current loop body until the accumulation result write-back instruction is completed before issuing a freeze confirmation signal, thereby avoiding forced interruption in the middle of an accumulation operation.

[0064] IV. Ultra-low power breakpoint snapshot module based on non-volatile memory circuits

[0065] This module features a non-volatile memory circuit tightly coupled to the critical register group. The specific processing procedure is as follows.

[0066] First, the snapshot write control logic continuously monitors the freeze confirmation signal output by the pipeline freeze control logic. When the signal is detected to be set, the write enable terminal corresponding to each memory cell in the non-volatile memory circuit is immediately driven within the same clock cycle.

[0067] Secondly, within the same clock cycle when the write enable terminal is driven, the current values ​​in the general-purpose register file, program counter, status register, and atomic barrier tag register are simultaneously written to the corresponding memory cells in the non-volatile memory circuit through their respective independent parallel data bypass buses. This write process does not go through the arbitration of the on-chip system bus, the write latency is on the order of nanoseconds, and the write energy consumption is on the order of picojoules.

[0068] Secondly, after the snapshot is completed, the snapshot write control logic sends a snapshot completion signal to the power management unit. Based on this, the power management unit allows the main power supply voltage of the microcontroller chip to continue to drop to zero and enter a completely power-off hibernation state. At this time, the data stored in the non-volatile memory circuit is retained for a long time without being lost due to its non-volatile characteristics.

[0069] Then, when ambient energy accumulates again and the voltage of the energy storage capacitor rises back to the normal operating voltage of the chip and remains stable, the power-on recovery detection circuit detects this stable voltage state and generates a recovery enable signal.

[0070] Finally, the recovery enable signal drives the non-volatile memory circuit to write back the stored general-purpose register file values, program counter values, status register values, and atomic barrier tag values ​​to the corresponding registers in reverse parallel through the original parallel data bypass bus.

[0071] After the write-back is completed, the hardware circuit directly hands over pipeline control to the next instruction pointed to by the program counter. The pipeline then resumes execution from that instruction at the normal rhythm described in the aforementioned semantic boundary freezing method. The entire process does not load or run the software bootloader, and the recovery delay from power-on to task continuation is compressed to the microsecond level.

[0072] V. Overall Processing Flow of Three-Module Linkage

[0073] The complete closed-loop processing of this invention is as follows: environmental energy acquisition and storage, voltage tracking state machine module continuously samples and calculates voltage drop slope, determines whether the warning voltage value is reached, and outputs a sleep signal if it is reached.

[0074] The decoding level continuously marks atomic barrier tags. The pipeline freeze control logic waits for the nearest atomic barrier tag point. Upon reaching the boundary point, it sends a freeze confirmation signal to the clock tree and clock gating controller. The clock tree and clock gating controller then shut down the clock level by level.

[0075] The snapshot write control logic writes to the non-volatile memory circuit in parallel.

[0076] The power supply completely failed and entered sleep mode.

[0077] After the ambient energy is re-accumulated, the power-on recovery detection circuit triggers the recovery enable signal;

[0078] Parallel reverse recovery of the critical register set using non-volatile memory circuitry;

[0079] The pipeline continues execution from the breakpoint instruction and then loops back to the environmental energy harvesting and storage node, forming a complete intermittent computational closed-loop processing process.

[0080] VI. Alternative Example 1

[0081] Without departing from the inventive concept, the hardware-level low-power energy prediction module can also adopt the following alternative structure: instead of using a time prediction method based on voltage drop slope extrapolation, multiple sequentially decreasing fixed voltage threshold points are set. The time interval between the voltage across the energy storage capacitor falling below each fixed voltage threshold point is detected, and the voltage drop rate is determined based on this time interval. When the voltage falls below a pre-set fixed voltage threshold point, an imminent sleep signal is triggered. This alternative embodiment replaces the voltage slope digitization circuit with a multi-stage comparator circuit structure, which can further reduce the circuit complexity and static power consumption of the prediction module, making it suitable for IoT chip scenarios where chip area is relatively sensitive.

[0082] VII. Alternative Example 2

[0083] Without departing from the concept of this invention, the breakpoint state saving module can also adopt the following alternative structure: instead of using a distributed non-volatile storage circuit that is tightly coupled to each register, a centralized non-volatile cache block with a capacity greater than the space required for a single context is set up next to the processor core. Through a dedicated high-width internal bus, when the freeze confirmation signal arrives, the values ​​in the key register group are read in parallel at once and written to the centralized non-volatile cache block.

[0084] Upon power-on recovery, the data is read out in parallel and distributed to each register in the critical register group at once via the same dedicated bus. This alternative embodiment replaces the distributed, tightly coupled structure with a centralized storage plus dedicated bus structure, which can reduce the area of ​​redundant layout of non-volatile memory cells and is suitable for microcontroller scenarios with a large number of registers and high requirements for chip layout and routing flexibility.

[0085] In summary, the present invention enables microcontroller chips to safely save the semantic integrity of computing tasks under intermittent power supply conditions with almost zero software overhead, through hardware circuitry-based energy trend prediction, precise freezing of computational semantic boundaries, and low-power snapshot and recovery of breakpoint states. This allows the chips to continue execution from the breakpoint after charging is restored, thereby enabling large computing tasks spanning multiple charge-discharge cycles to be completed cumulatively.

[0086] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, any modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope defined by the claims of the present invention.

Claims

1. A microcontroller chip processing method based on Internet of Things (IoT) hardware, characterized in that, Includes the following steps: The voltage across the energy storage capacitor of the microcontroller is continuously collected, and a sleep signal is generated before the voltage drops below the maintenance threshold voltage based on the voltage's decreasing trend. The decoding stage of the processor core pipeline identifies semantic boundary instructions in the computation flow based on predefined instruction characteristics and marks atomic barrier tags in the pipeline control word of the corresponding instruction; Upon receiving the impending hibernation signal, the pipeline freeze control logic does not immediately interrupt the pipeline. Instead, it controls the pipeline to continue executing at its original pace until it detects that an instruction carrying the atomic barrier tag has completed a write-back operation at the write-back stage. At this point, it sends a freeze confirmation signal to the clock gating controller. After receiving the freeze confirmation signal, the clock gating controller disables the corresponding clock enable signals in the order of instruction fetch stage, decode stage, execution stage, memory access stage, and write-back stage, so that the pipeline completely stops stepping at the instruction corresponding to the atomic barrier tag. After detecting the freeze confirmation signal, the snapshot write control logic writes the current values ​​in the processor core's general-purpose register file, program counter, status register, and atomic barrier tag register into the non-volatile memory circuit in parallel. After the write is completed, it sends a snapshot completion signal back to the power management unit, which then allows the microcontroller's main power supply voltage to continue to drop until power is cut off. When the ambient energy accumulates again, the microcontroller is powered on again, and the voltage stabilizes, a recovery enable signal is generated, which drives the non-volatile storage circuit to write the stored value back to the corresponding register in parallel. After the write-back is completed, pipeline control is returned to the instruction pointed to by the program counter, and the pipeline continues to execute from that instruction.

2. The method according to claim 1, characterized in that, The step of generating a sleep signal before the voltage drops below the maintenance threshold voltage based on the voltage decline trend includes: continuously sampling the voltage across the energy storage capacitor at a fixed sampling period to obtain two adjacent sampling values, and calculating the voltage drop slope based on the two sampling values ​​and the sampling time interval. The warning voltage value is calculated based on the maintenance threshold voltage, the absolute value of the voltage drop slope, and the pre-calibrated safety time margin. The current sampled voltage value is compared with the warning voltage value. When the current sampled voltage value is not greater than the warning voltage value, it is determined that the energy is about to enter a low energy state, and the impending hibernation signal is generated.

3. The method according to claim 1, characterized in that, The step of generating an imminent sleep signal before the voltage drops below a maintenance threshold voltage, based on the voltage's decreasing trend, includes: setting multiple sequentially decreasing fixed voltage thresholds; detecting the time interval between the voltage across the energy storage capacitor dropping below each of the fixed voltage thresholds; determining the voltage drop rate based on the time interval; and generating the imminent sleep signal when the voltage drops below a pre-set fixed voltage threshold.

4. The method according to claim 1, characterized in that, The semantic boundary instructions include at least one of the following: loop bounce instruction, accumulation result write-back instruction, and cryptographic round function end flag instruction.

5. The method according to claim 1, characterized in that, The non-volatile storage circuit includes non-volatile trigger units that correspond one-to-one with the general-purpose register file, the program counter, the status register, and the atomic barrier tag register. Each non-volatile trigger unit is connected to the corresponding register through an independent parallel data bypass bus. Within the same clock cycle when the freeze confirmation signal arrives, the write enable terminal of each non-volatile trigger unit is synchronously driven to achieve parallel writing.

6. The method according to claim 1, characterized in that, The non-volatile storage circuit is a centralized non-volatile cache block. The current values ​​in the general-purpose register file, the program counter, the status register, and the atomic barrier tag register are written to the centralized non-volatile cache block at once through a dedicated parallel bus.

7. The method according to claim 1, characterized in that, The steps for generating the recovery enable signal include: continuously detecting whether the main power supply voltage of the microcontroller has recovered to the preset normal operating voltage and remained stable through the power-on recovery detection circuit; generating the recovery enable signal when the voltage is detected to be stable; and not loading and running the software boot program during the recovery process.

8. A microcontroller chip, characterized in that, include: The power management unit has an embedded voltage tracking state machine module, which is used to continuously collect the voltage value across the energy storage capacitor and generate a sleep signal before the voltage drops below the maintenance threshold voltage based on the voltage's downward trend. The processor core includes a pipeline consisting of an instruction fetch stage, a decode stage, an execution stage, a memory access stage, and a write-back stage connected in sequence. The decode stage has embedded atomic barrier tag generation logic, which is used to identify semantic boundary instructions in the computation flow and mark atomic barrier tags according to predefined instruction characteristics. The pipeline freeze control logic is connected to the voltage tracking state machine module and the atomic barrier tag generation logic. After receiving the impending hibernation signal, it controls the pipeline to continue execution until the instruction carrying the atomic barrier tag completes the write-back operation and outputs a freeze confirmation signal. A clock gating controller, connected to the pipeline freeze control logic, is used to disable the corresponding clock enable signals in the order of instruction fetch stage, decode stage, execution stage, memory access stage, and write-back stage after receiving the freeze confirmation signal. A non-volatile memory circuit is connected to the general-purpose register file, program counter, status register, and atomic barrier tag register of the processor core, and is used to write the current value in the general-purpose register file, program counter, status register, and atomic barrier tag register in parallel when the freeze confirmation signal arrives; The power-on recovery detection circuit is used to generate a recovery enable signal after the microcontroller is powered on again and the voltage stabilizes, driving the non-volatile storage circuit to write the saved values ​​back to the corresponding registers in parallel.

9. The microcontroller chip according to claim 8, characterized in that, The non-volatile storage circuit includes non-volatile trigger units that correspond one-to-one with the general-purpose register file, the program counter, the status register, and the atomic barrier tag register. Each non-volatile trigger unit is connected to the corresponding register through an independent parallel data bypass bus.

10. The microcontroller chip according to claim 8, characterized in that, The voltage tracking state machine module includes a low-power analog comparator array, a voltage slope digitization circuit, and an adaptive threshold judgment logic. It is used to continuously sample the voltage across the energy storage capacitor at a fixed sampling period and calculate the voltage drop slope. Based on the maintenance threshold voltage, the absolute value of the voltage drop slope, and the pre-calibrated safety time margin, it obtains a warning voltage value and compares the current sampled voltage value with the warning voltage value to generate the upcoming sleep signal.

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