Controller and system for satancq command

Abstract

The application provides a controller and system for SATA NCQ commands. A decision module polls M command registers, M relay units and M descriptor units, and generates and sends a target message based on a set priority order, wherein the target message is any one of a base address read request, a frame information structure read request, a physical region descriptor read request and a data read request in a descending order of priority. The serial processing mechanism of a single queue command is broken, and multiple queue commands can be processed in parallel, so that deep overlap of NCQ multiple queues in the command analysis, parameter acquisition and data transmission stages is realized, and the overall IOPS (input / output operations per second) of the system is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and more specifically, to a controller and system for SATA NCQ commands. Background Technology

[0002] Native Command Queuing (NCQ) is an important technology in the Serial Advanced Technology Attachment (SATA) protocol. It allows hard drives to dynamically adjust the read and write order based on the current position of the read and write head and the position of the data request, thereby reducing the number of head seeks, reducing access latency, and improving multitasking capabilities.

[0003] In existing SATA NCQ transmission schemes, the host typically employs a serial processing mechanism: it must wait for the current queue's command list to finish reading and the frame information structure (FIS) to finish sending before receiving the device's DMA Setup FIS, reading the Physical Region Descriptor Table (PRD), and initiating data transmission. During this data transmission process, the controller is usually in a busy-wait state, unable to process commands from other queues in a timely manner. This serial processing mode prevents multiple NCQ queues from truly executing in parallel, resulting in wasted transmission efficiency, especially in scenarios with multi-task concurrent access, where system throughput is limited. Summary of the Invention

[0004] The purpose of this invention is to provide a controller and system for SATA NCQ commands to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a controller for SATA NCQ commands, the controller being configured with M command registers, M relay units, M descriptor units, and a decision module; The m-th command register is used to store the m-th queue command issued by the host. The m-th queue command includes the storage address of the m-th base address and the storage address of the m-th frame information structure. The m-th relay unit is used to store the m-th base address and the m-th frame information structure related to the m-th queue command. The m-th descriptor unit is used to store the physical area descriptor related to the m-th queue command, 1≤m≤M. The decision module is used to poll M command registers, M relay units, and M descriptor units, and generate and send target messages based on a set priority order. The target message is any one of the following in descending priority order: base address read request, frame information structure read request, physical region descriptor read request, and data read request.

[0006] It can poll M command registers, M relay units, and M descriptor units, and generate and send target messages based on the set priority order. This breaks the serial processing mechanism of a single queue command and allows multiple queue commands to be processed in parallel. It enables deep overlap of NCQ multi-queues in the command parsing, parameter acquisition, and data transmission stages, effectively improving the overall system IOPS (input / output operations per second).

[0007] Secondly, embodiments of the present invention provide a SATA NCQ command processing system, which includes a first memory, a host, a SATA device, and the aforementioned controller for SATA NCQ commands; The controller is connected to both the host and the SATA device, and the host is connected to the first memory.

[0008] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of the SATA NCQ command processing system provided in an embodiment of the present invention.

[0011] Figure 2 This is a schematic diagram of the controller provided in an embodiment of the present invention. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0013] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0014] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0015] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0016] This invention provides a SATA NCQ command processing system. Please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic diagram of the SATA NCQ command processing system provided in an embodiment of the present invention. The SATA NCQ command processing system includes a first memory, a controller, a host, and SATA devices. The controller is connected to both the host and the SATA devices, and the host is connected to the first memory. The controller communicates with the first memory through the host. The controller can be a SATA controller that acts as a bridge between the host and the SATA devices. The host can be, but is not limited to, a central processing unit (CPU). The first memory is not part of the controller and can be, but is not limited to, RAM.

[0017] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the controller provided in an embodiment of the present invention. The controller is provided with M command registers, M relay units, M descriptor units, and a decision module, where M can be, but is not limited to, 32.

[0018] The m-th command register is used to store the m-th queue command issued by the host. The m-th queue command includes the storage address of the m-th base address and the storage address of the m-th frame information structure. The m-th relay unit is used to store the m-th base address and the m-th frame information structure related to the m-th queue command. The m-th descriptor unit is used to store the physical area descriptor related to the m-th queue command, where 1 ≤ m ≤ M.

[0019] M command registers are Figure 2 The Q1 command register - QM command register shown in the diagram, where Qm command register represents the m-th command register, 1 ≤ m ≤ M. The controller is equipped with a second memory, which contains a relay list and a descriptor list. The relay list includes M relay units, and the descriptor list includes M descriptor units. Qm relay unit represents the m-th relay unit, and Qm descriptor unit represents the m-th descriptor unit.

[0020] The decision module is used to poll the M command registers, M relay units, and M descriptor units, and generate and send target messages based on the set priority order. That is, the target messages are sent to the peer device, which can be the first memory or a SATA device. It should be understood that the peer device receiving the target message can feed back the corresponding information to the controller. The target message is any one of the following in descending priority order: base address read request, frame information structure read request, physical region descriptor read request, and data read request.

[0021] This invention provides a controller for SATA NCQ commands, which can poll M command registers, M relay units, and M descriptor units, and generate and send target messages based on a set priority order. This breaks the serial processing mechanism of a single queue command and can process multiple queue commands in parallel. It achieves deep overlap of NCQ multi-queues in the command parsing, parameter acquisition, and data transmission stages, effectively improving the overall system IOPS (input / output operations per second).

[0022] Please continue to refer to this. Figure 2 The decision-making module includes a first scheduling unit, a second scheduling unit, a third scheduling unit, and a Strict Priority (SP) scheduling unit; the first scheduling unit, the second scheduling unit, and the third scheduling unit are all round-robin (RR) scheduling units.

[0023] The first scheduling unit is used to poll the M command registers. If there are command registers in a pending state, a corresponding base address read request is generated. The second scheduling unit is used to poll the M relay units. If there are relay units in the pending state, a corresponding relay request is generated. The relay request is either a frame information structure read request or a physical region descriptor read request. The third scheduling unit is used to poll the M descriptor units. If there are descriptor units in the pending state, a corresponding data read request is generated. The priority scheduling unit is used to poll the first scheduling unit, the second scheduling unit, and the third scheduling unit, and select one of the base address read request, relay request, and data read request as the target message based on the set priority order, and then send the target message.

[0024] It should be understood that if the first scheduling unit generates a base address read request during polling, the base address read request will be used as the target message; if the first scheduling unit does not generate a base address read request and the second scheduling unit generates a relay request, the relay request will be used as the target message; if the first scheduling unit does not generate a base address read request and the second scheduling unit does not generate a relay request, and the third scheduling unit generates a data read request, the data read request will be used as the target message.

[0025] Regarding how to ensure that the reading order of the base address conforms to the host's settings when the first scheduling unit polls the M command registers to generate base address read requests, this embodiment of the invention also provides an optional implementation method, please refer to the following.

[0026] The first scheduling unit polls the M command registers. If there is a command register in a pending state, it generates a read request for the ka-th base address based on the storage address of the ka-th base address. The read request for the ka-th base address includes the storage address of the ka-th base address and the identifier of the ka-th command register. The ka-th command register is the command register that has been in a pending state for the longest time. The ka-th command register includes the storage address of the ka-th base address and the storage address of the ka-th frame information structure, where 1≤ka≤M.

[0027] It should be understood that the host writes the m-th queue command into the m-th command register by modifying the command register in the controller, and marks the m-th command register as pending. The m-th queue command includes the storage address of the m-th base address of the m-th queue and the storage address of the m-th frame information structure.

[0028] In one alternative implementation, when the target message is a read request for the ka-th base address, the priority scheduling unit is used to send the target message to the first memory.

[0029] The first memory is used to send base address feedback information to the controller based on the storage address of the ka-th base address. The base address feedback information includes the ka-th base address and the identifier of the ka-th command register.

[0030] When the controller receives the base address feedback information, it writes the storage address of the ka-th base address and the ka-th frame information structure into the ka-th relay unit and marks the ka-th relay unit as pending (at this time, the ka-th relay unit is the primary relay unit mentioned below).

[0031] It should be understood that the controller is used to mark the ka-th command register as processed after sending the ka-th base address read request to the first memory, or after receiving the ka-th base address from the first memory.

[0032] Regarding the specific implementation method of the second scheduling unit polling M relay units to generate relay requests, this embodiment of the invention also provides an optional implementation method, please refer to the following.

[0033] The second scheduling unit is used to poll the M relay units. If there is a primary relay unit, it generates a read request for the kb-th frame information structure based on the storage address of the kb-th frame information structure. The read request for the kb-th frame information structure includes the storage address of the kb-th frame information structure and the identifier of the kb-th relay unit. The first-order relay unit is the relay unit that is in a pending state and has not yet obtained the frame information structure. The kb-th relay unit is the first-order relay unit that has been in a pending state for the longest time (the kb-th relay unit includes the kb-th base address and the storage address of the kb-th frame information structure, 1≤kb≤M).

[0034] If only higher-order relay units exist (i.e., no lower-order relay units exist), then a read request for the kc-th descriptor is generated.

[0035] The kc-th descriptor read request includes the storage address of the kc-th physical region descriptor and the identifier of the kc-th relay unit. The higher-order relay unit is a relay unit that is in a pending state and has obtained FIS feedback information, but has not yet obtained the physical region descriptor. The kc-th relay unit is the higher-order relay unit that has been in a pending state for the longest time. The kc-th relay unit includes the kc-th base address, the storage address of the kc-th frame information structure, the kc-th frame information structure, and the kc-th FIS feedback information. The storage address of the kc-th physical region descriptor is the kc-th base address + a preset offset, where 1 ≤ kc ≤ M.

[0036] Optionally, when the target message is a read request for the kb-th frame information structure, the priority scheduling unit is used to send the target message to the first memory; The first memory is used to send frame information structure feedback information to the controller according to the storage address of the kb frame information structure. The frame information structure feedback information includes the kb frame information structure and the identifier of the kb relay unit. The controller is used to send the frame information structure feedback information to the SATA device when it receives the frame information structure feedback information (indicating that the frame information structure of the kb relay unit has been obtained, and the kb relay unit is no longer the primary relay unit). After obtaining the kb frame information structure, the SATA device sends a transmission request feedback message to the controller. The transmission request feedback message includes the kb FIS feedback message and the identifier of the kb relay unit.

[0037] It should be understood that a SATA device is, for example, a SATA hard drive. Of course, the frame information structure may also include the operation type, data length, and operation address to prepare the SATA device. Once prepared, the SATA device sends a DMA Setup FIS feedback message to the controller.

[0038] The controller is used to mark the kb-th relay unit as a higher-order relay unit when it receives a transmission request feedback message; When the target message is a read request for the kc-th descriptor, the priority scheduling unit is used to send the target message to the first memory; The first memory is used to send descriptor feedback information to the controller after receiving the kc descriptor read request. The descriptor feedback information includes the kc physical area descriptor and the identifier of the kc relay unit. The controller is used to write the kc-th physical region descriptor into the kc-th descriptor unit when it receives descriptor feedback information, and to mark the kc-th descriptor unit as pending.

[0039] The second scheduling unit is used to mark the kc relay unit as processed after sending the kc descriptor read request to the first memory, or after receiving the kc physical region descriptor fed back by the first memory.

[0040] Regarding the specific implementation method of the third scheduling unit polling M descriptor units to generate data read requests, this embodiment of the invention also provides an optional implementation method, please refer to the following.

[0041] The third scheduling unit polls the M descriptor units. If there are descriptor units in a pending state, it generates a data read request corresponding to the kd-th physical region descriptor. The data read request includes the data storage address and the identifier of the kd-th descriptor unit. The kd-th descriptor unit is the descriptor unit that has been in the pending state for the longest time. The kd-th descriptor unit includes the kd-th physical region descriptor, and 1≤kd≤M.

[0042] Optionally, when the target message is a data read request, the priority scheduling unit is used to send the data read request to the first device. When the operation type corresponding to the kd-th physical region descriptor is write data, the first device is the first memory. When the operation type corresponding to the kd-th physical region descriptor is read data, the first device is the SATA device. The write direction is to read data from memory and write it to the hard disk, and the read direction is to read data from the hard disk and read it into memory. When the controller is writing data, it sends a data read request to the memory. The storage address of the data read request is in the PRD data. When the controller is reading data, it sends a data read request to the SATA device.

[0043] The first device is used to send data feedback information to the controller according to the data storage address. The data feedback information includes the target data corresponding to the data storage address and the identifier of the kd-th descriptor unit.

[0044] The controller is used to cache the target data when it receives data feedback information, and delete the cached target data after sending the cached target data to the second device according to the identifier of the kd-th descriptor unit.

[0045] When the operation type is write data, the first device is the first memory and the second device is the SATA device. When the operation type is read data, the first device is the SATA device and the second device is the first memory.

[0046] Optionally, generating a data read request corresponding to the kd-th physical region descriptor includes: generating a corresponding data read request based on the remaining unread first segment of the kd-th physical region descriptor, and marking the first segment as read.

[0047] The PCIe protocol imposes limits on each read request. Typically, a physical region descriptor (PDR) is quite long and may need to be split into multiple segments for separate processing. When all segments in the kd-th PDR have been read, the kd-th descriptor unit can be marked as processed.

[0048] It should be understood that the internal cache space of the controller is limited. In order to avoid data from multiple queues competing for cache space and causing data to be erased without cause, data can be read in the order of the set priority.

[0049] Using Q1, Q2, and Q3 as examples, this invention provides an example of the controller's parallel processing of SATA NCQ commands. Initially, the host modifies the command register in the controller, writing the first queue command into the first command register and marking the first command register as pending. The first queue command includes the storage address of the first base address of the first queue and the storage address of the first frame information structure.

[0050] At this point, the decision module sends the first base address read request as the target message to the first memory. During the idle period while waiting for the first memory to return the first base address, if the host modifies the command register in the controller to write the second queue command into the second command register and marks the second command register as pending, the second queue command includes the storage address of the second base address of the second queue and the storage address of the second frame information structure. The decision module then sends the second base address read request as the target message to the first memory.

[0051] Similarly, during the idle period while the decision module sends the data read request corresponding to the first physical region descriptor to the first device and waits for the first device to return the target data corresponding to the data read request, if the host modifies the command register in the controller to write the second queue command into the second command register and marks the second command register as pending, the second queue command includes the storage address of the second base address of the second queue and the storage address of the second frame information structure. The decision module sends the second base address read request as the target message to the first memory. Alternatively, if there is no command register in the pending state and the third relay unit is a higher-order relay unit, the third descriptor read request can be sent as the target message to the first memory.

[0052] The time for the first memory to return the base address is typically long, involving PCIe transmission latency. In this embodiment of the invention, by utilizing the time gap while waiting for the base address and physical region descriptor to return, the controller actively polls and reads control information from other queues, achieving pipelined processing of NCQ multi-queues. While data is being transmitted on the physical link, the controller backend can pre-prepare the transmission parameters for the next queue, thereby significantly improving the bandwidth utilization and multi-task concurrency performance of the SATA interface.

[0053] In summary, the controller and system for SATA NCQ commands provided in this embodiment of the invention poll the M command registers, M relay units, and M descriptor units, and generate and send target messages based on a set priority order. The target message is any one of the following in descending priority order: base address read request, frame information structure read request, physical region descriptor read request, and data read request. This breaks the serial processing mechanism of a single queue command, allowing parallel processing of multiple queue commands. It achieves deep overlap between NCQ multi-queues in the command parsing, parameter acquisition, and data transmission stages, effectively improving the overall system IOPS (input / output operations per second).

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0055] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A controller for SATA NCQ commands, characterized in that, The controller is equipped with M command registers, M relay units, M descriptor units, and a decision module; The m-th command register is used to store the m-th queue command issued by the host. The m-th queue command includes the storage address of the m-th base address and the storage address of the m-th frame information structure. The m-th relay unit is used to store the m-th base address and the m-th frame information structure related to the m-th queue command. The m-th descriptor unit is used to store the physical region descriptor related to the m-th queue command, where 1 ≤ m ≤ M; The decision module is used to poll M command registers, M relay units, and M descriptor units, and generate and send target messages based on a set priority order. The target message is any one of the following in descending priority order: base address read request, frame information structure read request, physical region descriptor read request, and data read request.

2. The controller for SATA NCQ commands as described in claim 1, characterized in that, The decision-making module includes a first scheduling unit, a second scheduling unit, a third scheduling unit, and a priority scheduling unit; The first scheduling unit is used to poll the M command registers. If there are command registers in a pending state, a corresponding base address read request is generated. The second scheduling unit is used to poll the M relay units. If there are relay units in a pending state, a corresponding relay request is generated. The relay request is either a frame information structure read request or a physical region descriptor read request. The third scheduling unit is used to poll the M descriptor units. If there are descriptor units in a pending state, a corresponding data read request is generated. The priority scheduling unit is used to poll the first scheduling unit, the second scheduling unit and the third scheduling unit, and select one of the base address read request, relay request and data read request as the target message based on the set priority order, and send the target message.

3. The controller for SATA NCQ commands as described in claim 2, characterized in that, The first scheduling unit polls the M command registers. If there is a command register in a pending state, it generates a read request for the ka-th base address based on the storage address of the ka-th base address. The read request for the ka-th base address includes the storage address of the ka-th base address and the identifier of the ka-th command register. The ka-th command register is the command register that has been in a pending state for the longest time.

4. The controller for SATA NCQ commands as described in claim 3, characterized in that, When the target message is a read request for the ka-th base address, the priority scheduling unit is used to send the target message to the first memory; The first memory is used to send base address feedback information to the controller according to the storage address of the ka-th base address. The base address feedback information includes the ka-th base address and the identifier of the ka-th command register. When the controller receives the base address feedback information, it writes the storage address of the ka-th base address and the ka-th frame information structure into the ka-th relay unit and marks the ka-th relay unit as pending.

5. The controller for SATA NCQ commands as described in claim 2, characterized in that, The second scheduling unit is used to poll the M relay units. If there is a primary relay unit, a read request for the kb-th frame information structure is generated according to the storage address of the kb-th frame information structure. The kb-th frame information structure read request includes the storage address of the kb-th frame information structure and the identifier of the kb-th relay unit. The first-order relay unit is a relay unit that is in a pending state and has not yet obtained the frame information structure. The kb-th relay unit is the first-order relay unit that has been in a pending state for the longest time. If only higher-order relay units exist, then generate a read request for the kc-th descriptor; The kc descriptor read request includes the storage address of the kc physical region descriptor and the identifier of the kc relay unit. The higher-order relay unit is a relay unit that is in a pending state and has obtained FIS feedback information, but has not yet obtained the physical region descriptor. The kc relay unit is the higher-order relay unit that has been in a pending state for the longest time.

6. The controller for SATA NCQ commands as described in claim 5, characterized in that, When the target message is a read request for the information structure of the kb-th frame, the priority scheduling unit is used to send the target message to the first memory; The first memory is used to send frame information structure feedback information to the controller according to the storage address of the kb frame information structure. The frame information structure feedback information includes the kb frame information structure and the identifier of the kb relay unit. The controller is used to send the frame information structure feedback information to the SATA device when it receives the frame information structure feedback information; The SATA device is used to send transmission request feedback information to the controller after obtaining the kb frame information structure. The transmission request feedback information includes the kb FIS feedback information and the identifier of the kb relay unit. The controller is used to mark the kb-th relay unit as a higher-order relay unit when it receives a transmission request feedback message; When the target message is a read request for the kc-th descriptor, the priority scheduling unit is used to send the target message to the first memory; The first memory is used to send descriptor feedback information to the controller after receiving the kc descriptor read request. The descriptor feedback information includes the kc physical area descriptor and the identifier of the kc relay unit. The controller is used to write the kc-th physical region descriptor into the kc-th descriptor unit when it receives descriptor feedback information, and to mark the kc-th descriptor unit as pending.

7. The controller for SATA NCQ commands as described in claim 2, characterized in that, The third scheduling unit polls the M descriptor units. If there are descriptor units in a pending state, it generates a data read request corresponding to the kd-th physical region descriptor. The data read request includes the data storage address and the identifier of the kd-th descriptor unit, which is the descriptor unit that has been in the pending state for the longest time.

8. The controller for SATA NCQ commands as described in claim 7, characterized in that, When the target message is a data read request, the priority scheduling unit is used to send the data read request to the first device. When the operation type corresponding to the kd-th physical region descriptor is write data, the first device is the first memory. When the operation type corresponding to the kd-th physical region descriptor is read data, the first device is the SATA device. The first device is used to send data feedback information to the controller according to the data storage address. The data feedback information includes the target data corresponding to the data storage address and the identifier of the kd-th descriptor unit. The controller is used to cache the target data when it receives data feedback information, and delete the cached target data after sending the cached target data to the second device according to the identifier of the kd-th descriptor unit.

9. The controller for SATA NCQ commands as described in claim 7, characterized in that, Generate a data read request corresponding to the kd-th physical region descriptor, including: Based on the remaining unread first segment of the kd-th physical region descriptor, generate the corresponding data read request and mark the first segment as read.

10. A SATA NCQ command processing system, characterized in that, The SATA NCQ command processing system includes a first memory, a host, a SATA device, and a controller for SATA NCQ commands as described in any one of claims 1-9; The controller is connected to both the host and the SATA device, and the host is connected to the first memory.

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