A storage module

Abstract

A memory module includes a substrate and at least one stack unit disposed on the substrate; the stack unit includes a plurality of connectors and a plurality of memory sticks disposed on the substrate, the plurality of memory sticks partially overlap in the area of the orthographic projection on the substrate; or the stack unit includes a connector and a memory stick disposed on the substrate, and a patch memory grain on the substrate, the patch memory grain is located in the area of the orthographic projection of the memory stick on the substrate. Through the stack design, as many memory grains as possible can be placed in a limited space, providing greater storage capacity.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of computer storage, and more specifically, to a storage module. Background Technology

[0002] With the continuous progress of human society, intelligence is a prominent feature of the Fourth Industrial Revolution. The foundation of intelligence is powerful computing power. However, computing power is not only reflected in the processor's operating frequency and instruction throughput, but also in the throughput of data processing. Therefore, there is a strong demand for memory capacity and bandwidth in the operating environment. Although the industry has developed high-bandwidth memory (HBM) in response to the extremely urgent needs, it is expensive and difficult to use in ubiquitous computing nodes, machines, and networks. Summary of the Invention

[0003] This disclosure provides a storage module, including a substrate and at least one stacking unit disposed on the substrate; the stacking unit includes a first connector and a second connector disposed opposite to each other on the substrate and perpendicularly connected to the substrate, a first memory module inserted into the side of the first connector facing the second connector, and a second memory module inserted into the side of the second connector; the first memory module, the second memory module and the substrate are parallel to each other and spaced apart; the orthographic projection areas of the first memory module and the second memory module on the substrate partially overlap.

[0004] The system includes a substrate and at least one stacking unit disposed on the substrate. The stacking unit includes a first connector and a second connector disposed opposite to each other on the substrate and perpendicular to the substrate, a first memory module inserted into the side of the first connector facing the second connector, and a second memory module inserted into the side of the second connector. The first memory module, the second memory module, and the substrate are disposed parallel to each other and spaced apart. The first memory module and the second memory module are located above the substrate, and the orthographic projections of the first memory module and the second memory module on the substrate overlap.

[0005] The storage module of the above embodiments of this disclosure has stacking units on a substrate, which spatially stack multiple memory modules such that their orthographic projections on the substrate overlap. This reduces the space occupied by these memory modules, allowing as many memory chips as possible (each memory module has multiple memory chips) to be placed within a limited space, providing a larger storage capacity. The storage module of this embodiment can be applied to servers and data centers to improve the storage capacity of servers and data centers.

[0006] This disclosure also provides a storage module, including a substrate and at least one stacking unit disposed on the substrate. The stacking unit includes a connector disposed on the substrate and perpendicularly connected to the substrate, a memory module inserted into one side of the connector and spaced apart from the substrate, and a plurality of memory chips disposed on the upper surface and / or lower surface of the substrate in a patch manner; part or all of the plurality of memory chips are located in the orthographic projection area of ​​the memory module on the substrate.

[0007] The storage module of the above embodiments of this disclosure comprises stacked units on a substrate. Each stacked unit includes memory modules spaced apart on the substrate and multiple memory chips mounted in a surface-mount manner on the upper and / or lower surfaces of the substrate. The surface-mount memory chips are located within the orthographic projection area of ​​the memory modules on the substrate; that is, they are stacked. This allows for the placement of as many memory chips as possible (multiple memory chips on each memory module) within a limited space, providing greater storage capacity. The storage module of this embodiment can be applied to servers and data centers to improve their storage capacity.

[0008] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0009] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0010] Figure 1A This is a top view schematic diagram of a storage module according to an embodiment of the present disclosure;

[0011] Figure 1B for Figure 1A AA section view;

[0012] Figure 2A This is a top view schematic diagram of a storage module according to another embodiment of the present disclosure;

[0013] Figure 2B for Figure 2A AA section view;

[0014] Figure 3A This is a top view schematic diagram of a storage module according to another embodiment of the present disclosure;

[0015] Figure 3B for Figure 3A AA section view;

[0016] Figure 4A This is a top view schematic diagram of a storage module according to another embodiment of the present disclosure;

[0017] Figure 4B for Figure 4A A bottom view of the storage module shown;

[0018] Figure 4C for Figure 4A AA section view;

[0019] Figure 5 This is a cross-sectional view of yet another embodiment of this disclosure;

[0020] Figure 6 This is a logic circuit diagram of the storage module according to an embodiment of this disclosure. Detailed Implementation

[0021] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0022] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form an inventive scheme protected by this disclosure. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another inventive scheme protected by this disclosure. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0023] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0024] Since the Compute Express Link (CXL) industry group introduced the CXL protocol based on PCIe high-speed interconnect bus technology, it has had a wide-ranging impact on memory expansion methods. The Type 3 CXL device (also referred to as a CXL memory module in this article) defined by CXL allows the host CPU to access the expanded memory via PCIe (Peripheral Component Interconnect Express) as the physical layer, providing the host with a large capacity of memory, and its performance is gradually approaching that of the processor's local memory.

[0025] The price of a single memory module (such as the CXL memory module) increases non-linearly with capacity. It is necessary to find an architecture that can integrate as many memory chips as possible within a certain space in order to save costs.

[0026] To this end, one embodiment of the present disclosure provides a storage module, including a substrate and at least one stacking unit disposed on the substrate; the stacking unit includes a first connector and a second connector disposed opposite to each other on the substrate and perpendicularly connected to the substrate, a first memory module inserted into the side of the first connector facing the second connector, and a second memory module inserted into the side of the second connector; the first memory module, the second memory module and the substrate are parallel to each other and spaced apart; the orthographic projection areas of the first memory module and the second memory module on the substrate partially overlap.

[0027] In this embodiment, the memory module can be a CXL memory module, such as a Type 3 CXL device, but is not limited to this.

[0028] The storage module of this embodiment features stacking units on a substrate, spatially stacking multiple memory modules such that their orthographic projections on the substrate overlap. This reduces the space occupied by the memory modules, allowing for the placement of as many memory chips (each memory module has multiple memory chips) within a limited space, thus providing greater storage capacity. This storage module can be applied to servers and data centers to improve their storage capacity.

[0029] In an exemplary embodiment of this disclosure, the shape of the storage module conforms to the shape specifications specified by E3.S2T or E3.L 2T, and the storage module is a CXL memory module.

[0030] The Enterprise Data Center SSD Form Factor (EDSFF) is a hard drive form factor design specification developed by the Storage Networking Industry Association (SNIA) specifically for enterprises and data centers. It is a universal and popular standard that guides the data storage interface of data centers. It can achieve petabyte-level storage capacity on 1U servers (44.45mm high) and obtain even more extreme storage performance on 2U servers (88.9mm high).

[0031] EDSFFs are available in two main series: E1 and E3, each further divided into long and short versions. The E3 series includes E3.S1T, E3.S2T, E3.L 1T, and E3.L 2T. This embodiment uses the E3.S2T with dimensions of 112.75mm (L) × 76mm (W) × 16.8mm (H), and the E3.L2T with dimensions of 142.2mm (L) × 76mm (W) × 16.8mm (H). The E3.S2T and E3.L 2T support x4, x8, and x16 PCIe data transfer lanes, meaning they can support 4, 8, and 16 lanes respectively.

[0032] The storage module in this embodiment conforms to the E3.S2T or E3.L 2T form factor, which facilitates the integration of interface specifications and CXL technology. It can be easily expanded to include memory devices used in data centers without requiring changes to the existing PCIe physical layer hardware, and the software ecosystem for applications to access memory is not affected.

[0033] In an exemplary embodiment of this disclosure, the length direction of all connectors in the stacking unit is consistent with the length direction of the substrate, and the insertion direction of all memory modules in the stacking unit is consistent with the width direction of the substrate; the second memory module is inserted into the side of the second connector facing away from the first connector, and the second connector is located between the first memory module and the substrate.

[0034] Figure 1A and Figure 1B The figure shows the storage module of this embodiment. As shown, the storage module conforms to the E3.S2T or E3.L 2T form factor and includes a substrate 3 and a stacking unit disposed on the substrate 3. The stacking unit includes a first connector 11 and a second connector 21 disposed opposite to each other and perpendicularly connected to the substrate 3, a first memory module 12 inserted into the side of the first connector 11 facing the second connector 21, and a second memory module 22 inserted into the side of the second connector 21. The first memory module 12, the second memory module 22 and the substrate 3 are parallel to each other and spaced apart. The orthographic projection areas of the first memory module 12 and the second memory module 22 on the substrate 3 partially overlap.

[0035] The length direction of substrate 3 is the direction of the side with a dimension of 112.75 mm in the figure, and the width direction of substrate 3 is the direction of the side with a dimension of 76 mm in the figure. In this text, the length direction of the substrate is also taken as the length direction of the stacking unit, and the width direction of the substrate is also taken as the width direction of the stacking unit. The height direction of the stacking unit is perpendicular to the plane of the substrate.

[0036] from Figure 1B It can be seen that the length direction of all connectors (including the first connector 11 and the second connector 21) in the stacking unit is consistent with the length direction of the substrate 3, and the insertion direction of all memory modules (including the first memory module 21 and the second memory module 22) in the stacking unit is consistent with the width direction of the substrate 3; Figure 1B In the example shown, the second memory module 22 is inserted into the side of the second connector 21 facing away from the first connector 11. The second connector 21 is located between the first memory module 12 and the substrate 3, meaning that the two memory modules are horizontally inserted into their respective connectors from the same side to the other. Figure 1B In this embodiment, both the first memory module 11 and the second memory module 21 are horizontally inserted into their respective connectors from right to left, providing more operating space and facilitating insertion. However, in another embodiment, the second memory module 22 can be inserted into the side of the second connector 21 facing the first connector 11, with the second memory module 22 positioned between the first connector 11 and the second connector 21. This is equivalent to... Figure 1B The second connector 21 shown is now positioned on the other side of the second memory module 22 and plugged into it, as indicated by the dashed box in the figure.

[0037] The height direction of the stacked cells is used as the height direction of the first connector and the second connector, such as... Figure 1B As shown, the height of the first connector plus the substrate thickness is 9.2mm, but this is only exemplary. This height only needs to be less than the height of E3.S / L2TForm Factor, which is 16.8mm. The net distance between the first memory module and the substrate (i.e., the distance between the lower surface of the first memory module and the upper surface of the substrate) is 4.0mm. The height of the second connector 21 can be equal to or slightly less than 4.0mm, and the second memory module 22 can be positioned at the middle position in the height direction of the second connector 21, so that there are gaps between the second memory module 22 and the parallel substrate 3 and the first memory module 12 to facilitate heat dissipation. As an example, the thickness of the first memory module and the second memory module itself (the dimension in the height direction of the storage module, including the thickness of the memory chips on the memory module) can be 1.2mm, but it can also be 1.0mm, 0.8mm, or greater than 1.2mm. This is related to the process parameters of the memory module and its memory chips. This disclosure is not limited to this. The thickness of the memory module in other embodiments is also the same, and will not be repeated below. The first memory module 12 can be inserted into the first connector 11 at a position slightly above the middle in the height direction, so that there is enough space for the second connector 21 and the second memory module 22 below it to be installed, and it is also convenient for heat dissipation of the memory module and the substrate after installation.

[0038] Figure 1B The dimensions shown are merely exemplary and must meet the E3.S / L 2T Form Factor requirements while also satisfying heat dissipation needs. Specifically, thermal simulations can be performed on the temperatures of various parts of the storage module during operation based on the designed dimensions. If the simulation results do not meet the temperature requirements of the components (such as memory chips, various chips on the substrate, etc.), these dimensions can be adjusted to improve heat dissipation conditions until the simulation results meet the requirements.

[0039] In an exemplary embodiment of this disclosure, the storage module further includes a controller chip disposed on the substrate, the controller chip including a CXL controller and a memory controller; a connector is provided at one end of the substrate in the length direction, and the controller chip is disposed between the connector and the stacking unit.

[0040] The storage module in this embodiment can be a CXL memory module, such as a Type 3 CXL device, but this disclosure is not limited thereto. Figure 1AAs shown, a controller chip 42 is also provided on the substrate 3. This controller chip 42 integrates a CXL controller and a memory controller (such as a DDR controller), but the CXL controller and the memory controller can also be set separately. The CXL controller can communicate with the host (CPU) based on the CXL protocol, and the DDR controller can access the memory chips 5 on the memory module (shown in the figure as DDR memory chips, i.e., DDR dies). The storage module may also include other chips and auxiliary chips required to implement memory access functions. For example, a power chip 41 is provided on the substrate, a registered clock driver chip (RCD) 43 is provided on the first memory module, etc., which will not be described in detail here.

[0041] Figure 1A The diagram also shows a connector 31 at one end of the substrate 3 along its length. This connector 31 is used to mate with a slot on the server to connect the storage module (also known as a memory card) to the server. In addition to components such as chips, the substrate also has electrical wiring such as metal wires. Connectors can be fixedly connected to the substrate. Through the electrical wiring in the substrate and connectors, the memory module plugged into the connector can be connected to the corresponding chip on the substrate, establishing a connection channel between the memory chip and other circuits on the memory module and the chips and other circuits on the substrate. In this embodiment, within the available space, existing connectors for Small Outline Dual In-line Memory Modules (SO-DIMM) can be used, but other types of connectors such as HS-DIMM connectors can also be used, or new connectors can be customized as needed.

[0042] exist Figure 1A In the example shown, the storage module conforms to the E3.S2T form factor and features a stacking unit containing two memory modules, such as a Horizontal Stacking Dual In-line Memory Module (HS-DIMM). The memory chips on the memory modules can be DDR series chips, such as DDR4 or DDR5 chips, with dimensions of 11mm x 9mm and a capacity of 2GB. Each HS-DIMM has 10 memory chips mounted on each of its two surfaces, allowing for a total of 20 memory chips. Therefore, the maximum capacity per module is 2GB x 20 = 40GB. Figure 1A The structure shown in the example can support one stacking unit (also known as a horizontal stacking unit). One stacking unit can hold two HS-DIMMs. Therefore, the maximum capacity that the storage module can support is: 2×40GB=80GB, and the number of supported Ranks is: 80GB / 32GB=2.5.

[0043] In an exemplary embodiment of this disclosure, two stacked units are disposed on the substrate of the storage module, arranged sequentially in the width direction of the substrate.

[0044] like Figure 2A and Figure 2B As shown, the storage module in this embodiment is relative to Figure 1A and Figure 1B The storage module shown has an additional stacking unit on substrate 3, for a total of two stacking units. As shown in the figure, the second stacking unit includes a first connector 11', a first memory module 12', a second connector 21', and a second memory module 22'. The two stacking units have the same or substantially the same structure (e.g., the RCD chip can be placed in only one of the units), and are arranged sequentially along the width of substrate 3. To avoid exceeding the width specified in E3.S2T or E3.L 2T, the overlapping portion of the orthographic projection area of ​​the two memory modules in the stacking unit on the substrate in this embodiment is greater than [missing information]. Figure 1A The overlapping portion of the orthographic projection areas of the two memory modules in the stacked unit of the illustrated embodiment on the substrate, such as... Figure 1B The width of the overlapping portion shown is 10mm. Figure 2B The width of the overlapping portion shown is 25mm. In other words, the distance between the two connectors in the stacked unit of this embodiment is less than... Figure 1A The distance between the two connectors in the stacked unit of the illustrated embodiment. In this embodiment, one end of the substrate 3 is also provided with a connector. Figure 2A and Figure 2B The connector has been omitted.

[0045] The storage module in this embodiment also conforms to the external dimensions specified by E3.S2T or E3.L 2T, wherein the structure of the stacked units, the chips on the substrate 3, and other structures can be consistent with... Figure 1A The embodiments shown are the same or substantially the same, and will not be repeated. It is still assumed that the memory chips on the memory module are DDR4 or DDR5 chips, with a size of 11mm x 9mm and a capacity of 2GB. Assuming that each HS-DIMM can hold 20 chips, the maximum capacity of a single memory module is 2GB x 20 = 40GB. Since this embodiment's storage module is set up with 2 stacking units, and each unit has 2 HS-DIMMs, the maximum supported capacity is: 2 × 2 × 40GB = 80GB, and the supported Rank number is: 160GB / 32GB = 5, which is greater than... Figure 1A The storage capacity of the storage module in the illustrated embodiment. However... Figure 1A The storage module in the illustrated embodiment has a more sparse structure, better heat dissipation, and can use higher power DDR chips.

[0046] In an exemplary embodiment of this disclosure, such as Figure 3A and Figure 3B As shown, the storage module in this embodiment conforms to the E3.S2T or E3.L 2T form factor specifications, including a substrate 3 and a stacking unit disposed on the substrate 3; the stacking unit includes a first connector 11 and a second connector 21 disposed opposite to each other on the substrate 3 and perpendicularly connected to the substrate 3, a first memory module 12 inserted into the side of the first connector 11 facing the second connector 21, and a second memory module 22 inserted into the side of the second connector 21 facing away from the first connector 11; the first memory module 12, the second memory module 22 and the substrate 3 are parallel to each other and spaced apart; the second connector 21 is located between the first memory module 12 and the substrate 3, and the orthographic projection areas of the first memory module 12 and the second memory module 22 on the substrate 3 partially overlap. As shown in the figure, the stacking unit also includes: a third connector 61 vertically connected to the substrate 3 and a third memory module 62 inserted into the side of the third connector 61 facing away from the second connector 21. The first connector 11, the second connector 21 and the third connector 61 are arranged sequentially in the width direction of the same surface of the substrate 3. The third memory module 62 is parallel to the substrate 3 and is spaced apart from the second memory module 22. The third connector 61 is located between the second memory module 22 and the substrate 3. The orthographic projection areas of the second memory module 22 and the third memory module 62 on the substrate 3 partially overlap.

[0047] This embodiment's storage module includes a stacking unit, which has three sets of connectors and memory modules, equivalent to... Figure 1A In the illustrated embodiment 2, based on the existing stack of connectors and memory modules, another set of connectors and memory modules is stacked. See also... Figure 3B Because there are three stacked layers, the height of the first connector 11 plus the thickness of the substrate is 15.6mm. The distance from the first memory module 12, which is inserted into the first connector 11, to the substrate can be 10.4mm. The second connector 21 is located below the first memory module 12, and its height can be equal to or slightly less than 10.4mm. The distance from the second memory module 22, which is inserted into the second connector 21, to the substrate 3 can be 5.2mm. The third connector 61 is located below the second memory module 22, and its height can be equal to or slightly less than 5.2mm. The distance from the third memory module 62, which is inserted into the third connector 61, to the substrate can be 2.0mm. The width of the overlapping portion of the orthographic projection areas of the first memory module 12 and the second memory module 22 on the substrate 3 can be 10mm, and the width of the overlapping portion of the orthographic projection areas of the second memory module 22 and the third memory module 62 on the substrate 3 can also be 10mm. As mentioned above, these dimensions are merely exemplary, and other dimensions that conform to the E3.S2T or E3.L2T form factor and meet heat dissipation requirements can also be used.

[0048] Assuming this embodiment uses an HS-DIMM memory module with DDR4 or DDR5 memory chips, and an exemplary size of 11mm x 9mm and a capacity of 2GB, and assuming each HS-DIMM can hold 20 chips, such as... Figure 3A As shown, the maximum capacity of a single memory module is 2GB x 20 = 40GB. Since the storage module in this embodiment is set up with one stacking unit, and each unit is set with 3 HS-DIMMs, the maximum capacity that can be supported is: 1×3×40GB = 120GB. The number of supported Ranks is approximately 3.5, which can effectively increase the memory capacity within a limited space.

[0049] In this embodiment, the substrate is also provided with multiple power chips 41 and controller chips 42. The controller chip 41 integrates a CXL controller and a memory controller (such as a DDR controller), but the CXL controller and the memory controller can also be provided separately. At least one of the memory modules, such as the first memory module 11, is provided with an RCD chip. Other necessary circuits can also be provided on the substrate and the memory modules, which will not be described in detail here.

[0050] The above embodiments of this disclosure, such as Figure 1A , Figure 2A and Figure 3A In the illustrated embodiment, the area of ​​the orthographic projection region of the memory modules in the stacked unit onto the substrate is equal to the area of ​​the memory module itself; that is, the memory modules are all located in the space directly above the substrate. Furthermore, the distance from the insertion point of at least one memory module and its corresponding connector in the stacked unit to the substrate is greater than or equal to the distance from the midpoint of the connector in the height direction to the substrate. In other words, the memory module can be inserted at the midpoint or a higher position in the height direction of the connector (i.e., offset away from the substrate) to leave sufficient space for the connectors and memory modules stacked below.

[0051] The storage modules in the above embodiments of this disclosure all conform to the form factor of E3.S2T or E3.L 2T, wherein Figure 1A The storage module of the embodiment shown is configured with a stacking unit, and each unit contains two memory modules; Figure 2A The storage module of the embodiment shown is configured with two stacked units, each unit having two memory modules; Figure 3AThe storage module of the illustrated embodiment is configured with a stacking unit, each unit containing three memory modules. These embodiments reduce space occupation by stacking the memory modules (their orthographic projection areas on the substrate partially overlap), allowing more memory modules to be placed in a limited space, thereby providing greater storage capacity. The storage module of this embodiment can be applied to servers and data centers to improve their storage capacity. The structure and capacity of these storage modules vary, allowing users to choose according to their memory capacity requirements and available space.

[0052] The memory module with the horizontally inserted connector in the above embodiments can be called HS-DIMM. Within the thickness limit of E3.S / L 2T, the number of layers that can be stacked is calculated, and it is not limited to the number of layers in the above embodiments.

[0053] One embodiment of this disclosure also provides a storage module, proposing a surface-mount design at the board level. The storage module includes a substrate and at least one stacking unit disposed on the substrate. The stacking unit includes a connector vertically connected to the substrate, a memory module inserted into one side of the connector and spaced apart from the substrate, and a plurality of memory chips disposed on the upper and / or lower surface of the substrate in a surface-mount manner; some or all of the plurality of memory chips are located in the orthographic projection area of ​​the memory module on the substrate. The storage module of this embodiment can be a CXL memory module.

[0054] An example of this embodiment is as follows: Figure 4A , Figure 4B and Figure 4C As shown, the storage module of this embodiment conforms to the external dimensions specified by E3.S1T or E3.L 1T. The external dimensions of E3.S1T are 112.75mm (length) × 76mm (width) × 7.5mm (height); the external dimensions of E3.L 1T are 142.2mm (length) × 76mm (width) × 7.5mm (height). The storage module includes a substrate 3 and two stacked units disposed on the substrate 3, arranged sequentially along the width direction of the substrate 3. The first stacked unit includes a connector 71 vertically connected to the substrate 3, a memory module 72 inserted into one side of the connector 71 and spaced apart from the substrate 3, and multiple memory chips 51 disposed on the upper and lower surfaces of the substrate 3 in a patch manner; all memory chips 51 are located within the orthographic projection area of ​​the memory module 72 on the substrate 3. The second stacking unit includes another connector 81 vertically connected to the substrate 3, a memory module 82 inserted into one side of the connector 81 and spaced apart from the substrate 3, and multiple memory chips 52 disposed in a patch manner on the upper surface (the side of the substrate facing the memory module) and the lower surface of the substrate 3; the multiple memory chips 52 are all located in the orthographic projection area of ​​the memory module 72 on the substrate 3.

[0055] Figure 4A This is a top view of the storage module in this embodiment. The substrate is 112.75mm long and 76mm wide, which are equal to the length and width specified in E3.S1T or E3.L1T, respectively. The height of the storage module is equal to the height of connectors 71 and 81, and must be less than or equal to the height of 7.5mm specified in E3.S1T or E3.L1T. The distance from the memory modules 72 and 82 to the substrate is greater than 2.0mm. The memory chips 51 and 52, which are surface-mounted on the upper surface of the substrate 3, are higher than the substrate, but their height is less than 2.0mm. Figure 4C As shown, this creates a gap between the memory chips and memory modules located on the upper surface of the substrate. In other examples, to ensure heat dissipation and signal stability, the height dimension can be reduced through appropriate processes. For instance, an ultra-thin heat sink with liquid-cooled circulation can be filled between the surface-mount chips and memory modules on the substrate to isolate them. In other words, the overall height of the storage module can be reduced by filling the space between the memory modules and the memory chips on the substrate with a heat dissipation medium.

[0056] like Figure 4A As shown, the upper surface of the substrate 3 is also provided with multiple chips, such as a power chip 41 and a controller chip 42. The controller chip 42 integrates a CXL controller and a memory controller. An RCD chip 43 is provided on a memory module 72. A connector (not shown in the figure) is also provided at the end of the substrate 3 near the controller chip 42 in the length direction. The controller chip 42 is disposed between the connector and the stacking unit.

[0057] Figure 4B This is a bottom view of the memory module in this embodiment. It shows that a power chip 41, a CXL controller configuration circuit 44, and an RCD chip 43 are disposed on the lower surface of the substrate. Two sets of memory chips (taking DDR chips as an example) are also provided. One set of memory chips 51 is located within the orthographic projection area of ​​the memory module 72 in the first stacking unit on the substrate, and the other set of memory chips 52 is located within the orthographic projection area of ​​the memory module 82 in the second stacking unit on the substrate. The two sets of memory chips 51 and 52 are arranged sequentially along the width direction of the substrate, with each set including 10 DDR chips.

[0058] In this embodiment, multiple memory chips 51 and 52 disposed on the same surface of substrate 3 are arranged in an array at intervals, divided into two groups of 10 memory chips each. Thus, a total of 40 memory chips are disposed on the two surfaces of the substrate. Assuming the memory module in this embodiment is an HS-DIMM, and the memory chips disposed on substrate 3 and the memory module are both DDR4 or DDR5 chips, with an exemplary size of 11mm x 9mm and a capacity of 2GB, a single memory module can be configured with 20 memory chips, resulting in a maximum capacity of 2GB × 20 = 40GB. Since the storage module in this embodiment is configured with two stacking units, each unit containing one HS-DIMM, the maximum capacity supported by the memory module is 2 × 1 × 40GB = 80GB. Adding the capacity of the 40 memory chips disposed on substrate 3 (40 × 2GB = 80GB), the total capacity is 160GB. The supported Rank number is 160GB / 32GB = 5, effectively increasing memory capacity within a limited space.

[0059] Another example of the storage module structure in this embodiment is similar to... Figure 4A , Figure 4B and Figure 4C The storage modules shown have a basically the same structure, also including two stacked units arranged sequentially along the width of the substrate. Each stacked unit includes a connector vertically connected to the substrate and a memory module horizontally inserted into the connector, as well as multiple memory chips mounted on the upper and lower surfaces of the substrate in a surface-mount manner. Figure 4A , Figure 4B and Figure 4C Unlike the previous example, this example storage module conforms to the E3.S2T or E3.L 2T form factor specifications, and has more space in the height direction, such as... Figure 5 As shown, in this example, the height of the two connectors plus the thickness of the substrate should be less than (or equal to) 16.8mm, and the distance between the two memory modules and the substrate should be greater than 8.4mm. This example storage module can also support a capacity of 160GB. Compared to the previous example, the spacing between the memory chips in different layers is larger, resulting in better heat dissipation and the ability to use more powerful chips.

[0060] In the two examples above, the length direction of connectors 71 and 81 in the stacking unit is consistent with the length direction of substrate 3, and the insertion direction of memory modules 72 and 82 is consistent with the width direction of substrate 3; the area of ​​the orthographic projection area of ​​memory modules 72 and 82 on the substrate is equal to the area of ​​memory modules 72 and 82 (i.e., the memory modules are located directly above the substrate); similar to the previous embodiment, the distance from the insertion interface of the memory module and the connector to the substrate is greater than or equal to the distance from the middle position of the connector in the height direction to the substrate, that is, the insertion position of the memory module is located on the side away from the substrate in the middle position of the connector in the height direction, which is the upper position as seen in the figure.

[0061] In the embodiments described above, after selecting the size of the memory die, the sizes of the memory module and connector can be determined. This means that existing memory modules and / or connectors can be used, or custom-made memory modules and / or connectors can be used. After determining the sizes of the memory module and connector, an optimized spatial structure is designed to maintain a compact structure while also considering heat dissipation requirements.

[0062] The storage module of the above embodiments of this disclosure proposes various structural forms, including: a horizontal stacking layout form under E3.S / L-2T FormFactor, such as... Figure 1A , Figure 2A and Figure 3A The embodiments shown; and the horizontal stacking and tiling layout of memory chips (DDR SDRAM Die) under the E3.S / L-1T and E3.S / L-2T Form Factors, as follows: Figure 4A The embodiment shown in this disclosure utilizes horizontal stacking for memory expansion within the E3.S and E3.L interface size range. Through new spatial layout, structural design, and optimized connection methods, a greater number of memory chips are deployed within a limited physical size, enabling computing nodes to have more memory capacity.

[0063] The logic circuit diagram of a storage module according to an embodiment of this disclosure is as follows: Figure 6 As shown, this logic circuit diagram can be used for storage modules with various structures in the embodiments of this disclosure. As shown, the storage module communicates with the host (CPU or switching network, etc.) via the CXL protocol, with its physical layer based on PCIe. The storage module includes a controller chip and a memory module, with DRAM as an example of memory. The controller chip can integrate a CXL controller and a DDR controller, and the memory module includes an RCD chip, a DRAM device logic module, and multiple DRAM chips (as an example of memory chips). The RCD chip is used to implement functions such as address / control signal buffering and clock signal driving, while the DRAM device logic module is used to implement the core control and data management functions of the DRAM chip. In addition, debug chips and interface circuits can also be included.

[0064] There are control signal channels and data channels between the memory module and the controller chip. In one example, the CXL controller is a CXL 3.x version controller, the DRAM controller is a DDR5 controller, and the DRAM memory chips are DDR5 chips. The data channel mode of the DDR5 chips includes, but is not limited to, x8, and can also be x4, x16, or even x32. The controller chip can support up to 2 channels and 8 ranks; the connector in this embodiment can also be called a DIMM connector.

[0065] This embodiment employs a method of integrating DDR in E3.S and E3.L, based on the CXL controller derived from PCIe and a memory controller supporting multiple RANK and multiple channels to expand memory capacity. The CXL controller and memory controller can be combined into one, such as by integrating them onto a single SOC chip or by using heterogeneous interconnect packaging.

[0066] In the design of the storage module in this embodiment, considerations also need to be given to board-level signal integrity, electrical routing, heat dissipation, and electrical connections. Regarding electrical routing, the main consideration is the alignment of PCIe differential signals, with equal-length processing performed inside the DIMM connectors to maintain signal integrity. In the case of horizontal stacking, space needs to be reserved for lower stacking layers, while higher stacking layers can use custom DIMM connectors. In the case of horizontal stacking, where the projections between stacked layers do not overlap or only partially overlap, the bottom board level requires effective heat dissipation and routing. For example, high-power devices such as logic modules and devices that affect signal integrity, such as capacitors and inductors, should not be placed in the frontal projection area of ​​the substrate; this area is mainly used for routing, although small-capacity capacitors and other devices can also be placed there.

[0067] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A storage module, characterized in that, The system includes a substrate and at least one stacking unit disposed on the substrate. The stacking unit includes a first connector and a second connector disposed opposite to each other on the substrate and perpendicularly connected to the substrate, a first memory module inserted into the side of the first connector facing the second connector, and a second memory module inserted into the side of the second connector. The first memory module, the second memory module and the substrate are disposed parallel to each other and spaced apart. The orthographic projection areas of the first memory module and the second memory module on the substrate partially overlap.

2. The storage module as described in claim 1, characterized in that: The shape of the storage module conforms to the shape specifications specified by E3.S2T or E3.L 2T, and the storage module is a CXL memory module.

3. The storage module as described in claim 1, characterized in that: The length direction of all connectors in the stacking unit is consistent with the length direction of the substrate, and the insertion direction of all memory modules in the stacking unit is consistent with the width direction of the substrate. The second memory module is inserted into the side of the second connector facing away from the first connector, and the second connector is located between the first memory module and the substrate; or, the second memory module is inserted into the side of the second connector facing the first connector, and the second memory module is located between the first connector and the second connector.

4. The storage module as described in claim 1, characterized in that: The storage module also includes a controller chip disposed on the substrate, the controller chip including a CXL controller and a memory controller; The substrate has a connector at one end along its length, and the controller chip is disposed between the connector and the stacked unit.

5. The storage module as described in any one of claims 1 to 4, characterized in that: The substrate has one stacking unit; or, the substrate has two stacking units arranged sequentially in the width direction of the substrate.

6. The storage module as described in any one of claims 1 to 3, characterized in that: The second memory module is inserted into the side of the second connector facing away from the first connector, and the second connector is located between the first memory module and the substrate; the stacking unit further includes: A third connector vertically connected to the substrate, wherein the first connector, the second connector, and the third connector are arranged sequentially along the width direction on the same surface of the substrate; and A third memory module is inserted into the side of the third connector facing away from the second connector. The third memory module and the substrate are parallel to each other and spaced apart from the second memory module. The third connector is located between the second memory module and the substrate, and the orthographic projection areas of the second memory module and the third memory module on the substrate partially overlap.

7. The storage module as described in claim 1, characterized in that: The area of ​​the orthographic projection region of the memory module in the stacked unit onto the substrate is equal to the area of ​​the memory module. The distance from the insertion position of at least one memory module in the stacked unit to the substrate is greater than or equal to the distance from the midpoint of the connector in the height direction to the substrate.

8. A storage module, characterized in that, The device includes a substrate and at least one stacking unit disposed on the substrate. The stacking unit includes a connector vertically connected to the substrate, a memory module inserted into one side of the connector and spaced apart from the substrate, and a plurality of memory chips disposed on the upper surface and / or lower surface of the substrate in a surface mount manner. Some or all of the plurality of memory chips are located in the orthographic projection area of ​​the memory module on the substrate.

9. The storage module as described in claim 8, characterized in that: Two stacking units are disposed on the substrate, and the two stacking units are arranged sequentially in the width direction of the substrate; There are gaps or heat dissipation media between the memory chips disposed on the upper surface of the substrate and the memory modules.

10. The storage module as described in claim 8, characterized in that: The substrate also includes a controller chip, which includes a CXL controller and a memory controller; The substrate has a connector at one end along its length, and the controller chip is disposed between the connector and the stacking unit. The memory chips located on the same surface are arranged in an array at intervals.

11. The storage module as described in claim 8, 9, or 10, characterized in that: The storage module is a CXL memory module; The shape of the storage module conforms to the shape specifications specified in E3.S1T or E3.L 1T; or, the shape of the storage module conforms to the shape specifications specified in E3.S2T or E3.L 2T.

12. The storage module as described in claim 8, 9, or 10, characterized in that: The length direction of the connector is consistent with the length direction of the substrate, and the insertion direction of the memory module is consistent with the width direction of the substrate; The area of ​​the orthographic projection region of the memory module on the substrate is equal to the area of ​​the memory module itself. The distance from the insertion interface of the memory module to the substrate is greater than or equal to the distance from the midpoint of the connector in the height direction to the substrate.

Images