Test data parallel processing apparatus, method and tester

Abstract

The application relates to a test data parallel processing device, method and tester, wherein a host computer issues a code type timing storage parameter for running a current test item to a test unit, the test unit reads code type data and timing parameters of the current test item from a storage module according to the code type timing storage parameter of the current test item, runs a test based on the code type data and the timing parameters, generates capture data of the current test item, and sends the capture data to the storage module for storage. During the running of the current test item, if it is detected that capture data of a previous test item has not been read completely, the capture data of the previous test item is read from the storage module by the test unit for processing, the time for reading and analyzing the capture data is hidden in a test flow of a next test item through a parallel processing mode, the overall occupation time length of back-and-forth communication between the host computer and the test unit is reduced, and the test efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a test data parallel processing apparatus, method and test machine. Background Technology

[0002] During chip testing, the ATE (Automated Test Equipment) sends a series of waveforms to the input pins of the chip under test and compares the timing of the output waveforms of the chip's output pins to determine if the chip meets the required functionalities. The pattern data required for the test is stored in the resource board's storage module. During testing, pattern data is read from the storage module and executed, while capture data is simultaneously stored in the storage module. Each test item is executed serially, sequentially reading pattern data and storing capture data. After all pattern data has been executed, the host computer reads all capture data from the storage module for processing. The entire testing process is time-consuming. Improving testing efficiency is a pressing issue that needs to be addressed. Summary of the Invention

[0003] Therefore, it is necessary to provide a test data parallel processing device, method, and test machine that can improve test efficiency in order to address the above problems.

[0004] The first aspect of this application provides a test data parallel processing device, including a host computer and a test unit, wherein the test unit is connected to the host computer and a storage module; the host computer sends code pattern timing storage parameters for running the current test item to the test unit, and during the running of the current test item, if it is detected that the captured data of the previous test item has not been fully read, the test unit also reads the captured data of the previous test item from the storage module for processing; the test unit reads the code pattern data and timing parameters of the current test item from the storage module according to the code pattern timing storage parameters of the current test item, runs the test based on the code pattern data and timing parameters, generates the captured data of the current test item, and sends it to the storage module for storage.

[0005] The aforementioned parallel test data processing device involves the host computer sending the code pattern and timing storage parameters for running the current test item to the test unit. The test unit, based on these parameters, reads the code pattern data and timing parameters for the current test item from the storage module, runs the test based on the code pattern data and timing parameters, and generates the captured data for the current test item, which is then sent to the storage module for storage. During the execution of the current test item, if the host computer detects that the captured data for the previous test item has not been fully read, it also reads and processes the captured data from the storage module through the test unit. This parallel processing method hides the time for reading and parsing the captured data within the test flow of the next test item, reducing the overall time spent on back-and-forth communication between the host computer and the test unit, thus improving test efficiency.

[0006] In one embodiment, the test unit includes a communication main control module, a read / write control module, a code pattern data processing module, and a capture data control module. The communication main control module is connected to the host computer, the read / write control module, the code pattern data processing module, and the capture data control module. The read / write control module is connected to the code pattern data processing module, the capture data control module, and the storage module. The code pattern data processing module is connected to the capture data control module and the chip under test.

[0007] The communication control module communicates with the host computer, receives and parses the code pattern timing storage parameters used to run the current test item, and uploads the captured data to the host computer. The read / write control module reads the code pattern data and timing parameters from the storage module and sends them to the code pattern data processing module. The code pattern data processing module collects the feedback signal returned by the chip under test based on the code pattern data and timing parameters, and generates captured data based on the feedback signal. The captured data control module processes the captured data and sends it to the storage module for storage through the read / write control module.

[0008] In this embodiment, the communication master control module communicates with the host computer, and the read / write control module, code pattern data processing module, and capture data control module are used to perform corresponding data reading, processing, and storage operations to ensure testing efficiency.

[0009] In one embodiment, the read / write control module includes a read / write arbitration unit and a read / write control unit. The read / write arbitration unit is connected to the communication main control module, the code pattern data processing module, the capture data control module, and the read / write control unit. The read / write control unit is connected to the storage module. The read / write arbitration unit performs operations according to a preset priority, including reading code pattern data and timing parameters from the storage module, writing capture data to the storage module, and uploading capture data to the host computer. Combining the preset priority for data reading, writing, and uploading ensures testing efficiency.

[0010] In one embodiment, the communication master control module sends the code pattern timing storage parameters to the code pattern data processing module; the code pattern data processing module reads the code pattern data and corresponding timing parameters from the storage module through the read / write control module according to the code pattern timing storage parameters, sends them to the cache unit inside the test unit, and returns a preprocessing completion instruction to the host computer through the communication master control module; the communication master control module receives a trigger start instruction issued by the host computer based on the preprocessing completion instruction, and sends the trigger start instruction to the code pattern data processing module; after receiving the trigger start instruction, the code pattern data processing module reads the code pattern data and corresponding timing parameters of the current test item in the cache unit, outputs test signals to the chip under test or collects feedback signals from the chip under test according to the code pattern data and corresponding timing parameters of each cycle, and generates capture data based on the feedback signals and sends it to the capture data control module.

[0011] In this embodiment, the test unit first reads the code pattern data and corresponding timing parameter cache from the storage module. After receiving the trigger start command, it outputs test signals or collects feedback signals from the chip under test according to the code pattern data and corresponding timing parameters for each cycle, thereby further improving test efficiency.

[0012] In one embodiment, the pattern data processing module determines the pattern parameters and timing parameters of the pins of the chip under test corresponding to the current period based on the pattern timing index value of the current period issued by the host computer and a preset mapping table; or, the pattern data processing module determines the pattern parameters of the pins of the chip under test corresponding to the current period based on the pattern data of the current period, and determines the timing parameters of the pins of the chip under test corresponding to the current period based on the index value of the current period issued by the host computer and a preset mapping table; the pattern data processing module executes the output of test signals to the chip under test or the acquisition of feedback signals from the chip under test according to the type of pattern parameters, and generates capture data based on the feedback signals. In this embodiment, the preset mapping table can be used to quickly determine the required parameters, thereby executing the output of test signals to the chip under test or the acquisition of feedback signals from the chip under test, ensuring test efficiency.

[0013] In one embodiment, the communication master control module sends capture data storage parameters to the capture data control module. These parameters include the capture data start address and the capture quantity, where the capture quantity is the maximum number of capture data points for each pin. The capture data control module frames the received capture data according to pins and sends the framed capture data to the read / write control module based on the capture data storage parameters. The read / write control module then stores the framed capture data in the corresponding space of the storage module. The capture data control module also stores the capture quantity for each pin in the corresponding register. In this embodiment, by combining the capture data start address and capture quantity, the capture data is quickly framed and stored in the corresponding space of the storage module, ensuring the efficiency and accuracy of data acquisition and storage.

[0014] In one embodiment, the host computer is further configured to process, based on the capture data storage parameters of the previous or current test item, the capture data read from the storage module by the read-write control module after the read-write control module stores the captured data into the storage module, and the capture count read from the register after the current test item is completed and before the next test item begins. In this embodiment, the host computer performs the capture data reading and processing of each test item in parallel, further improving testing efficiency.

[0015] In one embodiment, the host computer is further configured to preload each test item into the test unit, and the test unit pre-stores the code pattern data and timing parameters of each test item into the storage module. Pre-storing the code pattern data and timing parameters of each test item into the storage module by the host computer reduces the round-trip communication time compared to loading and running test items one by one, thus enabling faster execution of each test item and improving testing efficiency.

[0016] In one embodiment, the host computer has a main thread and several sub-threads. After the main thread calls any of the sub-threads to execute the foreground portion of the current test item's test process, it calls another sub-thread to execute the foreground portion of the next test item's test process. After the sub-thread preloads the test item into the test unit and the test unit completes the execution of the corresponding test item, the foreground portion of the test process is completed, and the background portion of the test process continues to execute, reading and processing the captured data of the corresponding test item. Using a main thread and several sub-threads for multi-threaded parallel processing also improves testing efficiency.

[0017] In one embodiment, the sub-thread dynamically requests a storage area for the captured data of the current test item from the storage module before the test unit executes the current test item, and dynamically releases the storage area for the captured data of the current test item after the test unit completes the execution of the current test item. Requesting a storage area for the captured data in the storage module for each test item and dynamically releasing the corresponding storage area after the test is completed allows for the storage of captured data collected by subsequent test items, reducing the required storage space.

[0018] A second aspect of this application provides a test machine, including a storage module and the aforementioned test data parallel processing device.

[0019] In the aforementioned test unit, the host computer sends the code pattern and timing storage parameters for running the current test item to the test unit. The test unit, based on these parameters, reads the code pattern data and timing parameters for the current test item from the storage module, runs the test based on the code pattern data and timing parameters, and generates the captured data for the current test item, which is then sent to the storage module for storage. During the execution of the current test item, if the host computer detects that the captured data for the previous test item has not been fully read, it also reads the captured data from the storage module through the test unit for processing. This parallel processing method hides the time for reading and parsing the captured data within the test flow of the next test item, reducing the overall time spent on back-and-forth communication between the host computer and the test unit, thus improving test efficiency.

[0020] A third aspect of this application provides a method for parallel processing of test data, comprising: a host computer sending code pattern timing storage parameters for running the current test item to a test unit; during the running of the current test item, if the host computer detects that the captured data of the previous test item has not been fully read, it also reads the captured data of the previous test item from the storage module through the test unit for processing; the test unit obtains the code pattern data and timing parameters of the current test item from the storage module according to the code pattern timing storage parameters of the current test item, runs the test based on the code pattern data and timing parameters, generates the captured data of the current test item, and sends it to the storage module for storage.

[0021] The above-described parallel data processing method involves the host computer sending the code pattern and timing storage parameters for running the current test item to the test unit. The test unit, based on these parameters, reads the code pattern data and timing parameters for the current test item from the storage module, runs the test based on the code pattern data and timing parameters, and generates the captured data for the current test item, which is then sent to the storage module for storage. During the execution of the current test item, if the host computer detects that the captured data for the previous test item has not been fully read, it also reads and processes the captured data from the storage module through the test unit. This parallel processing method hides the time for reading and parsing the captured data within the test flow of the next test item, reducing the overall time spent on back-and-forth communication between the host computer and the test unit, and improving test efficiency. Attached Figure Description

[0022] Figure 1 This is a structural block diagram of a test data parallel processing device in one embodiment;

[0023] Figure 2 This is a schematic diagram of the test data parallel processing device in one embodiment;

[0024] Figure 3 This is a schematic diagram illustrating the determination of code pattern parameters and timing parameters in one embodiment;

[0025] Figure 4 This is a schematic diagram of a multi-threaded concurrency test process in one embodiment;

[0026] Figure 5 This is a schematic diagram of the test item execution vector flow in one embodiment;

[0027] Figure 6 This is a schematic diagram of a multi-threaded concurrent testing process in another embodiment. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. It is understood that the term "connection" in the following embodiments, if the connected circuits, modules, units, etc., transmit electrical signals or data to each other, should be understood as "electrical connection," "communication connection," etc.

[0030] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0031] In one embodiment, such as Figure 1 As shown, a parallel test data processing device is provided, including a host computer 100 and a test unit 200. The test unit 200 is connected to the host computer 100 and a storage module 300. The host computer 100 sends the pattern timing storage parameters for running the current test item to the test unit 200. During the running of the current test item, if it is detected that the capture data (CAPTURE data) of the previous test item has not been fully read, the test unit 200 also reads the capture data of the previous test item from the storage module 300 for processing. Based on the pattern timing storage parameters of the current test item, the test unit 200 reads the pattern data (PATTERN data) and timing parameters (TIMING parameters) of the current test item from the storage module 300, runs the test based on the pattern data and timing parameters, generates the capture data of the current test item, and sends it to the storage module 300 for storage. The host computer 100 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. Portable wearable devices can be smartwatches, smart bracelets, head-mounted devices, etc. The test unit 200 can be set on the FPGA of the resource board in the test machine, and the storage module 300 can be DDR or other types of memory.

[0032] The host computer 100 is also used to preload each test item into the test unit 200, and the test unit 200 pre-stores the code pattern data and timing parameters of each test item into the storage module 300. By using the host computer 100 to pre-store the code pattern data and timing parameters of each test item into the storage module 300, the round-trip communication time can be reduced compared to loading and running the test items one by one, so as to execute each test item quickly and improve testing efficiency.

[0033] Specifically, during the execution of the test project, the host computer 100 first preloads several test items included in the test project into the test unit 200, and sends relevant data such as code pattern data, timing parameters, microinstructions, and data loading parameters (PATTERNBURST parameters) for each test item to the test unit 200. The data loading parameters include the start address and end address of the code pattern data / timing parameters. Based on the data loading parameters in each test item, the test unit 200 pre-stores the corresponding code pattern data and timing parameters into the storage module 300. When running the current test item, the host computer 100 sends the code pattern and timing storage parameters of the current test item to the test unit 200. The code pattern and timing storage parameters include code pattern storage parameters and timing storage parameters. The code pattern storage parameters may specifically include the storage address and data length of the code pattern data, and the timing storage parameters may specifically include the storage address and data length of the timing parameters. The storage address includes the start address and end address. The test unit 200 obtains the code pattern data and timing parameters of the current test item from the storage module 300 according to the received code pattern timing storage parameters, and outputs a test signal to the chip under test (DUT) in combination with the code pattern data and timing parameters, or collects the signal output by the chip under test (DUT), and stores the captured data in the storage module 300 for the host computer 100 to read.

[0034] The host computer 100 also sends the capture data storage parameters for the current test item to the test unit 200. The test unit 200 stores the capture data of the current test item into the corresponding space in the storage module 300 according to the capture data storage parameters. When the host computer 100 is running the current test item, if other test items have been completed but their capture data has not been read, it can run the current test item in parallel and read the capture data of other completed test items, reducing communication waiting time.

[0035] The aforementioned parallel test data processing device involves the host computer 100 sending the code pattern and timing storage parameters for running the current test item to the test unit 200. The test unit 200, based on these parameters, reads the code pattern data and timing parameters of the current test item from the storage module 300, runs the test based on the code pattern data and timing parameters, and generates the captured data for the current test item, which is then sent to the storage module 300 for storage. Even while running the current test item, if the host computer 100 detects that the captured data of the previous test item has not been fully read, it also reads the captured data of the previous test item from the storage module 300 through the test unit 200 for processing. This parallel processing method reduces the time spent on back-and-forth communication between the host computer 100 and the test unit 200, thus improving test efficiency.

[0036] In one embodiment, the host computer 100 is equipped with a main thread and several sub-threads. After the main thread calls any sub-thread to execute the foreground part of the test process for the current test item, it calls another sub-thread to execute the foreground part of the test process for the next test item. After the sub-thread preloads the test item into the test unit 200 and the test unit 200 completes the execution of the corresponding test item, the foreground part of the test process is completed, and the background part of the test process continues to be executed, reading the captured data of the corresponding test item for processing. Using a main thread and several sub-threads for multi-threaded parallel processing also improves testing efficiency.

[0037] In this scenario, a child thread might complete its foreground testing phase for the current test item and then send a feedback message to the main thread. Upon receiving this feedback, the main thread calls another child thread to execute the foreground testing phase of the next test item, while simultaneously executing the background testing phase of the current test item in parallel. Alternatively, the main thread might actively monitor each child thread, and after the current child thread completes its foreground testing phase, it calls another child thread to execute the foreground testing phase of the next test item. Finally, each child thread, after executing its background testing phase, reads and processes the captured data for the corresponding test item, and then notifies the main thread that the process has ended. After receiving these end notifications from all child threads, the main thread checks the test results for all test items to determine whether the test item succeeded or failed.

[0038] Furthermore, before the test unit 200 executes the current test item, the sub-thread dynamically requests a storage area for the captured data of the current test item from the storage module 300, and determines the captured data storage parameters. The test unit 200 then stores the captured data of the current test item into the corresponding space in the storage module 300 according to the captured data storage parameters. After the test unit 200 finishes executing the current test item, the sub-thread dynamically releases the storage area for the captured data of the current test item. This process of requesting a storage area for the captured data in the storage module 300 for each test item and dynamically releasing the corresponding storage area after the test is completed is designed to store the captured data collected by subsequent test items, thereby reducing the required storage space.

[0039] In other embodiments, the foreground test process, dynamic allocation, and release of storage areas for captured data can also be performed through the main thread. Specifically, the host computer 100 is equipped with a main thread and several background threads. Each time the main thread preloads a test item into the test unit 200 and the test unit 200 finishes executing the corresponding test item, it calls any of the background threads to obtain the captured data of the corresponding test item. The other background threads read and process the captured data of the corresponding test item in parallel after the main thread preloads a test item into the test unit 200 and the test unit 200 finishes executing the current test item. During the execution of the test project, the main thread and multiple background threads execute in parallel, which also improves the testing efficiency.

[0040] Furthermore, before executing the current test item in test unit 200, the main thread dynamically requests a storage area for the captured data of the current test item from storage module 300, determines the captured data storage parameters, and then stores the captured data of the current test item into the corresponding space in storage module 300 according to the captured data storage parameters. After test unit 200 finishes executing the current test item, the main thread dynamically releases the storage area for the captured data of the current test item. This process of requesting a storage area for the captured data in storage module 300 for each test item and dynamically releasing the corresponding storage area after the test is completed is designed to store the captured data collected by subsequent test items, thereby reducing the required storage space.

[0041] It is understood that the specific structure of the test unit 200 is not unique. In one embodiment, such as... Figure 2 As shown, the test unit 200 includes a communication main control module 210, a read / write control module 220, a code pattern data processing module 230, and a capture data control module 240. The communication main control module 210 is connected to the host computer 100, the read / write control module 220, the code pattern data processing module 230, and the capture data control module 240. The read / write control module 220 is connected to the code pattern data processing module 230, the capture data control module 240, and the storage module 300 (specifically DDR). The code pattern data processing module 230 is connected to the capture data control module 240 and the chip under test (DUT).

[0042] The communication control module 210 communicates with the host computer 100, receives and parses the code pattern timing storage parameters used to run the current test item, and uploads the captured data to the host computer 100. The read / write control module 220 reads the code pattern data and timing parameters from the storage module 300 and sends them to the code pattern data processing module 230. The code pattern data processing module 230 collects the feedback signal returned by the chip under test (DUT) based on the code pattern data and timing parameters, and generates captured data based on the feedback signal. The captured data control module 240 processes the captured data and sends it to the storage module 300 for storage through the read / write control module 220. In this embodiment, the communication control module 210 communicates with the host computer 100, and the read / write control module 220, code pattern data processing module 230, and captured data control module 240 perform corresponding data reading, processing, and storage operations to ensure testing efficiency.

[0043] The read / write control module 220 includes a read / write arbitration unit 222 and a read / write control unit 224. The read / write arbitration unit 222 is connected to the communication main control module 210, the code pattern data processing module 230, the capture data control module 240, and the read / write control unit 224. The read / write control unit 224 is connected to the storage module 300. The read / write arbitration unit 222 performs operations according to preset priorities: reading code pattern data and timing parameters from the storage module 300, writing capture data to the storage module 300, and uploading capture data to the host computer 100. In this embodiment, reading code pattern data and timing parameters has the highest priority, while uploading capture data has the lowest priority. Combining preset priorities for data reading, writing, and uploading ensures testing efficiency.

[0044] In one embodiment, the communication master control module 210 sends the code pattern timing storage parameters to the code pattern data processing module 230; the code pattern data processing module 230 reads the code pattern data and corresponding timing parameters from the storage module 300 through the read / write control module 220 according to the code pattern timing storage parameters, sends them to the cache unit inside the test unit 200, and returns a preprocessing completion instruction to the host computer 100 through the communication master control module 210; the communication master control module 210 receives the trigger start instruction issued by the host computer 100 based on the preprocessing completion instruction, and sends the trigger start instruction to the code pattern data processing module 230; after receiving the trigger start instruction, the code pattern data processing module 230 reads the code pattern data and corresponding timing parameters of the current test item in the cache unit, and processes them in cycles (CYCLE 0, CYCLE 1, ..., CYCLE 2). The code pattern data and corresponding timing parameters of N) are used to output test signals to the chip under test (DUT) or to collect feedback signals from the chip under test. Based on the feedback signals, capture data is generated and sent to the capture data control module 240.

[0045] The cache unit can be RAM or other types of cache. Each test item contains several cycles, and each cycle contains the pattern data and timing parameters of all pins of the chip under test (DUT). Before running the current test item, the host computer 100 sends the pattern and timing storage parameters of the current test item to the pattern data processing module 230. The pattern data processing module 230 preprocesses the pattern and timing storage parameters according to the pattern and timing storage parameters, reads the pattern data and corresponding timing parameters of the current test item, and stores them in the cache unit. In this embodiment, since the cache unit cannot cache all the pattern data, the pattern data processing module 230 reads part of the pattern data (e.g., the part of the pattern data that needs to be used first during the test) from the storage module 300 through the read / write control module 220 and sends it to the cache unit. Specifically, it can be done serially, first sending all the timing parameters to the cache unit, and then reading part of the pattern data and sending it to the cache unit. After the code pattern data processing module 230 is full, it returns a preprocessing completion instruction to the host computer 100 through the communication master control module 210.

[0046] Upon receiving the trigger start command, the code pattern data processing module 230 reads the timing parameters and partial code pattern data of the current test item from the cache unit, and reads the remaining code pattern data of the current test item from the storage module 300 according to the code pattern timing storage parameters for testing. According to the code pattern data and corresponding timing parameters of each cycle, it outputs test signals to the chip under test (DUT) or collects feedback signals from the chip under test. Based on the feedback signals, it generates capture data and sends it to the capture data control module 240.

[0047] Specifically, whether the pattern data processing module 230 outputs test signals to the chip under test (DUT) or acquires feedback signals from the DUT is determined by the pattern parameters of each cycle. For example, the current test item includes cycles CYCLE0, CYCLE1, etc. Taking cycle CYCLE0 as an example, all pins of the DUT in cycle CYCLE0 share a single microinstruction. Cycle CYCLE0 includes pin0 and pin1, which correspond to pattern data and timing parameters, respectively. The timing parameters include pattern parameters, edge information, etc. When running the current test item, the pattern data processing module 230, based on the type of pattern parameters in each cycle, combines the pattern data and timing parameters of the corresponding cycle to output test signals to the DUT or acquire feedback signals from the DUT, and generates capture data based on the feedback signals. The captured data includes raw result data and failure result data. Depending on the code pattern parameters, the feedback signal from the DUT (Device Under Test) chip is processed differently: First, the feedback signal is compared with the PE (Precision Equipment) chip to obtain the raw result data (pass or fail); second, the feedback signal is compared with the PE chip to obtain the raw result data, and then matched by the code pattern data processing module 230 to obtain the failure result data. The code pattern data processing module 230 sends the captured data (including raw result data and failure result data) to the capture data control module 240 for processing. The communication master control module 210 also sends the capture data storage parameters issued by the host computer 100 to the capture data control module 240. The capture data control module 240, according to the capture data storage parameters, stores the processed captured data into the corresponding space in the storage module 300 through the read / write control module 220.

[0048] In this embodiment, the test unit 200 first reads the code pattern data and corresponding timing parameter cache from the storage module 300. After receiving the trigger start command, it outputs test signals or collects feedback signals from the chip under test according to the code pattern data and corresponding timing parameters for each cycle, thereby further improving test efficiency.

[0049] The method for determining the pattern parameters and timing parameters of each cycle is not unique. In one embodiment, the pattern data processing module 230 determines the pattern parameters and timing parameters of some pins of the chip under test corresponding to the current cycle based on the pattern and timing index value of the current cycle issued by the host computer 100 and a preset mapping table. The preset mapping table can be one or more, and the pattern data processing module 230 performs one or more indexing operations based on the pattern and timing index value issued by the host computer 100 to determine the pattern parameters and timing parameters. In this embodiment, the preset mapping table includes a first mapping table and a second mapping table. Taking one cycle as an example, during the loading phase, the host computer issues micro-instructions, the first pattern and timing index value, and the pattern data and timing parameters of all pins of the chip under test to the test unit 200. The communication master control module 210 sends the code pattern data and timing parameters to the read / write control module 220, which then stores the code pattern data and timing parameters into the storage module 300 according to the data loading parameters. The communication master control module 210 then sends the micro-instruction, the storage address of the first code pattern timing index value, and its length to the code pattern data processing module 230. For example... Figure 3 As shown, during the execution of the current cycle, the pattern data processing module 230 determines the address and length of the second pattern timing index value (FormatSet) of the corresponding pin of the chip under test in the current cycle based on the address and length of the first pattern timing index value (WaveFormSet) and the first mapping table. Then, based on the address and length of the second pattern timing index value (FormatSet) and the second mapping table, it determines the pattern parameters (Format) and timing parameters (timingA / B / C) of the corresponding pin of the chip under test in the current cycle. The pattern data processing module 230 uses microinstructions to call the pattern data and then combines the pattern parameters and timing parameters to perform corresponding output signal / acquisition signal operations.

[0050] The code pattern parameters include three main categories: EC (capture), EP (P / F), and Driver. For example, if the code pattern parameter of pin0 in the current cycle is Driver, the code pattern data processing module 230 sends a signal to pin0 of the chip under test (DUT) based on the code pattern data. If the code pattern parameter of pin0 in the current cycle is EC (capture), the code pattern data processing module 230 collects the raw result data (pass or fail) after comparing the feedback signal from the PE chip to the DUT. If the code pattern parameter of pin0 in the current cycle is P / F, the PE chip obtains the raw result data after comparing the feedback signal from the DUT, and the code pattern data processing module 230 matches the raw result data with the code pattern data of the current cycle to obtain the failure result data.

[0051] In another embodiment, the code pattern data processing module 230 can also determine the code pattern parameters of the pins of the chip under test (DUT) corresponding to the current cycle based on the code pattern data of the current cycle, and determine the timing parameters of the pins of the DUT corresponding to the current cycle based on the index value of the current cycle issued by the host computer 100 and a preset mapping table. Specifically, 01Z in the code pattern data represents the driver direction, and the code pattern data processing module 230 sends a signal to the DUT based on the code pattern data; C in the code pattern data represents capture data, and the code pattern data processing module 230 collects the original result data (pass or fail) after comparing the feedback signal of the PE chip with the DUT; HLMX in the code pattern data represents the compare direction, and the PE chip obtains the original result data after comparing the feedback signal of the DUT. The code pattern data processing module 230 matches the original result data with the code pattern data of the current cycle to obtain the failure result data. The timing parameters can also be determined by indexing once or multiple times using the index value issued by the host computer 100 to determine the code pattern parameters and timing parameters. In this embodiment, the preset mapping table includes a first mapping table and a second mapping table. The code pattern data processing module 230 determines the second index value of the pins of the chip under test corresponding to the current cycle based on the first index value issued by the host computer 100 and the preset first mapping table. Then, it determines the timing parameters of the pins of the chip under test corresponding to the current cycle based on the second index value and the preset second mapping table.

[0052] The above presents two methods for determining code pattern parameters and timing parameters, which can be selected according to actual needs. Combining these with a preset mapping table allows for rapid determination of the required parameters, enabling the output of test signals to the chip under test (DUT) or the acquisition of feedback signals from the DUT, ensuring testing efficiency.

[0053] The method by which the capture data control module 240 processes the captured data is not unique. In one embodiment, the capture data storage parameters include the capture data start address and the capture quantity, where the capture quantity is the maximum number of capture data points for each pin. The actual number of captured data points stored can be less than the capture quantity. The capture data control module 240 frames the received capture data according to pins and sends the framed capture data to the read / write control module 220 according to the capture data storage parameters. The read / write control module 220 then stores the framed capture data in the corresponding space of the storage module 300. The capture data control module 240 stores the capture quantity for each pin in the corresponding register. In this embodiment, by combining the capture data start address and the capture quantity, the capture data is quickly framed and stored in the corresponding space of the storage module 300, ensuring the efficiency and accuracy of data acquisition and storage.

[0054] Furthermore, the host computer 100 is also used to process the captured data read from the storage module 300 by the read / write control module 220 after the captured data is stored in the storage module 300, and during the execution of the next test item, based on the captured data storage parameters of the previous or current test item. It also processes the number of captured data read from the register after the current test item is completed and before the next test item begins. By having the host computer 100 perform parallel reading and processing of captured data for each test item, testing efficiency is further improved.

[0055] The parallel test data processing device provided in this application separates the test result acquisition and analysis process from the chip testing process, thereby improving the testing efficiency of the test machine. Specifically, the chip testing process is placed in the foreground of the main thread of the host computer 100, while the acquisition and analysis process of captured data is placed in the background thread of the host computer 100. Combined with a multi-threaded and thread pool model, the chip test runs in parallel using multiple threads, thus improving testing efficiency. This allows for safe and efficient scheduling of multi-threaded software, enhancing the overall testing efficiency of the test machine. To distinguish the captured data generated when each thread executes a test item, the main thread requests a space from the storage module 300 to store the captured data each time a test item is executed, and configures the captured data storage parameters to the test unit 200. After the captured data acquisition is complete, the storage space area of ​​the storage module 300 is dynamically released for subsequent test item execution.

[0056] like Figure 4 As shown, in the multi-threaded concurrent execution architecture, the main thread continuously performs the foreground testing process of the chip, while multiple background threads concurrently execute the chip test result acquisition and parsing process. Specifically, when the operator clicks the run button on the interactive interface of the host computer 100 to start the chip test project, the main thread of the host computer 100 begins to execute the foreground testing process of test item one, such as... Figure 5 As shown, it includes the following steps 1 to 5.

[0057] Step 1: The host computer 100 is responsible for controlling the start / end of the test and parsing and processing the captured data generated during the test. First, the host computer 100 preloads each test item into the DDR.

[0058] Before starting test item one, the host computer 100 sends the capture data storage parameters for storing the captured data to the capture data control module 240 on the FPGA, and sends the DC, AC and vector parameters used to run test item one. The vector parameters include code pattern timing storage parameters (timing parameters, code pattern data storage address, data length, etc.).

[0059] After the host computer sends the parameters, it checks whether the FPGA preprocessing is complete. The code pattern data processing module 230 on the FPGA, according to the configured code pattern timing storage parameters, first moves part of the code pattern data and all timing parameters from DDR to the internal cache RAM on the FPGA. When the cache is full, the code pattern data processing module 230 returns a preprocessing completion instruction and sends it to the host computer 100 through the communication master control module 210.

[0060] After receiving the preprocessing completion instruction, the host computer 100 sends a trigger start instruction to the FPGA. Upon receiving the trigger start instruction, the code pattern data processing module 230 on the FPGA begins to run test item one.

[0061] Step 2: All instructions sent by the host computer 100 need to be processed by the communication master control module 210 on the FPGA. The communication master control module 210 is responsible for performing protocol parsing operations on all read and write instructions and distributing the parsed instructions to the corresponding modules. For example, the communication master control module 210 sends the capture data storage parameters to the capture data control module 240, sends the code pattern timing storage parameters and trigger start instructions of test item one to the code pattern data processing module 230, and distributes the read and write instructions to the read and write control module 220.

[0062] Step 3: The process of running Test Item 1 is as follows: After receiving the trigger start command, the code pattern data processing module 230 reads the code pattern data and timing parameters of Test Item 1 from the FPGA's internal cache RAM, as well as the remaining code pattern data of Test Item 1 in the DDR, and executes it cycle by cycle to send signals to the chip under test (DUT) or to acquire signals output by the DUT. Specifically, the code pattern data processing module 230 analyzes each pin individually in conjunction with the code pattern parameters to determine whether it is necessary to acquire capture data. After one cycle is completed, the code pattern data processing module 230 sends the capture data of the current cycle to the capture data control module 240.

[0063] Step 4: The capture data control module 240 organizes the received capture data into frames according to pins, forming a row of data with each 480 bits. The framed data is then written to the DDR space corresponding to the capture data storage parameters. The framing format can be that after capturing data from one pin is framed into a row, the next row of capture data is framed.

[0064] Step 5: After the code pattern data of all pins in all cycles of Test Item 1 has been executed, the capture data control module 240 stores the capture count of each pin in the corresponding internal register. Each pin has only one capture data in one cycle. The host computer 100 can obtain the capture count of Test Item 1 by directly reading the register. At this point, the front-end test process of Test Item 1 is completed.

[0065] After the main thread completes the foreground test process for test item one, it switches to background thread 1 to execute the test result retrieval and parsing process for test item one. The process of background thread 1 retrieving the test result of test item one is shown in step 6.

[0066] Step 6: The background thread 1 of the host computer 100 starts reading the captured data of Test Item 1 from DDR for processing according to the capture data storage parameters and capture quantity of Test Item 1. At this time, the main thread runs the foreground test process of Test Item 2, which is carried out in parallel with the background thread 1 to read and process the test results of Test Item 1, reducing time consumption.

[0067] The main thread and background thread 1 execute simultaneously. The main thread continues to execute the foreground part of the test process for test item 2. After the foreground test process for test item 2 is completed, it switches to background thread 2 to execute the test result acquisition and parsing process for test item 2.

[0068] Before the chip test project is completed, the main thread sequentially executes the foreground test process of each test item. After the foreground process of each test item is completed, it is converted into a background thread to execute the test result acquisition and parsing process. During the execution of the chip test project, multiple background threads and one main thread execute in parallel.

[0069] After all background threads have completed the test result acquisition and parsing process, the dynamically allocated DDR storage space resources will be released, and the main thread will be notified that the background test process has been completed. After receiving the completion status of all background threads, the main thread will execute the end process (FlowEnd) of the test project to complete the chip test.

[0070] Furthermore, the parallel processing device for test data provided in this application can also place the chip testing process, the acquisition of captured data, and the analysis process all in a sub-thread of the host computer 100, with the main thread of the host computer 100 responsible for calling the sub-threads sequentially. Each time a test item is executed, the sub-thread requests a space from the storage module 300 to store the captured data and configures the captured data storage parameters to the test unit 200. After the captured data acquisition is complete, the sub-thread dynamically releases the storage space area of ​​the storage module 300 for subsequent test item execution.

[0071] like Figure 6 As shown, in the multi-threaded concurrent execution architecture, when the operator clicks the run button on the interactive interface of the host computer 100 to start the chip test project, the main thread of the host computer 100 calls sub-thread 1 to start executing the foreground part of the test process of test item one, such as... Figure 5As shown, steps 1 to 5 are included and will not be repeated here. After sub-thread 1 completes the foreground test process of test item 1, the main thread calls sub-thread 2 to execute the foreground test process of test item 2; at the same time, sub-thread 1 executes the background test process of test item 1 in parallel, reading and processing the captured data of the corresponding test item.

[0072] Before the chip test project is completed, the main thread is responsible for calling each sub-thread to execute the foreground and background test processes of the corresponding test items. After each sub-thread completes the foreground test process of a test item, the main thread calls the next sub-thread to execute the foreground test process of the next test item. At the same time, the threads that have completed the foreground test process continue to execute the background test process. During the execution of the chip test project, multiple sub-threads and one main thread execute in parallel.

[0073] After completing the background testing process, multiple sub-threads release the dynamically allocated DDR storage space resources and notify the main thread that the background testing process has been completed. After receiving the completion status of all sub-threads, the main thread executes the final process of the test project to complete the chip test.

[0074] In one embodiment, a test machine is also provided, including a storage module and the aforementioned test data parallel processing device. The storage module may be DDR or other types of memory.

[0075] In the aforementioned test unit, the host computer sends the code pattern and timing storage parameters for running the current test item to the test unit. The test unit, based on these parameters, reads the code pattern data and timing parameters for the current test item from the storage module, runs the test based on the code pattern data and timing parameters, and generates the captured data for the current test item, which is then sent to the storage module for storage. During the execution of the current test item, if the host computer detects that the captured data for the previous test item has not been fully read, it also reads the captured data from the storage module through the test unit for processing. This parallel processing method hides the time for reading and parsing the captured data within the test flow of the next test item, reducing the overall time spent on back-and-forth communication between the host computer and the test unit, thus improving test efficiency.

[0076] In one embodiment, a method for parallel processing of test data is also provided, comprising: a host computer sending code pattern timing storage parameters for running the current test item to a test unit; during the running of the current test item, if the host computer detects that the captured data of the previous test item has not been fully read, it also reads the captured data of the previous test item from the storage module through the test unit for processing; the test unit obtains the code pattern data and timing parameters of the current test item from the storage module according to the code pattern timing storage parameters of the current test item, runs the test based on the code pattern data and timing parameters, generates the captured data of the current test item, and sends it to the storage module for storage.

[0077] It is understood that the specific embodiments of this method have been explained in detail in the above-mentioned test data parallel processing device, and will not be repeated here.

[0078] The above-described parallel data processing method involves the host computer sending the code pattern and timing storage parameters for running the current test item to the test unit. The test unit, based on these parameters, reads the code pattern data and timing parameters for the current test item from the storage module, runs the test based on the code pattern data and timing parameters, and generates the captured data for the current test item, which is then sent to the storage module for storage. During the execution of the current test item, if the host computer detects that the captured data for the previous test item has not been fully read, it also reads and processes the captured data from the storage module through the test unit. This parallel processing method hides the time for reading and parsing the captured data within the test flow of the next test item, reducing the overall time spent on back-and-forth communication between the host computer and the test unit, and improving test efficiency.

[0079] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A test data parallel processing device, characterized in that, It includes a host computer and a testing unit, wherein the testing unit is connected to the host computer and the storage module; The host computer sends the code pattern timing storage parameters for running the current test item to the test unit. In addition, if it is detected that the captured data of the previous test item has not been read in the process of running the current test item, the test unit also reads the captured data of the previous test item from the storage module for processing. The testing unit reads the code pattern data and timing parameters of the current test item from the storage module according to the code pattern timing storage parameters of the current test item, runs the test based on the code pattern data and timing parameters, generates the capture data of the current test item, and sends it to the storage module for storage.

2. The test data parallel processing device according to claim 1, characterized in that, The test unit includes a communication main control module, a read / write control module, a code pattern data processing module, and a capture data control module. The communication main control module is connected to the host computer, the read / write control module, the code pattern data processing module, and the capture data control module. The read / write control module is connected to the code pattern data processing module, the capture data control module, and the storage module. The code pattern data processing module is connected to the capture data control module and the chip under test. The communication main control module communicates with the host computer, receives the code pattern timing storage parameters for running the current test item, parses and sends them down, and uploads the captured data to the host computer; The read / write control module reads the code pattern data and timing parameters from the storage module and sends them to the code pattern data processing module; The code pattern data processing module acquires the feedback signal returned by the chip under test based on the code pattern data and timing parameters, and generates capture data based on the feedback signal. After processing the captured data, the capture data control module sends it to the storage module for storage via the read / write control module.

3. The test data parallel processing device according to claim 2, characterized in that, The read / write control module includes a read / write arbitration unit and a read / write control unit. The read / write arbitration unit is connected to the communication main control module, the code pattern data processing module, the capture data control module, and the read / write control unit. The read / write control unit is connected to the storage module. The read / write arbitration unit performs operations according to a preset priority: reading code pattern data and timing parameters from the storage module, writing captured data to the storage module, and uploading captured data to the host computer.

4. The test data parallel processing device according to claim 2, characterized in that, The communication master control module sends the code pattern timing storage parameters to the code pattern data processing module; The code pattern data processing module reads the code pattern data and corresponding timing parameters from the storage module through the read / write control module according to the code pattern timing storage parameters, sends them to the cache unit inside the test unit, and returns a preprocessing completion instruction to the host computer through the communication main control module; The communication master control module receives the trigger start command issued by the host computer based on the preprocessing completion command, and sends the trigger start command to the code pattern data processing module; After receiving the trigger start command, the code pattern data processing module reads the code pattern data and corresponding timing parameters of the current test item in the cache unit, outputs test signals to the chip under test or collects feedback signals from the chip under test according to the code pattern data and corresponding timing parameters of each cycle, and sends the captured data generated according to the feedback signals to the captured data control module.

5. The test data parallel processing device according to claim 4, characterized in that, The code pattern data processing module determines the code pattern parameters and timing parameters of the pins of the chip under test corresponding to the current period based on the code pattern timing index value of the current period issued by the host computer and a preset mapping table; or, the code pattern data processing module determines the code pattern parameters of the pins of the chip under test corresponding to the current period based on the code pattern data of the current period, and determines the timing parameters of the pins of the chip under test corresponding to the current period based on the index value of the current period issued by the host computer and a preset mapping table. The code pattern data processing module outputs test signals to the chip under test or collects feedback signals from the chip under test according to the type of code pattern parameters, and generates capture data based on the feedback signals.

6. The test data parallel processing device according to claim 2, characterized in that, The communication master control module sends the capture data storage parameters to the capture data control module; the capture data storage parameters include the capture data start address and the capture quantity, wherein the capture quantity is the maximum number of capture data per pin; The capture data control module frames the received capture data according to pins, and sends the framed capture data to the read-write control module according to the capture data storage parameters, so that the read-write control module stores it in the corresponding space of the storage module. The capture data control module stores the capture count for each pin into the corresponding register.

7. The test data parallel processing device according to claim 2, characterized in that, The host computer is also used to process the captured data of the previous test item or the current test item read from the storage module by the read-write control module and the number of captured data read from the register after the current test item is completed and before the next test item starts, based on the captured data storage parameters of the previous test item or the current test item.

8. The test data parallel processing apparatus according to any one of claims 1-7, characterized in that, The host computer is also used to preload each test item into the test unit, and the test unit pre-stores the code pattern data and timing parameters of each test item into the storage module.

9. The test data parallel processing apparatus according to any one of claims 1-7, characterized in that, The host computer is equipped with a main thread and several sub-threads. After the main thread calls any of the sub-threads to execute the foreground part of the test process for the current test item, it calls another sub-thread to execute the foreground part of the test process for the next test item. Once the sub-thread preloads the test items into the test unit and the test unit has completed executing the corresponding test items, the front-end test process is completed, and the back-end test process continues to execute, reading and processing the captured data of the corresponding test items.

10. The test data parallel processing apparatus according to claim 9, characterized in that, Before the test unit executes the current test item, the sub-thread dynamically requests a storage area for the captured data of the current test item from the storage module, and after the test unit finishes executing the current test item, it dynamically releases the storage area for the captured data of the current test item.

11. A testing machine, characterized in that, It includes a storage module and a test data parallel processing device as described in any one of claims 1-10.

12. A method for parallel processing of test data, characterized in that, include: The host computer sends the code pattern timing storage parameters for running the current test item to the test unit; During the execution of the current test item, if the host computer detects that the captured data of the previous test item has not been fully read, it will also read the captured data of the previous test item from the storage module through the test unit for processing. The testing unit obtains the code pattern data and timing parameters of the current test item from the storage module according to the code pattern timing storage parameters of the current test item, runs the test based on the code pattern data and timing parameters, generates the capture data of the current test item, and sends it to the storage module for storage.

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