FPGA-based virtual FIFO data caching method, system and medium

Abstract

The application belongs to the field of signal processing, and discloses a virtual FIFO data cache method and system based on FPGA and a medium. A DDR write module writes AXIS protocol data into a DDR memory through a DDR controller according to a preset burst length, and transmits a total number of write burst packets and a valid length of a last packet to a DDR read module; the DDR read module calculates a read address according to the information transmitted by the DDR write module and transmits the read address to the DDR controller, the DDR controller reads data from the DDR memory, and the DDR read module packs the data into an AXIS protocol output. The virtual FIFO DDR cache space configuration is realized, direct DDR cache space caching and reading are achieved, the data length does not need to be known in advance, address calculation is not needed in the module periphery, the FPGA resources consumed are less than those consumed by an existing Xilinx Virtual FIFO cache scheme, and the flexibility of signal processing system design is improved.

Description

Technical Field

[0001] This invention relates to the field of signal processing, and specifically to a virtual FIFO data caching method, system, and medium based on FPGA. Background Technology

[0002] FPGAs offer advantages such as high parallel computing speed and high data throughput, making them a common choice for implementing complex signal processing algorithms. However, when computational complexity is high, pipelining is not feasible. Data needs to be cached in DDR memory during processing, and retrieved from DDR for computation when needed. DDR read / write operations are complex, requiring prior knowledge of the cached data length and strict mapping between write burst length and data packet length; otherwise, read / write crashes can occur. To simplify DDR read / write operations based on the AXIS protocol, Xilinx provides an IP core called Virtual FIFO (VFIFO). This IP core can directly interface with the user's AXIS interface, outputting AXIS interface data without requiring address operations on the user port. However, even with FPGA-external DDR memory space reaching gigabytes or tens of gigabytes, the maximum cache capacity of Xilinx VFIFO is only 256MB, while complex signal processing algorithms can handle data in the gigabyte range. The limited capacity of VFIFO restricts its application in signal processing system design. Summary of the Invention

[0003] To address the problems in existing technologies and achieve flexible configuration of virtual FIFO cache space, this application provides a virtual FIFO data caching method, system, and medium based on FPGA.

[0004] Firstly, an FPGA-based virtual FIFO data caching method is provided, employing the following technical solution:

[0005] Configure the operating parameters of the virtual FIFO, including the start address of the DDR read / write space, the end address of the DDR read / write space, the length of each read / write burst, and the input / output data bit width;

[0006] The DDR write module writes AXIS protocol data to the DDR memory through the DDR controller according to the preset burst length, and transmits the total number of write burst packets and the effective length of the last packet to the DDR read module;

[0007] The DDR read module receives the total number of write burst packets and the effective length of the last packet from the DDR write module, passes the DDR read address to the DDR controller, the DDR controller reads the data from the DDR memory, and then the DDR read module packages the data into AXIS protocol output.

[0008] Furthermore, when the DDR write module writes AXIS protocol data to the DDR memory through the DDR controller according to a preset burst length, it includes the following steps:

[0009] 2-1) The DDR write module receives the data stream sent by the upstream device through the AXIS interface and counts each burst of data packets;

[0010] 2-2) When the DDR write module receives a burst of data from the upstream device, it generates the DDR write address for that burst data packet and passes the DDR write address to the DDR controller. When it receives the s_axis_tlast signal from the upstream device, it indicates that it has received all the data that needs to be buffered. The DDR write module then determines whether the effective length of the last packet is equal to the burst length: if the effective length of the last packet is equal to the burst length, it writes the data to the DDR memory in a single burst write; if the effective length of the last packet is not equal to the burst length, it performs a padding operation on the last packet data, padding its length upwards to the single burst length, and then writes the data to the DDR memory in a single burst write.

[0011] 2-3) The DDR controller stores data into the DDR memory based on the DDR write address, burst length, and data.

[0012] 2-4) When all data has been written, the DDR write module will pass the total number of write burst packets and the effective length of the last packet to the DDR read module.

[0013] Furthermore, when the DDR controller stores data into the DDR memory based on the DDR write address, burst length, and data, the specific steps are as follows:

[0014] The DDR controller starts from the beginning address of the DDR read / write space. When generating the address validity signal for each burst data packet, it determines whether the current write address has exceeded the end address. If it has not exceeded the end address, the address of each subsequent burst transmission will increment sequentially according to the total number of bytes in a single burst. If it has exceeded the end address, the DDR write address needs to start again from the beginning address.

[0015] Furthermore, the DDR read module calculates the DDR read address based on the total number of write burst packets and the effective length of the last packet, and passes it to the DDR controller. The DDR controller reads the data from the DDR memory, and the DDR read module then packages the data into an AXIS protocol output, including the following steps:

[0016] 3-1) The DDR read module receives the total number of write burst packets and the effective length of the last packet from the DDR write module, and counts the total number of write burst packets;

[0017] 3-2) When the received address packet count is greater than 1, start the DDR read operation, generate the corresponding read address, and send the DDR read address to the DDR controller;

[0018] 3-3) When outputting the last packet of data, the data of the last packet is truncated to the valid length according to the last packet valid length passed by the DDR write module to ensure that the input data and output data are consistent.

[0019] Furthermore, when the received address packet count is greater than 1, the DDR read operation is initiated, a corresponding read address is generated, and the DDR read address is transmitted to the DDR controller, as follows:

[0020] The DDR read address starts from the beginning address of the DDR read / write space. When the address validity signal for each burst data packet is generated, it is determined whether the current read address has exceeded the end address: if it has not exceeded the end address, the address of each subsequent burst transmission is incremented sequentially according to the total number of bytes in a single burst; if it has exceeded the end address, the read address restarts from the beginning address of the DDR read / write space.

[0021] Secondly, an FPGA-based virtual FIFO data caching system is provided, comprising the following modules:

[0022] The parameter configuration module is used to configure the operating parameters of the virtual FIFO, including the DDR read / write space start address, DDR read / write space end address, read / write burst length, and input / output data bit width.

[0023] The DDR write module, integrated inside the FPGA, is used to write AXIS protocol data into the DDR memory through the DDR controller according to the preset burst length, and to transmit the total number of write burst packets and the effective length of the last packet to the DDR read module.

[0024] The DDR read module, integrated inside the FPGA, is used to receive the total number of write burst packets and the effective length of the last packet transmitted by the DDR write module, and to pass the DDR read address to the DDR controller. The DDR controller reads the data from the DDR memory, and then the DDR read module packages it into AXIS protocol output.

[0025] The DDR controller, connected to the DDR read module and DDR write module via an internal bus, is used to receive read / write requests and perform address mapping.

[0026] DDR memory is used to store AXIS protocol data received by the DDR write module.

[0027] Thirdly, a computer-readable storage medium is provided, on which a computer program is stored, wherein when the computer program is executed by a processor, the steps of the FPGA-based virtual FIFO data caching method as described in any of the first aspects are implemented.

[0028] The beneficial effects of this invention are as follows:

[0029] This application enables the configuration of DDR cache free space in a virtual FIFO by configuring the start and end addresses of the DDR read / write space, thus adjusting the cache size. This is superior to the 256MB cache space of Xilinx's existing VFIFO cache solution. It supports configurable input and output data bit widths and features backward compatibility and scalability.

[0030] This application enables large amounts of data based on the AXIS protocol to be directly cached and read from the DDR cache space, making full use of the DDR cache space, simplifying data caching operations, eliminating the need to know the data length in advance, and eliminating the need for address calculation and address allocation operations outside the module. Furthermore, it consumes fewer FPGA resources than the existing Xilinx Virtual FIFO caching solution, thus improving the flexibility of signal processing system design. Attached Figure Description

[0031] Figure 1 This is a framework diagram of an FPGA-based virtual FIFO data caching system according to an embodiment of the present invention;

[0032] Figure 2 This is a framework diagram of the DDR write module in an embodiment of the present invention;

[0033] Figure 3 This is a framework diagram of the DDR read module in an embodiment of the present invention;

[0034] Figure 4 This is a flowchart of an FPGA-based virtual FIFO data caching method according to an embodiment of the present invention. Detailed Implementation

[0035] The present invention will now be described in further detail.

[0036] One embodiment of this application is a virtual FIFO data caching system based on FPGA, such as... Figure 1 As shown, it includes a parameter configuration module, a DDR write module, a DDR read module, a DDR controller, and a DDR memory, as detailed below:

[0037] The parameter configuration module, integrated within the FPGA chip, is used to configure the operating parameters of the virtual FIFO. These parameters include the physical address range of the DDR memory (including start and end addresses), the burst length for each read / write operation, and the input / output data bit width. The DDR memory is configured as a unified shared storage space for both written and read data. The physical address range of the DDR memory determines the available cache space occupied by the virtual FIFO within the DDR, and can be configured and modified according to system requirements. Generally, the start address is set to 0, and the end address can be set according to actual system needs, with a maximum value equal to the cache space size of the DDR chip. The burst length for each read / write operation refers to the number of consecutive data steps transmitted on the same line after a single read / write command is triggered, determining the data packet size (total data in one burst) and address offset (the byte difference between the current address and the burst start address). The input / output data bit width refers to the bit width of the TDATA signal (the "data signal" in the AXIS protocol, used to transmit the actual payload data), representing the number of parallel data bits that can be carried in one transmission.

[0038] DDR write module, such as Figure 2 As shown, integrated within the FPGA chip, AXIS protocol data is written to the DDR memory via the DDR controller according to a preset burst length, and the total number of write burst packets and the effective length of the last packet are transmitted to the DDR read module. Specifically:

[0039] The DDR write module uses the AXIS bus protocol as its data interface. It writes AXIS protocol data to the DDR controller according to the DDR read / write burst length preset by the parameter configuration module, including the following signals:

[0040] s_axis_tdata: Data input signal, which carries the data payload sent from the upstream device to this slave device;

[0041] s_axis_tvalid: Valid input signal. This signal is driven by the upstream device. When this signal is at a valid level (e.g., high level), it indicates that the data provided by the upstream device on s_axis_tdata in the current clock cycle is valid.

[0042] s_axis_tready: Ready output signal, driven by this slave device. When this signal is active, it indicates that this slave device is ready to receive data from the upstream device.

[0043] s_axis_tlast: End input signal. This signal is driven by the upstream device. When this signal is at an active level, it indicates that the data currently being transmitted is the last data unit of the entire data packet.

[0044] The handshake rules for data transmission are as follows: data on s_axis_tdata is sampled and written to the data buffer only when both s_axis_tvalid and s_axis_tready are high; if either signal is invalid, no data transmission occurs in that cycle. When the s_axis_tlast signal is valid, it indicates that the currently transmitted data belongs to the end of all data packets, and the DDR write module uses this to identify and process packet boundaries.

[0045] The DDR write module counts the received AXIS interface data. When the count reaches the single burst length, the DDR write module generates the corresponding DDR write address in the address packet and passes the DDR write address to the DDR controller. The DDR controller stores the data in the DDR memory according to the DDR write address, burst length, and data.

[0046] The DDR write address starts from the beginning address of the DDR read / write space. When the address validity signal for each burst data packet is generated, it is determined whether the current write address has exceeded the end address of the DDR read / write space.

[0047] If the DDR write address does not exceed the end address of the DDR read / write space, the write address of each subsequent burst transfer will increase sequentially according to the total number of bytes in a single burst.

[0048] If the DDR write address exceeds the end address of the DDR read / write space, the DDR write address needs to start again from the beginning address of the DDR read / write space.

[0049] When the DDR write module receives the s_axis_tlast signal from the AXIS interface, it determines whether the effective length of the last packet equals the burst length:

[0050] If the effective length of the last packet is equal to the burst length, there is no need to pad the last packet data. It is directly written to the DDR controller in burst transmission mode. The DDR controller writes the data to the DDR memory and updates the burst counter.

[0051] If the effective length of the last packet is not equal to the burst length, it means that the length of the input data is not an integer multiple of the single burst length. In this case, the last packet needs to be padded to the single burst length to ensure that each written burst packet has the same burst length. After padding, the burst data packet is sent to the DDR controller, which writes the data to the DDR memory and updates the burst counter.

[0052] Once all data has been written, the DDR write module will transmit the total number of write burst packets and the effective length of the last packet to the DDR read module.

[0053] DDR read module, such as Figure 3 As shown, integrated within the FPGA chip, it receives the total number of write burst packets and the effective length of the last packet from the DDR write module, passes the DDR write address to the DDR controller, the DDR controller reads the data from the DDR memory, and then the DDR read module packages it into AXIS protocol output. Specifically:

[0054] The DDR read module uses the AXIS bus protocol as its data interface. It reads data from the DDR memory in packets, packages them into AXIS protocol packets, and outputs them. The AXIS interface signals involved are defined as follows:

[0055] m_axis_tdata, the data output signal, is driven by the master device and is used as a bus signal to transmit data load;

[0056] m_axis_tvalid is a valid output signal driven by the master device. When this signal is at a valid level (such as high level), it indicates that the current data provided by the master device on the data signal is valid data.

[0057] m_axis_tready is a ready input signal driven by the slave device. When this signal is active, it indicates that the slave device is ready to receive data from the master device.

[0058] m_axis_tlast is the end output signal, driven by the master device. When this signal is active, it indicates that the currently transmitted data is the last data in a data packet.

[0059] Within one clock cycle, the current data on m_axis_tdata is considered to have been successfully transmitted from the master device to the slave device if and only if both m_axis_tvalid and m_axis_tready are at an active level.

[0060] The DDR read module counts the total number of received write burst packets. When the count of received address packets (AXIS control information transmission packets sent by the DDR write module to the DDR read module, which do not carry valid data payload but contain configuration parameters such as the start address, burst length, and data bit width required for this read operation) is greater than 1, the DDR controller can initiate the read operation and generate a DDR read address. The DDR read address also starts from the start address. When generating the address validity signal for each burst data packet, it is determined whether the current read address has exceeded the end address. If it has not exceeded the end address, the read address for each subsequent burst transmission increases sequentially according to the total number of bytes in a single burst. If the end address is exceeded, the read address needs to start again from the start address. When outputting to the address of the last packet, the data of the last packet is output. This requires using the last packet validity length parameter passed from the DDR write module to truncate the data of the last packet to the validity length, thus ensuring that the output length of the DDR read module is consistent with the input length of the DDR write module, i.e., the input data and output data are consistent.

[0061] The DDR controller, integrated inside the FPGA, uses an IP core provided by Xilinx and is connected to the DDR read module and DDR write module via an internal bus. It instantiates the physical management of the DDR memory and is used to receive read and write requests, perform address mapping, and generate DDR timing.

[0062] The DDR memory, located outside the FPGA, is connected to the DDR controller via a physical interface and is used to store AXIS protocol data received by the DDR write module.

[0063] Another embodiment of this application is a virtual FIFO data caching method based on FPGA, such as... Figure 4 As shown, it includes the following steps:

[0064] Step 1: Configure the virtual FIFO's operating parameters. These parameters include the start and end addresses of the DDR read / write space, the burst length of each DDR read / write operation, and the bit width of the input / output data, as detailed below:

[0065] The start and end addresses of the DDR read / write space determine the available space size of the DDR cache in the virtual FIFO. They can be configured and modified according to system requirements. Generally, the start address is set to 0, and the end address can be set according to the actual needs of the system. The maximum value can be set to the cache space size of the DDR chip.

[0066] The burst length of each DDR read / write operation refers to the number of data packets continuously transmitted on the same line after a single read / write command is triggered. It determines the data packet size (total data in a burst) and address offset (the difference in bytes between the current address and the burst start address) of each read / write operation.

[0067] The bit width of input and output data refers to the bit width of the TDATA signal (the "data signal" in the AXIS protocol, used to transmit the actual payload data), representing the number of parallel data bits that can be carried in a single transmission.

[0068] Step 2: The DDR write module writes AXIS protocol data to the DDR memory through the DDR controller according to the preset burst length, and transmits the total number of write burst packets and the effective length of the last write packet to the DDR read module; specifically, it includes the following steps:

[0069] 2-1) The DDR write module receives the data stream sent by the upstream device through the AXIS interface and counts the burst data packets one by one.

[0070] 2-2) When the DDR write module receives a burst of data from the upstream device, it generates the DDR write address for that burst data packet and transmits the DDR write address to the DDR controller. The DDR write module determines whether the effective length of the last packet is equal to the burst length: if the effective length of the last packet is equal to the burst length, no padding operation is needed for the last packet data, and it is directly written to the DDR memory in a single burst write (via the DDR controller). If the effective length of the last packet is not equal to the burst length, it means that the length of the input data is not an integer multiple of the single burst length, and the last packet data needs to be padded to the single burst length to ensure that the length of each burst packet written is the same, which facilitates subsequent address operations, i.e., it is written to the DDR memory in a single burst write.

[0071] 2-3) The DDR controller stores data into the DDR memory based on the DDR write address, burst length, and data. Specifically, when storing data into the DDR memory, the DDR controller starts from the beginning address of the DDR read / write space. When generating the address validity signal for each burst data packet, it checks whether the current write address has exceeded the end address. If it has not exceeded the end address, the write address for each subsequent burst transmission increments sequentially according to the total number of bytes in the single burst. If the end address is exceeded, the write address needs to restart from the beginning address.

[0072] 2-4) When all data has been written, the DDR write module will pass the total number of write burst packets and the effective length of the last packet to the DDR read module.

[0073] Step 3: The DDR read module receives the total number of write burst packets and the effective length of the last packet from the DDR write module, and passes the DDR read address to the DDR controller. The DDR controller reads the data from the DDR memory, and then the DDR read module packages the data into AXIS protocol packets for output. Specifically, this includes the following steps:

[0074] 3-1) The DDR read module receives the total number of write burst packets and the effective length of the last packet from the DDR write module, and counts the total number of write burst packets;

[0075] 3-2) When the count of received address packets (referring to the AXIS control information transmission packets sent by the DDR write module to the DDR read module, which do not carry valid data payloads but contain configuration parameters such as the starting address, burst length, and data bit width required for this read operation) is greater than 1, the DDR read operation is started, the corresponding read address is generated, and the DDR read address is transmitted to the DDR controller. The DDR read address starts from the starting address of the DDR read / write space. When the address validity signal of each burst data packet is generated, it is determined whether the current read address has exceeded the end address. If it has not exceeded the end address, the read address of each subsequent burst transmission is incremented sequentially according to the total number of bytes in a single burst. If it has exceeded the end address, the read address starts again from the starting address of the DDR read / write space.

[0076] 3-3) When outputting the last packet of data, the data of the last packet is truncated to the valid length according to the last packet valid length transmitted by the DDR write module. This ensures that the output length of the DDR read module is consistent with the input length of the DDR write module, that is, the input data and output data are consistent.

[0077] To enable those skilled in the art to better understand the present invention, the above method will be described in detail below with reference to specific examples.

[0078] In this embodiment, the DDR interface has a bit width of 256 bits, and the physical storage medium of the virtual FIFO is a 2GB DDR memory. The AXIS data cache with a data transmission bit width of 64 bits and a data transmission length of 1023 is used as an example for description.

[0079] The specific implementation of step one is as follows:

[0080] The starting address of the DDR read / write space is set to 0, and the ending address is set to 32'h80000000;

[0081] The burst length of each read / write operation in DDR is set to 64 beats, so the address space of each data packet is 64 * 256 = 16384 bits, which is 2048 bytes.

[0082] The input and output data width is 64 bits.

[0083] The specific implementation of step two is as follows:

[0084] The DDR write module counts the received AXIS interface data. When the input data counter reaches 255 (indicating 256 data packets received), it generates the corresponding DDR write address, starting from address 0. It checks if the current write address exceeds the end address. If it doesn't, the write address increments by 2048 bytes; if it does, it restarts from the beginning address. For AXIS interface data of length 1023, when the s_axis_tlast signal of the input data is received, the counter can count to 1023, corresponding to a total of 3 write burst packets. The effective length of the last packet is 1023 - 256 * 3 = 255, insufficient for a single burst write operation. One more number is added after the last packet, making the last packet 256 long enough for a 64-byte burst write operation. Finally, the total number of write burst packets for this input data is 3 + 1 = 4, and the effective length of the last packet is 255. These parameters (total number of write burst packets (4) and the effective length of the last packet (255)) are passed to the DDR read module.

[0085] The specific implementation of step three is as follows:

[0086] The DDR read operation is initiated when the count of received write burst packets (the transmission packet containing control information such as the start address, burst length, and data width used by the DDR read module to obtain this read operation, excluding the valid data payload) is greater than 1, generating a DDR read address. The DDR read address also starts from the start address, with each packet's corresponding read address increasing by 2048 bytes. Taking the AXIS interface data reading with a data width of 64 bits and a data length of 1023 as an example, four DDR read operations are required. When the output reaches the address of the fourth packet, the last packet of data is output. This requires using the last packet's valid length parameter of 255 passed from the DDR write to truncate the last packet's data to the valid length. Thus, the total output read data length is 256*3+255=1023, ensuring that the DDR read output length is consistent with the DDR write input length, meaning that the module's input and output data remain consistent.

[0087] Taking a 64-bit input / output width and a 256-bit DDR interface width as an example, this embodiment consumes a total of 14 36kBRAMs without using a DSP. Specifically: the address buffer FIFO of the DDR write module consumes 1 36kBRAM; the data buffer FIFO of the DDR write module consumes 4 36kBRAMs; the burst count and last packet length information buffer FIFO of the DDR read module consumes 1 36kBRAM; the data buffer FIFO of the DDR read module consumes 4 36kBRAMs; and the AXIS protocol conversion FIFO of the DDR read module consumes 4 36kBRAMs. The Xilinx VFIFO IP core consumes 57 36kBRAMs and 18 DSPs. It is evident that the method in this application significantly reduces the resource consumption within the FPGA.

[0088] This application enables the configuration of DDR cache free space in a virtual FIFO by configuring the start and end addresses of the DDR read / write space, thus adjusting the cache size. This is superior to the 256MB cache space of Xilinx's existing VFIFO cache solution. It supports configurable input and output data bit widths and features backward compatibility and scalability.

[0089] This application enables large amounts of data based on the AXIS protocol to be directly cached and read from the DDR cache space, making full use of the DDR cache space, simplifying data caching operations, eliminating the need to know the data length in advance, and eliminating the need for address calculation and address allocation operations outside the module. Furthermore, it consumes fewer FPGA resources than the existing FPGA-based FIFO caching scheme, thus improving the flexibility of signal processing system design.

[0090] In some embodiments, certain aspects of the above-described techniques may be implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly implemented on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by one or more processors, manipulate one or more processors to perform one or more aspects of the above-described techniques. The non-transitory computer-readable storage medium may include, for example, magnetic or optical disk storage devices, solid-state storage devices such as flash memory, cache, random access memory (RAM), or other non-volatile memory devices. The executable instructions stored on the non-transitory computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats interpreted or otherwise executed by one or more processors.

[0091] Computer-readable storage media can include any storage medium or combination of storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media can include, but are not limited to, optical media (e.g., optical discs (CDs), digital versatile optical discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tapes, or magnetic hard disks), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS) based storage media. Computer-readable storage media can be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard disk drive), removably attached to a computing system (e.g., an optical disc or universal serial bus-based (USB) flash memory), or coupled to a computer system via a wired or wireless network (e.g., network-accessible storage (NAS)).

[0092] While the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the invention. Any equivalent changes or modifications made without departing from the spirit and scope of the invention are also within the scope of protection of the invention. Therefore, the scope of protection of the present invention should be determined by the claims of this application.

Claims

1. A virtual FIFO data caching method based on FPGA, characterized in that, Includes the following steps: Configure the operating parameters of the virtual FIFO, including the start address of the DDR read / write space, the end address of the DDR read / write space, the length of each read / write burst, and the input / output data bit width; The DDR write module writes AXIS protocol data to the DDR memory through the DDR controller according to the preset burst length, and transmits the total number of write burst packets and the effective length of the last packet to the DDR read module; The DDR read module receives the total number of write burst packets and the effective length of the last packet from the DDR write module, passes the DDR read address to the DDR controller, the DDR controller reads the data from the DDR memory, and then the DDR read module packages the data into AXIS protocol output.

2. The FPGA-based virtual FIFO data caching method according to claim 1, characterized in that, When the DDR write module writes AXIS protocol data to the DDR memory through the DDR controller according to a preset burst length, it includes the following steps: 2-1) The DDR write module receives the data stream sent by the upstream device through the AXIS interface and counts each burst of data packets; 2-2) When the DDR write module receives a burst of data from the upstream device, it generates the DDR write address for that burst data packet and passes the DDR write address to the DDR controller. When it receives the s_axis_tlast signal from the upstream device, it indicates that it has received all the data that needs to be buffered. The DDR write module then determines whether the effective length of the last packet is equal to the burst length: if the effective length of the last packet is equal to the burst length, it writes the data to the DDR memory in a single burst write; if the effective length of the last packet is not equal to the burst length, it performs a padding operation on the last packet data, padding its length upwards to the single burst length, and then writes the data to the DDR memory in a single burst write. 2-3) The DDR controller stores data into the DDR memory based on the DDR write address, burst length, and data. 2-4) When all data has been written, the DDR write module will pass the total number of write burst packets and the effective length of the last packet to the DDR read module.

3. The FPGA-based virtual FIFO data caching method according to claim 2, characterized in that, When the DDR controller stores data into the DDR memory based on the DDR write address, burst length, and data, the specific steps are as follows: The DDR controller starts from the beginning address of the DDR read / write space. When generating the address validity signal for each burst data packet, it determines whether the current write address has exceeded the end address. If it has not exceeded the end address, the address of each subsequent burst transmission will increment sequentially according to the total number of bytes in a single burst. If it has exceeded the end address, the DDR write address needs to start again from the beginning address.

4. The FPGA-based virtual FIFO data caching method according to claim 1, characterized in that, The DDR read module calculates the DDR read address based on the total number of write burst packets and the effective length of the last packet, and passes it to the DDR controller. The DDR controller reads the data from the DDR memory, and the DDR read module then packages the data into an AXIS protocol output, including the following steps: 3-1) The DDR read module receives the total number of write burst packets and the effective length of the last packet from the DDR write module, and counts the total number of write burst packets; 3-2) When the received address packet count is greater than 1, start the DDR read operation, generate the corresponding read address, and send the DDR read address to the DDR controller; 3-3) When outputting the last packet of data, the data of the last packet is truncated to the valid length according to the last packet valid length passed by the DDR write module to ensure that the input data and output data are consistent.

5. The FPGA-based virtual FIFO data caching method according to claim 4, characterized in that, When the received address packet count is greater than 1, a DDR read operation is initiated, a corresponding read address is generated, and the DDR read address is transmitted to the DDR controller, as follows: The DDR read address starts from the beginning address of the DDR read / write space. When the address validity signal for each burst data packet is generated, it is determined whether the current read address has exceeded the end address: if it has not exceeded the end address, the address of each subsequent burst transmission is incremented sequentially according to the total number of bytes in a single burst; if it has exceeded the end address, the read address restarts from the beginning address of the DDR read / write space.

6. An FPGA-based virtual FIFO data caching system for implementing the FPGA-based virtual FIFO data caching method as described in claim 1, characterized in that, Includes the following modules: The parameter configuration module is used to configure the operating parameters of the virtual FIFO, including the DDR read / write space start address, DDR read / write space end address, read / write burst length, and input / output data bit width. The DDR write module, integrated inside the FPGA, is used to write AXIS protocol data into the DDR memory through the DDR controller according to the preset burst length, and to transmit the total number of write burst packets and the effective length of the last packet to the DDR read module. The DDR read module, integrated inside the FPGA, is used to receive the total number of write burst packets and the effective length of the last packet transmitted by the DDR write module, and to pass the DDR read address to the DDR controller. The DDR controller reads the data from the DDR memory, and then the DDR read module packages it into AXIS protocol output. The DDR controller, connected to the DDR read module and DDR write module via an internal bus, is used to receive read / write requests and perform address mapping. DDR memory is used to store AXIS protocol data received by the DDR write module.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the FPGA-based virtual FIFO data caching method as described in any one of claims 1-5.

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