High-synchronization multi-sensor I2C parallel acquisition method

Abstract

The application discloses a high-synchronization multi-sensor I2C parallel collection method, relates to the technical field of high-synchronization multi-sensor I2C parallel collection, and a main controller sends a specific clock waveform generated through transient modulation to each sensor as a synchronous trigger signal through an SCL line; after an external timing recognition circuit at the front end of each sensor recognizes the waveform, the external timing recognition circuit synchronously outputs a collection starting level at the same clock edge, and drives all the sensors to perform AD sampling and data latching at the same time; each communication channel is calibrated and configured with compensation parameters through progressive hardware delay, so that the data edges of all the channels are aligned to the same capture window; and the main controller captures the sampling data output by all the sensors in parallel through independent SDA lines once. The application discards the address addressing and ACK response mechanism of the standard I2C protocol, realizes nanosecond-level timing synchronization of all channels, and improves the collection efficiency.

Description

Technical Field

[0001] This invention generally relates to the field of high-synchronization multi-sensor I2C parallel acquisition technology, and specifically to a high-synchronization multi-sensor I2C parallel acquisition method. Background Technology

[0002] Synchronous data acquisition from multi-sensor arrays is a core technology in fields such as industrial measurement and control, UAV attitude fusion, vibration monitoring, and inertial navigation. As UAVs, robots, and the Industrial Internet of Things (IIoT) continue to demand higher levels of sensing accuracy and real-time performance, the number of sensors integrated into a single system is constantly increasing, and the requirements for consistency in the timing of data acquisition among multiple sensors are becoming increasingly stringent.

[0003] Currently, the vast majority of commercial sensors (such as accelerometers, gyroscopes, magnetometers, temperature and humidity sensors, and barometric pressure sensors) use the standard I2C bus interface as their communication method. The standard I2C bus employs a shared serial clock and data line architecture, with all slave devices connected in parallel on the same bus. However, when this architecture is directly applied to scenarios involving large-scale, multi-sensor synchronous data acquisition, the master controller must address and poll each sensor individually, resulting in millisecond-level or even tens of millisecond-level timing discrepancies in the acquisition times of different channels. This fails to meet the nanosecond-level synchronization requirements of high-precision fusion. Furthermore, it necessitates the forced insertion of an ACK response clock cycle after each byte transmission. In multi-channel parallel acquisition scenarios, if multiple sensors simultaneously attempt to reply with ACK on their respective SDA lines, crosstalk and level contention between response signals arise due to the inconsistent electrical characteristics of each channel. In summary, existing solutions exhibit significant technological gaps in achieving high synchronization, high efficiency, and high reliability in parallel acquisition of multi-sensor arrays. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a highly synchronous multi-sensor I2C parallel acquisition method.

[0005] This invention provides a high-synchronization multi-sensor I2C parallel acquisition method. The I2C bus has a serial clock line and multiple independently configured serial data lines. Each general-purpose input / output port of the main controller leads out an independent SDA line as the serial data line and connects it to the SDA pin of a sensor, so that each sensor and the main controller form an independent communication channel. The acquisition method includes the following steps: The shared clock drive unit in the main controller sends data acquisition signals to the SCL pins of each sensor via the serial clock line output terminal. The data acquisition signals are specific clock waveforms after instantaneous modulation of pulse width or frequency characteristics. Based on the data acquisition signals, after the external timing recognition circuit corresponding to each sensor recognizes the data acquisition signal through each communication channel, it synchronously outputs the acquisition start level to the sensor connected to it at the same clock edge, driving all sensors to perform AD sampling and data latching at the same time to obtain sampled data; each communication channel is set with a corresponding compensation parameter, which is used to align the sampling data edges of all communication channels to the same clock window during subsequent acquisition; The main controller receives the sampled data latched by each of the sensors through each of the serial data lines, so that the raw data on all the serial data lines arrives at the input terminal of the main controller synchronously.

[0006] According to the technical solution provided by the present invention, the shared clock drive unit in the main controller further includes, after the system is powered on: After the system is powered on, the shared clock drive unit continuously outputs a constant frequency synchronous beat signal to the SCL pin of each sensor via its serial clock line, so that all sensors are continuously locked to the same physical clock reference and are in a standby listening state.

[0007] According to the technical solution provided by the present invention, the specific clock waveform is a first special clock cycle in which at least one pulse width is compressed to less than 1 / 3 of the normal pulse width, or a second special clock cycle in which at least one pulse width is extended to twice the normal pulse width is inserted into the constant frequency synchronous beat signal. The total duration of the specific clock waveform is less than or equal to three complete clock cycles of the synchronization beat signal.

[0008] According to the technical solution provided by the present invention, the external timing identification circuit has a pulse width counting threshold range or frequency counting reference pre-stored inside, which corresponds to the specific clock waveform; The external timing recognition circuit monitors the actual waveform on the serial clock line in real time. When it detects that the pulse width of the actual waveform exceeds the upper or lower boundary of the pulse width counting threshold range, or when it detects that the frequency offset of the actual waveform exceeds the tolerance range of the frequency counting reference, it determines that the specific clock waveform is successfully recognized, and then outputs the acquisition start level on the same clock edge. The acquisition start level is a hardware level pulse that lasts for one or more clock cycles, which directly drives the enable pin of the sensor.

[0009] According to the technical solution provided by the present invention, the main controller receives the sampled data latched by each of the sensors through each of the serial data lines, including: After emitting the specific clock waveform, the shared clock driving unit waits for a preset time interval, and in the first stable data window adjacent to the preset time interval, directly captures the raw data on all the serial data lines in parallel at the same clock window.

[0010] According to the technical solution provided by the present invention, the main controller is configured with a programmable hardware delay unit corresponding to each communication channel, and the process for determining the compensation parameters is as follows: The main controller sends a standard calibration edge signal to each of the communication channels through a programmable hardware delay unit in each of the communication channels; The measured phase difference between the standard calibration edge signal and the clock capture edge of the preset unified serial clock line is detected on each of the communication channels. Based on the measured phase difference of each communication channel, compensation parameters for each communication channel are independently configured to compensate for timing deviations in the synchronous acquisition of raw data by all communication channels.

[0011] According to the technical solution provided by the present invention, the method further includes: The main controller monitors the level transition integrity, signal edge steepness, and data pattern validity on each communication channel in real time, and confirms the communication status of each communication channel based on the level transition integrity, signal edge steepness, and data pattern validity. When the communication status of any of the communication channels is determined to be faulty, the physical connection between the communication channel and the input terminal of the main controller is cut off, and an idle backup channel is called from the preset redundant backup SDA channel group. The channel mapping table is updated, and the output of the sensor corresponding to the communication channel in the faulty state is physically switched to the idle backup channel.

[0012] According to the technical solution provided by the present invention, while the main controller captures the raw data on all serial data lines within the same continuous clock window, it uses the constant frequency synchronization beat signal as the same source time reference to instantaneously read the current time count value and bind a unified timestamp to the sampling data of all communication channels in the current batch.

[0013] In summary, this technical solution specifically discloses a high-synchronization multi-sensor I2C parallel acquisition method, comprising: a shared clock driving unit in the main controller sending data acquisition signals to the SCL pins corresponding to each sensor via the serial clock line output terminal; the data acquisition signals being specific clock waveforms whose pulse width or frequency characteristics are instantaneously modulated; based on each data acquisition signal, after the external timing recognition circuit corresponding to each sensor recognizes the data acquisition signal via each communication channel, it synchronously outputs an acquisition start level to the respective connected sensor at the same clock edge, driving all sensors to perform AD sampling and data latching at the same time to obtain sampled data; each communication channel is set with corresponding compensation parameters, which are used to align the sampling data edges of all communication channels to the same clock window during subsequent acquisition; the main controller receives the sampled data latched by each sensor through each serial data line, so that the raw data on all serial data lines arrives at the main controller input terminal synchronously.

[0014] Beneficial effects: This invention reduces timing deviation across the entire communication channel by redefining the serial clock line as a continuously outputting global clock reference and the serial data line as an independent physical channel for each sensor to transmit raw data unidirectionally to the main controller. Combined with clock waveform modulation triggering and hardware delay calibration, it improves acquisition efficiency by eliminating address matching and ACK responses and capturing all SDA data in parallel within the same continuous clock window. It further reduces timing deviation across the entire communication channel by using external reference source phase-locked loop calibration and instantaneous hardware binding of the data latch to the same source clock timestamp. Finally, it achieves single-point fault isolation and system fault tolerance through independent SDA physical isolation, parallel fault detection, and seamless switching of redundant channels. These features collectively break through the inherent architectural constraints of standard I2C ("shared bus, serial polling, mandatory acknowledgment"), providing a new path for high-synchronization, high-efficiency, and high-reliability parallel acquisition of large-scale sensor arrays. Attached Figure Description

[0015] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a flowchart illustrating a highly synchronous multi-sensor I2C parallel acquisition method. Detailed Implementation

[0016] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0017] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0018] Example 1 To make the technical solutions of the embodiments of the present invention clearer and easier to understand, the application background of the embodiments of the present invention will be introduced below.

[0019] Synchronous data acquisition from multi-sensor arrays is a core component in fields such as industrial measurement and control, UAV attitude fusion, and vibration monitoring. The existing standard I2C bus uses a shared SCL clock and SDA data line architecture, which has problems such as bus conflicts, large polling delays, and low synchronization accuracy. Moreover, in the standard I2C protocol, the serial clock line is directly generated and controlled by the master controller. Its start / stop, frequency, and number of pulses are all dynamically scheduled by the master controller according to the protocol process. The master controller undertakes all timing control tasks.

[0020] While existing shared SCL clock and multi-channel independent SDA architectures achieve physical line separation, they still have significant drawbacks: inconsistent SDA wiring and device delays lead to large timing alignment errors in high-speed acquisition; the use of the standard I2C protocol and retention of the ACK response mechanism results in severe response interference and low transmission efficiency when multiple channels are in parallel; the lack of real-time parallel fault detection makes it easy for a single point of failure to cause the entire data set to fail; relying solely on software to add timestamps results in low synchronization accuracy and inability to interface with high-precision clock references such as GPS and PPS; and the use of software to simulate I2C timing leads to high master control occupancy and complex synchronization scheduling of large numbers of channels.

[0021] For ease of understanding, the following terms are explained in this invention: Serial Clock Line (SCL): The clock signal line in the I2C bus, generated by the master controller, used to synchronize the timing of all data transmissions on the bus. In the standard I2C protocol, SCL is an intermittent clock generated on demand.

[0022] Serial Data Line (SDA): The data signal line in the I2C bus, used to transmit data between the master controller and slave devices. In the standard I2C protocol, all slave devices share the same SDA line, and data is transmitted bidirectionally between the master and slave devices.

[0023] Inter-Integrated Circuit (I2C): A half-duplex, bidirectional two-wire serial communication bus consisting of two signal lines, SCL and SDA. It supports a multi-master, multi-slave topology and uses 7-bit or 10-bit device addresses for slave device addressing.

[0024] Acknowledgement (ACK): In the standard I2C protocol, this is a confirmation signal returned by the device to the master controller. After each byte is transmitted, the receiver pulls the SDA line low within the 9th SCL clock cycle to indicate that the byte has been successfully received. The ACK signal is used to confirm the normal progress of the communication process byte by byte.

[0025] The general purpose input / output (GPIO) ports of the main controller support dynamic reconfiguration of direction at the physical layer. In standard I2C-compatible mode, GPIOs are configured as open-drain outputs or bidirectional modes to send device addresses, register addresses, and read / write commands to the sensor, and to receive ACK responses. In high-synchronous parallel acquisition mode, GPIOs are configured as high-impedance inputs, used only to receive raw data transmitted back from the sensor via a dedicated SDA line. The GPIO direction switching between the two modes is uniformly controlled by internal registers of the main controller, with a switching time of less than 100 nanoseconds, without introducing additional timing overhead.

[0026] Raw data specifically refers to the original sampled digital quantity latched in the sensor's data register and shifted out via the SDA line after the sensor responds to a sampling trigger. It does not contain any I2C protocol additional fields (including device address bits, read / write control bits, acknowledge bits, and stop bits). Raw data only contains a valid bit stream of sensor measurements, and its bit width is determined by the sensor's inherent resolution (typically 8 to 24 bits).

[0027] In summary, existing solutions fail to address core pain points such as timing alignment, protocol optimization, fault tolerance, and high-precision time stamp binding, leaving a significant technological gap in the field of high-volume, high-synchronization sensor acquisition. A completely new architecture and methodology are urgently needed for upgrades. Therefore, this invention proposes a method that independently implements timing calibration, parallel acquisition, fault detection, clock synchronization, and data output functions, belonging to the fields of embedded sensor signal acquisition, I2C bus communication, multi-channel synchronous data acquisition, industrial measurement and control, and UAV attitude sensor array technology.

[0028] For details, please refer to Figure 1 This embodiment illustrates a highly synchronized multi-sensor I2C parallel acquisition method, applied to a highly synchronized multi-sensor I2C parallel acquisition system. In this invention, compared to the serial clock line in the standard I2C bus, the acquisition system no longer carries the protocol syntax information defined by the standard I2C protocol, such as start conditions, stop conditions, and clock synchronization. Instead, it is configured to continuously output a constant-frequency synchronization clock signal as the global physical timing reference for all sensors. Similarly, the serial data line in the standard I2C bus is also redefined, no longer carrying the device address matching, read / write commands, and handshake signals defined by the standard I2C protocol. Instead, it is configured as a physical transmission channel for unidirectional transmission of raw data acquired only from the sensors to the main controller.

[0029] At the physical connection level, each general-purpose input / output port of the main controller is uniquely connected to the SDA pin of a corresponding sensor via an independent SDA trace, forming a one-to-one independent data transmission channel between each sensor and the main controller. The general-purpose input / output ports support dynamic switching of input / output direction during operation, and are configured in input mode to receive sensor data during the parallel acquisition phase. These independent data transmission channels are physically isolated from each other, with no electrical parallel or shared relationships. All independent data transmission channels share the same SCL clock signal output by the shared clock drive unit, and this SCL clock signal is broadcast in parallel to all sensors.

[0030] The main controller no longer uses the chip's internal hardware I2C controller. Instead, it configures the general-purpose input / output ports as input mode to receive sampling data transmitted from each sensor through independent SDA channels. The core functions of the main controller include: global clock parameter configuration, full-channel delay calibration parameter scheduling, synchronous acquisition trigger command issuance, parallel data batch reading, data buffering, hardware timestamp data integration, fault diagnosis and redundant channel scheduling, and data normalization output.

[0031] Furthermore, the data collection method includes the following steps: S100, the main controller is configured with a shared clock drive unit. The shared clock drive unit sends data acquisition signals to the SCL pins of each sensor via its serial clock line output. The data acquisition signals are specific clock waveforms after instantaneous modulation of pulse width or frequency characteristics.

[0032] The shared clock drive unit includes a clock generation circuit, a phase-locked loop circuit, a differential drive circuit, and an external clock interface. It supports adjustable high-frequency clocks from 4MHz to 10MHz and can be connected to GPS timing signals, 1PPS pulse signals, or a temperature-controlled crystal oscillator for phase-locked loop calibration. It possesses long-line drive capability, meeting the requirements for long-distance synchronous transmission of multi-sensor arrays.

[0033] Specifically, under the initial configuration of the main controller, the shared clock drive unit continuously outputs a constant frequency synchronization beat signal to the SCL pins of each sensor via its SCL output terminal after the system is powered on. The "data acquisition signal" specifically refers to a specific clock waveform generated by instantaneously modulating the pulse width or frequency of one or more clock cycles based on the constant frequency synchronization beat signal continuously output by the shared clock drive unit. This specific clock waveform is different from the normal clock waveform and serves as a trigger command for global synchronous acquisition. In other words, the shared clock drive unit sends the instantaneously modulated specific clock waveform to each sensor as a synchronization trigger signal via the SCL line. The shared clock drive unit continuously outputs the clock signal after the system is powered on, and the main controller does not interfere with the start and stop of the clock.

[0034] The shared clock drive unit integrates a high-precision clock synchronization phase-locked loop (PLL) unit as its supporting PLL calibration submodule. This PLL unit provides an external high-precision time base access interface, supporting three types of standard industrial-grade high-precision time bases: clock signals output from the GPS timing module, 1PPS second pulse signals, and reference clock signals output from an external temperature-controlled, high-stability crystal oscillator. These external time bases are used to input an absolute standard time / frequency reference to the system, eliminating frequency and phase drift caused by local crystal oscillator temperature variations and long-term operation. The high-precision clock synchronization PLL unit and the shared clock drive unit are deeply coupled and integrated, together forming a complete clock link from external time base access and PLL calibration to co-source clock output, ensuring that the cumulative error of timestamps from multiple batches of continuously acquired data is controlled within the nanosecond level.

[0035] S200: Based on the data acquisition signals, after the external timing recognition circuit corresponding to each sensor recognizes the data acquisition signal through each communication channel, it synchronously outputs the acquisition start level to the sensor connected to it on the same clock edge, driving all sensors to perform AD sampling and data latching at the same time to obtain the sampled data.

[0036] Specifically, the external timing recognition circuit is a pure hardware comparator circuit independent of the sensor. Its input is coupled to the SCL line, and its output is coupled to the sampling trigger pin or enable pin of the corresponding sensor. Each channel's external timing recognition circuit simultaneously monitors the waveform on the SCL line. When a specific clock waveform is detected, it synchronously outputs a sampling start level on the same clock edge, ensuring that all sensors start sampling at the same time. The sampling start level is a hardware level pulse lasting one or more clock cycles, directly driving the sensor's enable pin without requiring internal firmware analysis.

[0037] For some commercial I2C sensors that lack external hardware enable pins (such as EN, CS, SYNC), this system incorporates a hardware command injection circuit in series at the front end of each channel. This circuit internally stores the standard I2C read command sequence (including device address, read opcode, and register address) for the corresponding sensor model. When the external timing identification circuit recognizes a specific clock waveform and outputs a data acquisition start level, this level simultaneously serves as the enable signal for the hardware command injection circuit. Upon receiving the enable signal on the same clock edge, the injection circuit uses the current SCL tick as a timing reference and automatically sends the pre-stored read command sequence to the sensor's SDA pin using standard I2C timing (at this time, the main controller's GPIO is in a high-impedance state, preventing bus contention). Upon receiving the hardware-injected read command, the sensor responds according to the standard protocol and outputs sampled data. This process does not rely on main controller software intervention, and all channel hardware command injection circuits share the same SCL trigger edge, thus ensuring the synchronization of sampling start times for each channel.

[0038] S300: The main controller receives the sampled data latched by each sensor through each serial data line, so that the raw data on all serial data lines arrives at the input terminal of the main controller synchronously.

[0039] Specifically, within the first stable data window after the preset time interval following the emission of a specific clock waveform, the main controller captures all raw data transmitted on the SDA line in parallel within the same continuous clock window, without sending any start conditions, stop conditions, slave device addresses, read / write commands defined by the I2C protocol, or waiting for any ACK response signals.

[0040] The main controller uses the last modulation edge of a specific clock waveform as the zero point. After adding a preset time interval (e.g., 500ns) to this zero point, it initiates a one-time parallel acquisition, replacing the ACK handshake with hardware timing to achieve open-loop predictive non-acknowledgment reading. The first stable data window refers to the time period during which the data level on the SDA line has stabilized and can be safely read. The main controller performs acquisition within the first stable data window encountered after the preset time interval ends, ensuring that data from all channels is read at its optimal point.

[0041] Therefore, the downlink read command is actively and synchronously sent by the pre-programmed read timing circuits of each channel under the global SCL clock cycle. The main controller does not directly send the read timing, but only pre-stores the command parameters of each channel. After the pre-programmed circuits of each channel obtain the read command parameters during the configuration phase, they automatically send them in each subsequent acquisition cycle without the need for sequential intervention from the main controller. After the sensor responds to the read command, it transmits the latched sampled data back through its own independent SDA line. The data is transmitted to the input of the main controller through the independent SDA lines of each channel and the programmable hardware delay calibration network. After all channels have completed data alignment, the main controller acquires the data of all SDA channels in parallel in the same clock cycle.

[0042] In a preferred embodiment, the shared clock drive unit continuously outputs a constant frequency synchronization clock signal to the SCL pin of each sensor via its serial clock line after the system is powered on, so that all sensors are continuously locked to the same physical clock reference and are in a standby listening state.

[0043] Specifically, the shared clock drive unit includes a clock generation circuit, a phase-locked loop circuit, a differential drive circuit, and an external clock interface. During normal system operation, the shared clock drive unit adopts an uninterrupted constant frequency output mode, continuously outputting a standard square wave clock signal with the same source, frequency, and phase, which is stably input to the clock input pins of all sensors over a long period of time, without requiring the main controller to perform clock enable, disable, and start / stop control.

[0044] Uninterrupted output after system power-on means that the SCL clock signal output by the shared clock drive unit remains constant throughout the entire operation period from system power-on to system power-off, without clock enable, clock shutdown, clock pause, or clock frequency switching operations.

[0045] When no synchronous acquisition trigger command is received, all sensors are only in a timing standby listening state, receiving only the reference timing clock and not performing AD sampling or data output actions. Continuous constant clock input will not have any negative impact on the sensors, and will not cause missampling, data corruption, or device damage.

[0046] In a preferred embodiment, the specific clock waveform is: in a constant frequency synchronous beat signal, at least one first special clock cycle with a pulse width compressed to less than 1 / 3 of the normal pulse width is inserted, or at least one second special clock cycle with a pulse width extended to twice the normal pulse width is inserted, or a set of composite modulation waveforms containing 2 to 4 consecutive pulse width gradient sequences is inserted; the total duration of the specific clock waveform is less than or equal to 3 complete clock cycles of the synchronous beat signal.

[0047] Specifically, pulse width compression refers to shortening the high-level duration of a clock cycle within a normal 50% duty cycle square wave to less than one-third of the normal value, forming an extremely narrow high-level pulse as a unique identifier. Pulse width expansion refers to extending the high-level duration of a clock cycle to more than twice the normal value, forming a wideband pulse as a unique identifier. Composite modulation waveform refers to a pulse width that gradually changes over 2-4 consecutive clock cycles (e.g., from narrow to wide or from wide to narrow), forming a uniquely identifiable waveform fingerprint. The total duration of a specific clock waveform is limited to within 3 complete clock cycles to ensure that the identification delay of the trigger command is less than 1 microsecond, thus not affecting the timing budget of subsequent data acquisition windows.

[0048] In a preferred embodiment, the external timing identification circuit has a pre-stored pulse width counting threshold range or frequency counting reference corresponding to a specific clock waveform.

[0049] This external timing recognition circuit does not rely on any software program or firmware for parsing; waveform monitoring, comparison, and judgment are entirely performed by hardware logic. The external timing recognition circuit monitors the actual waveform on the serial clock line in real time. When it detects that the pulse width of the actual waveform exceeds the upper or lower boundary of the pulse width counting threshold range, or when it detects that the frequency offset of the actual waveform exceeds the tolerance range of the frequency counting reference, it determines that the specific clock waveform has been successfully recognized, and then outputs a sampling start level on the same clock edge. In other words, when the external timing recognition circuit determines that a specific clock waveform has been successfully recognized, it immediately outputs a sampling start level to the enable pin or sampling trigger pin of the connected sensor on the same clock edge, triggering the sensor to perform a sampling action. The sampling start level is a hardware level pulse lasting one or more clock cycles, directly driving the sensor's enable pin.

[0050] It should be noted that the present invention designs a triggering mechanism to address the differences in hardware of different sensors: for high-end sensors with built-in FSYNC / SYNC hardware synchronization pins, a global common synchronization trigger bus is added; for general-purpose I2C sensors without any dedicated synchronization pins, the above-mentioned clock waveform modulation method is adopted.

[0051] In a preferred embodiment, step S300, "the main controller receives the sampled data latched by each sensor through each serial data line", specifically includes: after the shared clock drive unit emits a specific clock waveform, it waits for a preset time interval, and in the first stable data window adjacent to the preset time interval, it directly captures the raw data on all serial data lines in parallel at the same clock window.

[0052] Specifically, the preset time interval is pre-calculated and determined by the main controller based on the following parameters: The physical wiring length of the SDA line corresponding to each sensor is used to calculate the SDA line transmission delay time of each channel based on the physical wiring length of the SDA line of each channel and the propagation delay constant per unit length; the response delay of the external timing identification circuit; and the maximum sampling conversion time of the sensor at different operating temperatures. In practical applications, the preset time interval is equal to the maximum value of the sum of "sensor sampling conversion time + external timing identification circuit response delay + SDA line transmission delay" in all channels, and a timing margin of not less than 5% of this maximum value is reserved on this basis.

[0053] In a preferred embodiment, the main controller is configured with a programmable hardware delay unit corresponding to each communication channel. The process of determining the compensation parameters is as follows: the main controller sends a standard calibration edge signal to each communication channel through the programmable hardware delay unit in each communication channel; detects the measured phase difference between the standard calibration edge signal on each communication channel and the clock capture edge of the preset unified serial clock line; and independently configures the compensation parameters of each communication channel according to the measured phase difference of each communication channel to reduce the timing deviation of all communication channels when synchronously capturing raw data.

[0054] Specifically, programmable hardware delay units are connected in series in each independent SDA acquisition channel. The calibration logic is as follows: for channels with measured transmission delays less than the standard value, the hardware delay compensation is increased; for channels with measured transmission delays greater than the standard value, the hardware delay compensation is reduced. Inverse hardware compensation forces the data edges of all channels to align with the global clock acquisition edge. After calibration, the timing deviation of all channels can be controlled within 5 nanoseconds, completely solving the multi-channel timing inconsistency problem from the hardware level, unlike the coarse alignment method of traditional software-uniform delay or software timestamp fitting.

[0055] In addition to performing independent hardware delay calibration for each SDA data channel, this system fully considers the time deviation of the trigger edges received by each sensor due to differences in wiring length under the shared SCL line broadcast method. During the compensation parameter determination process, the standard calibration edge signal is simultaneously emitted by the clock drive unit through the SCL line. The external timing identification circuits of each channel receive this edge at the same time and start their internal timing. The main controller measures the closed-loop delay difference between the SCL edge emission and the output response of the external timing identification circuit for each channel. This closed-loop delay difference comprehensively includes the sum of the SCL broadcast arrival delay, the timing identification circuit response delay, and the SDA line return delay. Based on this closed-loop delay difference, the compensation parameters of the programmable hardware delay unit for each channel are configured, effectively compensating for inconsistencies on the SCL broadcast path without requiring strict equal-length constraints on the SCL physical wiring.

[0056] In addition, the system supports timed dynamic recalibration during operation to compensate for temperature drift and long-term timing drift in real time. The recalibration process is completed during the intervals of uninterrupted data acquisition by the system. During the recalibration, the output of the constant frequency synchronous beat signal is not stopped, and all sensors remain in a timing anchored state.

[0057] In a preferred embodiment, after the system enters the parallel acquisition mode without ACK, the ACK response mechanism no longer participates in the communication status confirmation during operation. Instead, an independent parallel fault detection unit monitors the communication integrity of each communication channel in real time.

[0058] Specifically, the main controller monitors the integrity of level transitions, the steepness of signal edges, and the validity of data codes on each communication channel in real time, and confirms the communication status of each communication channel based on the integrity of level transitions, the steepness of signal edges, and the validity of data codes. The communication status includes at least the fault status.

[0059] When the communication status of any communication channel is determined to be faulty, the physical connection between the communication channel and the input terminal of the main controller is cut off, and an idle backup channel is called from the preset redundant backup SDA channel group. The channel mapping table is updated, and the output of the sensor corresponding to the communication channel in the faulty state is physically switched to the idle backup channel.

[0060] Among them, level transition integrity refers to whether the signal on the SDA line has a normal transition at the SCL clock edge, and whether there is an abnormal state of constant high, constant low or fixed level; signal edge steepness refers to whether the slope of the rising and falling edges of the SDA signal is normal, and whether there is excessive edge distortion caused by capacitor tailing; data code validity refers to whether the data code output by the sensor is within the expected value range, and whether there are all 0s, all 1s or other invalid codes.

[0061] In practical applications, this system uses channel status monitoring as an auxiliary fault screening function in open-loop acquisition mode without ACK response. Level transition integrity detection is used to detect physical disconnection faults such as constantly high, constantly low, or floating SDA lines; signal edge steepness detection is used to detect signal distortion caused by excessive capacitive load or insufficient drive capability; data code validity verification is based on the preset physical range of each sensor for reasonableness judgment. For example, if a temperature sensor continuously outputs values ​​exceeding its upper limit under normal temperature conditions, or a barometric pressure sensor continuously outputs all zeros, it is considered an anomaly. These three criteria are comprehensively weighted and evaluated, and a fault flag is triggered when a set threshold is exceeded. While this method cannot identify all failure modes (such as progressive failures with numerical drift but still within a reasonable range), combined with a redundant channel switching mechanism, it can minimize the impact of single-point physical faults on the system.

[0062] In a preferred embodiment, while the main controller captures raw data on all serial data lines within the same continuous clock window, it uses a constant frequency synchronization clock signal as the same source time reference to instantaneously read the current time count value and bind a unified timestamp to the sampling data of all channels in the current batch.

[0063] Specifically, based on step S100, after the high-precision clock synchronization phase-locked loop unit is connected to an external high-precision time base, a dual phase-locked calibration of frequency and phase is performed on the constant-frequency synchronization beat signal to suppress long-term drift of the local clock. Frequency phase-locking refers to the phase-locked loop unit comparing the actual output frequency of the local clock source with the standard frequency of the external reference signal, adjusting the control voltage of the local clock source through closed-loop feedback to lock the local clock frequency to the frequency of the external reference signal, eliminating frequency deviation. Phase phase-locking refers to the phase-locked loop unit further synchronizing the rising or falling edge of the local clock signal with the corresponding edge of the external reference signal after frequency locking, aligning the local clock edge with the edge of the external reference signal by adjusting the initial phase offset of the local clock signal. Frequency phase-locking and phase phase-locking are performed simultaneously within the phase-locked loop circuit, jointly achieving dual locking of the local clock and the external reference in both frequency and phase dimensions.

[0064] A standard clock, calibrated by a high-precision clock synchronization phase-locked loop unit, is synchronously supplied to a high-precision hardware counter as a time reference. Upon arrival of the synchronous acquisition trigger edge, the hardware logic simultaneously latches two signals: one is the sensor sampling data transmitted in parallel on each SDA channel, and the other is the current count value of the high-precision hardware counter. These two signals together generate a hardware timestamp. The timestamp binding is directly completed by the hardware logic, without software interruption or software time function call. Unlike traditional methods of post-processing timestamps via software, this invention employs a hardware instantaneous timestamp binding mechanism. That is, the moment all sensors complete synchronous sampling and data latching, the hardware circuit directly binds a unified high-precision timestamp to each data set based on the globally synchronized clock after phase-locked loop calibration. Without the access of an external high-precision time base and phase-locked loop calibration by a high-precision clock synchronization phase-locked loop unit, the local clock will continuously drift due to temperature drift and aging. The timestamps of data collected in multiple batches will accumulate errors at the nanosecond to microsecond level, failing to meet the application requirements of high-precision scenarios such as UAV attitude fusion and vibration array synchronous monitoring.

[0065] In a preferred embodiment, the acquisition system supports seamless switching between two operating modes: The first mode is the standard I2C compatible mode. The main controller sends the start condition, device address, and read / write commands according to the standard I2C protocol timing and receives ACK responses, enabling compatible read / write access to a single standard I2C device. In this mode, the SCL clock is generated on demand.

[0066] The second mode is a high-synchronization multi-sensor I2C parallel acquisition method. The main controller performs multi-sensor synchronous batch acquisition according to steps one through eight above. In this mode, the SCL clock switches to uninterrupted output mode. The switching between the two modes is achieved by the main controller through internal register configuration bits, without the need for power-on or hardware jumpers. This dual-mode compatible design meets both the traditional single-point debugging and maintenance needs and the application requirements of high-synchronization acquisition of large-scale arrays, making it highly versatile.

[0067] In practical applications, during the system power-on initialization and sensor register configuration phases, the system switches to standard I2C compatible mode, fully retaining the ACK response mechanism to complete online pre-detection and configuration of all sensor channels. Specifically, the main controller sends the sensor slave address to each channel and waits for ACK responses from each channel. If a channel does not return an ACK, it is directly determined that the sensor on that channel is not connected, the line is broken, or the device is faulty. This channel is pre-marked as a faulty channel and added to the fault list, and is not included in the subsequent parallel acquisition queue. All sensors that pass the ACK detection have their addresses, sampling register parameters, and reading timing reliably configured with ACK responses during the configuration phase. Only sensors that detect valid ACKs are included in subsequent parallel acquisition tasks. Through the above configuration phase operations, the system completes the sensor existence verification and parameter configuration for all channels before entering the ACK-free parallel acquisition mode, equivalent to completing a full-channel identity verification before acquisition.

[0068] It should be noted that the switching between the two modes is mainly performed during the system power-on initialization phase and offline maintenance phase. Once the system enters high-synchronization parallel acquisition mode and enables continuous constant-frequency SCL output, if it is necessary to switch back to standard I2C compatible mode to reconfigure individual sensors, the switching action will be performed under the unified control of the main controller. First, all channels' acquisition trigger outputs will be temporarily disabled (so that the sensors do not respond to external triggers). After the SCL clock is reconfigured and the target sensor register is rewritten, the SCL constant-frequency output will be restored and the trigger masking will be removed. During the above switching, all sensor data acquisition tasks are paused, the total switching time is less than 500 microseconds, and a full-channel hardware delay calibration must be performed again after the switching is completed to ensure timing alignment. For application scenarios requiring continuous uninterrupted acquisition, the parameters of all sensors can be pre-configured during the system initialization phase to avoid performing mode switching during operation.

[0069] The highly synchronous multi-sensor I2C parallel data acquisition method provided by this invention can be widely applied in fields requiring high-precision synchronous data acquisition from a large number of sensors, such as industrial measurement and control, UAV attitude sensing arrays, vibration monitoring, inertial navigation, and robot perception systems. This method is implemented based on sensors with a universal standard I2C interface, requiring no modification to sensor hardware or firmware, and possesses excellent industrial practicality and economic value. The system architecture is highly modular, allowing for flexible expansion of the number of channels based on the actual number of sensors, meeting the differentiated needs of application scenarios of different scales.

[0070] This invention physically connects the main controller's GPIO to the I2C interfaces of each sensor. The serial clock line serves only as the physical timing reference for continuously outputting a constant-frequency synchronous beat signal, while the serial data line serves only as the physical carrier line for unidirectional transmission of raw data from the sensors to the main controller. After system power-on, the SCL output is uninterrupted, locking the timing of all sensors to the same physical clock reference. When data acquisition is needed, the main controller modulates the pulse width or frequency characteristics of one or more clock cycles on the SCL line to generate a specific clock waveform as a global synchronization trigger command. The external timing recognition circuits at the front end of each sensor simultaneously capture, recognize, and synchronously output the acquisition start level, driving all sensors to complete sampling and latching at the same time. Subsequently, the main controller waits for the data to stabilize at preset time intervals. Within the first stable data window, without sending any start conditions, addresses, read / write commands, or waiting for ACK responses, it directly and in parallel captures the raw data on all SDA lines within the same continuous clock window. Combined with hardware timestamp binding and parallel fault detection redundancy switching, a complete synchronous acquisition cycle is completed.

[0071] Therefore, this invention achieves nanosecond-level synchronous acquisition with a full-channel timing deviation ≤5ns, acquisition efficiency improved by 3-8 times, and a time stamp deviation ≤10ns through the synergistic effects of physical layer redefinition of SCL and SDA functions, uninterrupted global clock output, clock waveform modulation triggering, channel-by-channel hardware delay calibration, address-free and ACK-free one-time parallel acquisition, open-loop predictive reading, and hardware instantaneous timestamp binding. Simultaneously, it achieves single-point fault isolation and system fault tolerance through independent SDA physical isolation, parallel fault detection, and seamless switching of redundant channels, and supports seamless switching between standard I2C and high-synchronization parallel modes, compatible with general I2C sensors. These features are mutually supportive and deeply coupled, jointly breaking through the inherent architectural constraints of the standard I2C protocol's "shared bus, serial polling, and mandatory acknowledgment" architecture, providing a new technical path for high-synchronization, high-efficiency, and high-reliability parallel acquisition of large-scale sensor arrays.

[0072] The above description is merely a preferred embodiment of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention is not limited to the specific combination of the above-described technical features, but also includes other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this invention.

Claims

1. A high-synchronization multi-sensor I2C parallel acquisition method, wherein the I2C bus has a serial clock line and multiple independently configured serial data lines, characterized in that, Each general purpose input / output port of the main controller has an independent SDA trace as a serial data line connected to the SDA pin of a sensor, so that each sensor and the main controller form an independent communication channel. The acquisition method includes the following steps: The shared clock drive unit in the main controller sends data acquisition signals to the SCL pins of each sensor via the serial clock line output terminal. The data acquisition signals are specific clock waveforms after instantaneous modulation of pulse width or frequency characteristics. Based on the data acquisition signals, after the external timing recognition circuit corresponding to each sensor recognizes the data acquisition signal through each communication channel, it synchronously outputs the acquisition start level to the sensor connected to it at the same clock edge, driving all sensors to perform AD sampling and data latching at the same time to obtain sampled data; each communication channel is set with a corresponding compensation parameter, which is used to align the sampling data edges of all communication channels to the same clock window during subsequent acquisition; The main controller receives the sampled data latched by each of the sensors through each of the serial data lines, so that the raw data on all the serial data lines arrives at the input terminal of the main controller synchronously.

2. The highly synchronous multi-sensor I2C parallel acquisition method according to claim 1, characterized in that, The method also includes: After the system is powered on, the shared clock drive unit continuously outputs a constant frequency synchronous beat signal to the SCL pin of each sensor via its serial clock line, so that all sensors are continuously locked to the same physical clock reference and are in a standby listening state.

3. The highly synchronous multi-sensor I2C parallel acquisition method according to claim 2, characterized in that, The specific clock waveform is a first special clock cycle in which at least one pulse width is compressed to less than 1 / 3 of the normal pulse width, or a second special clock cycle in which at least one pulse width is extended to twice the normal pulse width, is inserted into the constant frequency synchronous beat signal. The total duration of the specific clock waveform is less than or equal to three complete clock cycles of the synchronization beat signal.

4. The highly synchronous multi-sensor I2C parallel acquisition method according to claim 1, characterized in that, The external timing recognition circuit has a pre-stored pulse width counting threshold range or frequency counting reference corresponding to the specific clock waveform. The external timing recognition circuit monitors the actual waveform on the serial clock line in real time. When it detects that the pulse width of the actual waveform exceeds the upper or lower boundary of the pulse width counting threshold range, or when it detects that the frequency offset of the actual waveform exceeds the tolerance range of the frequency counting reference, it determines that the specific clock waveform is successfully recognized, and then outputs the acquisition start level on the same clock edge. The acquisition start level is a hardware level pulse that lasts for one or more clock cycles, directly driving the enable pin of the sensor.

5. The highly synchronous multi-sensor I2C parallel acquisition method according to claim 3, characterized in that, The main controller receives sampled data latched by each sensor through each of the serial data lines, including: After emitting the specific clock waveform, the shared clock driving unit waits for a preset time interval, and in the first stable data window adjacent to the preset time interval, directly captures the raw data on all the serial data lines in parallel at the same clock window.

6. The highly synchronous multi-sensor I2C parallel acquisition method according to claim 3, characterized in that, The main controller is configured with a programmable hardware delay unit corresponding to each communication channel, and the process for determining the compensation parameters is as follows: The main controller sends a standard calibration edge signal to each of the communication channels through a programmable hardware delay unit in each of the communication channels; The measured phase difference between the standard calibration edge signal and the clock capture edge of the preset unified serial clock line is detected on each of the communication channels. Based on the measured phase difference of each communication channel, compensation parameters for each communication channel are independently configured to compensate for timing deviations in the synchronous acquisition of raw data by all communication channels.

7. The highly synchronous multi-sensor I2C parallel acquisition method according to claim 1, characterized in that, The method also includes: The main controller monitors the level transition integrity, signal edge steepness, and data code validity on each communication channel in real time, and confirms the communication status of each communication channel based on the level transition integrity, signal edge steepness, and data code validity. When the communication status of any of the communication channels is determined to be faulty, the physical connection between the communication channel and the input terminal of the main controller is cut off, and an idle backup channel is called from the preset redundant backup SDA channel group. The channel mapping table is updated, and the output of the sensor corresponding to the communication channel in the faulty state is physically switched to the idle backup channel.

8. The highly synchronous multi-sensor I2C parallel acquisition method according to claim 2, characterized in that, While capturing raw data on all serial data lines within the same continuous clock window, the main controller uses the constant frequency synchronization beat signal as the same source time reference to instantaneously read the current time count value and bind a unified timestamp to the sampled data of all communication channels in the current batch.

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