A bus arbitration system, method and electronic device

Abstract

The application discloses a bus arbitration system, method and electronic equipment, and relates to the technical field of integrated circuits. Since bus arbitration between a plurality of master devices and a plurality of slave devices is realized through a logic device, and the logic device comprises a routing matrix module for establishing a plurality of bidirectional buffer channels for full cross communication connection between the plurality of master devices and the plurality of slave devices, the routing matrix module can connect and control a corresponding target bidirectional buffer channel according to a bus authorization signal and a bus state identification signal corresponding to a bus arbitration result, multicast communication of the master device to the plurality of slave devices is realized, and polling switching channels are not needed, thereby improving bus utilization.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a bus arbitration system, method and electronic device. Background Technology

[0002] With the increasing integration of electronic systems, the demand for communication and parallel access between multiple master devices and multiple slave devices via the I3C bus is growing. In related technologies, I3C bus arbitration is typically based on bus multiplexers. However, because bus multiplexers are usually limited by a fixed channel structure, they cannot achieve one-to-many multicast communication, and synchronous control of multiple devices requires polling and switching channels, resulting in extremely low bus utilization. Summary of the Invention

[0003] This application provides a bus arbitration system, method, and electronic device to at least solve the problems in the related art where one-to-many multicast communication cannot be realized, and where multi-device synchronous control requires polling and switching channels, resulting in extremely low bus utilization.

[0004] This application provides a bus arbitration system, including: a logic device connecting multiple master devices and multiple slave devices, wherein the logic device is provided with a hardware priority arbitration module, a protocol awareness module and a routing matrix module, and the routing matrix module includes multiple bidirectional buffer paths for establishing a fully cross-communication connection between multiple master devices and multiple slave devices; The hardware priority arbitration module is used to acquire bus requests from multiple master devices and in-band interrupt requests from multiple slave devices. It performs hardware arbitration on the bus requests and in-band interrupt requests according to preset priorities, and outputs a bus authorization signal to the routing matrix module according to the arbitration result. The protocol awareness module is used to acquire bus requests and in-band interrupt requests. Based on the bus requests and in-band interrupt requests, it identifies the bus link status between each master device and each slave device, and outputs a bus status identification signal to the routing matrix module based on the status identification results. The routing matrix module is used to receive bus authorization signals, select the corresponding target bidirectional buffer path, and perform status control on the target bidirectional buffer path according to the bus status identification signal, so as to enable bidirectional communication between the master device and at least one slave device corresponding to the target bidirectional buffer path.

[0005] This application also provides a bus arbitration method, which is applied to any of the bus arbitration systems described above, and the method includes: The hardware priority arbitration module obtains bus requests from multiple master devices and in-band interrupt requests from multiple slave devices, performs hardware arbitration on the bus requests and in-band interrupt requests according to preset priorities, and outputs a bus authorization signal to the routing matrix module based on the arbitration result. The protocol awareness module acquires bus requests and in-band interrupt requests. Based on the bus requests and in-band interrupt requests, it identifies the bus link status between each master device and each slave device, and outputs a bus status identification signal to the routing matrix module based on the status identification results. The routing matrix module receives the bus authorization signal, selects the corresponding target bidirectional buffer path, and performs status control on the target bidirectional buffer path according to the bus status identifier signal, so as to enable bidirectional communication between the master device and at least one slave device corresponding to the target bidirectional buffer path.

[0006] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described bus arbitration methods when executing the computer program.

[0007] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described bus arbitration methods.

[0008] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described bus arbitration methods.

[0009] By implementing bus arbitration between multiple master devices and multiple slave devices through this application, and by including a routing matrix module that establishes multiple bidirectional buffer paths for fully cross-communication connections between multiple master devices and multiple slave devices, the routing matrix module can connect and control the corresponding target bidirectional buffer channels according to the bus authorization signal and bus status identifier signal corresponding to the bus arbitration result. This enables multicast communication between master devices and multiple slave devices without the need for polling and switching channels, thereby improving bus utilization. Attached Figure Description

[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of a bus arbitration system provided in an embodiment of this application; Figure 2 This is a schematic diagram of the interaction process of the bus arbitration system provided in the embodiments of this application; Figure 3 This is a schematic diagram of another bus arbitration system provided in an embodiment of this application; Figure 4A flowchart illustrating the bus arbitration method provided in this application embodiment; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0013] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0014] As a classic half-duplex serial bus, I2C has been widely used in industrial automation, automotive electronics, server hardware management, consumer electronics and other fields due to its core advantages of simple structure, low pin resource consumption and mature and stable protocol. It is one of the core buses for communication between board-level peripherals and sensors.

[0015] With the continuous improvement of electronic system integration, the number of board-level peripherals and sensor nodes has increased significantly, making the needs for concurrent management of multiple master devices, synchronous control of multiple slave devices, bus isolation, and fault tolerance increasingly urgent. The newly introduced I3C bus, as the next-generation upgrade protocol of I2C, while maintaining compatibility with I2C devices, achieves core functions such as increased transmission rate, in-band interrupts, dynamic address allocation, and hot-joining. It has already been widely applied in scenarios such as AI server BMC management, automotive-grade BMS, and intelligent multi-sensor arrays, becoming the mainstream development direction for high-performance serial buses.

[0016] Current industry-standard multi-master / multi-slave architecture extension solutions for I2C / I3C systems consistently fail to balance routing flexibility, real-time communication, and system reliability, making them ill-suited for complex bus management requirements. In particular, core scenarios such as multi-master concurrency, multi-slave synchronous control, and functional safety fault tolerance exhibit fundamental technical bottlenecks. There is an urgent need for a multi-master / multi-slave bus management solution that is fully compatible with standard protocols, enables flexible routing control, hardware-level arbitration, and fault isolation, thereby addressing the inherent shortcomings of existing technologies.

[0017] Currently, the expansion of I2C / I3C multi-master multi-slave buses is based on hardware expansion solutions using commercial bus multiplexers (MUX / Hub). This solution uses dedicated I2C / I3CMUX chips as the core, such as I2C multiplexers like TCA9548 and PCA9548, and corresponding dedicated I3C hub chips. The selection and switching of bus channels are realized through analog switches integrated inside the chip. The external master controller configures the connection between a single master device and a single slave device through registers. This is currently the most widely used bus expansion solution in the industry.

[0018] However, commercial MUX / Hub solutions have inherent limitations in routing capabilities. They only support fixed one-to-one channel switching and cannot achieve directional one-to-many multicast communication from the master device to a specified subset of slave devices. Synchronous control of multiple devices requires polling to switch channels, resulting in extremely low bus utilization. Channel expansion requires cascading multiple chips, which significantly increases system hardware complexity and cost. Furthermore, there is no built-in bus arbitration and fault isolation capability, and a single channel failure can easily affect the operation of the entire bus.

[0019] To address the aforementioned technical problems, embodiments of this application provide a bus arbitration system, method, and electronic device. By implementing bus arbitration between multiple master devices and multiple slave devices through logic devices, and including a routing matrix module that establishes multiple bidirectional buffer paths for fully cross-communication connections between the master devices and multiple slave devices, the routing matrix module can connect and control the corresponding target bidirectional buffer channels based on the bus authorization signal and bus status identifier signal corresponding to the bus arbitration result. This enables multicast communication from the master device to multiple slave devices without requiring polling and channel switching, thus improving bus utilization.

[0020] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] This application provides a bus arbitration system for performing bus arbitration in a multi-master, multi-slave scenario.

[0022] like Figure 1 The diagram shown is a schematic of a bus arbitration system provided in an embodiment of this application. The system includes a logic device (I3C / I2C slave device 0 to I3C / I2C slave device n) that connects multiple master devices (I3C / I2C master device 0 to I3C / I2C master device m) and multiple slave devices.

[0023] Among them, such as Figure 2The diagram shown is an interactive flow diagram of the bus arbitration system provided in the embodiment of this application. The logic device includes a hardware priority arbitration module, a protocol awareness module, and a routing matrix module. The routing matrix module includes multiple bidirectional buffer paths for establishing fully cross-communication connections between multiple master devices and multiple slave devices.

[0024] The hardware priority arbitration module is used to acquire bus requests from multiple master devices and in-band interrupt requests from multiple slave devices. It performs hardware arbitration on the bus requests and in-band interrupt requests according to preset priorities and outputs a bus grant signal to the routing matrix module based on the arbitration result. The protocol awareness module is used to acquire bus requests and in-band interrupt requests, identify the bus link status between each master device and each slave device based on the bus requests and in-band interrupt requests, and output a bus status identification signal to the routing matrix module based on the status identification result. The routing matrix module is used to receive the bus grant signal, select the corresponding target bidirectional buffer path, and perform status control on the target bidirectional buffer path based on the bus status identification signal, so as to enable bidirectional communication between the master device and at least one slave device corresponding to the target bidirectional buffer path.

[0025] It should be noted that the master device can be a Baseboard Management Controller (BMC), the slave device can be a Power Supply Unit (PSU), and the logic device can be a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA).

[0026] This application uses a logic device as the core hardware carrier to construct a fully hardware-based I2C / I3C multi-master, multi-slave configurable routing matrix and hardware-level priority arbitration system. It is fully compatible with the MIPI I3C V1.2 specification and the I2C standard specification, requiring no hardware or firmware modifications to external master / slave devices, and can directly replace existing MUX / Hub solutions for application deployment. The logic device is configured with M master device physical interfaces, N slave device physical interfaces, and 1 master control configuration interface (SPI / I2C bus optional). The M master device interfaces connect to external master devices, the N slave device interfaces connect to external I3C / I2C slave devices, and the master control configuration interface connects to the external system master controller to complete parameter configuration and status reading. With this architecture, users can control the logic device via I2C / SPI buses to flexibly control and switch the connection relationships between multiple master and slave devices.

[0027] Specifically, the hardware priority arbitration module can monitor all master and slave devices connected to the logic device in parallel. When multiple master devices simultaneously initiate bus requests (START signals), or multiple slave devices simultaneously initiate in-band interrupt (IBI) requests, this module performs hardware-level comparisons based on a preset priority strategy. Through a pre-arbitration mechanism, this module determines the unique highest-priority bus occupant before the bus physical layer is activated, fundamentally avoiding bus conflicts and reducing arbitration latency.

[0028] Specifically, the protocol awareness module can capture and parse the serial clock (SCL) and serial data (SDA) signals on the bus in real time, identify various states defined by the I3C / I2C protocol, and then output bus status identification signals to the routing matrix module based on the status identification results.

[0029] It should be further clarified that the bidirectional buffer path established by the routing matrix module refers to a controlled buffer circuit capable of bidirectional signal transmission. In the I3C / I2C bus, the data line (SDA) is bidirectional (master transmits, slave receives, or master receives, slave transmits), and although the clock line (SCL) is usually unidirectionally transmitted by the master device, it also requires bidirectional response capability under certain modes (such as clock stretching). The bidirectional buffer path is activated under authorization from the arbitration module to achieve low-latency signal pass-through; when unauthorized, it presents a high-impedance state to achieve physical isolation. Moreover, the routing matrix module performs state control on the selected target bidirectional buffer path based on the bus status indicator signal, such as controlling the buffer's drive strength or response mode, to ensure that signal transmission conforms to the electrical characteristics and timing requirements of the I3C / I2C protocol.

[0030] Specifically, in one embodiment, the hardware priority arbitration module can also perform hardware-level physical isolation of the interfaces corresponding to unauthorized bus requests and / or in-band interrupt requests while outputting the bus authorization signal.

[0031] It should be noted that the core design of the hardware priority arbitration module is essentially a zero-conflict arbitration mechanism based on pre-arbitration and physical isolation, which is fundamentally different from the native mechanism of standard I2C / I3C bus level-by-level arbitration: standard protocol arbitration involves all devices occupying the bus simultaneously, comparing levels bit by bit, and the losing party backs off after arbitration, still posing a risk of bus conflict; the hardware priority arbitration module first completes the priority decision within the logic device, opening the bus path only to the single highest priority request, and physically isolating all other unauthorized requests at the hardware level, completely eliminating bus conflicts from the root, with an arbitration delay of ≤5 system clock cycles (only 25ns at a 200MHz system clock).

[0032] Based on the above embodiments, such as Figure 3The schematic diagram of another bus arbitration system provided in this application embodiment shows that, as an implementable approach, in one embodiment, the logic device is further provided with multiple first bus sampling modules and multiple second bus sampling modules; the logic device is connected to the master device through the first bus sampling modules and connected to the slave device through the second bus sampling modules. The first bus sampling module is used to receive bus requests sent by the master device and forward the obtained bus requests to the hardware priority arbitration module, the protocol awareness module and the routing matrix module; the second bus sampling module is used to receive in-band interrupt requests sent by the slave device and forward the obtained in-band interrupt requests to the hardware priority arbitration module, the protocol awareness module and the routing matrix module.

[0033] It should be noted that the first bus sampling module and the second bus sampling module are the only hardware interfaces between the logic device and external I3C devices (master and slave devices). Each external device corresponds to one independent synchronous sampling channel with no resource sharing, thus avoiding interference between channels.

[0034] Specifically, in one embodiment, both the first bus sampling module and the second bus sampling module are equipped with a register synchronization circuit, a glitch filtering circuit, and a start signal edge detection circuit; the bus request includes a bus clock signal (SCL signal) and a bus data signal (SDA signal), and the in-band interrupt request includes an in-band interrupt clock signal (SCL signal) and an in-band interrupt data signal (SDA signal). In practical applications, a system global clock and a system reset signal are also included.

[0035] The register synchronization circuit is used to perform register synchronization processing on the bus clock signal and bus data signal to eliminate metastability in the bus clock signal and bus data signal, or to perform register synchronization processing on the in-band interrupt clock signal and in-band interrupt data signal to eliminate metastability in the in-band interrupt clock signal and in-band interrupt data signal; the glitch filtering circuit is used to perform glitch filtering on bus requests or in-band interrupt requests to eliminate interference pulses during request transmission; the start signal edge detection circuit is used to perform start signal edge detection on bus requests or in-band interrupt requests to generate the corresponding master device bus request flag or slave device in-band interrupt request flag.

[0036] It should be noted that the register synchronization circuit, glitch filtering circuit, and start signal edge detection circuit are all logic circuits set on the logic device.

[0037] Specifically, the register synchronization circuit can be a synchronous logic circuit composed of multiple cascaded flip-flops. Since the operating clock domain of external master or slave devices may differ from the internal system clock domain of the logic device, direct sampling can lead to metastability issues. This means the flip-flop output may be at an uncertain intermediate level for a period of time, causing the internal state machine of the logic device to malfunction or produce incorrect decisions. The register synchronization circuit synchronizes the asynchronous input signal to the internal clock domain of the logic device by performing multi-stage pacing processing on the input bus clock signal (SCL) and bus data signal (SDA) (or in-band interrupt clock / data signal). This effectively eliminates the metastability risk caused by cross-clock domain signal transmission and improves the system's operational stability under high load or high-frequency switching scenarios.

[0038] A glitch filtering circuit can specifically be a pulse suppression circuit designed based on the principles of digital filters. In complex electrical environments such as servers or industrial control systems, bus signals are highly susceptible to external electromagnetic interference during transmission, generating narrow pulses (i.e., glitches). If these glitches are misinterpreted as valid logic level changes, it will lead to protocol parsing errors or trigger false arbitration requests. A glitch filtering circuit, by setting a configurable sampling window time, determines a valid level only when the input signal maintains the same level for multiple consecutive clock cycles; otherwise, it treats it as interference pulses and filters it out. This enhances the system's anti-interference capability and avoids system malfunctions caused by transient interference.

[0039] The start signal edge detection circuit is hardware detection logic used to identify specific start conditions defined by the I2C / I3C protocol. In the I2C / I3C protocol, the start signal (START) is defined as a falling edge from high to low on the data line (SDA) while the clock line (SCL) is held high; the stop signal (STOP) is defined as a rising edge from low to high on SDA. The start signal edge detection circuit monitors the synchronized and filtered SDA and SCL signals in real time. When it detects a START condition that conforms to the protocol specification, it immediately generates the corresponding master bus request flag. Similarly, for in-band interrupts (IBI) initiated by slave devices, this circuit can also detect the falling edge of SDA within a specific window and generate a slave device in-band interrupt request flag.

[0040] Furthermore, the first bus sampling module and the second bus sampling module send the bus request or in-band interrupt request that has passed through the register synchronization circuit and the glitch filtering circuit to the protocol sensing module and the routing matrix module, respectively. They also send the obtained master device bus request flag and slave device in-band interrupt request flag to the hardware priority arbitration module, and send the bus timing and level signals to the protocol sensing module.

[0041] Based on the above embodiments, such as Figure 3 The diagram below illustrates another bus arbitration system provided in this application. As an implementable approach, in one embodiment, the logic device is further provided with a configuration processing module for receiving configuration parameters issued by an external master controller or master device; and configuring a preset priority, bus communication mode, and bus path enable according to the configuration parameters.

[0042] Among them, the external master controller is Figure 1 The external system master controller is connected to the logic devices via the SPI / I2C bus.

[0043] Specifically, the configuration processing module is the parameter hub of the entire system and the interface for interaction with the external master controller. The external master controller has two control modes, one of which is as follows: Figure 1 Therefore, one type has an independent external input (such as SPI / I2C bus), and another type is... Figure 3 As shown, the connector configuration is obtained directly from the I3C instructions of the uplink BMC (master device), which reduces wiring costs and the number of buses. Regardless of the configuration method, this module provides precise register mapping for multi-master, multi-slave scenarios and is the sole source of all module configuration parameters, which can be read and written by the uplink master device.

[0044] The configuration parameters are a set of specific data used to define the working behavior of the bus arbitration system, including priority configuration parameters, bus mode configuration parameters, and routing masks.

[0045] Specifically, in one embodiment, the configuration processing module includes: The priority register is used to send the priority configuration parameters in the configuration parameters to the hardware priority arbitration module to configure the preset priority; The bus mode control register is used to send the bus mode configuration parameters in the configuration parameters to the protocol awareness module in order to configure the bus communication module. The routing mask register is used to send the routing mask in the configuration parameters to the hardware priority arbitration module, so that the hardware priority arbitration module can determine the bus path enable between each master device and each slave device.

[0046] Specifically, the priority register is a storage unit in the configuration processing module used to store and manage arbitration priority policies. During system initialization or runtime configuration, the external master controller or master device writes configuration parameters containing priority information into this register. The priority configuration parameters specifically define the arbitration priority order among multiple master devices (such as multiple BMCs) and the priority order among in-band interrupt (IBI) requests initiated by multiple slave devices.

[0047] Specifically, the bus mode control register is a storage unit in the configuration processing module used to define the bus protocol operating mode. This register receives and stores the bus mode configuration parameters from the configuration parameters. The bus mode configuration parameters indicate under which protocol standard the current bus should operate, such as the traditional I2C mode, I3C Standard Data Rate (SDR) mode, I3C Double Data Rate (DDR) mode, and Dynamic Address Allocation (DAA) mode, or whether to enable specific I3C features (such as in-band interrupts or hot-join). The bus mode control register sends the configured mode information to the protocol awareness module, enabling the protocol awareness module to load the corresponding state machine logic and timing parameters based on the configuration information. This allows for accurate parsing of the signal sequence on the current bus, ensuring that the system can achieve correct link-layer behavior under different protocol standards.

[0048] Specifically, the routing mask register is a storage unit in the configuration processing module used to control the physical topology connections. This register stores the routing mask issued externally. The routing mask is a bitmask, where each bit corresponds to a specific intersection (i.e., a bidirectional buffered path) in the routing matrix module of the logic device. When a bit is set (e.g., set to 1), it indicates that the corresponding master-slave device path is allowed; when a bit is cleared, it indicates that the path is disabled. The routing mask register outputs the routing mask to the hardware priority arbitration module, enabling the priority arbitration module to determine the access permissions between the master and slave devices based on the routing mask, thus ensuring the legitimacy of the arbitration result.

[0049] Specifically, in one embodiment, the protocol awareness module includes: a full protocol stage identification unit, used to identify the current transmission stage of the corresponding bus link on a clock cycle according to bus requests and in-band interrupt requests, so as to obtain the status identification result of the bus link.

[0050] The transmission phase includes the idle phase, start phase, arbitration / address phase, acknowledge phase, data transmission phase, in-band interrupt phase, dynamic address allocation phase, and stop phase.

[0051] Specifically, the full protocol stage identification unit can be implemented based on a state machine. This full protocol stage identification unit does not rely on software instruction execution, but instead uses hard-wired logic to perform parallel decoding of the level combinations and transition edges of SCL and SDA (bus request and in-band interrupt request) to map the continuously changing serial bus signals into discrete, edge-aligned bus link state identification results.

[0052] Specifically, in one embodiment, the protocol awareness module further includes: The dynamic address learning unit is used to monitor the dynamic address allocation process (DAA process) of the bus to determine the mapping relationship between the dynamic address and physical interface of each slave device in order to maintain the internal routing mapping table. The device role identification unit is used to identify the device type of each master device and slave device.

[0053] Among them, the master and slave devices are divided into at least two types: I2C devices and I3C devices.

[0054] It should be noted that I3C slave devices do not have a fixed communication address at the factory; they only come with a unique identifier (PID). During bus initialization or hot-joining, the master device sends a dynamic address to the slave device through the DAA process and saves it. All subsequent read and write processes use this dynamic address for addressing. The dynamic address learning unit monitors the bus's dynamic address allocation process, which is precisely the process by which each master device allocates a dynamic address to a slave device. This is to determine the mapping relationship between each slave device's dynamic address and the physical interface (the port number of the second bus sampling module, such as S0 or S1), and to maintain the internal routing mapping table.

[0055] The routing table records the mapping entries between dynamic addresses and physical interfaces. When the hardware priority arbitration module authorizes a master device to access a certain dynamic address in subsequent bus communication, the routing matrix module can query the mapping table to locate the physical slave device interface corresponding to the dynamic address, thereby accurately selecting the corresponding bidirectional buffer path and further improving the efficiency of bus communication.

[0056] Specifically, in one embodiment, the protocol awareness module further includes: The protocol compliance verification unit is used to detect timing violations, frame format errors, and address conflict anomalies in the bus links between each master device and each slave device in real time. When the timing violations, frame format errors, and address conflict anomalies indicate that the preset link disconnection conditions are met, the unit sends the corresponding link abnormal disconnection signal to the routing matrix module so that the routing matrix module disconnects the corresponding abnormal bidirectional buffer path.

[0057] Specifically, the protocol compliance verification unit can receive the bus clock signal (SCL) and bus data signal (SDA) after synchronous processing from the first bus sampling module and the second bus sampling module, and perform cycle-by-cycle comparison and verification of the bus link status according to the electrical characteristics and timing parameters defined in the I2C and I3C protocol specifications.

[0058] Timing violation information refers to specific deviations of bus signals from the protocol specifications in terms of timing, such as clock stretching timeouts, bus idle time violations, or data setup / hold time violations. Frame format error information refers to situations where data frames do not conform to the protocol definition in terms of structure, such as incorrect start / stop conditions, misaligned acknowledge bits, or parity errors. The specific judgment criteria for timing violation information and frame format error information can be set according to actual conditions, and are not limited in this embodiment.

[0059] Address conflict exception information refers to illegal conflicts that occur during the bus arbitration process, such as dynamic address conflicts.

[0060] Specifically, the preset link disconnection conditions can be set according to actual application requirements. For example, three consecutive clock stretch timeouts or a single address conflict detection can be set to meet the preset link disconnection conditions. Then, a corresponding link abnormality disconnection signal is sent to the routing matrix module, causing the routing matrix module to disconnect the corresponding abnormal bidirectional buffer path to ensure bus communication security.

[0061] Specifically, in one embodiment, the hardware priority arbitration module includes: The request latch unit is used to synchronously latch multiple master device bus requests and multiple slave device in-band interrupt requests using the internal clock of the logic device. The priority mapping unit is used to classify the priority levels of latched bus requests and in-band interrupt requests according to preset priorities, so as to obtain the priority level classification results of bus requests and in-band interrupt requests. The parallel comparison unit is used to perform a parallel comparison of the priority level classification results of bus requests and in-band interrupt requests to determine the unique highest priority bus request or the unique highest priority in-band interrupt request in order to obtain the arbitration result.

[0062] It should be noted that the request latch unit can be a parallel full-scenario request latch circuit, synchronously latching 8 request signals (e.g., using the internal clock of the logic device as the frequency) Figure 3 It includes 4 master bus requests and 4 slave in-band interrupt requests, with no polling delay.

[0063] Specifically, the priority mapping unit can classify urgent in-band interrupt requests into the highest preemption level; classify master device bus requests into the core scheduling level; and classify ordinary in-band interrupt requests into the basic scheduling level.

[0064] For example, taking a PSU device as the slave device, an emergency in-band interruption request may include an overvoltage / overcurrent alarm, an emergency thermal threshold interruption triggered by a temperature sensor, or a data ready signal from a critical sensor. A normal in-band interruption request may include periodic data reporting from environmental monitoring sensors (temperature, humidity, and air pressure) or notification of status changes from a non-critical state machine.

[0065] Furthermore, since the number of priority classifications is limited (e.g., only three priorities can be distinguished), synchronously latched bus requests and in-band interrupt requests may have the same priority. Therefore, a parallel comparison unit can be used to perform further parallel priority comparison on the priority classification results of bus requests and in-band interrupt requests to determine the unique highest priority bus request or the unique highest priority in-band interrupt request, thereby obtaining an arbitration result. The specific comparison rules of the parallel comparison unit can be set according to actual needs, and this application embodiment does not impose specific limitations.

[0066] Since the parallel comparison unit can be implemented based on a fully hardware parallel priority comparison circuit, it can achieve fast comparison and further improve the arbitration efficiency in the bus communication process.

[0067] Furthermore, after obtaining the arbitration result, the hardware priority arbitration module feeds the arbitration result back to the configuration processing module. For low-priority requests, an interrupt needs to be triggered in a timely manner or the request needs to be reported to the uplink Master device that has not obtained bus control.

[0068] Specifically, in one embodiment, the routing matrix module includes an N-row, M-column fully cross-connect matrix (such as a 4×4 routing matrix), where N is the number of master devices and M is the number of slave devices.

[0069] Each row corresponds to a master device channel, and each column corresponds to a slave device channel. At the intersection of each row and column, there is an independent bidirectional buffer (two sets of completely independent adaptive open-drain / push-pull bidirectional synchronous buffers, corresponding to the SCL clock line and SDA data line respectively). Each bidirectional buffer has an enable control terminal. The target enable control terminal in the target bidirectional buffer receives the bus grant signal to activate the corresponding target bidirectional buffer channel according to the bus grant signal. M0~M3 correspond to I3C_M_0~I3C_M_3 respectively, and S0~S3 correspond to I3C_S_0~I3C_S_3 respectively.

[0070] It's important to note that a bidirectional buffer is a physical switch for signal on / off, typically constructed from a transmission gate or a tri-state buffer with an enable pin. Unlike a simple passive switch, this bidirectional buffer provides signal shaping, level matching, and enhanced drive capability. In the I3C / I2C bus, because the SDA line is bidirectional (master transmit / slave receive or master receive / slave transmit), and the SCL line also requires bidirectional response in certain modes (such as clock stretching), this bidirectional buffer supports lossless bidirectional signal transmission. It not only achieves physical signal connectivity but also improves signal integrity through signal regeneration. The enable control pin refers to the control signal input pin of each independent bidirectional buffer. This pin receives the bus authorization signal from the hardware priority arbitration module, which determines whether the buffer is enabled. When a bidirectional buffer at a certain intersection is not authorized, its enable control pin is invalid, and the buffer exhibits a high-impedance state. This path is physically equivalent to an open circuit, thus achieving electrical isolation.

[0071] Specifically, when the target enable control terminal receives a valid bus authorization signal, the target bidirectional buffer is activated, thereby establishing a target bidirectional buffer channel from the master device channel to the slave device channel at the physical layer. At this time, bus requests issued by the master device can be transmitted to the target slave device through this buffer; simultaneously, acknowledgment signals, data signals, or clock stretching signals returned by the target slave device can also be transmitted back to the master device through this buffer. Since the buffers at other intersections in the matrix are in a high-impedance state, this communication process is not affected by other non-target devices on the bus, nor does it interfere with other idle channels, achieving physical isolation of the communication link and further ensuring the security of bus communication.

[0072] Specifically, in one embodiment, the bidirectional buffer is an adaptive open-drain / push-pull bidirectional buffer. The bidirectional buffer can also receive the bus status identification signal output by the protocol sensing module and switch between open-drain mode and push-pull mode according to the bus status identification signal.

[0073] It should be noted that the adaptive open-drain / push-pull bidirectional buffer is a hardware buffer circuit with two selectable output drive architectures. In open-drain (OD) mode, the buffer's output is connected to the drain of an N-type field-effect transistor (NFET), with the source grounded and the gate controlled by the input signal. When the input is high, the transistor is off, the output is in a high-impedance state, and the bus is pulled high by an external or internal pull-up resistor; when the input is low, the transistor is on, and the output is forced to low. In push-pull (PP) mode, the buffer internally uses complementary P-type (PFET) and N-type (NFET) field-effect transistors to form a totem-pole structure. When the input is high, the PFET is on, the PPFET is off, and the output is actively driven to high; when the input is low, the PFET is off, the NFET is on, and the output is actively driven to low.

[0074] Specifically, the routing matrix module performs state control on the selected bidirectional buffer path based on the bus status identification signal, such as controlling the drive strength or response mode of the buffer, to ensure that the signal transmission conforms to the electrical characteristics and timing requirements of the I3C / I2C protocol.

[0075] For example, when the bus status indicator signal indicates that it is currently in a high-speed data transmission phase of I3C SDR (Single Data Rate) or DDR (Double Data Rate), the buffer can switch to push-pull mode. In push-pull mode, the buffer can actively and quickly drive the bus to a full-swing high or low level. The specific switching rules between open-drain mode and push-pull mode can be limited according to the actual application scenario, and are not limited in the embodiments of this application.

[0076] The bus arbitration system provided in this application embodiment achieves bus arbitration between multiple master devices and multiple slave devices through logic devices. These logic devices include a routing matrix module that establishes multiple bidirectional buffer paths for fully cross-communication connections between the master devices and multiple slave devices. The routing matrix module can connect and control the corresponding target bidirectional buffer channels based on the bus authorization signal and bus status identifier signal corresponding to the bus arbitration result. This enables multicast communication from the master device to multiple slave devices without the need for polling and channel switching, thus improving bus utilization. Furthermore, it implements core functions such as flexible routing management under the I2C / I3C bus multi-master multi-slave architecture, nanosecond-level zero-conflict bus arbitration, native I3C protocol adaptation, and high-reliability fault isolation. It possesses high feasibility, strong full-scenario compatibility, and high real-time performance, fundamentally solving the long-standing technical problems of insufficient routing flexibility, high bus conflict rate, poor real-time performance, single-point failure leading to full bus paralysis, and inability to natively adapt to the core characteristics of the I3C protocol in existing I2C / I3C multi-master multi-slave extension solutions.

[0077] This application provides a bus arbitration method applied to the bus arbitration system provided in the above embodiments. The executing entity in this application is an electronic device, such as a server, desktop computer, laptop computer, tablet computer, or other electronic devices that can be used to implement bus arbitration.

[0078] like Figure 4 The diagram shown is a flowchart illustrating a bus arbitration method provided in an embodiment of this application. The method includes: Step 401: Based on the hardware priority arbitration module, obtain bus requests from multiple master devices and in-band interrupt requests from multiple slave devices, perform hardware arbitration on the bus requests and in-band interrupt requests according to the preset priority, and output a bus authorization signal to the routing matrix module according to the arbitration result. Step 402: Based on the protocol awareness module, obtain bus requests and in-band interrupt requests, identify the bus link status between each master device and each slave device according to the bus requests and in-band interrupt requests, and output bus status identification signals to the routing matrix module according to the status identification results. Step 403: Based on the bus authorization signal received by the routing matrix module, the corresponding target bidirectional buffer path is selected, and the status of the target bidirectional buffer path is controlled according to the bus status identifier signal, so as to enable bidirectional communication between the master device and at least one slave device corresponding to the target bidirectional buffer path.

[0079] Specifically, in one embodiment, the logic device further includes multiple first bus sampling modules and multiple second bus sampling modules; the logic device is connected to a master device through the first bus sampling modules and to a slave device through the second bus sampling modules, and the method further includes: Step 501: Receive the bus request sent by the master device based on the first bus sampling module, and forward the obtained bus request to the hardware priority arbitration module, the protocol awareness module and the routing matrix module; Step 502: Receive the in-band interrupt request sent by the device based on the second bus sampling module, and forward the obtained in-band interrupt request to the hardware priority arbitration module, protocol awareness module and routing matrix module.

[0080] Specifically, in one embodiment, both the first bus sampling module and the second bus sampling module are provided with a register synchronization circuit, a glitch filtering circuit and a start signal edge detection circuit; the bus request includes a bus clock signal and a bus data signal, and the in-band interrupt request includes an in-band interrupt clock signal and an in-band interrupt data signal; Specifically, register synchronization processing can be performed on the bus clock signal and bus data signal based on the register synchronization circuit to eliminate metastability in the bus clock signal and bus data signal, or register synchronization processing can be performed on the in-band interrupt clock signal and in-band interrupt data signal to eliminate metastability in the in-band interrupt clock signal and in-band interrupt data signal; glitch filtering circuit can be used to filter glitch in bus requests or in-band interrupt requests to eliminate interference pulses during request transmission; and start signal edge detection circuit can be used to detect the start signal edge of bus requests or in-band interrupt requests to generate the corresponding master device bus request flag or slave device in-band interrupt request flag.

[0081] Specifically, in one embodiment, the logic device is further provided with a configuration processing module, which can receive configuration parameters issued by an external master controller or master device based on the configuration processing module; and configure preset priority, bus communication mode and bus path enable according to the configuration parameters.

[0082] Specifically, in one embodiment, the configuration processing module includes a priority register, a bus mode control register, and a routing mask register. Specifically, it can send priority configuration parameters in the configuration parameters to the hardware priority arbitration module based on the priority register to configure a preset priority; send bus mode configuration parameters in the configuration parameters to the protocol awareness module based on the bus mode control register to configure the bus communication module; and send the routing mask in the configuration parameters to the hardware priority arbitration module based on the routing mask register so that the hardware priority arbitration module can determine the bus path enablement between each master device and each slave device.

[0083] Specifically, in one embodiment, the protocol awareness module includes: a full protocol stage identification unit, which can identify the current transmission stage of the corresponding bus link on a clock cycle based on bus requests and in-band interrupt requests, so as to obtain the status identification result of the bus link.

[0084] The transmission phase includes the idle phase, start phase, arbitration / address phase, acknowledge phase, data transmission phase, in-band interrupt phase, dynamic address allocation phase, and stop phase.

[0085] Specifically, in one embodiment, the protocol awareness module further includes: a dynamic address learning unit and a device role identification unit. Specifically, the dynamic address learning unit can monitor the dynamic address allocation process of the bus to determine the mapping relationship between the dynamic address and the physical interface of each slave device in order to maintain an internal routing mapping table; and the device role identification unit can identify the device type of each master device and slave device.

[0086] Specifically, in one embodiment, the protocol awareness module further includes: a protocol compliance verification unit, which can detect in real time the timing violation information, frame format error information, and address conflict anomaly information of the bus link between each master device and each slave device, and when the timing violation information, frame format error information, and address conflict anomaly information indicate that the preset link disconnection condition is met, send the corresponding link abnormal disconnection signal to the routing matrix module so that the routing matrix module disconnects the corresponding abnormal bidirectional buffer path.

[0087] Specifically, in one embodiment, the hardware priority arbitration module includes: a request latching unit, a priority mapping unit, and a parallel comparison unit. Specifically, the request latching unit can synchronously latch multiple master device bus requests and multiple slave device in-band interrupt requests using the internal clock of the logic device; the priority mapping unit can classify the latched bus requests and in-band interrupt requests according to preset priorities to obtain the priority classification results of the bus requests and in-band interrupt requests; and the parallel comparison unit can perform a parallel priority comparison on the priority classification results of the bus requests and in-band interrupt requests to determine the unique highest priority bus request or the unique highest priority in-band interrupt request to obtain the arbitration result.

[0088] Specifically, in one embodiment, urgent in-band interrupt requests can be classified into the highest preemption level based on the priority mapping unit; bus requests from the master device can be classified into the core scheduling level; and ordinary in-band interrupt requests can be classified into the basic scheduling level.

[0089] Specifically, in one embodiment, the hardware priority arbitration module can also perform hardware-level physical isolation of the interfaces corresponding to unauthorized bus requests and / or in-band interrupt requests while outputting the bus authorization signal.

[0090] Specifically, in one embodiment, the routing matrix module includes an N-row, M-column fully cross matrix, where N is the number of master devices and M is the number of slave devices; Each row corresponds to a master device channel, and each column corresponds to a slave device channel. An independent bidirectional buffer is provided at the intersection of each row and column. The bidirectional buffer has an enable control terminal. The target enable control terminal in the target bidirectional buffer receives the bus authorization signal to turn on the corresponding target bidirectional buffer channel according to the bus authorization signal.

[0091] Specifically, in one embodiment, the bidirectional buffer is an adaptive open-drain / push-pull bidirectional buffer, which can receive the bus status identification signal output by the protocol sensing module based on the bidirectional buffer, and switch between open-drain mode and push-pull mode according to the bus status identification signal.

[0092] For a description of the features in the embodiments corresponding to the bus arbitration method, please refer to the relevant descriptions in the embodiments corresponding to the bus arbitration system, which will not be repeated here.

[0093] Embodiments of this application also provide an electronic device, such as... Figure 5 The diagram shown is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, including a processor 10 and a memory 20. The memory 20 stores a computer program, and the processor 10 is configured to run the computer program to perform the steps in any of the above-described bus arbitration method embodiments.

[0094] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described bus arbitration method embodiments when it is run.

[0095] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0096] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described bus arbitration method embodiments.

[0097] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above-described bus arbitration method embodiments.

[0098] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0099] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0100] The above provides a detailed description of a bus arbitration system, method, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A bus arbitration system, characterized in that, include: A logic device that connects multiple master devices and multiple slave devices, wherein the logic device is provided with a hardware priority arbitration module, a protocol awareness module and a routing matrix module, and the routing matrix module includes multiple bidirectional buffer paths for establishing a fully cross-communication connection between the multiple master devices and the multiple slave devices; The hardware priority arbitration module is used to acquire bus requests from multiple master devices and in-band interrupt requests from multiple slave devices, perform hardware arbitration on the bus requests and in-band interrupt requests according to preset priorities, and output a bus authorization signal to the routing matrix module according to the arbitration result. The protocol awareness module is used to acquire the bus request and the in-band interrupt request, identify the bus link status between each master device and each slave device based on the bus request and the in-band interrupt request, and output a bus status identification signal to the routing matrix module based on the status identification result. The routing matrix module is used to receive the bus authorization signal, select the corresponding target bidirectional buffer path, and perform state control on the target bidirectional buffer path according to the bus status identifier signal, so as to enable bidirectional communication between the master device and at least one slave device corresponding to the target bidirectional buffer path.

2. The bus arbitration system according to claim 1, characterized in that, The logic device is further provided with multiple first bus sampling modules and multiple second bus sampling modules; the logic device is connected to the master device through the first bus sampling modules and to the slave device through the second bus sampling modules. The first bus sampling module is used to receive the bus request sent by the master device and forward the obtained bus request to the hardware priority arbitration module, the protocol awareness module and the routing matrix module; The second bus sampling module is used to receive the in-band interrupt request sent by the slave device and forward the obtained in-band interrupt request to the hardware priority arbitration module, the protocol awareness module and the routing matrix module.

3. The bus arbitration system according to claim 2, characterized in that, Both the first bus sampling module and the second bus sampling module are equipped with a register synchronization circuit, a glitch filtering circuit, and a start signal edge detection circuit; the bus request includes a bus clock signal and a bus data signal, and the in-band interrupt request includes an in-band interrupt clock signal and an in-band interrupt data signal; The register synchronization circuit is used to perform register synchronization processing on the bus clock signal and the bus data signal to eliminate metastability in the bus clock signal and the bus data signal, or to perform register synchronization processing on the in-band interrupt clock signal and the in-band interrupt data signal to eliminate metastability in the in-band interrupt clock signal and the in-band interrupt data signal. The glitch filtering circuit is used to filter the bus request or in-band interrupt request to eliminate interference pulses during the request transmission process. The start signal edge detection circuit is used to perform start signal edge detection on the bus request or in-band interrupt request to generate the corresponding master device bus request flag or slave device in-band interrupt request flag.

4. The bus arbitration system according to claim 1, characterized in that, The logic device also includes a configuration processing module for: Receive configuration parameters issued by an external master controller or the master device; Configure the preset priority, bus communication mode, and bus path enable according to the configuration parameters.

5. The bus arbitration system according to claim 4, characterized in that, The configuration processing module includes: A priority register is used to send the priority configuration parameters in the configuration parameters to the hardware priority arbitration module to configure the preset priority; The bus mode control register is used to send the bus mode configuration parameters in the configuration parameters to the protocol awareness module to configure the bus communication module. A routing mask register is used to send the routing mask in the configuration parameters to the hardware priority arbitration module, so that the hardware priority arbitration module can determine the bus path enable between each master device and each slave device.

6. The bus arbitration system according to claim 1, characterized in that, The protocol awareness module includes: The full protocol stage identification unit is used to identify the current transmission stage of the corresponding bus link on a clock cycle according to the bus request and the in-band interrupt request, so as to obtain the status identification result of the bus link; The transmission phase includes an idle phase, a start phase, an arbitration / address phase, an acknowledgment phase, a data transmission phase, an in-band interrupt phase, a dynamic address allocation phase, and a stop phase.

7. The bus arbitration system according to claim 6, characterized in that, The protocol awareness module further includes: The dynamic address learning unit is used to monitor the dynamic address allocation process of the bus to determine the mapping relationship between the dynamic address and the physical interface of each slave device, so as to maintain the internal routing mapping table. The device role identification unit is used to identify the device type of each master device and slave device.

8. The bus arbitration system according to claim 6, characterized in that, The protocol awareness module further includes: The protocol compliance verification unit is used to detect in real time the timing violation information, frame format error information, and address conflict anomaly information of the bus link between each master device and each slave device. When the timing violation information, frame format error information, and address conflict anomaly information indicate that the preset link disconnection condition is met, the unit sends the corresponding link abnormal disconnection signal to the routing matrix module so that the routing matrix module disconnects the corresponding abnormal bidirectional buffer path.

9. The bus arbitration system according to claim 1, characterized in that, The hardware priority arbitration module includes: A request latching unit is configured to synchronously latch the bus requests of the plurality of master devices and the in-band interrupt requests of the plurality of slave devices using the internal clock of the logic device. The priority mapping unit is used to classify the latched bus requests and in-band interrupt requests according to the preset priority, so as to obtain the priority classification result of the bus requests and in-band interrupt requests. The parallel comparison unit is used to perform a parallel priority comparison on the priority level division results of the bus request and the in-band interrupt request, and determine the unique highest priority bus request or the unique highest priority in-band interrupt request to obtain the arbitration result.

10. The bus arbitration system according to claim 9, characterized in that, The priority mapping unit is specifically used for: Emergency in-band interrupt requests are classified as the highest preemption level; The bus requests from the master device are divided into core scheduling levels; Ordinary in-band interrupt requests are classified as basic scheduling level.

11. The bus arbitration system according to claim 1, characterized in that, The hardware priority arbitration module is also used for: While outputting the bus authorization signal, hardware-level physical isolation is performed on the interfaces corresponding to unauthorized bus requests and / or in-band interrupt requests.

12. The bus arbitration system according to claim 1, characterized in that, The routing matrix module includes an N-row, M-column fully cross matrix, where N is the number of master devices and M is the number of slave devices; Each row corresponds to a master device channel, and each column corresponds to a slave device channel. An independent bidirectional buffer is provided at the intersection of each row and column. The bidirectional buffer has an enable control terminal. The target enable control terminal in the target bidirectional buffer receives the bus authorization signal to turn on the corresponding target bidirectional buffer channel according to the bus authorization signal.

13. The bus arbitration system according to claim 12, characterized in that, The bidirectional buffer is an adaptive open-drain / push-pull bidirectional buffer, and the bidirectional buffer is also used for: It receives the bus status identification signal output by the protocol sensing module and switches between open-drain mode and push-pull mode according to the bus status identification signal.

14. A bus arbitration method, characterized in that, The method is applied to the bus arbitration system as described in any one of claims 1 to 13, the method comprising: The hardware priority arbitration module acquires bus requests from multiple master devices and in-band interrupt requests from multiple slave devices, performs hardware arbitration on the bus requests and in-band interrupt requests according to preset priorities, and outputs a bus authorization signal to the routing matrix module according to the arbitration result. The protocol awareness module acquires the bus request and the in-band interrupt request, identifies the bus link status between each master device and each slave device based on the bus request and the in-band interrupt request, and outputs a bus status identification signal to the routing matrix module based on the status identification result. The routing matrix module receives the bus authorization signal, selects the corresponding target bidirectional buffer path, and performs state control on the target bidirectional buffer path according to the bus status identifier signal, so as to enable bidirectional communication between the master device and at least one slave device corresponding to the target bidirectional buffer path.

15. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the bus arbitration method as described in claim 14 when executing the computer program.

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