Memory access bridge device, system and method

Abstract

The present disclosure relates to the technical field of storage, and discloses a memory access bridging device, system and method. The memory access bridging device can comprise: a memory controller port, configured to connect the memory access bridging device with a memory controller; a memory chip port, configured to connect the memory access bridging device with a memory chip; an instruction transmission channel, connected with the memory controller port and the memory chip port respectively, configured to receive first instruction information provided by the memory controller, convert the first instruction information into second instruction information recognizable by the memory chip, and provide the second instruction information to the memory chip; and a data transmission channel, connected with the memory controller port and the memory chip port respectively, configured to transmit interactive data between the memory controller and the memory chip. The memory controller and the memory chip are of different memory generations. Through the technical solution provided by the present disclosure, free access control between the memory controller and the memory chip of different generations can be realized.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a memory access bridging device, system and method. Background Technology

[0002] With the rapid development of integrated circuits and System-on-Chips (SOC) technologies, Dynamic Random Access Memory (DRAM, such as LPDDR / DDR series), as the main memory of a system, plays a decisive role in overall system performance in terms of data throughput and energy efficiency. To standardize memory interfaces and achieve interoperability across the industry chain, the Joint Electron Device Engineering Council (JEDEC) has established strict generational standards for memory (such as LPDDR4, LPDDR4X, LPDDR5, etc.).

[0003] In existing system-on-a-chip (SoC) architectures, the memory controller and its corresponding physical layer are core components. Typically, after a specific generation of memory standard is selected during the silicon design phase, the address mapping logic, instruction state machine, periodic timing constraints, and electrical characteristics of the physical layer (such as VDDQ supply voltage, I / O signaling standards, and pin topology) of the memory controller are all hardened within the chip. This rigid underlying architecture means that existing memory controllers only support access to a single generation of memory chips and cannot support free access control for newer versions. Furthermore, considering the current severe shortage of memory chips in the global market, newer versions of memory controllers also cannot support free access control for older versions, resulting in memory chip resources not being fully, rationally, and efficiently utilized. Summary of the Invention

[0004] The purpose of this disclosure is to provide a memory access bridging device, system, and method that enables free access control between memory controllers and memory chips of different generations, flexibly adapts to the access needs of various memory chips, and realizes flexible and free configuration of memory chip access.

[0005] To address the aforementioned technical problems, a first aspect of this disclosure provides a memory access bridging device, specifically comprising: a memory controller port for connecting the memory access bridging device to a preset memory controller; a memory chip port for connecting the memory access bridging device to a preset memory chip; an instruction transmission channel connected to both the memory controller port and the memory chip port, for receiving first instruction information provided by the memory controller, converting the first instruction information into second instruction information recognizable by the memory chip, and providing the second instruction information to the memory chip; and a data transmission channel connected to both the memory controller port and the memory chip port, for transmitting interactive data between the memory controller and the memory chip; wherein the memory controller and the memory chip are of different memory generations.

[0006] In one possible implementation of the first aspect above, the memory access bridging device may include multiple memory chip ports, each memory chip port corresponding to a memory chip; the memory generation versions of the memory chips corresponding to each memory chip port may be the same or different.

[0007] In one possible implementation of the first aspect described above, such memory access bridging device may include a memory controller port configured based on the memory generation version of the memory controller; the memory controller port includes at least one or any combination of a reset receive interface, a clock receive interface, a clock enable interface, a chip select receive interface, a first instruction bus interface, a first data bus interface, a first data strobe signal interface, a data mask / invert interface, and a first impedance calibration interface.

[0008] In one possible implementation of the first aspect described above, the memory access bridge device may further include a serial communication interface, which is used to implement the initialization configuration of the memory access bridge device by the memory controller.

[0009] In one possible implementation of the first aspect above, the memory chip port is configured based on the memory generation version of the memory chip; the memory chip port includes at least one or any combination of a reset output interface, a clock output interface, a data clock output interface, a chip select output interface, a second instruction bus interface, a second data bus interface, and a second impedance calibration interface.

[0010] In one possible implementation of the first aspect described above, the instruction transmission channel includes a controller physical layer, an instruction translation layer, and a memory chip physical layer connected in sequence; wherein the controller physical layer matches the memory generation version of the memory controller; and the memory chip physical layer matches the memory generation version of the memory chip.

[0011] In one possible implementation of the first aspect described above, the data transmission channel includes a data buffer for caching interactive data to match the memory generation version of the memory controller or memory chip receiving the interactive data; the data transmission channel is independent of the instruction transmission channel.

[0012] In one possible implementation of the first aspect described above, the memory access bridging device may further include a bridging control unit connected to an instruction transmission channel, for identifying first instruction information based on a first preset form; and for determining second instruction information corresponding to the first instruction information based on a second preset form according to the identified first instruction information.

[0013] In one possible implementation of the first aspect described above, the memory access bridging device may further include a power supply voltage port for supplying power to the memory controller port and the memory chip port; wherein the power supply voltage of the memory controller port is matched with the memory generation version of the memory controller; and the power supply voltage of the memory chip port is matched with the memory generation version of the memory chip.

[0014] The second aspect of this disclosure provides a memory access bridging system, which may specifically include a memory controller, a memory chip, and the memory access bridging device provided in the first aspect: the memory controller and the memory chip are communicatively connected through the memory access bridging device to realize instruction interaction and / or data interaction between the memory controller and the memory chip; wherein the memory controller and the memory chip are of different memory generations.

[0015] In one possible implementation of the second aspect described above, such a memory access bridging system may include a memory controller, multiple memory access bridging devices, and multiple memory chips; each memory access bridging device corresponds to one or more memory chips.

[0016] In one possible implementation of the second aspect above, when the memory chip is a dual-channel memory chip, each memory chip corresponds to two memory access bridge devices, and each memory access bridge device corresponds to one data channel of the memory chip.

[0017] The third aspect of this disclosure provides a memory access bridging method applied to the memory access bridging device provided in the first aspect. Specifically, it may include the following steps: receiving first instruction information provided by a memory controller, converting the first instruction information into second instruction information recognizable by a memory chip, and providing the second instruction information to the memory chip; and receiving interactive data provided by the memory controller and / or the memory chip, and performing data buffering processing on the interactive data to match the memory generation version of the memory controller or memory chip receiving the interactive data.

[0018] The technical solution provided in this disclosure enables free access control between memory controllers and memory chips of different generations. It supports the access of memory controllers of older generations to memory chips of newer generations, and also supports the access of memory controllers of newer generations to memory chips of older generations. It can flexibly adapt to the access requirements of various memory chips and realize flexible and free configuration of memory chip access. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1 This is a schematic diagram of a memory access bridging device provided according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of a physical layer structure on the memory chip side that supports the connection of multiple memory chips according to an embodiment of this disclosure; Figure 3 This is a detailed structural diagram of a memory access bridging device provided according to an embodiment of the present disclosure; Figure 4 This is a schematic diagram of a memory access bridging system provided according to an embodiment of the present disclosure; Figure 5 This is a schematic diagram of another memory access bridging system provided according to an embodiment of the present disclosure; Figure 6 This is a schematic diagram of another memory access bridging system provided according to an embodiment of the present disclosure; Figure 7 This is a flowchart illustrating a memory access bridging method provided according to an embodiment of the present disclosure. Detailed Implementation

[0021] Based on the background technology, existing memory controllers only support access to memory chips of a single generation, limiting the application scenarios for memory chip access. To address these technical issues, this disclosure provides a memory access bridging device, system, and method that enables free access control between memory controllers of different generations and memory chips, flexibly adapting to various memory chip access requirements and achieving flexible and free configuration of memory chip access.

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0023] In some embodiments of this disclosure, Figure 1A schematic diagram of a memory access bridging device is shown; as follows: Figure 1 As shown, the memory access bridging device 100 may specifically include a memory controller port 110, a memory chip port 120, an instruction transfer channel 130, and a data transfer channel 140. The specific implementation structure of the memory controller port 110 to the data transfer channel 140 will be described and explained below with reference to specific embodiments.

[0024] In some embodiments, specifically, such as Figure 1 The memory controller port 110 shown can be used to connect the memory access bridge device 100 to a preset memory controller (not shown in the figure), receive and parse data and / or instruction information provided by the memory controller, and provide data information provided by the memory chip to the memory controller; correspondingly, such as Figure 1 The memory chip port 120 shown can be used to connect the memory access bridge device 100 to a preset memory chip (also not shown in the figure), providing data and / or instruction information provided by the memory controller to the memory chip in a data format that the memory chip can understand, and receiving data information provided by the memory chip. It is understood that the memory controller, as an important bridge between the on-chip interconnect bus and the memory physical layer in the on-chip system, can translate and schedule the system's logical read / write requests into low-level physical instructions, strictly instructing the onboard memory chip to complete data access and status maintenance according to timing / cycle. In typical application scenarios, the memory controller and memory chip usually use the same memory generation version; for example, both the memory controller and memory chip can use the DDR4 generation version, or both can use the LPDDR5 generation version, without limitation here. When the memory controller and memory chip use the same memory generation version, the instruction information, clock signals, data information, etc., provided by the memory controller can be directly accepted and parsed by the memory chip, that is, the memory controller and memory chip... While direct connection between memory chips is possible, in the application scenarios provided in this disclosure, the memory controller and memory chip have different memory generation versions, making it impossible for the memory chip to directly parse the instruction information provided by the memory controller. Furthermore, the settings of various port pins differ between different memory generation versions (for example, the instruction bus width under the LPDDR4 generation version is 6 CA lines, while the instruction bus width under the LPDDR5 generation version is 7 CA lines). This prevents direct connection and data / instruction transmission between memory controllers and memory chips of different generation versions. Therefore, the memory access bridging device provided in this disclosure is needed for bridging and relaying, thereby enabling a memory controller that only supports a single memory interface to freely access memory chips of different generation versions.

[0025] In some embodiments, specifically, such as Figure 1The instruction transmission channel 130 shown can be connected to the memory controller port 110 and the memory chip port 120 respectively. It is used to receive first instruction information provided by the memory controller through the memory controller port 110, convert the first instruction information into second instruction information recognizable by the memory chip, and provide the second instruction information to the memory chip through the memory chip port 120. In some embodiments, specifically, such as... Figure 1 The data transmission channel 140 shown is also connected to the memory controller port 110 and the memory chip port 120 respectively, for transmitting interactive data between the memory controller and the memory chip. It is understandable that, in situations such as... Figure 1 The memory access bridging device 100 shown features two independent and parallel data channels: an instruction transfer channel and a data transfer channel. This design caters to the low-latency requirements of memory access. In the standard JEDEC memory protocol, the instruction / address (CA) bus and data (DQ) bus are physically separated. Therefore, the instruction transfer channel and data transfer channel are decoupled and run in parallel in the memory access bridging device's structure. The instruction transfer channel can focus on parsing and converting instruction information between different generations of memory, while the data transfer channel uses a data buffer area to re-synchronize the signals between the memory controller and the memory chip. This eliminates the need for additional data packet encapsulation or complex packet / unpacking processes, enabling cross-generational compatibility of memory chips without sacrificing the inherent low-latency characteristics of the memory. The specific implementation structures of the data transfer channel and instruction transfer channel will be further explained and illustrated later with reference to specific embodiments, and will not be elaborated upon here.

[0026] It is understandable that, through the above, Figure 1 The memory access bridging device 100 shown enables free access control between memory controllers and memory chips of different generations. It supports both older generation memory controllers connecting to newer generation memory chips and vice versa. Especially in the current context of a severe global memory chip shortage, it can flexibly adapt to various memory chip access requirements, achieving flexible and free configuration of memory chip access. The following will further explain and illustrate the detailed composition of each part of the memory access bridging device 100 with specific embodiments.

[0027] In some embodiments of this disclosure, the memory access bridging device may include a memory controller port for communicating with a memory controller. In other embodiments, the memory access bridging device may also have multiple memory controller ports to simultaneously support communication with multiple memory controllers, thereby achieving memory access bridging of multiple memory controllers. Users can configure the number of memory controller ports according to the needs of actual application scenarios, and this is not limited here. In some embodiments, specifically, the memory controller port needs to be configured based on the memory generation version of the memory controller. For example, if the generation version of the memory controller is LPDDR4, then the memory controller port of the memory access bridging device needs to be configured accordingly according to the requirements of LPDDR4. In some embodiments, specifically, the memory controller port may include at least one or any combination of a reset receive interface, a clock receive interface, a clock enable interface, a chip select receive interface, a first instruction bus interface, a first data bus interface, a first data strobe signal interface, a data mask / inversion interface, and a first impedance calibration interface. The specific definitions of each interface will be further explained and described below.

[0028] In some embodiments, the reset receiving interface can be defined as “RESET_n_X”, where “RESET” indicates receiving the reset signal from the memory controller, “n” indicates active-low, and “X” indicates the generation version of the memory controller. For example, when the reset receiving interface is configured as “RESET_n_4”, it means that for the LPDDR4 generation version memory controller, when the interface pin is pulled low, the physical layer and internal state machine of the memory access bridge device facing the LPDDR4 generation version memory controller need to be reset to the initial state. This usually occurs during the initial stage of system power-on or when the on-chip system encounters a serious error and needs to restart the memory subsystem. This is not limited here.

[0029] In some embodiments, the clock receiving interface can be defined as "CK_X", where "CK" represents the received clock signal and "X" also represents the generation version of the memory controller. In some embodiments, the clock receiving interface may further include "CK_t_X" and "CK_c_X", where "CK_t" represents the positive-phase differential clock input and "CK_c" represents the negative-phase differential clock input, which can resist external electromagnetic interference and common-mode noise at extremely high frequencies, and is not limited here. For example, when the clock receiving interface is configured as "CK_t_4" and "CK_c_4", it means that for the LPDDR4 generation version memory controller, it provides a global reference clock to the memory access bridge device. The memory access bridge device can use the intersection of the positive-phase clock and the negative-phase clock to accurately sample subsequent instruction signals, etc., and is not limited here.

[0030] In some embodiments, the clock enable interface can be defined as "CKE_X", where "CKE" indicates receiving the clock enable signal from the controller. This clock enable signal is used for power management control: when the memory controller needs to control a memory chip to enter a sleep or self-refresh state to reduce the power consumption of the memory chip, it can choose to pull the clock enable signal level low; "X" is used to indicate the generation version of the memory controller. For example, when the clock enable interface is configured as "CKE_4", it indicates that for the LPDDR4 generation memory controller, it is necessary to control a memory chip to switch to a low-power mode. It is worth noting that in the LPDDR5 generation, the physical CKE pin of the memory chip has been deprecated. Therefore, when implementing sleep control of LPDDR5 generation memory chips by the LPDDR4 generation memory controller, the memory access bridge device needs to intercept and parse the received physical CKE level changes, convert them into a "sleep command frame" in the LPDDR5 generation, and provide it to the corresponding memory chip. This is not limited here.

[0031] In some embodiments, the chip select receive interface can be defined as "CS_X", where "CS" represents the chip select signal provided by the memory controller and "X" represents the generation version of the memory controller. In some embodiments, the first instruction bus interface can be defined as "CA_X", where "CA" represents the command / address bus on the memory controller side and "X" represents the generation version of the memory controller. For example, when the first instruction bus interface is configured as "CA_4", it indicates that for the LPDDR4 generation memory controller, the supported instruction bus width is 6 CA lines, while the instruction bus width for the LPDDR5 generation is 7 CA lines, requiring a memory access bridge device to perform instruction format conversion, which is not limited here.

[0032] In some embodiments, the first data bus interface can be defined as "DQ_X", where "DQ" represents the data bus on the memory controller side, enabling bidirectional data transmission between the memory access bridge device and the memory controller, and "X" represents the generation version of the memory controller. In some embodiments, the first data strobe signal interface can be defined as "DQS_X", where "DQS" represents the data strobe signal, which can eliminate the delay difference of the global clock (CK) arriving at each data pin in high-speed data transmission, ensuring that the transmitted data signal is accurately sampled, and "X" also represents the generation version of the memory controller.

[0033] In some embodiments, the data mask / inversion interface can be defined as "DMI_X", where "DMI" represents the dual-function multiplexing of data masking and data inversion, and "X" represents the generation version of the memory controller. For example, when the data mask / inversion interface is configured as "DMI_4", it means that for the LPDDR4 generation version memory controller, it can shield data bits that do not need to be written during the write operation by pulling the corresponding DMI high, or it can invert all the data to be sent and pull the DMI pin high to notify the memory access bridge device when the number of "0"s in the transmitted data exceeds half, thereby reducing possible signal interference. This is not limited here.

[0034] In some embodiments, the first impedance calibration interface can be defined as "ZQ_X", where "ZQ" represents the impedance calibration reference for the memory controller and "X" represents the generation version of the memory controller. For example, when the first impedance calibration interface is configured as "ZQ_4", it means that for the LPDDR4 generation version memory controller, this pin is externally connected to a high-precision impedance calibration resistor on the PCB board to the power supply. The physical layer on the memory controller side of the memory access bridge device can use this impedance calibration resistor as a reference to dynamically calibrate its internal termination resistors and the resistance values ​​of the output drivers to eliminate chip manufacturing process deviations and / or operating temperature and voltage drift, thereby ensuring the stability and clarity of signal transmission. This is not limited here. It is understood that the above physical interface configuration of the memory controller port is determined according to the generation version of the memory controller. For example, for the LPDDR5 generation version memory controller, there is no need to configure the CKE physical interface. Users can freely configure the memory controller port according to the actual configuration of the memory controller, which is not limited here.

[0035] In some embodiments of this disclosure, the memory access bridging device may include a memory chip port for implementing memory access bridging with a single memory chip; in other embodiments, the memory access bridging device may include multiple memory chip ports, each corresponding to one memory chip, thus enabling a single memory access bridging device to bridge memory access to multiple memory chips. Further, in some embodiments, the memory generation versions of the memory chips corresponding to each memory chip port may be the same or different, meaning a single memory access bridging device can support memory access bridging of multiple memory chips with different generation versions, which is not limited herein.

[0036] It is understandable that when a memory access bridging device needs to connect multiple memory chips / memory particles, the capacitive load on the physical bus increases significantly, signal reflection becomes severe, and the physical distances at which signals reach different memory chips / memory particles vary, leading to timing deviations. To overcome these problems, in some embodiments of this disclosure, exemplarily, Figure 2 A schematic diagram of a physical layer structure on the memory chip side that supports the interconnection of multiple memory chips is shown, such as... Figure 2As shown, the physical layer structure 200 includes a data transmission path and a data reception path. The data transmission path is responsible for writing data to the memory chip, converting the logic signals inside the main controller into physical levels that can drive multiple external memory chips, and ensuring precise timing. Specifically, it may include a data trigger 211, a controllable delay module 212, an impedance calibration module 213, and an adjustable output driver module 214. In some embodiments, the data trigger 211, as the core of the data transmission path, temporarily stores the received data to be output 210 and determines whether to perform a data write operation based on the received output enable signal 215; the controllable delay module 212 is based on a controllable delay chain. The implementation uses a chain mechanism: Since the physical trace lengths between different memory chips and the memory access bridging device may vary, the arrival time of the clock signal 216 may differ slightly. The controllable delay module 212 can be configured to fine-tune the clock signal 216 at the picosecond level to ensure that the data content and the clock signal can be precisely aligned when they reach the target memory chip / memory particle. The impedance calibration module 213 and the adjustable output drive module 214 are used to adjust the output signal. When the memory access bridging device is connected to multiple memory chips / memory particles, the drive load is in a relatively heavy range. The impedance calibration module 213 can calibrate the internal driver impedance in real time based on the high-precision impedance calibration resistor provided in the aforementioned embodiment, and provide the calibration result to the adjustable output drive module 214 to dynamically adjust the drive capability and voltage swing of the output buffer. This can ensure that the output signal can support multiple memory chips / memory particles while avoiding severe overshoot. No further limitations are made here.

[0037] In some embodiments, such as Figure 2As shown, the data receiving path is further responsible for reading data from the memory chip. It can accurately extract the data sent back from the memory amidst high-speed, interference-laden physical signals. Specifically, it may include an adjustable reference source module 221 and an adjustable terminating resistor 222. In some embodiments, the adjustable reference source module 221 provides an adjustable reference voltage. The input receiver compares the received high-speed memory signal with this reference voltage to determine if it is the received data 220 that needs to be received. Since the signal attenuation levels of different memory chips / memory particles may vary, the reference voltage provided by the adjustable reference source module 221 can be dynamically calibrated and adjusted according to the differences in memory chips / memory particles; this is not limited here. In some embodiments, considering the signal reflection interference caused by the access of multiple memory chips / memory particles, the adjustable terminating resistor 222 can dynamically switch different terminating resistor values ​​(ODT) according to the currently read memory chip to absorb reflected waves and ensure a clean and clear received signal; this is not limited here either. It is understandable that by setting up the physical layer structure on the memory chip side that supports the connection of multiple memory chips as described above, various application problems that occur when the memory access bridging device connects multiple memory chips / memory particles can be overcome. Users can also configure the relevant physical layer structure according to the needs of actual application scenarios, which is not limited here.

[0038] In some embodiments of this disclosure, the memory chip port also needs to be configured based on the memory generation version of the memory chip. For example, if the generation version of the memory chip is LPDDR5, then the memory chip port of the memory access bridge device needs to be configured accordingly according to the requirements of LPDDR5. In some embodiments, specifically, the memory chip port may include at least one or any combination of a reset output interface, a clock output interface, a data clock output interface, a chip select output interface, a second instruction bus interface, a second data bus interface, a second data strobe signal interface, and a second impedance calibration interface. The specific definitions of each interface will be further explained and described below.

[0039] In some embodiments, the reset output interface can be defined as “RESET_n_Y”, where “RESET” indicates that a reset signal is provided to the memory chip, “n” indicates active-low, and “Y” indicates the generation version of the memory chip. For example, when the reset output interface is configured as “RESET_n_5”, it means that for the LPDDR5 generation version memory chip, it needs to be reset to the initial state when it receives the “RESET_n_5” signal. This is not limited here.

[0040] In some embodiments, the clock output interface can be defined as "CK_Y", where "CK" represents the clock signal received by the memory chip, and "Y" also represents the generation version of the memory chip. In some embodiments, the clock output interface may further include "CK_t_Y" and "CK_c_Y", where "CK_t" represents a positive-phase differential clock output and "CK_c" represents an inverted differential clock output, capable of resisting external electromagnetic interference and common-mode noise at extremely high frequencies, and is not limited here. For example, when the clock output interface is configured as "CK_t_5" and "CK_c_5", it indicates that for the LPDDR5 generation version memory chip, the received reference clock signal is used to synchronize subsequently received instruction signals, etc., and is not limited here.

[0041] In some embodiments, the data clock output interface can be defined as “WCK_Y”, where “WCK” represents the data clock signal received by the memory chip. Unlike the clock signal provided in the previous embodiments, the data clock signal is dedicated to capturing write data and outputting read data. It was introduced in the LPDDR5 generation version. The frequency of the data clock signal is usually 2 or 4 times that of the clock signal, and has a higher frequency. “Y” is also used to represent the generation version of the memory chip (generally 5 or above).

[0042] In some embodiments, the chip select receive interface can be defined as "CS_Y", where "CS" represents the chip select signal provided to the memory chip, and "Y" represents the generation version of the memory chip. In some embodiments, the second instruction bus interface can be defined as "CA_Y", where "CA" represents the command / address bus on the memory chip side, and "Y" represents the generation version of the memory chip. For example, when the second instruction bus interface is configured as "CA_5", it indicates that for LPDDR5 generation memory chips, the supported instruction bus width is 7 CA lines. The memory access bridge device needs to perform instruction format conversion on the instruction information of the memory controller before providing it, which is not limited here.

[0043] In some embodiments, the second data bus interface can be defined as "DQ_Y", where "DQ" represents the data bus on the memory chip side, enabling bidirectional data transfer between the memory access bridge device and the memory chip, and "Y" represents the generation version of the memory chip. In some embodiments, the second data strobe signal interface can be defined as "RDQS_X", where "RDQS" represents the data strobe signal on the memory chip side; "X" also represents the generation version of the memory controller. In the LPDDR5 generation version, "RDQS" is specifically responsible for the read operation of the memory chip, while the write operation is handled by "WCK", which is not limited here.

[0044] In some embodiments, the second impedance calibration interface can be defined as "ZQ_Y", where "ZQ" represents the impedance calibration reference for the memory chip, and "Y" represents the generation version of the memory chip. For example, when the second impedance calibration interface is configured as "ZQ_5", it indicates that for LPDDR5 generation version memory chips, this pin is externally connected to ground on the PCB board with another high-precision impedance calibration resistor to ensure the integrity of high-speed signal transmission on the memory chip side. This is not limited here. It is understood that the above physical interface configuration of the memory chip port is determined according to the generation version of the memory chip. Users can freely configure the memory chip port according to the actual configuration of the memory chip, which is not limited here.

[0045] In some embodiments of this disclosure, Figure 3 A detailed structural diagram of a memory access bridging device is shown, such as... Figure 3 As shown, the memory access bridging device 300 also includes a bridging control unit 310. In some embodiments, the bridging control unit 310 is connected to the instruction transmission channel 130 and is used to identify first instruction information based on a first preset form. In some embodiments, the bridging control unit 310 can further determine the second instruction information corresponding to the first instruction information based on a second preset form according to the identified first instruction information. The second preset form may be pre-loaded and set by the memory access bridging device as needed for generational version conversion, or it may be configured by the memory controller according to the accessed memory chip and issued to the memory access bridging device, which is not limited here. In some embodiments, the second preset form may simultaneously support the memory generational versions of both the memory controller and the memory chip, thereby achieving smooth conversion at the instruction information level. In other embodiments, the user may also choose other instruction conversion implementation forms according to actual needs, such as directly identifying the first instruction information and generating second instruction information matching the generational version of the memory chip through code, which is not limited here.

[0046] In some embodiments of this disclosure, such as Figure 3As shown, the instruction transmission channel 130 may further include a controller physical layer 131, an instruction translation layer 132, and a memory chip physical layer 133 connected in sequence, wherein the controller physical layer 131 matches the memory generation version of the memory controller, and the memory chip physical layer 133 matches the memory generation version of the memory chip. In some embodiments, the controller physical layer 131 and the memory chip physical layer 133 may include a portion of the memory controller ports, a portion of the memory chip ports, and corresponding circuit configuration structures, which are not limited here. In some embodiments, the bridging control unit 310 may further interact with the controller physical layer 131, the instruction translation layer 132, and the memory chip physical layer 133 respectively to realize the identification of the first instruction information, the conversion and generation of the second instruction information, and the sending of the second instruction information to the memory chip, which are not limited here.

[0047] In some embodiments of this disclosure, such as Figure 3 As shown, the data transmission channel 140 may further include a controller physical layer 141, a data buffer 142, and a memory chip physical layer 143 connected in sequence. The controller physical layer 141 and the memory chip physical layer 143 may include a portion of the memory controller port, a portion of the memory chip port, and corresponding circuit configuration structures. At least a portion of the controller physical layer 141 may share the same electronic components as at least a portion of the controller physical layer 131, and at least a portion of the memory chip physical layer 143 may share the same electronic components as at least a portion of the memory chip physical layer 133, without limitation. The data buffer 142 may be used to cache interactive data to match the memory generation version of the memory controller or memory chip receiving the interactive data. It is understandable that memory controllers and memory chips of different memory generations operate at different clock frequencies, and their clock phases are not exactly the same. Direct data transfer through the memory access bridge device can easily lead to data loss. In this case, the clock domain can be switched and matched using the data buffer 142. Furthermore, since the instruction transfer channel 130 needs to perform instruction translation between different generations, the brief time consumed by instruction translation can also be buffered by the data buffer 142. This is not limited here. In some embodiments, such as Figure 1 and Figure 3 As shown, the data transmission channel 140 is independent of the instruction transmission channel 130. The two are physically independent and logically decoupled, enabling the memory access bridging device to match the read / write latency specified by the protocol using a precise clock cycle counter. When the instruction transmission channel is processing the generational version conversion of the Nth instruction, the data transmission channel can forward the Nth instruction in parallel without blocking. The single-transfer interactive data eliminates the additional clock overhead of serial processing, effectively compressing the insertion latency of memory access bridging devices. Furthermore, compared to the traditional PCIe physical layer-based open standard Compute Express Link (CXL) protocol, the data transmission channel provided in this disclosure operates at the JEDEC native memory channel level, without any packet encapsulation or the introduction of complex link-layer retransmission mechanisms, enabling ultra-low latency for memory access.

[0048] In some embodiments of this disclosure, the memory access bridging device may further include a serial communication interface for implementing the initialization configuration of the memory access bridging device by the memory controller. Specifically, in some embodiments, the serial communication interface can enable the memory controller to configure information and write parameters to the memory access bridging device, such as sending the first preset form and the second preset form provided in the aforementioned embodiments to the memory access bridging device; this is not limited here. In some embodiments, the serial communication interface can also be used to enable the memory controller to wake up the memory access bridging device and the memory access bridging device to provide status information feedback to the memory controller; this is not limited here.

[0049] In some embodiments of this disclosure, the memory access bridging device may further include a power supply voltage port for supplying power to the memory controller port and the memory chip port. Specifically, the power supply voltage of the memory controller port matches the memory generation version of the memory controller, and the power supply voltage of the memory chip port matches the memory generation version of the memory chip. It is understood that there are differences in the input / output interface power supply voltages between different generation versions. For example, for the LPDDR4 generation version, the corresponding voltage is 0.6V; while for the LPDDR5 generation version, the corresponding voltage is 0.5V. Therefore, the memory access bridging device needs to configure different physical layer power supply voltages for the connected memory controllers and memory chips of different generation versions, which is not limited here.

[0050] In some embodiments of this disclosure, exemplarily, Figure 4 A schematic diagram of a memory access bridging system is shown, such as... Figure 4 As shown, this memory access bridging system 400 may specifically include a memory controller 410, a memory chip 420, and the memory access bridging device 300 provided in the foregoing embodiments. The memory controller 410 and the memory chip 420 are communicatively connected through the memory access bridging device 300 to enable instruction and / or data interaction between the memory controller and the memory chip. Furthermore, the memory controller and the memory chip have different memory generation versions. In some embodiments, such as... Figure 4As shown, the memory controller 410 includes an instruction-side port 411, a control port 412, and a data-side port 413. The instruction-side port 411 is connected to the controller physical layer 131 of the memory access bridge device 300, the control port 412 is connected to the bridge control unit 310, and the data-side port 413 is connected to the controller physical layer 141 of the memory access bridge device 300. The memory chip 420 may include an instruction-side port 421 and a data-side port 422. The instruction-side port 421 is connected to the memory chip physical layer 133 of the memory access bridge device 300, and the data-side port 422 is connected to the memory chip physical layer 143 of the memory access bridge device 300. This connection is not limited here.

[0051] In some embodiments of this disclosure, exemplarily, Figure 5 A schematic diagram of another memory access bridging system is shown. In some embodiments, such as... Figure 5 As shown, this memory access bridging system 500 may include a memory controller 510, multiple memory access bridging devices 520, and multiple memory chips 530, wherein each memory access bridging device 520 corresponds to one or more memory chips 530, thereby enabling access bridging between multiple memory chips and a single memory controller. In some embodiments of this disclosure, exemplarily... Figure 6 A schematic diagram of another memory access bridging system is shown. In some embodiments, such as... Figure 6 As shown, for the memory access bridging system 600, when the memory chip 630 is a dual-channel memory chip, each memory chip 630 can correspond to two memory access bridging devices 621 and 622 respectively, wherein each memory access bridging device corresponds to one data channel 631 or 632 of the memory chip 630. In some embodiments, the memory controller 610 may include two parallel instruction-side ports 611 and 612, two parallel data-side ports 613 and 614, and a control port 615, wherein the instruction-side ports 611 and 613 are connected to the memory access bridging device 621, the instruction-side ports 612 and 614 are connected to the memory access bridging device 622, and the control port 615 provides a chip select signal CS1 to the memory access bridging device 621 and a chip select signal CS2 to the memory access bridging device 622, thereby realizing the channel-wise bridging of the dual-channel memory chip 630, which is not limited here.

[0052] In some embodiments of this disclosure, exemplarily, Figure 7 A flowchart illustrating a memory access bridging method is shown. In some embodiments, such as Figure 7 The memory access bridging method 700 shown can be applied to the memory access bridging device provided in the foregoing embodiments, and may specifically include the following steps: Step 710: Receive first instruction information provided by the memory controller, convert the first instruction information into second instruction information recognizable by the memory chip, and provide the second instruction information to the memory chip. In some embodiments, the acquisition of the first instruction information and the second instruction information can be achieved by querying a preset table, which is not limited here.

[0053] Step 720: Receive interactive data provided by the memory controller and / or memory chip, and perform data buffering processing on the interactive data to match the memory generation version of the memory controller or memory chip receiving the interactive data. In some embodiments, steps 710 and 720 above can be executed synchronously or asynchronously, which is not limited here. In some embodiments, the specific execution of steps 710 and 720 above can refer to the relevant descriptions in the foregoing embodiments, which will not be repeated here.

[0054] In some embodiments of this disclosure, a computer program product is also involved, including a computer program that, when executed by a processor, implements the steps of the memory access bridging method provided in the foregoing embodiments.

[0055] In some embodiments, the computer program product may involve only a computer program, which may be carried on a storage medium or a processing device. In other embodiments, the computer program product may also be a storage medium or processing device containing the aforementioned computer program. The processing device may include one or more processors, and the storage medium. Those skilled in the art will understand that the implementation of all or part of the steps in the memory access bridging method provided in the foregoing embodiments can be accomplished by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the memory access bridging method provided in the foregoing embodiments of this disclosure.

[0056] The basic concepts have been described above. It is obvious that the detailed disclosure above is merely illustrative and does not constitute a limitation of this specification. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to this specification by those skilled in the art. Such modifications, improvements, and corrections are taught in this specification and therefore remain within the spirit and scope of the exemplary embodiments described herein.

Claims

1. A memory access bridging device, characterized in that, include: A memory controller port is used to connect the memory access bridge device to a preset memory controller; A memory chip port is used to connect the memory access bridge device to a preset memory chip. An instruction transmission channel is connected to the memory controller port and the memory chip port respectively, and is used to receive first instruction information provided by the memory controller, convert the first instruction information into second instruction information that the memory chip can recognize, and provide the second instruction information to the memory chip; A data transmission channel is connected to the memory controller port and the memory chip port respectively, and is used to transmit interactive data between the memory controller and the memory chip; The memory controller is a different generation version of the memory chip.

2. The memory access bridging device according to claim 1, characterized in that, The memory access bridging device includes multiple memory chip ports, and each memory chip port corresponds to one memory chip; The memory generation versions of the memory chips corresponding to each of the memory chip ports may be the same or different.

3. The memory access bridging device according to claim 1, characterized in that, The memory access bridging device includes a memory controller port configured based on the memory generation version of the memory controller; The memory controller port includes at least one or any combination of a reset receiving interface, a clock receiving interface, a clock enable interface, a chip select receiving interface, a first instruction bus interface, a first data bus interface, a first data strobe signal interface, a data mask / invert interface, and a first impedance calibration interface.

4. The memory access bridging device according to claim 1 or 3, characterized in that, The memory controller port also includes a serial communication interface, which is used to implement the initialization configuration of the memory access bridge device by the memory controller.

5. The memory access bridging device according to claim 1 or 2, characterized in that, The memory chip port is configured based on the memory generation version of the memory chip; The memory chip port includes at least one or any combination of multiple of the following: a reset output interface, a clock output interface, a data clock output interface, a chip select output interface, a second instruction bus interface, a second data bus interface, a second data strobe signal interface, and a second impedance calibration interface.

6. The memory access bridging device according to claim 1, characterized in that, The instruction transmission channel includes a controller physical layer, an instruction translation layer, and a memory chip physical layer connected in sequence. The physical layer of the controller is matched with the memory generation version of the memory controller; The physical layer of the memory chip is matched with the memory generation version of the memory chip.

7. The memory access bridging device according to claim 1 or 6, characterized in that, The data transmission channel includes a data buffer, which is used to cache the interactive data to match the memory generation version of the memory controller or the memory chip receiving the interactive data; The data transmission channel is independent of the instruction transmission channel.

8. The memory access bridging device according to claim 1, characterized in that, The memory access bridging device further includes a bridging control unit, which is connected to the instruction transmission channel and is used to identify the first instruction information based on a first preset form; as well as Based on the identified first instruction information, the second instruction information corresponding to the first instruction information is determined based on the second preset form.

9. The memory access bridging device according to claim 1, characterized in that, The memory access bridging device also includes a power supply voltage port for supplying power to the memory controller port and the memory chip port; The power supply voltage of the memory controller port is matched with the memory generation version of the memory controller; The power supply voltage of the memory chip port is matched with the memory generation version of the memory chip.

10. A memory access bridging system, characterized in that, The memory access bridging system includes a memory controller, a memory chip, and a memory access bridging device as described in any one of claims 1 to 9: The memory controller and the memory chip are communicatively connected through the memory access bridge device to enable instruction and / or data interaction between the memory controller and the memory chip; The memory controller is a different generation version of the memory chip.

11. The memory access bridging system according to claim 10, characterized in that, The memory access bridging system includes a memory controller, multiple memory access bridging devices, and multiple memory chips; Each of the memory access bridging devices corresponds to one or more of the memory chips.

12. The memory access bridging system according to claim 10, characterized in that, When the memory chip is a dual-channel memory chip, each memory chip corresponds to two memory access bridge devices, and each memory access bridge device corresponds to one data channel of the memory chip.

13. A memory access bridging method, characterized in that, Applied to the memory access bridging device as described in any one of claims 1 to 9, the method comprises: Receive first instruction information from the memory controller, convert the first instruction information into second instruction information recognizable by the memory chip, and provide the second instruction information to the memory chip; and The system receives interactive data provided by the memory controller and / or the memory chip, and performs data buffering processing on the interactive data to match the memory generation version of the memory controller or memory chip that received the interactive data.

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