Multi-memory access bridge device, system and method

Abstract

The present disclosure relates to the technical field of storage, and discloses a multi-memory access bridge device, system and method, wherein the multi-memory access bridge device can comprise: a memory control port connected to a memory controller, configured to receive first instruction information, the first instruction information comprising a first chip select signal, a first clock enable signal and a first command address signal for controlling a target memory chip; a memory gating port connected to a plurality of memory chips, configured to provide a second chip select signal and a second clock enable signal to the target memory chip in the plurality of memory chips based on the first instruction information; and a memory bridge port connected to the plurality of memory chips, configured to provide a second command address signal to the target memory chip in the plurality of memory chips based on the first instruction information; and the memory controller and the plurality of memory chips are not completely identical in memory generation version. The scheme provided by the present disclosure can realize access control of a single memory controller to a plurality of memory chips of different memory generation versions.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a multi-memory access bridging device, system, and method. Background Technology

[0002] With the rapid development of integrated circuits and System-on-Chips (SOC) technologies, Dynamic Random Access Memory (DRAM, such as LPDDR / DDR series), as the main memory of a system, plays a decisive role in overall system performance in terms of data throughput and energy efficiency. To standardize memory interfaces and achieve interoperability across the industry chain, the Joint Electron Device Engineering Council (JEDEC) has established strict generational standards for memory (such as LPDDR4, LPDDR4X, LPDDR5, etc.).

[0003] In existing system-on-a-chip (SoC) architectures, the memory controller and its corresponding physical layer (PHY) are core components. Their internal chip select (CS) mapping logic, periodic timing constraints, and electrical characteristics (such as drive impedance and pin topology) are all hardened during the silicon design phase. This results in existing memory controllers typically supporting only a single generation or specific protocol of memory chip access, lacking the flexibility for cross-generational compatibility. Especially in scenarios involving large-scale AI models, tasks requiring extensive contextual understanding necessitate storing large amounts of data in memory. Therefore, improving system-level memory capacity has become one of the most pressing technical challenges. Summary of the Invention

[0004] The purpose of this disclosure is to provide a multi-memory access bridging device, system, and method that enables a single memory controller to support the access of multiple memory chips and supports different settings for memory generation versions between the memory controller and the accessed memory chips, thereby enabling flexible and free configuration of multiple memory generation version chips and effectively improving the system-level memory carrying capacity.

[0005] To address the aforementioned technical problems, a first aspect of this disclosure provides a multi-memory access bridging device, specifically comprising: a memory control port connected to a preset memory controller, used to receive first instruction information provided by the memory controller, the first instruction information including a first chip select signal, a first clock enable signal, and a first command address signal for controlling a target memory chip; a memory strobe port connected to multiple memory chips, used to provide a second chip select signal and a second clock enable signal to a target memory chip among the multiple memory chips based on the first instruction information; a memory bridging port connected to multiple memory chips, used to provide a second command address signal to a target memory chip among the multiple memory chips based on the first instruction information; and a bridging access controller connected to the memory control port, the memory strobe port, and the memory bridging port, used to convert the first instruction information into second instruction information based on the memory generation version of the memory controller and the memory generation version of the target memory chip, the second instruction information including a second chip select signal, a second clock enable signal, and a second command address signal; wherein the memory generation version of the memory controller is not entirely the same as that of the multiple memory chips.

[0006] In one possible implementation of the first aspect above, the memory strobe port includes multiple chip select signal interfaces and multiple clock enable signal interfaces; the chip select signal interfaces correspond one-to-one with memory chips; the clock enable signal interfaces correspond one-to-one with memory chips.

[0007] In one possible implementation of the first aspect described above, the memory bridge port includes a command address sharing signal interface; each memory chip is connected to the command address sharing signal interface to receive a second command address signal upon receiving a second chip select signal and a second clock enable signal.

[0008] In one possible implementation of the first aspect above, the multi-memory access bridging device may further include: a memory configuration port connected to a preset memory controller for receiving memory configuration information provided by the memory controller; a configuration memory connected to the memory configuration port for storing the memory configuration information; and a bridging access controller connected to the configuration memory for converting first instruction information into second instruction information based on the memory configuration information.

[0009] In one possible implementation of the first aspect described above, the memory configuration information includes the impedance calibration value for each memory chip and the command address bus calibration value for each chip.

[0010] In one possible implementation of the first aspect described above, the configuration memory is non-volatile memory.

[0011] In one possible implementation of the first aspect described above, the multi-memory access bridging device may further include: a first memory data port and a second memory data port, wherein the first memory data port is connected to a memory controller and is used to provide bidirectional first data information transmission to the memory controller, and the second memory data port is connected to multiple memory chips and is used to provide bidirectional second data information transmission to the multiple memory chips; the bridging access controller is connected to the first memory data port and the second memory data port respectively, and is used to convert the first data information into second data information, or convert the second data information into first data information, based on the memory generation version of the memory controller and the memory generation version of the target memory chip.

[0012] The second aspect of this disclosure provides a multi-memory access bridging system, which may include a memory controller, multiple memory chips, and the multi-memory access bridging device provided in the first aspect: the memory controller and the multiple memory chips are communicatively connected through the multi-memory access bridging device to realize access control between the memory controller and the memory chips; wherein the memory generation versions of the memory controller and the multiple memory chips are not completely the same.

[0013] In one possible implementation of the second aspect above, the memory generation versions of multiple memory chips may be the same or not completely identical.

[0014] The third aspect of this disclosure provides a multi-memory access bridging method applied to the multi-memory access bridging device provided in the first aspect. This multi-memory access bridging method may include the following steps: receiving first instruction information provided by a memory controller, the first instruction information including a first chip select signal, a first clock enable signal, and a first command address signal for controlling a target memory chip; determining the target memory chip based on the first chip select signal; converting the first instruction information into second instruction information based on the memory generation version of the memory controller and the memory generation version of the target memory chip, the second instruction information including a second chip select signal, a second clock enable signal, and a second command address signal; and providing the second instruction information to the target memory chip.

[0015] In one possible implementation of the third aspect described above, the multi-memory access bridging method may further include: during the power-on startup phase of the memory controller and the multi-memory access bridging device, determining the multiple memory chips connected to the multi-memory access bridging device; determining whether memory configuration information for the multiple memory chips is pre-stored; if so, performing a conversion operation between first instruction information and second instruction information based on the memory configuration information; if not, performing an initialization calibration configuration operation for the memory chips; wherein the initialization calibration configuration operation includes an impedance calibration operation corresponding to each memory chip and a command address bus calibration operation corresponding to each chip.

[0016] The technical solution provided in this disclosure enables a single memory controller to support the access of multiple memory chips and supports different settings for memory generation versions between the memory controller and the accessed memory chips. This meets the current needs of multi-memory chip collaborative scenarios for handling long-term problems, allowing for free configuration of various memory generation versions and effectively improving the system-level memory capacity. Furthermore, the technical solution provided in this disclosure supports targeted transmitter impedance configuration and receiver reference source configuration for different memory chips during the power-on startup phase of the multi-memory access bridging device, and stores the memory configuration information through non-volatile memory. This further improves the signal transmission quality and clock synchronization accuracy during the multi-memory access bridging process, and can flexibly adapt to the needs of different multi-memory application scenarios. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 This is a schematic diagram of the structure of a multi-memory access bridging device according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of another multi-memory access bridging device provided according to an embodiment of the present disclosure; Figure 3 This is a schematic diagram of a multi-memory access bridging system provided according to an embodiment of the present disclosure; Figure 4 This is a flowchart illustrating a multi-memory access bridging method provided according to an embodiment of this disclosure; Figure 5 This is a schematic diagram of a process for configuring memory configuration information during the power-on startup phase, according to an embodiment of this disclosure. Detailed Implementation

[0019] Based on the background technology, existing memory controllers only support access to a single generation of memory chips, lack the flexibility for cross-generation compatibility, and have weak system-level memory integration capabilities. To address these issues, this disclosure provides a multi-memory access bridging device, system, and method. This enables a single memory controller to support access to multiple memory chips and supports different memory generation versions between the memory controller and the accessed memory chips. It meets the current needs of multi-memory chip collaborative scenarios for handling long-term problems, allowing for flexible and free configuration of various memory generation versions.

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0021] In some embodiments of this disclosure, Figure 1 A schematic diagram of a multi-memory access bridging device is shown; as follows: Figure 1 As shown, the multi-memory access bridging device 100 may specifically include a memory control port 110, a memory strobing port 120, a memory bridging port 130, and a bridging access controller 140. The specific implementation structure of the memory control port 110 to the bridging access controller 140 will be described and explained below with reference to specific embodiments.

[0022] In some embodiments, specifically, such as Figure 1The memory control port 110 shown can be used to connect a multi-memory access bridge device and a preset memory controller (not shown in the figure) to receive first instruction information provided by the memory controller. In some embodiments, specifically, the first instruction information may include a first chip select signal, a first clock enable signal, and a first command address signal for controlling the target memory chip. The target memory chip may be the memory chip that the memory controller currently wants to perform access control on, and may be a single memory chip or multiple memory chips, which is not limited here. In some embodiments, the first chip select signal can be used to select the target memory chip to be accessed from the multiple memory chips provided by the multi-memory access bridge device 100. The enable function of the first chip select signal can be used to wake up the corresponding target memory chip to enable the reception of the command address bus. In some embodiments, when the clock enable signal is high, the internal clock circuit, input buffer, and output driver of the memory chip will be activated; when the clock enable signal is low, the internal clock circuit, input buffer, and output driver will be deactivated. The entry and exit of the memory chip's power-saving mode can be realized by the level transition / switching of the clock enable signal, which is not limited here. In some embodiments, the first command address signal is used to determine the specific operation instruction carried by the first instruction information and the access memory location of the target memory chip. The specific operation instruction may include read instructions, write instructions, activate row instructions, precharge instructions, refresh instructions, etc., and is not limited thereto. The access memory location includes operating on and / or accessing specific banks, specific rows, and specific columns of data in multiple target memory chips, and is not limited thereto. In some embodiments, the memory control port 110 may specifically include a command address signal interface CA_X, a clock enable signal interface CKE_X, and a chip select signal interface CS_X, where X represents the memory generation version of the memory controller, and Y represents the memory generation version of the memory chip, and is not limited thereto.

[0023] In some embodiments, specifically, such as Figure 1The memory strobe port 120 shown can connect to multiple memory chips (also not shown in the figure) and is used to provide a second chip select signal and a second clock enable signal to a target memory chip among the multiple memory chips based on the first instruction information. In some embodiments, the memory controller enables access to multiple memory chips through the multi-memory access bridging device 100 provided in this disclosure. The memory generation version of these memory chips may be the same as or different from the memory generation version of the memory controller. That is, the memory controller is not completely the same as the memory generation version of the multiple memory chips. The memory generation version of the memory controller may be different from at least some of the memory generation versions of the multiple memory chips, or it may be different from all of the memory generation versions of the multiple memory chips. This is not limited here. It is understandable that when the memory controller and a memory chip share the same memory generation version, the command address signals and clock enable signals provided by the memory controller can be directly received and parsed by the memory chip. However, when the memory controller and a memory chip have different memory generation versions, due to the strict differences in instruction information transmission between different memory generations (for example, the instruction bus width under the LPDDR4 generation is 6 CA lines, while the instruction bus width under the LPDDR5 generation is 7 CA lines), the memory chip cannot directly parse the instruction information provided by the memory controller. Therefore, the multi-memory access bridging device 100 provided in this disclosure is needed for instruction translation and bridging. In some embodiments, such as Figure 1 The memory strobe port 120 shown can select a target memory chip and perform corresponding chip select strobe control according to the first instruction information. In some embodiments, the second chip select signal can be determined based on the first chip select signal in the first instruction information; in other embodiments, the second clock enable signal can be determined based on the first clock enable signal in the first instruction information; the specific acquisition of the second chip select signal and the second clock enable signal provided by the memory strobe port 120 will be further explained and described later in conjunction with specific embodiments, and will not be repeated here.

[0024] In some embodiments, specifically, such as Figure 1The memory bridging port 130 shown can also connect to multiple memory chips, and is used to provide a second command address signal to the target memory chip among the multiple memory chips based on the first instruction information; the second command address signal can be specifically determined based on the first command address signal in the first instruction information, which will not be elaborated here. It can be understood that through the cooperation of the memory bridging port 130 and the memory strobe port 120, the instruction composition corresponding to the first instruction information can be divided into two parts. The memory strobe port 120 determines and wakes up the target memory chip from multiple memory chips and performs the corresponding clock domain synchronization; the memory bridging port 130 is used to provide bridging and conversion of the command address signal, thereby realizing the access bridging control of bridging the first instruction information provided by the memory controller to the target memory chip of different memory generations.

[0025] In some embodiments, specifically, such as Figure 1 The bridge access controller shown is connected to the memory control port 110, the memory strobe port 120, and the memory bridge port 130, respectively. It is used to convert first instruction information into second instruction information based on the memory generation version of the memory controller and the memory generation version of the target memory chip. Specifically, the second instruction information may include the second chip select signal, the second clock enable signal, and the second command address signal provided in the aforementioned embodiments. In some embodiments, the bridge access controller 140 is used to provide bridging conversion from the first instruction information to the second instruction information. The specific functional implementation of the bridge access controller 140 will be further explained later in conjunction with specific embodiments, and will not be repeated here.

[0026] It is understandable that, through the above, Figure 1 The multi-memory access bridging device 100 shown enables a single memory controller to support the access of multiple memory chips, and supports different memory generation versions between the memory controller and the accessed memory chips. This meets the needs of multi-memory chip collaboration scenarios for handling long-range problems encountered in current large-scale artificial intelligence model applications, allowing for flexible and free configuration of various memory generation versions of chips, effectively improving system-level memory capacity. The following will further explain and illustrate the detailed composition of each part of the multi-memory access bridging device 100 with specific embodiments.

[0027] In some embodiments of this disclosure, further, such as Figure 1As shown, the memory strobe port 120 may include multiple chip select signal interfaces CS_0, CS_1, CS_2...CS_n and multiple clock enable signal interfaces CKE_0, CKE_1, CKE_2...CKE_n, wherein the number of chip select signal interfaces and clock enable signal interfaces is the same, both equal to the number of memory chips connected to the multi-memory access bridge device 100. In some embodiments, further, the chip select signal interfaces CS_0, CS_1, CS_2...CS_n may correspond one-to-one with memory chips; similarly, the clock enable signal interfaces CKE_0, CKE_1, CKE_2...CKE_n may correspond one-to-one with memory chips. In some embodiments, when the multi-memory access bridge device is fully connected to memory chips, the number of chip select signal interfaces and clock enable signal interfaces of the memory strobe port 120 may be equal to the upper limit of the number of supported memory chips, and is not limited here.

[0028] In some embodiments of this disclosure, further, such as Figure 1 As shown, the memory bridge port 130 may include a command address sharing signal interface CA_Y, where Y corresponds to the memory generation version of the target memory chip, which is not limited here. In some embodiments, each memory chip is further connected to the command address sharing signal interface CA_Y to receive the second command address signal upon receiving the second chip select signal and the second clock enable signal. It is understood that for the chip select signal and clock enable signal provided by the multi-memory access bridge device, a point-to-point dedicated memory connection method can be adopted. For example, the first memory chip can be connected to the chip select signal interface CS_0 and the clock enable signal interface CKE_0 respectively, and the second memory chip can be connected to the chip select signal interface CS_1 and the clock enable signal interface CKE_1 respectively, etc., to achieve point-to-point access memory wake-up; while for the command address bus, a shared bus physical topology can be adopted, so that it can be connected to all access memory chips simultaneously to achieve synchronous sharing of command address signals, so that all the wake-up target memory chips can synchronously execute the corresponding access control operations, which is not limited here.

[0029] In some embodiments of this disclosure, further, Figure 2 A schematic diagram of another multi-memory access bridging device is shown; as follows: Figure 2 As shown, this type of multi-memory access bridging device 200 can also be used in, for example... Figure 1 Based on the multi-memory access bridging device 100 shown, it further includes a memory configuration port 210 and a configuration memory 220. In some embodiments, such as Figure 2The memory configuration port 210 shown can connect the multi-memory access bridge device 200 and the memory controller, and is used to receive memory configuration information provided by the memory controller. This memory configuration information may specifically include configuration information for each connected memory chip, including but not limited to impedance calibration values, command address bus calibration values, read / write data path calibration values, and specified access bridge rates for the connected memory chips, etc., which are not limited here. The specific composition and setting method of the memory configuration information will be further explained and described later in conjunction with specific embodiments, and will not be elaborated here. In some embodiments, such as... Figure 2 The configuration memory 220 shown can be connected to a memory configuration port for storing memory configuration information. In some embodiments, the configuration memory 220 can be non-volatile memory (NVM) for persistent storage of configuration information of the connected memory chip, allowing direct retrieval of memory configuration information after the multi-memory access bridging device 200 is powered on again. In other embodiments, the configuration memory 220 can also be volatile memory, requiring recalibration of various calibration values ​​after the multi-memory access bridging device 200 is powered on again to achieve higher read / write speeds and lower latency; this is not limited here. In some embodiments, such as Figure 2 As shown, the bridging access controller 140 is connected to the configuration memory 220 and is used to convert the first instruction information into the second instruction information based on the memory configuration information. That is, in the process of converting the first instruction information into the second instruction information, since the memory configuration information contains signal transmission correction information corresponding to different access memory chips, the specific timing control of the bridging conversion process can be precisely controlled based on the preset memory configuration information, which is not limited here.

[0030] In some embodiments of this disclosure, the memory configuration information may specifically include the impedance calibration value for each memory chip and the command address bus calibration value for each chip. It is understood that in scenarios with multiple memory chips connected, the physical distance between each memory chip and the multi-memory access bridging device varies, resulting in different parasitic capacitances on the traces in actual PCB board scenarios. By calibrating and setting the impedance calibration value, the resistance value of the transmitting end of the multi-memory access bridging device (i.e., the memory gating port and memory bridging port provided in the aforementioned embodiments) can be adjusted, thereby minimizing potential return loss, inter-symbol interference (ISI), and other issues. In other embodiments, the command address bus calibration value can calibrate the transmission of the command address signal to ensure that the high-speed toggling clock signal can accurately align with the middle position of the command address signal, ensuring that the memory chip can accurately receive the transmitted second command address signal; this is not limited to this specific embodiment.

[0031] In some embodiments provided in this disclosure, such as Figure 2 As shown, this type of multi-memory access bridging device 200 can also be used in, for example... Figure 1 Based on the multi-memory access bridging device 100 shown, it further includes a first memory data port 230 and a second memory data port 240. The first memory data port 230 connects the multi-memory access bridging device 200 to a memory controller, providing bidirectional first data information transmission to the memory controller. The second memory data port 240 connects the multi-memory access bridging device 200 to multiple memory chips, providing bidirectional second data information transmission to the multiple memory chips. In some embodiments, such as... Figure 2 As shown, the bridging access controller 140 is also connected to the first memory data port 230 and the second memory data port 240, respectively, for converting first data information into second data information, or vice versa, based on the memory generation version of the memory controller and the memory generation version of the target memory chip. In some embodiments, the bridging access controller 140 may further integrate multiple levels of data buffers and delay units to achieve data content caching and clock domain synchronization during data information transmission, which is not limited here. In some embodiments, specifically, the first memory data port 230 may include a first data interface DQ_X and a first data mask / inversion interface DMI_X, and the second memory data port 240 may include a second data interface DQ_Y and a second data mask / inversion interface DMI_Y, where X represents the memory generation version of the memory controller and Y represents the memory generation version of the memory chip, which is not limited here.

[0032] In some embodiments, further, when the multi-memory access bridging device 200 includes a data information path, the memory configuration information provided in the foregoing embodiments may also include data path read / write calibration values ​​corresponding to each memory chip, which can be used to fine-tune the data lines and / or data strobe lines in the multi-memory access bridging device 200 to select a better reference voltage and timing delay setting between the memory controller and a specific memory chip, without limitation.

[0033] In some embodiments of this disclosure, Figure 3 A schematic diagram of a multi-memory access bridging system is shown; as follows: Figure 3 As shown, this type of multi-memory access bridging system 300 may include a memory controller 310, multiple memory chips 320, and the multi-memory access bridging device 100 or multi-memory access bridging device 200 provided in the foregoing embodiments. In some embodiments, such as Figure 3 As shown, the memory controller 310 and multiple memory chips 320 are communicatively connected via a multi-memory access bridge device 100 or a multi-memory access bridge device 200 to achieve access control between the memory controller 310 and the memory chips 320. The memory generation versions of the memory controller 310 and the multiple memory chips 320 are not entirely the same. In some embodiments, specifically, such as... Figure 3 The memory generations of the multiple memory chips 320 shown may be the same or not completely identical, and this is not limited here. In some embodiments, further, such as Figure 3As shown, when the multi-memory access bridging device adopts the configuration of multi-memory access bridging device 200, the memory controller 310 may include a configuration providing port 311 and an access control port 312. The configuration providing port 311 may include multiple programmable general purpose input / output (GPIO) interfaces GPIO0, GPIO1, GPIO2...GPIOn. Each GPIO interface GPIO0, GPIO1, GPIO2...GPIOn is used for calibration and provision of memory configuration information for each memory chip, which is not limited here. In some embodiments, the access control port 312 may specifically include a command address signal interface CA, a chip select signal interface CS, a clock enable signal interface CKE, a data signal interface DQ, and a data mask / invert interface DMI. The chip select signal interface CS represents the chip select signal of the target memory chip to be woken up provided by the memory controller 310; the command address signal interface CA represents the command address signal provided by the memory controller 310 through the command / address bus; and the clock enable signal interface CKE activates the internal clock circuit, input buffer, and output driver of the memory chip when high, and deactivates the aforementioned internal clock circuit, input buffer, and output driver when low, through a level jump in the clock enable signal. The switching mechanism enables the entry and exit of the memory chip's power-saving mode; the data signal interface DQ is used to represent the first data signal provided by the memory controller 310 through the data bus, and the second data signal received through the data bus; the data mask / inversion interface DMI is used to represent the dual-function multiplexing of the memory controller 310's data mask and data inversion. For example, for the LPDDR4 generation version of the memory controller, it can shield the data bits that do not need to be written during the write operation by pulling the corresponding data mask / inversion interface DMI high, or when the number of "0"s in the transmitted data exceeds half, it can invert all the transmitted data and pull the DMI pin high to notify the multi-memory access bridge device, reducing possible signal interference. This is not limited here.

[0034] In some embodiments of this disclosure, Figure 4 A flowchart illustrating a multi-memory access bridging method is shown, which can be applied to the multi-memory access bridging device provided in the aforementioned embodiments; as follows: Figure 4 As shown, process 400 may specifically include the following steps: Step 410: Receive first instruction information provided by the memory controller, wherein the first instruction information includes a first chip select signal, a first clock enable signal, and a first command address signal for controlling the target memory chip.

[0035] Step 420: Determine the target memory chip based on the first chip select signal.

[0036] Step 430: Based on the memory generation version of the memory controller and the memory generation version of the target memory chip, convert the first instruction information into second instruction information, wherein the second instruction information includes a second chip select signal, a second clock enable signal, and a second command address signal. In some embodiments, specifically, when the target memory chip is determined, the target memory chip can be woken up by the second chip select signal corresponding to the first chip select signal, and the woken target memory chip can receive the second command address signal; this is not limited here.

[0037] Step 440: Provide the second instruction information to the target memory chip. It is understood that the specific implementations of steps 410 to 440 above can all be implemented with reference to the relevant technical solutions provided in the foregoing embodiments, and will not be elaborated upon here.

[0038] In some embodiments of this disclosure, further, Figure 5 This diagram illustrates a process for configuring memory configuration information during the power-on startup phase; for example... Figure 5 As shown, process 500 can be executed before process 400 provided in the foregoing embodiments, and is not limited thereto. In some embodiments, such as Figure 5 The process 500 shown may specifically include the following steps: Step 510: During the power-on startup phase of the memory controller and the multi-memory access bridge device, determine the multiple memory chips connected to the multi-memory access bridge device. In some embodiments, specifically, after the memory controller and the multi-memory access bridge device are powered on, the memory controller can determine the number of memory chips to be connected to the entire on-chip system as the number of multiple memory chips connected to the multi-memory access bridge device; this is not limited here.

[0039] Step 520: Determine whether memory configuration information for multiple memory chips is pre-stored: if yes, proceed to step 530; if no, proceed to step 540. In some embodiments, specifically, in the process of determining whether memory configuration information for multiple memory chips is pre-stored, this can be achieved by determining whether non-volatile memory exists in the multi-memory access bridging device. If non-volatile memory exists in the multi-memory access bridging device, the memory configuration information stored in the non-volatile memory can be directly loaded to implement the bridging path configuration related to each memory chip at a specified rate, which is not limited here; if non-volatile memory does not exist in the multi-memory access bridging device, it means that the multi-memory access bridging device does not have preset memory configuration information configured after power-on, and the memory controller needs to initiate an initialization configuration calibration operation, which is not limited here.

[0040] Step 530: Based on the memory configuration information, perform the conversion operation between the first instruction information and the second instruction information. It is understood that during the conversion from the first instruction information to the second instruction information, it is necessary not only to convert the instruction format to a format recognizable and parseable by the memory chip, but also to ensure clock synchronization switching between the first clock domain corresponding to the memory controller and the second clock domain corresponding to the memory chip, as well as instruction timing control. The memory configuration information enables transmitter impedance configuration and / or receiver reference source configuration in the memory access control process, achieving low-latency, high-precision memory access conversion control. This is not limited to specific steps here.

[0041] Step 540: Perform the initialization calibration configuration operation for the memory chips. In some embodiments, the initialization calibration configuration operation may specifically include an impedance calibration operation for each memory chip and a command address bus calibration operation for each chip. In some embodiments, the memory controller may initiate and sequentially perform impedance calibration on each memory chip to obtain the corresponding impedance calibration value, and store the impedance calibration value; then, the command address bus calibration operation may be initiated, and the obtained command address bus calibration value may be stored. In some embodiments, further, based on the bidirectional data transmission between the memory controller and the memory chips, the initialization calibration configuration operation may also include a data path read / write calibration operation, and the multi-memory access bridge device stores the obtained data path read / write calibration value, which is not limited here.

[0042] In some embodiments of this disclosure, a computer-readable storage medium is also disclosed, which stores computer instructions that, when executed by a processor, implement the steps of the multi-memory access bridging method provided in the foregoing embodiments. In some embodiments, the computer-readable storage medium may include flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the computer-readable storage medium may be an internal storage unit of a computer device, such as the hard disk or memory of the computer device. In other embodiments, the computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, smart media card (SMC), flash card, etc., provided on the computer device. Of course, the computer-readable storage medium may include both internal storage units and external storage devices of the computer device. Furthermore, the computer-readable storage medium may also be used to temporarily store various types of data that have been output or will be output, such as memory configuration information provided in the foregoing embodiments, etc., which are not limited herein.

[0043] In some embodiments of this disclosure, a computer program product is also involved, including a computer program that, when executed by a processor, implements the steps of the multi-memory access bridging method provided in the foregoing embodiments.

[0044] In some embodiments, the computer program product may involve only a computer program, which may be carried on a storage medium or a processing device. In other embodiments, the computer program product may also be a storage medium or processing device containing the aforementioned computer program. The processing device may include one or more processors, and the storage medium. Those skilled in the art will understand that the implementation of all or part of the steps in the multi-memory access bridging method provided in the foregoing embodiments can be accomplished by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the multi-memory access bridging method provided in the foregoing embodiments of this disclosure.

[0045] The basic concepts have been described above. It is obvious that the detailed disclosure above is merely illustrative and does not constitute a limitation of this specification. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to this specification by those skilled in the art. Such modifications, improvements, and corrections are taught in this specification and therefore remain within the spirit and scope of the exemplary embodiments described herein.

Claims

1. A multi-memory access bridging device, characterized in that, include: A memory control port is connected to a preset memory controller and is used to receive first instruction information provided by the memory controller. The first instruction information includes a first chip select signal, a first clock enable signal, and a first command address signal for controlling the target memory chip. A memory strobe port, connected to multiple memory chips, is used to provide a second chip select signal and a second clock enable signal to the target memory chip among the multiple memory chips based on the first instruction information; A memory bridge port, connecting multiple memory chips, is used to provide a second command address signal to the target memory chip among the multiple memory chips based on the first instruction information; A bridge access controller, connected to the memory control port, the memory strobe port, and the memory bridge port respectively, is used to convert the first instruction information into second instruction information based on the memory generation version of the memory controller and the memory generation version of the target memory chip. The second instruction information includes the second chip select signal, the second clock enable signal, and the second command address signal. The memory controller is not exactly the same as the memory generation version of the multiple memory chips.

2. The multi-memory access bridging device according to claim 1, characterized in that, The memory strobe port includes multiple chip select signal interfaces and multiple clock enable signal interfaces; Each chip select signal interface corresponds one-to-one with a memory chip; The clock enable signal interface corresponds one-to-one with the memory chip.

3. The multi-memory access bridging device according to claim 1 or 2, characterized in that, The memory bridge port includes a command address sharing signal interface; Each of the memory chips is connected to the command address sharing signal interface to receive the second command address signal upon receiving the second chip select signal and the second clock enable signal.

4. The multi-memory access bridging device according to claim 1, characterized in that, Also includes: A memory configuration port, connected to the memory controller, is used to receive memory configuration information provided by the memory controller; Configure the storage device, connect it to the memory configuration port, and use it to store the memory configuration information; The bridged access controller is connected to the configuration memory and is used to convert the first instruction information into the second instruction information based on the memory configuration information.

5. The multi-memory access bridging device according to claim 4, characterized in that, The memory configuration information includes the impedance calibration value for each memory chip and the command address bus calibration value for each memory chip.

6. The multi-memory access bridging device according to claim 4, characterized in that, The configuration memory is a non-volatile memory.

7. The multi-memory access bridging device according to claim 1, characterized in that, Also includes: A first memory data port and a second memory data port, wherein the first memory data port is connected to the memory controller and is used to provide bidirectional first data information transmission to the memory controller, and the second memory data port is connected to a plurality of memory chips and is used to provide bidirectional second data information transmission to the plurality of memory chips; The bridging access controller is connected to the first memory data port and the second memory data port respectively, and is used to convert the first data information into the second data information, or the second data information into the first data information, based on the memory generation version of the memory controller and the memory generation version of the target memory chip.

8. A multi-memory access bridging system, characterized in that, The multi-memory access bridging system includes a memory controller, multiple memory chips, and a multi-memory access bridging device as described in any one of claims 1 to 7. The memory controller is communicatively connected to multiple memory chips through the multi-memory access bridge device to realize access control between the memory controller and the memory chips; The memory controller is not exactly the same as the memory generation version of the multiple memory chips.

9. The multi-memory access bridging system according to claim 8, characterized in that, The memory generations of the multiple memory chips may be the same or not completely the same.

10. A multi-memory access bridging method, characterized in that, The method, applied to the multi-memory access bridging device as described in any one of claims 1 to 7, comprises: Receive first instruction information provided by the memory controller, the first instruction information including a first chip select signal, a first clock enable signal, and a first command address signal for controlling the target memory chip; The target memory chip is determined based on the first chip select signal; Based on the memory generation version of the memory controller and the memory generation version of the target memory chip, the first instruction information is converted into second instruction information, the second instruction information including a second chip select signal, a second clock enable signal, and a second command address signal; and The second instruction information is provided to the target memory chip.

11. The multi-memory access bridging method according to claim 10, characterized in that, The method further includes: During the power-on startup phase of the memory controller and the multi-memory access bridge device, the multiple memory chips connected to the multi-memory access bridge device are identified. Determine whether memory configuration information for multiple memory chips is pre-stored: if yes, then perform a conversion operation between the first instruction information and the second instruction information based on the memory configuration information; if no, then perform an initialization calibration configuration operation for the memory chips. The initialization calibration configuration operation includes impedance calibration operation for each memory chip and command address bus calibration operation for each memory chip.

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