Data transfer apparatus and method for circular buffering

Abstract

The present invention provides a data transfer apparatus and method for circular buffering. The data transfer apparatus for circular buffering can include a circular buffer and a controller. The controller can be coupled to the circular buffer. The controller can have an input direct memory access channel and a plurality of output direct memory access channels. The controller can control read operations and write operations of the circular buffer via the input direct memory access channel and the plurality of output direct memory access channels according to a circular buffer descriptor table string.

Description

Technical Field

[0001] The embodiments of the present invention are mainly related to a direct memory access (DMA) technology, and particularly to a direct memory access technology for a circular buffer. Background Technology

[0002] Peripheral Direct Memory Access (PDMA) technology is widely used in Systems on a Chip (SoC) to reduce the load on the central processing unit (CPU) for handling data transfers between peripheral devices and system memory. PDMA can have multiple channels. Each channel can transfer data independently and does not communicate with others. That is, each channel transfers data according to its corresponding descriptor table list.

[0003] A circular buffer is a commonly used data structure in software. In a multi-threaded execution environment, if the circular buffer is accessed by different threads, atomic operations are performed on the circular buffer to ensure thread safety.

[0004] How to combine multi-channel direct memory access operations with circular buffers is a topic worthy of research. Summary of the Invention

[0005] In view of the problems of the prior art described above, embodiments of the present invention provide a data transmission apparatus and method.

[0006] According to an embodiment of the present invention, a data transmission apparatus for a circular buffer is provided. The data transmission apparatus for a circular buffer may include a circular buffer and a controller. The controller may be coupled to the circular buffer. The controller may have an input direct memory access channel and multiple output direct memory access channels. The controller may control read and write operations of the circular buffer via the input direct memory access channel and the multiple output direct memory access channels according to a circular buffer descriptor table string.

[0007] According to some embodiments of the present invention, each descriptor table in the circular buffer descriptor table string includes a source address information, a destination address information, a next descriptor table information, a transfer type, and data information.

[0008] According to some embodiments of the present invention, each descriptor table in the circular buffer descriptor table string corresponds to one or more storage spaces of the aforementioned circular buffer.

[0009] According to some embodiments of the present invention, after the input direct memory access channel completes the write operation corresponding to a descriptor table of the circular buffer descriptor table string, the input direct memory access channel notifies all the output direct memory access channels in an idle state that the write operation corresponding to the descriptor table has been completed.

[0010] According to some embodiments of the present invention, when the input direct memory access channel completes the write operation corresponding to the descriptor table and the circular buffer has no space left to write, the input direct memory access channel enters an idle state.

[0011] According to some embodiments of the present invention, when one of the plurality of output direct memory access channels completes a read operation corresponding to a descriptor table of the circular buffer descriptor table string, the output direct memory access channel notifies the input direct memory access channel that the read operation corresponding to the descriptor table has been completed.

[0012] According to some embodiments of the present invention, when the above-mentioned output direct memory access channel completes the read operation corresponding to the above-mentioned descriptor table and the above-mentioned circular buffer has no unread data, the above-mentioned output direct memory access channel enters an idle state.

[0013] According to an embodiment of the present invention, a data transmission method for a circular buffer is provided. The above-described data transmission method for a circular buffer is applicable to a data transmission apparatus. The above-described direct memory access method for a circular buffer may include the following steps: A controller of the data transmission apparatus selects an input direct memory access channel and a plurality of output direct memory access channels from a plurality of direct memory access channels; and the controller controls read and write operations of a circular buffer of the data transmission apparatus via the input direct memory access channel and the plurality of output direct memory access channels, based on a circular buffer descriptor table string.

[0014] Other additional features and advantages of the present invention can be obtained by those skilled in the art through some modifications and refinements to the data transmission apparatus and method for cyclic buffering disclosed in the embodiments of the present invention, without departing from the spirit and scope of the present invention. Attached Figure Description

[0015] Figure 1 This is a block diagram showing a data transmission device 100 according to an embodiment of the present invention.

[0016] Figure 2 This is a schematic diagram of the operation of a direct memory access channel group for circular buffering according to an embodiment of the present invention.

[0017] Figure 3 This is a flowchart illustrating the operation of a direct memory access channel group for a circular buffer according to an embodiment of the present invention.

[0018] Figure 4 This is a flowchart of a data transmission method according to an embodiment of the present invention.

[0019] Symbol Explanation

[0020] 100: Data transmission device

[0021] 110: Controller

[0022] 120: Memory circuit

[0023] 200: Peripheral devices

[0024] 300: Memory device

[0025] 400: Process

[0026] 500: Circular Buffer

[0027] InCH: Input Direct Memory Access Channel

[0028] OutCH[0], OutCH[1]: Output Direct Memory Access Channel

[0029] TLB_0~TLB_N: Descriptor Tables

[0030] S410~S420: Steps Detailed Implementation

[0031] This section describes preferred embodiments of the invention and is intended to illustrate the spirit of the invention rather than to limit its scope of protection. The scope of protection of the invention shall be determined by the claims.

[0032] Figure 1 This is a block diagram showing a data transmission device 100 according to an embodiment of the present invention. Figure 1 As shown, the data transmission device 100 may include a controller 110 and a memory circuit 120. It should be noted that... Figure 1 The block diagrams shown are merely for illustrating embodiments of the present invention, and the present invention is not intended to be construed as such. Figure 1 This is a limitation. The data transmission device 100 may also include other components.

[0033] According to one embodiment of the present invention, the data transmission device 100 may be a Direct Memory Access (DMA) controller or a Peripheral DMA (PDMA) controller. Furthermore, the data transmission device 100 may be applied in a System on a Chip (SOC) and a Microcontroller Unit (MCU), but the present invention is not limited thereto. Furthermore, as... Figure 1 As shown, the data transmission device 100 can be configured between a peripheral device 200 (e.g., a Universal Asynchronous Receiver / Transmitter (UART), Serial Peripheral Interface Bus (SPI), graphics card, network card, or audio card, etc.) and a memory device (e.g., a working buffer, system memory, etc.) 300 to control read and write operations between the peripheral device 200 and the memory device 300. Specifically, the data transmission device 100 can control the read and write operations between the peripheral device 200 and the memory device 300 via a circular buffer (or ring buffer) 500. According to an embodiment of the present invention, the circular buffer 500 can also be configured in the peripheral device 200 and / or the memory device 300.

[0034] According to one embodiment of the present invention, the controller 110 may include multiple direct memory access channels (DMA channels) for controlling read and write operations of the circular buffer 500. Specifically, the controller 110 may select one input DMA channel and multiple output DMA channels from the multiple DMA channels. The selected input DMA channel and multiple output DMA channels may form a DMA channel group for reading and writing operations of the circular buffer 500. The input DMA channel may be used for writing operations to the circular buffer 500 (i.e., writing data to the circular buffer 500). The multiple output DMA channels may be used for reading operations to the circular buffer 500 (i.e., reading or moving data from the circular buffer 500). According to one embodiment of the present invention, the DMA channel may also include only one output DMA channel.

[0035] According to one embodiment of the present invention, the controller 110 can control the read and write operations of the circular buffer 500 via an input direct memory access channel and multiple output direct memory access channels based on a circular buffer descriptor table list. The circular buffer descriptor table list represents a string of descriptor tables used for the circular buffer. An input direct memory access channel can correspond to a descriptor table in the circular buffer descriptor table list. That is, an input direct memory access channel can process a write operation of the circular buffer 500 corresponding to a descriptor table at a time. One or more of the multiple output direct memory access channels can correspond to a descriptor table in the circular buffer descriptor table list. That is, each output direct memory access channel can process a read operation of the circular buffer 500 corresponding to a descriptor table at a time, or multiple output direct memory access channels can jointly process a read operation of the circular buffer 500 corresponding to a descriptor table. In an embodiment of the present invention, the input direct memory access channels and output direct memory access channels included in the direct memory access channel group share a circular buffer descriptor table list. A shared circular buffer descriptor table string can be called a circular buffer descriptor table string.

[0036] Furthermore, according to one embodiment of the present invention, each descriptor table in the circular buffer descriptor table string may correspond to one or more storage spaces (or storage addresses) of the circular buffer 500. That is, in one example, a descriptor table may correspond to a read operation or write operation corresponding to a storage space of the circular buffer 500. In another example, a descriptor table may correspond to a read operation or write operation corresponding to a group of contiguous storage spaces of the circular buffer 500.

[0037] According to one embodiment of the present invention, the circular buffer descriptor table string may be stored in memory circuitry 120. Furthermore, memory circuitry 120 may also be used to store data and software related to the data transmission method for circular buffering in the present invention for use by controller 110. According to another embodiment of the present invention, the circular buffer descriptor table string may be stored in memory device 300. Data transmission device 100 may retrieve (or load) the circular buffer descriptor table string from memory device 300.

[0038] According to one embodiment of the present invention, each descriptor table in the circular buffer descriptor table string may include source address information, destination address information, next descriptor table information, transfer type, and data information, but the present invention is not limited thereto. The source address information may include the address from which data is to be read from the circular buffer 500. The destination address information may include the address from which data is to be written to the circular buffer 500. The next descriptor table information may indicate and point to the next descriptor table corresponding to the operation to be performed after the operation corresponding to this descriptor table is completed. The transfer type may include peripheral to memory (P2M) transfer, memory to peripheral (M2P) transfer, and memory to memory (M2M) transfer, but the present invention is not limited thereto. The data information may include the size of the data to be written or read, but the present invention is not limited thereto.

[0039] According to one embodiment of the present invention, after an input direct memory access channel completes a write operation corresponding to a descriptor table in a circular buffer descriptor table string, the input direct memory access channel can notify or trigger all idle output direct memory access channels (e.g., output direct memory access channels that have completed a read operation, or output direct memory access channels that have not yet been assigned a task) that the write operation corresponding to this descriptor table has been completed (i.e., data has been written to the storage space of the circular buffer 500 corresponding to this descriptor table). Then, one or more idle output direct memory access channels can perform corresponding read operations on this descriptor table. Furthermore, after an input direct memory access channel completes a write operation corresponding to a descriptor table in a circular buffer descriptor table string, the input direct memory access channel can then perform a write operation corresponding to the next descriptor table pointed to by this descriptor table. When the input direct memory access channel completes the write operation corresponding to a descriptor table in the circular buffer descriptor table string, and there is no space left to write in the circular buffer 500 (for example, the next descriptor table pointed to by this descriptor table corresponds to an output direct memory access channel, or all write operations have been completed, but the present invention is not limited thereto), the input direct memory access channel will enter an idle state.

[0040] According to one embodiment of the present invention, when one of the plurality of output direct memory access channels completes a read operation corresponding to a descriptor table in the circular buffer descriptor table string, the output direct memory access channel may notify or trigger the input direct memory access channel that the read operation corresponding to the descriptor table has been completed (i.e., data has been read from the storage space of the circular buffer 500 corresponding to this descriptor table). Furthermore, when one of the plurality of output direct memory access channels completes a read operation corresponding to a descriptor table, and the circular buffer 500 has no unread data (e.g., the next descriptor table pointed to by the descriptor table corresponds to an input direct memory access channel, or all read operations have been completed, but the present invention is not limited thereto), the output direct memory access channel may enter an idle state.

[0041] Figure 2 This is a schematic diagram illustrating the operation of a direct memory access channel group for a circular buffer according to an embodiment of the present invention. Figure 2 As shown, the direct memory access channel group may include an input direct memory access channel InCH, an output direct memory access channel OutCH[0], and an output direct memory access channel OutCH[1]. The controller 110 can control the read and write operations of the circular buffer 500 via the input direct memory access channel InCH, the output direct memory access channel OutCH[0], and the output direct memory access channel OutCH[1] according to a circular buffer descriptor table string TBL_0~TBL_N. The input direct memory access channel InCH can be used for write operations on the circular buffer 500, and the output direct memory access channels OutCH[0] and OutCH[1] can be used for read operations on the circular buffer 500.

[0042] For example, such as Figure 2As shown, the input direct memory access channel InCH is performing a write operation on the corresponding descriptor table TBL_2, while the output direct memory access channels OutCH[0] and OutCH[1] are performing read operations on the corresponding descriptor tables TBL_0 and TBL_1, respectively. When the input direct memory access channel InCH completes the write operation on the corresponding descriptor table TBL_2, it can notify the idle output direct memory access channel OutCH[1] (for example, the output direct memory access channel OutCH[1] has completed the read operation on the corresponding descriptor table TBL_1 and entered an idle state), and the write operation on the corresponding descriptor table TBL_2 has been completed (i.e., the data has been written to the storage space of the circular buffer 500 corresponding to the descriptor table TBL_2). Therefore, the idle output direct memory access channel OutCH[1] can perform the read operation on the corresponding descriptor table TBL_2 (i.e., read data from the storage space of the circular buffer 500 corresponding to the descriptor table TBL_2). The input direct memory access channel InCH can continue to perform write operations corresponding to the next descriptor table (e.g., descriptor table TBL_3) pointed to by descriptor table TBL_2. When there is no space left to write in the circular buffer 500 (e.g., the next descriptor table pointed to by the descriptor table corresponds to the output direct memory access channel OutCH[0] or the output direct memory access channel OutCH[1], or all write operations have been completed, but this invention is not limited thereto), the input direct memory access channel InCH will enter an idle state.

[0043] It should be noted that, Figure 2 The illustrated direct memory access channel group of the circular buffer is only used to illustrate an embodiment of the present invention, but the invention is not limited thereto. The direct memory access channel group may also include a different number of output direct memory access channels.

[0044] According to one embodiment of the present invention, when the circular buffer 500 needs to perform a peripheral device-to-memory (P2M) transfer, the peripheral device can drive the data transmission device 100 to perform a write operation on the circular buffer 500 via an input direct memory access channel. Specifically, the data transmission device 100 can write data from the peripheral device into the circular buffer 500 via the input direct memory access channel according to the circular buffer descriptor table string. Furthermore, the data transmission device 100 can read the data corresponding to the write operation of the descriptor table completed by the input direct memory access channel (data already written to the circular buffer 500) from the circular buffer 500 via multiple output direct memory access channels according to the circular buffer descriptor table string, and move the read data to a memory device (e.g., a working buffer). In this embodiment, the operation of the multiple output direct memory access channels can be driven by software or by notification from the input direct memory access channels.

[0045] According to one embodiment of the present invention, when the circular buffer 500 needs to perform a memory-to-peripheral (M2P) transfer, the data transmission device 100 can be driven by software or by a notification from the output direct memory access channel to perform a write operation on the circular buffer 500 via the input direct memory access channel. Specifically, the data transmission device 100 can write data from a memory device (e.g., a working buffer) into the circular buffer 500 via the input direct memory access channel according to the circular buffer descriptor table string. Furthermore, the data transmission device 100 can read the data corresponding to the write operation completed in the descriptor table of the input direct memory access channel (i.e., the data already written to the circular buffer 500) from the circular buffer 500 via multiple output direct memory access channels according to the circular buffer descriptor table string, and transmit the read data to the peripheral device. In this embodiment, the operation of the multiple output direct memory access channels can be driven by the peripheral device.

[0046] According to one embodiment of the present invention, when the circular buffer 500 needs to perform a memory-to-memory (M2M) transfer, the data transmission device 100 can perform a write operation on the circular buffer 500 via an input direct memory access channel. Specifically, the data transmission device 100 can write data from a storage space of a memory device (e.g., a working buffer) into the circular buffer 500 according to the circular buffer descriptor table string via the input direct memory access channel. Furthermore, the data transmission device 100 can read data corresponding to the write operations completed in the descriptor tables of the input direct memory access channels (i.e., data already written to the circular buffer 500) from the circular buffer 500 via multiple output direct memory access channels according to the circular buffer descriptor table string, and move the read data to another storage space of the memory device (e.g., a working buffer). In this embodiment, the operation of the input direct memory access channel can be driven by software or by notifications from multiple output direct memory access channels. Furthermore, in this embodiment, the operation of the multiple output direct memory access channels can be driven by software or by notifications from the input direct memory access channels.

[0047] Figure 3 This is a flowchart illustrating the operation of a direct memory access channel group for a circular buffer according to an embodiment of the present invention. Figure 3 The flowchart can be applied to the data transmission device 100. For example... Figure 3 As shown, assume that the direct memory access channel group may include one input direct memory access channel InCH and N output direct memory access channels OutCHN. Controller 110 can control the read and write operations of the circular buffer 500 via the input direct memory access channel InCH and the output direct memory access channels OutCHN according to a circular buffer descriptor table string TBL_0~TBL_M. N and M can be the same integer value or different integer values.

[0048] like Figure 3As shown, in the operation of a circular buffer, in an initial state, the input direct memory access channel InCH is activated from the idle state and performs a write operation corresponding to descriptor table TBL_1. After the input direct memory access channel InCH completes the write operation corresponding to descriptor table TBL_1, it notifies the idle output direct memory access channel OutCHN that the write operation of descriptor table TBL_1 is complete. Then, the output direct memory access channel OutCHN can be activated to perform a read operation corresponding to descriptor table TBL_1. If there is still space to write in the circular buffer 500 (i.e., not full), the input direct memory access channel InCH can continue writing to the next descriptor table NextTBL pointed to by descriptor table TBL_1. If there is no space to write in the circular buffer 500 (i.e., full), the input direct memory access channel InCH can enter an idle state. Similarly, after the input direct memory access channel InCH completes the write operation corresponding to the next descriptor table NextTBL, the input direct memory access channel InCH will also notify the idle output direct memory access channel OutCHN that the write operation of the next descriptor table NextTBL has been completed, and continue to perform the write operation corresponding to another next descriptor table NextTBL.

[0049] Furthermore, when the output direct memory access channel OutCHN has completed the read operation corresponding to descriptor table TBL_1, if there is no data to be read in the circular buffer 500 (i.e., empty), the output direct memory access channel OutCHN can enter an idle state. If there is still data to be read in the circular buffer 500 (i.e., not empty), the output direct memory access channel OutCHN can continue to read the next descriptor table NextTBL pointed to by descriptor table TBL_1. In one embodiment, the reason why the input direct memory access channel InCH enters an idle state is that the descriptor table TBL it points to is still being used by an output direct memory access channel OutCH, so the input direct memory access channel InCH cannot perform a write operation. Therefore, in this embodiment, when the output direct memory access channel OutCH completes the read operation, the output direct memory access channel OutCH can notify the input direct memory access channel InCH. The input direct memory access channel InCH can check whether the circular buffer is full. If the circular buffer is not full, the input direct memory access channel InCH can perform a write operation.

[0050] It should be noted that, Figure 3The term OutCHN is used to represent all output direct memory access channels, but this invention is not limited to this. Different output direct memory access channels can also be used to handle read operations corresponding to different descriptor tables.

[0051] The circular buffer operation via a group of direct memory access channels (one input direct memory access channel and multiple output direct memory access channels) described in the embodiments of the present invention can also be applied to different data transmissions. For example, the input direct memory access channel can store the image input from a complementary metal-oxide-semiconductor (CMOS) sensor in the circular buffer for subsequent display preview and image recognition. Furthermore, the input direct memory access channel can also first compress the input image into a joint photographic experts group (JPEG) file before storing it in the circular buffer.

[0052] Figure 4 This is flow 400 of a data transmission method for circular buffering according to an embodiment of the present invention. The data transmission method for circular buffering can be applied to a data transmission device 100. In step S410, the controller of the data transmission device 100 selects an input direct memory access channel and multiple output direct memory access channels from multiple direct memory access channels.

[0053] In step S420, the controller of the data transmission device 100 controls the read and write operations of a circular buffer of the data transmission device according to a circular buffer descriptor table string, via the input direct memory access channel and the plurality of output direct memory access channels.

[0054] According to an embodiment of the present invention, in the data transmission method for a circular buffer, each descriptor table in the circular buffer descriptor table string may include source address information, destination address information, next descriptor table information, transmission type, and data information.

[0055] According to one embodiment of the present invention, in the data transmission method of the circular buffer, each descriptor table of the circular buffer descriptor table string may correspond to one or more storage spaces of the circular buffer.

[0056] According to an embodiment of the present invention, in the data transmission method for a circular buffer, after the input direct memory access channel completes the write operation corresponding to a descriptor table of the circular buffer descriptor table string, the input direct memory access channel can notify all the output direct memory access channels in an idle state that the write operation corresponding to the descriptor table has been completed.

[0057] According to an embodiment of the present invention, in the data transmission method for a circular buffer, when the input direct memory access channel completes the write operation corresponding to the descriptor table and the circular buffer has no space left to write, the input direct memory access channel can enter an idle state.

[0058] According to an embodiment of the present invention, in the data transmission method for a circular buffer, when one of the plurality of output direct memory access channels completes a read operation corresponding to a descriptor table of the circular buffer descriptor table string, the output direct memory access channel may notify the input direct memory access channel that the read operation corresponding to the descriptor table has been completed.

[0059] According to an embodiment of the present invention, in the data transmission method for a circular buffer, when the output direct memory access channel completes the read operation corresponding to the descriptor table and the circular buffer has no unread data, the output direct memory access channel can enter an idle state.

[0060] According to the data transfer method for circular buffers of the present invention, a group of direct memory access channels can be applied to write and read operations of a circular buffer (or ring buffer). Furthermore, the input and output direct memory access channels included in the group of direct memory access channels can share a single circular buffer descriptor table string and can communicate with each other to avoid interference between threads. In other words, the operations of the input and output direct memory access channels proposed in this invention can achieve the effect of atomic operations.

[0061] The serial numbers in this specification and in the scope of the patent application, such as "first," "second," etc., are for illustrative purposes only and there is no sequential relationship between them.

[0062] The steps of the methods and algorithms disclosed in this specification can be directly applied to hardware and software modules or a combination of both by executing a processor. A software module (including execution instructions and related data) and other data can be stored in a data memory, such as random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, optical disc read-only memory (CD-ROM), DVDs, or any other computer-readable storage medium format in the art. A storage medium can be coupled to a machine device, for example, a computer / processor (referred to as processor in this specification for convenience), through which the processor can read information (such as program code) and write information to the storage medium. A storage medium can integrate a processor. An application-specific integrated circuit (ASIC) includes a processor and a storage medium. A user equipment includes an application-specific integrated circuit. In other words, the processor and storage medium are included in the user equipment in a manner that is not directly connected to the user equipment. Furthermore, in some embodiments, any product suitable for computer programs includes a readable storage medium, wherein the readable storage medium includes program code associated with one or more of the disclosed embodiments. In some embodiments, the product of the computer program may include packaging material.

[0063] The preceding paragraphs use multiple levels of description. Clearly, the teachings herein can be implemented in various ways, and any particular architecture or functionality disclosed in the examples is merely a representative case. Based on the teachings herein, those skilled in the art will understand that the various levels disclosed herein can be implemented independently or that two or more levels can be implemented in combination.

[0064] Although this disclosure has been presented above with reference to embodiments, it is not intended to limit this disclosure. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of the invention shall be determined by the claims.

Claims

1. A data transmission device for circular buffering, characterized in that, include: A circular buffer; A controller, coupled to the aforementioned recurrent buffer, has one input direct memory access channel and multiple output direct memory access channels. The controller controls the read and write operations of the circular buffer based on a circular buffer descriptor table string, via the input direct memory access channel and the multiple output direct memory access channels.

2. The data transmission device for circular buffering as described in claim 1, characterized in that, Each descriptor table in the above circular buffer descriptor table string includes source address information, destination address information, next descriptor table information, transfer type, and data information.

3. The data transmission device for circular buffering as described in claim 1, characterized in that, Once the aforementioned input direct memory access channel completes the write operation corresponding to a descriptor table in the aforementioned circular buffer descriptor table string, the aforementioned input direct memory access channel notifies all the aforementioned output direct memory access channels that are in an idle state that the write operation corresponding to the aforementioned descriptor table has been completed.

4. The data transmission device for circular buffering as described in claim 3, characterized in that, When the aforementioned input direct memory access channel completes the write operation corresponding to the aforementioned descriptor table, and the aforementioned circular buffer has no space left for writing, the aforementioned input direct memory access channel enters the aforementioned idle state.

5. The data transmission device for circular buffering as described in claim 1, characterized in that, Once one of the aforementioned output direct memory access channels completes a read operation corresponding to a descriptor table in the aforementioned circular buffer descriptor table string, the aforementioned output direct memory access channel notifies the aforementioned input direct memory access channel that the read operation corresponding to the aforementioned descriptor table has been completed.

6. The data transmission apparatus for circular buffering as described in claim 5, characterized in that, When the aforementioned output direct memory access channels complete the read operation corresponding to the aforementioned descriptor table, and the aforementioned circular buffer has no unread data, the aforementioned multiple output direct memory access channels enter an idle state.

7. A data transmission method for a circular buffer, characterized in that, A data transmission device is applicable, comprising: By means of a controller in the aforementioned data transmission device, an input direct memory access channel and multiple output direct memory access channels are selected from multiple direct memory access channels; and The controller controls the read and write operations of a circular buffer of the data transmission device based on a circular buffer descriptor table string, via the input direct memory access channel and the plurality of output direct memory access channels.

8. The data transmission method for circular buffers as described in claim 7, characterized in that, Including: When the aforementioned input direct memory access channel completes a write operation corresponding to a descriptor table, and the aforementioned circular buffer has no space left for writing, the aforementioned input direct memory access channel enters an idle state.

9. The data transmission method for circular buffers as described in claim 7, characterized in that, Including: Once one of the aforementioned output direct memory access channels completes a read operation corresponding to a descriptor table in the aforementioned circular buffer descriptor table string, the output direct memory access channel notifies the input direct memory access channel that the read operation corresponding to the aforementioned descriptor table has been completed.

10. The data transmission method for a circular buffer as described in claim 9, characterized in that, Including: When the aforementioned output direct memory access channels complete the read operation corresponding to the aforementioned descriptor table, and the aforementioned circular buffer has no unread data, the aforementioned multiple output direct memory access channels enter an idle state.

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