Automatic channel management peripheral direct memory access controller device

Abstract

The application provides an automatic channel management peripheral direct memory access controller device, which is suitable for at least one peripheral and comprises at least one channel, embedded static random access memory, a peripheral request preprocessing module and a channel control module. The embedded static random access memory is used to store a channel description table of each channel and record at least one transmission information. The peripheral request preprocessing module is used to process the request sent by the peripheral. The channel control module selects a suitable channel according to the information provided by the peripheral request preprocessing module and performs data transmission.

Description

Technical Field

[0001] This application relates to an automatic channel management peripheral direct memory access (PDMA) controller, and more specifically, to an automatic channel management PDMA controller that automatically configures PDMA channels without software intervention. Background Technology

[0002] In conventional direct memory access controllers (DMA controllers), when a peripheral device requests more data transfers using peripheral direct memory access (PDMA) than the number of PDMA channels are available, the software program will arbitrate the use of DMA channels, arranging the data to be transferred sequentially in the limited number of DMA channels.

[0003] Figure 1 and Figure 2 This is a diagram and flowchart of a previous DMA controller architecture. When a peripheral device sends a request signal, the channel arbiter selects an already enabled DMA channel for data transfer and arbitrates the use of the DMA channel after each burst transfer. If the DMA channel experiences arbitration loss, data transfer is interrupted, an updated transfer descriptor table is stored, and then another incomplete data transfer continues. However, in previous DMA controllers, a PDMA channel needed to be pre-configured by the program for data transfer, preventing other peripheral devices from using the same channel. When the peripheral device's PDMA usage demand exceeds the PDMA channel's capacity, program management is also required.

[0004] Therefore, there is an urgent need for an automatic channel management PDMA controller and an automatic channel management PDMA control method, which can automatically allocate channels according to the time that data transmission will occupy on each PDMA channel at present, so as to serve more peripherals with limited PDMA channels at the same time and improve the overall PDMA utilization efficiency. Summary of the Invention

[0005] One objective of this application is to provide an automatic channel management peripheral direct memory access controller, applicable to at least one peripheral, including at least one channel, an embedded static random access memory (SRAM), a peripheral request preprocessing module, and a channel control module. The embedded SRAM stores a channel description table for each of the channels and records at least one piece of transmission information. The peripheral request preprocessing module processes requests issued by the at least one peripheral. The channel control module selects a suitable channel from the at least one peripheral for data transmission based on the information provided by the peripheral request preprocessing module.

[0006] In one embodiment, for each peripheral device, a peripheral description table is stored in the embedded static random access memory, storing the description table of each peripheral device for each channel.

[0007] In one embodiment, the embedded static random access memory includes a recording buffer for recording the at least one piece of transmission information.

[0008] In one embodiment, the at least one transmission information includes a combination of the following items: peripheral identifier, amount of data transmitted, and transmission time.

[0009] In one embodiment, the peripheral request preprocessing module includes a timer. When a request is received from the peripheral device, the peripheral request preprocessing module starts the timer to record the transmission time.

[0010] In one embodiment, the timer uses hardware timing.

[0011] In one embodiment, the peripheral request preprocessing module obtains at least one peripheral description table from the at least one peripheral to confirm the transmission type, the amount of data transmitted, and the peripheral identifier.

[0012] In one embodiment, the peripheral request preprocessing module includes a transmission model that estimates a second transmission time based on previous transmission records, wherein the previous transmission records include a first transmission time and the amount of data transmitted.

[0013] In one embodiment, when all of the channels are available, the channel control module allocates the channel with the least transmission time to the newly received request based on the currently pending requests, and updates the peripheral description table to the channel description table of the channel.

[0014] Another objective of this application is to provide an automatic channel management peripheral direct memory access control method, applicable to at least one peripheral, comprising: configuring an automatic channel management peripheral direct memory access controller to enable one or more channels; when the automatic channel management peripheral direct memory access controller receives a request from the at least one peripheral, starting a timer to record the start time of transmission, simultaneously obtaining a peripheral description table to confirm the peripheral identifier and the amount of data to be transmitted, and estimating the required transmission time based on the previous transmission time and the amount of data to be transmitted recorded in the recording buffer; and selecting the shortest currently occupied request based on the number of incomplete requests. The transmission time channel is allocated to the next received request, and the peripheral description table is updated to the channel description table of the channel. Data transmission is performed, and while waiting for data transmission, the timer is paused and resumed when data transmission begins. When a channel completes data transmission, the validity of the next peripheral description table is checked, and the transmission time is updated to the recording buffer. If the next peripheral description table exists, the next peripheral description table of the available channel is obtained, and data transmission is performed again. If the next peripheral description table does not exist, the peripheral description table of the available channel is removed, the transmission model is updated, and data transmission is completed.

[0015] As can be seen from the above, the automatic channel management PDMA controller provided in this application can automatically allocate channels without software intervention based on the time that data transmission will occupy on each PDMA channel at the moment, so as to serve more peripherals with limited PDMA channels at the same time and improve the overall PDMA utilization efficiency. Attached Figure Description

[0016] The accompanying drawings are provided to enable those skilled in the art to further understand this application and are incorporated in and constitute a part of this application's specification. The drawings illustrate exemplary embodiments of this application and are used, together with the description of this application, to explain the principles of the invention. The following is a brief description of the various figures of this application:

[0017] Figure 1 This is a diagram of a previous DMA controller architecture.

[0018] Figure 2 This is a flowchart of a previous DMA controller.

[0019] Figure 3 This is a device architecture diagram of an automatic channel management PDMA controller according to an embodiment of this application.

[0020] Figure 4 This is a flowchart of an automatic channel management PDMA control method according to an embodiment of this application.

[0021] Symbol explanation:

[0022] 300 Automatic Channel Management PDMA Controller; 302 Embedded SRAM; 303 Channel Description Table; 304a, 304b, 304n Peripheral Description Tables; 305 Record Buffer; 310 Peripheral Request Preprocessing Module; 312 Timer; 314 Peripheral Description Table; 316 Transmission Model; 320 Channel Control Module; 322a Channel 0; 322b Channel 1; 322m Channel m; 350a Peripheral Description Table 0; 350n Peripheral Description Table n; 352a Peripheral 0; 352n Peripheral n; Steps S402~S420. Detailed Implementation

[0023] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without making any inventive contributions are within the scope of protection of this application.

[0024] In view of the above problems, embodiments of this application develop an automatic channel management PDMA controller that can automatically allocate channels without software intervention based on the time that data transmission will take up on each PDMA channel at the moment, so as to serve more peripherals with limited PDMA channels at the same time and improve the overall PDMA utilization efficiency.

[0025] Please see Figure 3This application provides an Automatic Channel Management (PDMA) controller 300, including an embedded static random access memory (SRAM) 302 for storing channel description tables for each PDMA channel and recording valid transmission messages. In an embodiment with m channels and n peripherals (where the number of channels m is less than the number of peripherals n), the channel description tables 303 for channels 0, 1, ..., m are stored in the embedded SRAM 302 respectively. For each peripheral, peripheral description tables 304a, 304b, ..., 304n are stored in the embedded SRAM 302, storing the description table for each channel for each peripheral. For example, peripheral description table 304a includes description table P(0) of peripheral 0 to channel 0, description table P(1) of peripheral 1 to channel 1, ..., description table P(m) of peripheral m to channel m; peripheral description table 304b includes description table P(m+1) of peripheral (m+1) to channel 0, description table P(m+2) of peripheral (m+2) to channel 1, ..., description table P(2m) of peripheral 2m to channel m, ...; peripheral description table 304n includes description table P(nm) of peripheral (nm) to channel 0, description table P(n-m+1) of peripheral (n-m+1) to channel 1, ..., description table P(n) of peripheral n to channel m. The embedded SRAM 302 also includes a record buffer 305 for recording valid transmission information, such as peripheral identifier (ID), amount of data transmitted, transmission time, etc.

[0026] The PDMA controller 300 also includes a peripheral request preprocessing module 310 for processing PDMA requests from peripherals. The peripheral request preprocessing module 310 includes a timer 312, a peripheral description table 314, and a transmission model 316. When a request signal is received from a peripheral, the peripheral request preprocessing module 310 starts the timer 312 to record the transmission time. This timer 312 uses hardware timing, so it does not require Baud rate information for signal transmission to record the transmission time. Simultaneously, the peripheral request preprocessing module 310 obtains the peripheral description table 314 from the peripheral (e.g., peripheral description table 0350a, ..., peripheral description table n350n for peripheral 0352a) to confirm the transmission type, transmission data volume, and peripheral identifier (ID). The peripheral request preprocessing module 310 also includes a transmission model 316, which can estimate the required transmission time based on previous valid transmission records, including transmission time and transmission data volume.

[0027] The automatic channel management PDMA controller 300 also includes a channel control module 320, which selects a suitable PDMA channel (e.g., channel 0 322a, channel 1 322b, ..., channel m 322m) for data transmission based on information provided by the peripheral request preprocessing module 310. When all channels are active, the channel control module 320 can also allocate the channel with the least transmission time to a newly received peripheral request based on the currently pending transmission requests, and update the peripheral description table to the channel description table of this channel.

[0028] This application also provides an automatic channel management PDMA control method, which can automatically allocate channels based on the time that data transmission will occupy on each PDMA channel at the moment, so as to serve more peripherals with limited PDMA channels at the same time and improve the overall PDMA utilization efficiency. Please refer to Figure 4 See also Figure 3 To gain a more detailed understanding of the operation flow of the automatic channel management PDMA control method provided in this application.

[0029] First, in step S402, the process begins.

[0030] Next, in step S404, the automatic channel management PDMA controller 300 is configured to enable one or more PDMA channels.

[0031] Subsequently, in step S406, the process splits into two paths depending on whether there is a peripheral device transmission request. If yes, the process proceeds to step S408. If no, the process returns to step S404.

[0032] In step S408, when the PDMA controller receives a peripheral transmission request signal from a peripheral device, the peripheral request preprocessing module 310 starts timer 312 to record the start time of transmission. At the same time, it obtains peripheral description table 314 to confirm peripheral identifier (ID) and transmission data volume, and estimates the next required transmission time based on the previous transmission time and transmission data volume recorded in the recording buffer 305.

[0033] Subsequently, in step S410, the channel control module 320 selects the channel with the shortest transmission time based on the number of uncompleted requests and allocates it to the next received peripheral request, while updating the peripheral description table to the channel description table of this channel.

[0034] Subsequently, in step S412, PDMA data transmission is performed. While waiting for PDMA data transmission, timer 312 is paused and resumed when data transmission begins.

[0035] Subsequently, in step S414, the process splits into two paths based on whether the available PDMA has completed the transmission. If yes, the process proceeds to step S416. If no, the process returns to step S412 to continue data transmission.

[0036] In step S416, when a channel completes data transmission, the validity of the next peripheral description table is checked, and the transmission time is updated to the record buffer 305. Depending on whether the next peripheral description table exists, the process proceeds to two paths. If yes, the process proceeds to step S418. If no, the process proceeds to step S420.

[0037] In step S418, the next peripheral description table of the available PDMA channel is obtained. Then, the process returns to step S412, and data transmission is performed again.

[0038] In step S420, the peripheral description table of the available PDMA channel is removed and the transmission model is updated. Data transmission is completed and the process ends.

[0039] As can be seen from the above, the automatic channel management PDMA controller and automatic channel management PDMA control method provided in this application can automatically allocate channels without software intervention based on the time that data transmission will occupy on each PDMA channel at the moment, so as to serve more peripherals with limited PDMA channels at the same time and improve the overall PDMA utilization efficiency.

[0040] Although embodiments of this application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An automatic channel management peripheral direct memory access controller, applicable to at least one peripheral, characterized in that, include: At least one channel; An embedded static random access memory is used to store a channel description table for each of the channels and to record at least one transmission information; A peripheral request preprocessing module is provided for processing a request issued by the at least one peripheral device. as well as A channel control module selects a suitable channel from the at least one channel for data transmission based on the information provided by the peripheral request preprocessing module.

2. The automatic channel management peripheral direct memory access controller as described in claim 1, characterized in that, For each of the peripherals, a peripheral description table is stored in the embedded static random access memory, which stores the description table of each peripheral for each of the channels.

3. The automatic channel management peripheral direct memory access controller as described in claim 1, characterized in that, The embedded static random access memory includes a recording buffer for recording the at least one piece of transmitted information.

4. The automatic channel management peripheral direct memory access controller as described in claim 3, characterized in that, The at least one transmitted information includes a combination of the following items: a peripheral identifier, a transmitted data amount, and a transmission time.

5. The automatic channel management peripheral direct memory access controller as described in claim 1, characterized in that, The peripheral request preprocessing module includes a timer. When the request is received from the peripheral device, the peripheral request preprocessing module starts the timer to record a transmission time.

6. The automatic channel management peripheral direct memory access controller as described in claim 5, characterized in that, The timer uses hardware timing.

7. The automatic channel management peripheral direct memory access controller as described in claim 1, characterized in that, The peripheral request preprocessing module obtains at least one peripheral description table from the at least one peripheral to identify a transmission type, a transmission data volume, and a peripheral identifier.

8. The automatic channel management peripheral direct memory access controller as described in claim 1, characterized in that, The peripheral request preprocessing module includes a transmission model that estimates a second transmission time based on a previous transmission record, wherein the previous transmission record includes a first transmission time and a transmission data volume.

9. The automatic channel management peripheral direct memory access controller as described in claim 1, characterized in that, When all of the aforementioned channels are available, the channel control module allocates the channel with the least transmission time to the newly received request based on the currently pending requests, and updates a peripheral description table to the channel description table of the channel.

10. An automatic channel management peripheral direct memory access control method, applicable to at least one peripheral, characterized in that, include: Configure an automatic channel management peripheral direct memory access controller to enable one or more channels; When the automatic channel management peripheral direct memory access controller receives a request from at least one peripheral, it starts a timer to record the start time of the transmission, obtains a peripheral description table to identify a peripheral identifier and a transmission data amount, and estimates the next required transmission time based on the previous transmission time and transmission data amount recorded in a recording buffer. Based on the number of incomplete requests, select the channel with the shortest current transmission time and allocate it to the next received request, while updating the peripheral description table to the channel description table of the channel. During data transmission, the timer is paused while waiting for data transmission to occur, and then resumed when data transmission begins. When a channel completes data transmission, check if the next peripheral description table is valid and update the transmission time to the record buffer; If the next peripheral description table exists, obtain the next peripheral description table of an available channel and perform data transmission again; as well as If the next peripheral description table does not exist, remove the peripheral description table of the available channel and update a transmission model, and the data transmission is completed.

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