A method for adaptively suppressing internal signal noise of an MCU chip

Abstract

The application discloses an MCU chip internal signal noise adaptive suppression method, relates to the chip noise suppression technical field, and is used for solving the problem that when the MCU chip is in DMA burst transmission and ADC sampling concurrency, the sampling clock jitter pollutes the ADC data and cannot be accurately suppressed due to bus switching, determining burst window active characteristics by reading the DMA channel burst state flag and the bus master device switching event number, evaluating the sampling point pollution prediction value after fusing the ADC sampling trigger edge phase offset and the ADC channel analog front-end configuration word to calculate the channel jitter sensitive intermediate characteristics, outputting the jitter compensation sampling sequence after the ADC sampling data is suppressed and processed according to the sampling point pollution prediction value distribution differential suppression weight, generating the sampling conflict feedback after the low suppression weight sampling point proportion is counted and the residual jitter indication is evaluated, performing the staggered scheduling on the DMA channel subsequent burst transmission start phase, and improving the cleanliness of the ADC sampling data under the chip concurrent resource environment.

Description

Technical Field

[0001] This invention relates to the field of chip noise suppression technology, and more specifically, to an adaptive method for suppressing internal signal noise in an MCU chip. Background Technology

[0002] In modern embedded systems, microcontroller units (MCUs) are widely used in real-time data acquisition scenarios such as industrial control, automotive electronics, and medical equipment. MCU chips typically integrate a direct memory access (DMA) controller and an analog-to-digital converter (ADC) to achieve efficient data transfer and analog signal sampling. In practical applications, the DMA controller handles batch data transfers in the background, freeing up CPU computing power, while the ADC is responsible for periodically sampling and quantizing external analog signals. When DMA burst transfers and ADC sampling occur simultaneously, master switching and transient loads on the system bus introduce instantaneous current fluctuations in the on-chip digital power supply network and clock distribution tree. These fluctuations affect the sampling clock stability of the ADC through power supply noise and substrate coupling. As the integration density and operating frequency of MCU chips increase, the sampling clock jitter caused by on-chip resource concurrency has an increasingly significant impact on ADC data quality, becoming a key factor restricting the performance of high-precision data acquisition systems.

[0003] The existing technology has the following shortcomings: Currently, existing technologies use fixed threshold filtering or static weighted averaging to suppress noise in ADC sampling data. These technologies lack real-time sensing capabilities for the activity level of DMA burst transfers and the sensitivity of ADC channel jitter, and cannot accurately identify the degree of contamination at different sampling intervals. This results in high-contamination sampling points and low-contamination sampling points being assigned the same suppression weight, leading to over-smoothing of clean sampling points and insufficient suppression of residual jitter in contamination sampling points. This results in a decrease in the signal-to-noise ratio and loss of effective resolution of ADC sampling data. Therefore, an adaptive signal noise suppression method for MCU chips is proposed.

[0004] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] To overcome the aforementioned deficiencies of the prior art, embodiments of the present invention provide an adaptive signal noise suppression method for MCU chips. This method evaluates the activity characteristics of the burst window by fusing DMA burst states and bus switching events, calculates jitter sensitivity characteristics by combining the ADC sampling trigger phase offset and channel analog front-end configuration, and generates a sampling point contamination prediction value. Based on the contamination prediction value, differentiated suppression weights are allocated to implement sliding weighted average suppression on the ADC sampling data. The proportion of sampling points with low suppression weights is statistically analyzed, and the residual jitter indication is evaluated to generate a sampling conflict feedback value. This feedback value is used to perform peak-shifting scheduling on the subsequent burst transmission start phase of the DMA channel, thereby solving the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: an adaptive signal noise suppression method for an MCU chip, comprising the following steps: Step S1: Read the DMA channel burst status flag, monitor the number of bus master device switching events, and determine the burst window activity characteristics by combining the DMA channel burst status flag and the number of bus master device switching events. Step S2: Detect the phase offset along the ADC sampling trigger edge, obtain the ADC channel analog front-end configuration word, fuse the ADC sampling trigger edge phase offset and the ADC channel analog front-end configuration word to calculate the channel jitter sensitive intermediate feature, and combine the burst window activity feature to evaluate the sampling point contamination prediction value. Step S3: Retrieve ADC sampling data, allocate differential suppression weights based on the pollution prediction values ​​of the sampling points, and output the jitter compensation sampling sequence after suppressing the ADC sampling data using the differential suppression weights. Step S4: Based on the proportion of low-suppression weight sampling points within the differential suppression weight statistical sliding window, evaluate the residual jitter indication within the same sliding window according to the jitter compensation sampling sequence, generate the sampling conflict feedback quantity in combination with the proportion of low-suppression weight sampling points, and perform peak-shifting scheduling for the subsequent burst transmission start phase of the DMA channel through the sampling conflict feedback quantity.

[0007] In a preferred embodiment, in step S1, an active statistics window is set, and the DMA channel burst status flag is read in the active statistics window. The DMA channel burst status flag is a digital status bit that indicates whether the channel is in a bus burst transmission state. When a burst starts, the DMA channel burst status flag is set to 1, and when the burst ends or the bus is relinquished, the DMA channel burst status flag is cleared to 0. The cumulative count value of the system bus matrix arbitration event counter is read twice at the beginning and end of the active statistics window, and the difference between the two read values ​​is used to obtain the number of bus master device switching events.

[0008] In a preferred embodiment, in step S1, the percentage of DMA in burst state within the active statistics window is calculated by the DMA channel burst state flag, and the average switching intensity per unit cycle within the active statistics window is calculated by the bus master device switching event count. The characteristics of burst window activity are calculated by combining the percentage of cycles in burst mode of the combined DMA and the average switching intensity per cycle.

[0009] In a preferred embodiment, in step S2, the phase counter is reset by the nominal sampling clock edge and latched by the actual trigger edge reaching the ADC sample-and-hold network. The latched value is converted by the counter time base to obtain the ADC sampling trigger edge phase offset of the current sampling cycle. The ADC channel analog front-end configuration word is a combination of the input impedance range field and the sample-and-hold time setting field; The Max-Min normalization method is used to normalize the ADC sampling trigger edge phase offset, input impedance level field and sampling hold time setting field respectively. The three normalized terms are then calculated by power-weighted product to obtain the channel jitter sensitive intermediate feature.

[0010] In a preferred embodiment, in step S2, the channel jitter-sensitive intermediate feature is combined with the burst window activity feature. Assessment of pollution prediction values ​​at sampling points ,in, for The channel jitter-sensitive intermediate feature after Max-Min normalization, where λ is a preset tradeoff coefficient.

[0011] In a preferred embodiment, in step S3, the ADC sampling data of the current sampling cycle is retrieved, and the ADC sampling data is the first quantization output of the ADC on the input signal under test. The sampling point contamination prediction values ​​are mapped to differential suppression weights using a monotonically decreasing mapping function.

[0012] In a preferred embodiment, in step S3, the jitter-compensated sampling sequence is output after the ADC sampling data is suppressed using differential suppression weights. ,in, The output of the jitter-compensated sampling sequence at the i-th sampling beat. For the ADC sampling data of the (i+j)th sampling cycle, The differential suppression weights for the corresponding beats are summed in the interval j from -M to M, where M is the weighted neighborhood radius. The weighted neighborhood radius is preset based on the jitter tolerance, ADC sampling rate, and the bandwidth of the signal under test.

[0013] In a preferred embodiment, in step S4, a sliding window is set to include sampling beats with differential suppression weights less than the low weight determination threshold within the sliding window into the low suppression weight sampling point set. The proportion of low-suppression weighted sampling points is the ratio of the number of elements in the low-suppression weighted sampling point set to the length of the sliding window; The jitter compensation sampling sequence is first-order differencing to obtain a difference sequence. The median of the difference sequence is calculated, and the absolute deviation sequence of the difference sequence relative to the median is calculated. The residual jitter indicator is calculated based on the median of the absolute deviation sequence. The residual jitter indicator is combined with the proportion of low-suppression weighted sampling points to calculate the sampling conflict feedback.

[0014] In a preferred embodiment, in step S4, when the sampling conflict feedback amount is greater than the conflict trigger threshold, it is determined that there is a remaining conflict in this round of suppression. The subsequent burst transmission start phase of the DMA channel is offset relative to the execution phase of the ADC sampling trigger edge according to the sampling conflict feedback amount. The offset amount is obtained by the sampling conflict feedback amount through saturated linear mapping. Conversely, the current burst scheduling of the DMA channel is kept unchanged without phase adjustment.

[0015] The technical effects and advantages of this invention are as follows: This invention determines the burst window activity characteristics by reading the DMA channel burst status flag, monitoring the number of bus master device switching events, and combining the DMA channel burst status flag and the number of bus master device switching events. It also detects the ADC sampling trigger edge phase offset, obtains the ADC channel analog front-end configuration word, and calculates the channel jitter-sensitive intermediate characteristics by fusing the ADC sampling trigger edge phase offset and the ADC channel analog front-end configuration word. Finally, it evaluates the sampling point contamination prediction value based on the burst window activity characteristics, retrieves ADC sampling data, assigns differentiated suppression weights based on the sampling point contamination prediction value, and uses these differentiated suppression weights to suppress the ADC sampling data before outputting a jitter-compensated sampling sequence. The proportion of low-suppression weighted sampling points within the sliding window is calculated. Based on the jitter compensation sampling sequence, the residual jitter indication is evaluated within the same sliding window. The sampling conflict feedback is generated by combining the proportion of low-suppression weighted sampling points. The sampling conflict feedback is used to perform staggered scheduling of the start phase of subsequent burst transmissions of the DMA channel. This allows the MCU chip to sense the on-chip bus activity and channel jitter sensitivity through digital domain event streams when DMA burst transmissions and ADC sampling occur concurrently. Differentiated suppression weights matching the degree of contamination are assigned to each sampling cycle. The adaptive suppression of sampling noise is completed at the digital post-processing layer. A complete adaptive suppression link from contamination prediction to suppression processing to scheduling closed loop is formed without increasing the hardware cost on the analog side. Attached Figure Description

[0016] Figure 1This is a flowchart illustrating the implementation of an adaptive signal noise suppression method for an MCU chip according to the present invention.

[0017] Figure 2 This is a schematic diagram illustrating the steps of an adaptive noise suppression method for internal signals of an MCU chip according to the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] This invention determines the active characteristics of the burst window by reading the burst status flag of the DMA channel and the number of bus master switching events, detects the phase offset of the ADC sampling trigger edge and calculates the channel jitter-sensitive intermediate characteristics by fusing the ADC channel analog front-end configuration word, evaluates the sampling point contamination prediction value, assigns differentiated suppression weights to suppress the ADC sampling data based on the sampling point contamination prediction value, calculates the proportion of low suppression weight sampling points based on the differentiated suppression weights, evaluates the residual jitter indication based on the jitter compensation sampling sequence, generates the sampling conflict feedback quantity, and then performs staggered scheduling for the subsequent burst transmission of the DMA channel.

[0020] Example 1: Please refer to Figures 1 to 2 An adaptive noise suppression method for internal signals of an MCU chip, the specific operation process is as follows: Step S1: Read the DMA channel burst status flag, monitor the number of bus master device switching events, and determine the burst window activity characteristics by combining the DMA channel burst status flag and the number of bus master device switching events. Step S2: Detect the phase offset along the ADC sampling trigger edge, obtain the ADC channel analog front-end configuration word, fuse the ADC sampling trigger edge phase offset and the ADC channel analog front-end configuration word to calculate the channel jitter sensitive intermediate feature, and combine the burst window activity feature to evaluate the sampling point contamination prediction value. Step S3: Retrieve ADC sampling data, allocate differential suppression weights based on the pollution prediction values ​​of the sampling points, and output the jitter compensation sampling sequence after suppressing the ADC sampling data using the differential suppression weights. Step S4: Based on the proportion of low-suppression weight sampling points within the sliding window according to the differential suppression weight statistics, evaluate the residual jitter indication within the same sliding window according to the jitter compensation sampling sequence, generate the sampling conflict feedback quantity in combination with the proportion of low-suppression weight sampling points, and perform peak-shifting scheduling for the subsequent burst transmission start phase of the DMA channel through the sampling conflict feedback quantity.

[0021] The specific implementation is as follows: In step S1, each ADC sampling cycle of the MCU chip is used as the basic acquisition cycle, and an active statistical window consisting of several consecutive sampling cycles is set. As the acquisition time window for DMA channel burst status flags and bus master switching event counts, in this example, For example, the length is set to 16 sampling beats.

[0022] exist Internally, the DMA channel burst status flag is read by the DMA status sampling interface of the MCU's on-chip digital event monitoring unit. , This is a digital status bit in the DMA controller channel status register that indicates whether the channel is in a bus burst transfer state during burst start. When set to 1 by hardware, or when a sudden termination or bus relinquishment occurs. Cleared to 0, read once per sampling cycle and merged into a length of DMA channel burst state flag dataset.

[0023] Synchronously, the system bus matrix arbitration event counters are respectively in Read the cumulative count value twice, once at the start point and once at the end point. and The difference between the two readings is obtained. Bus master switching event count : ,in, for The cumulative count value of the arbitration event counter at the starting moment. for The cumulative count value of the arbitration event counter at the endpoint. for The cumulative number of bus master switchovers.

[0024] Integrated DMA channel burst status flags Number of events switching with bus master Determine the active characteristics of the sudden window The specific calculation method is as follows: First, from Dataset estimation The percentage of clock cycles in burst mode within the internal DMA Then by Estimate Average switching intensity per unit beat within Finally by and Mapped to a bounded interval by the Sigmoid function, we obtain : , , ,in, for The burst status flag of the DMA channel read in the kth sampling cycle. for The total number of sampling beats within, for The percentage of clock cycles in burst mode within the internal DMA, with a value range of [0,1]. for Average switching intensity per unit beat within; α and β are respectively and The combination coefficients are γ, which is the bias term.

[0025] Follow Monotonically increasing and following Monotonically increasing, that is, when The higher the percentage of clock cycles in a burst state within the internal DMA and the more frequent the average switching per clock cycle, the better. The closer it is to 1, the more active the DMA burst window is; conversely, when it is less active, the more active the DMA burst window is. When DMA bursts or sparse bus switching occur almost never. The closer it is to 0, the less likely it is to be an active DMA burst window.

[0026] It needs to be explained that in the above steps and The combination coefficients α, β, and bias term γ are set by those skilled in the art according to the DMA and bus activity intensity of the specific MCU chip. For example, α can be set to 3.0, β to 2.0, and γ to 1.5, etc., which will not be elaborated here.

[0027] In step S2, the sampling cycle at the start of each ADC conversion is used as the basic acquisition cycle. Internally, the phase offset of the ADC sampling trigger edge is detected for each sampling cycle, and the ADC channel analog front-end configuration word is read.

[0028] ADC sampling trigger edge phase offset The measurement was obtained by an on-chip high-resolution phase counter, specifically as follows: The phase counter is reset by the nominal sampling clock edge and latched by the actual trigger edge arriving at the ADC sample-and-hold network. The latched value is converted to the counter time base to obtain the current sampling cycle Δφ.

[0029] ADC channel analog front-end configuration word Obtained by parsing the ADC channel configuration register. From the input impedance range field With the sample hold time setting field Combining the two, the two are They are stored side-by-side in bit-field encoding format.

[0030] Fusion ADC sampling trigger along phase offset With ADC channel analog front-end configuration word Calculate channel jitter-sensitive intermediate features First by Parse and The Max-Min normalization method is used to normalize Δφ, , Normalize to the [0,1] interval to eliminate dimensional differences: ,in, and The parameters are determined by the measured extreme values ​​of each parameter in the preliminary experiment; then, they are formed by the power-weighted product of the three normalized terms. : ,in, for The result after normalization for The result after normalization for The normalized result, where a, b, and c are power exponent coefficients, respectively characterize the three terms on the power-law relationship. The intensity of marginal contribution, To prevent small positive numbers from approaching zero; Follow Monotonically increasing, following Monotonically increasing, following Monotonically decreasing, meaning that the larger the phase offset of the sampling trigger edge, the higher the input impedance level, and the shorter the sampling hold time setting, the more sensitive the channel is to trigger edge jitter. The larger.

[0031] It should be noted that the settings for the power coefficient and the small positive number protection term mentioned above are not unique and can be adjusted according to the actual situation. In this example, a is set to 1.0, b to 0.6, and c to 0.8. The value is set to 0.001, and will not be analyzed further here.

[0032] Channel jitter-sensitive intermediate features combined with burst window activity features Assessment of pollution prediction values ​​at sampling points , Continuous quantities generated for each sampling cycle: ,in, for The channel jitter-sensitive intermediate feature after Max-Min normalization, λ is and The preset trade-off coefficient between them, λ, takes values ​​in the range [0,1]. In this example, λ is set to 0.55.

[0033] Follow Monotonically increasing and following Monotonically increasing, meaning that the current situation is both within an active DMA burst window and has high channel jitter sensitivity. The closer the value is to 1, the higher the likelihood that the sampling cycle is contaminated by sampling clock jitter; conversely, when both are low, The closer it is to 0, the more likely that the sampling cycle is in a clean sampling state; By outputting continuous values ​​instead of making hard decisions, we leave room for adjustment in the continuous allocation of differential suppression weights in subsequent steps.

[0034] In step S3, the ADC sampling data of the current sampling cycle is retrieved from the ADC conversion result register. , This is the first quantization output of the ADC for the measured input signal, based on the contamination prediction value of the sampling points. Assign a differential suppression weight w to this sampling beat, and use a monotonically decreasing mapping function to filter samples within the interval [0,1]. Mapped to w within the interval, The larger the value, the closer w is to , The smaller the value, the closer w is to 1. This is the minimum suppression weight lower bound, used to avoid completely discarding sampling ticks.

[0035] Construct using an exponentially monotonically decreasing mapping : ,in, The coefficient of exponential decay is κ; the larger κ is, the greater the decay. right The steeper the response, Follow Monotonically decreasing.

[0036] Using differential suppression weights ADC sampling data After suppression processing, the jitter-compensated sampling sequence is output. Suppression is achieved using a sliding weighted average, where each sampled beat within a weighted neighborhood centered on the current beat is weighted according to its own... Weighted normalized average as weights: ,in, The output of the jitter-compensated sampling sequence at the i-th sampling beat. For the ADC sampling data of the (i+j)th sampling cycle, The differential suppression weights for the corresponding beats are summed in the interval j from -M to M, where M is the weighted neighborhood radius. It should be explained that sampling beats judged as highly contaminated contribute a small weighted amount to the numerator and a small weighted share in the denominator, thus their effect on shifting the neighborhood output is correspondingly weakened; sampling beats judged as low-contaminated participate with a weight close to 1, and are almost not suppressed. The exponential decay coefficient k and the lower limit of the minimum suppression weight mentioned above... The auxiliary hyperparameter M is set by those skilled in the art based on the specific application, considering jitter tolerance, ADC sampling rate, and the bandwidth of the signal under test. For example, κ can be set to 3.5. Set it to 0.10 and set M to 4; this will not be analyzed here.

[0037] In step S4, the sliding window is taken. Statistical analysis was performed on the differential suppression weights and jitter compensation sampling sequences. To cover a fixed-length time window of several consecutive sampling beats; Based on the statistical analysis of differential inhibition weights w Low-suppression weighted sampling point ratio ,Will The inner w is less than the low-weight judgment threshold The sampling beats are included in the set of low-suppression weighted sampling points, while other beats are not included. The proportion of low-suppression weighted sampling points is... The number of elements in the set and Ratio of lengths: ,in, For the differential suppression weight of the i-th sampling beat, This is the threshold for low-weight judgment.

[0038] Data was collected during the static calibration phase without DMA burst disturbances. The length of the w distribution is taken as the lower quintile. The candidate values ​​are selected, and after multiple rounds of calibration, the median of the candidate value sequence is taken as the median. The final value; for example, after pre-test calibration, Set it to 0.30.

[0039] Based on jitter compensation sampling sequence In the same sliding window Internal assessment of residual jitter indication The time-domain characterization of residual jitter is as follows The dispersion of the difference between adjacent beats is estimated using the median absolute deviation (MAD) as a robust measure of the dispersion of the difference sequence. The specific steps are as follows: Step 1, for exist The difference sequence is obtained by performing a first-order difference within the inner part. : ; Step 2, calculate the median of the difference sequence. ; Step 3: Calculate the absolute deviation sequence of the difference sequence relative to its median. ; Step 4: Take the median of the absolute deviation sequence and multiply it by the consistency constant 1.4826 to obtain the MAD estimate. ,in, for The first-order difference value in the i-th beat is the median operator, and 1.4826 is the consistency constant between MAD and standard deviation under the Gaussian assumption; Combined with the proportion of low-suppression weighted sampling points Generate sampling conflict feedback quantity : ,in, for Residual jitter indicator after Max-Min normalization, normalization upper and lower limits and From the static calibration stage of the pre-test The extreme values ​​of the distribution are determined; θ is and The trade-off coefficient between them, θ takes values ​​in the range [0,1].

[0040] Follow Monotonically increasing and following Monotonically increasing, that is The more sampling beats that are identified as highly contaminated, the stronger the residual jitter remains even after suppression. The larger the value, the more likely it is that the current suppression is no longer able to independently bear the responsibility of jitter compensation, and it is necessary to send the conflict signal back to the DMA scheduling side.

[0041] It should be added that the tradeoff coefficient θ is set by the application side according to its sensitivity preference to event frequency and residual magnitude. In this example, θ is set to 0.60.

[0042] By sampling conflict feedback quantity To implement staggered scheduling for the initiation phase of subsequent burst transfers on the DMA channel, staggered scheduling rules are established: Rule 1, when Greater than the conflict trigger threshold At that time, it was determined that there were residual conflicts in this round of suppression, according to The subsequent burst transfer start phase of the DMA channel is offset relative to the execution phase of the ADC sampling trigger edge, and the offset Δψ is determined by... The result obtained through saturated linear mapping is: ,in, ρ is the maximum offset of a single wheel, and ρ is the mapping slope; Rule 2, when Not greater than the conflict trigger threshold If the current suppression is deemed sufficient to independently suppress jitter, the DMA channel will maintain its current burst scheduling without phase adjustment.

[0043] Record each round of operation in the history of different loads. Final value, taken from history The median of the final value sequence as The candidates were then verified on-site and slightly adjusted to obtain the final version. The final value, for example, after historical statistics Set it to 0.45.

[0044] Using the median method based on historical data can avoid the influence of individual extreme rounds. Raising the price too high can cause the off-peak scheduling to remain dormant for extended periods, and can prevent individual extremely low-frequency shifts from causing problems. Excessive pressure causes frequent disturbances on the scheduling side. After completing this round of staggered scheduling, the next sampling cycle begins, and the DMA channel burst status flag is reread. And enter a new Statistically, a closed loop of adaptive suppression of sampling jitter driven by DMA events is formed.

[0045] It should be noted that the original parameters used in this method—DMA channel burst status flag, bus master switching event count, ADC sampling trigger edge phase offset, ADC channel analog front-end configuration word, and ADC sampling data—are all directly exposed by the DMA controller channel status register, bus matrix arbitration event counter, on-chip high-resolution phase counter, ADC channel configuration register, and ADC conversion result register within the MCU chip. The method does not rely on any analog front-end modifications and does not add any analog-side hardware costs. It only utilizes the MCU's existing event flow in the digital domain to achieve adaptive suppression of sampling clock jitter and closed-loop scheduling. The maximum offset per round in the above steps... And the mapping slope ρ is set by those skilled in the art, for example, by... Set to 8 bus clock cycles, ρ is set to 10 bus clock cycles per unit. The details are omitted here.

[0046] Finally, it should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0047] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0048] In this document, the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that terms such as “comprising / including” or “having” specify the presence of the stated features, integrals, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integrals, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0049] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referred to each other.

[0050] The above description of the disclosed embodiments will enable those skilled in the art to make or use various modifications to these embodiments. It will be readily apparent to those skilled in the art that the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An adaptive noise suppression method for internal signals of an MCU chip, characterized in that: Includes the following steps: Step S1: Read the DMA channel burst status flag, monitor the number of bus master device switching events, and determine the burst window activity characteristics by combining the DMA channel burst status flag and the number of bus master device switching events. Step S2: Detect the phase offset along the ADC sampling trigger edge, obtain the ADC channel analog front-end configuration word, fuse the ADC sampling trigger edge phase offset and the ADC channel analog front-end configuration word to calculate the channel jitter sensitive intermediate feature, and combine the burst window activity feature to evaluate the sampling point contamination prediction value. Step S3: Retrieve ADC sampling data, allocate differential suppression weights based on the pollution prediction values ​​of the sampling points, and output the jitter compensation sampling sequence after suppressing the ADC sampling data using the differential suppression weights. Step S4: Based on the proportion of low-suppression weight sampling points within the differential suppression weight statistical sliding window, evaluate the residual jitter indication within the same sliding window according to the jitter compensation sampling sequence, generate the sampling conflict feedback quantity in combination with the proportion of low-suppression weight sampling points, and perform peak-shifting scheduling for the subsequent burst transmission start phase of the DMA channel through the sampling conflict feedback quantity.

2. The adaptive signal noise suppression method for an MCU chip according to claim 1, characterized in that: In step S1, an active statistics window is set, and the DMA channel burst status flag is read in the active statistics window. The DMA channel burst status flag is a digital status bit that indicates whether the channel is in a bus burst transmission state. When a burst starts, the DMA channel burst status flag is set to 1, and when the burst ends or the bus is yielded, the DMA channel burst status flag is cleared to 0. The cumulative count value of the system bus matrix arbitration event counter is read twice at the beginning and end of the active statistics window, and the difference between the two read values ​​is used to obtain the number of bus master device switching events.

3. The adaptive noise suppression method for internal signals of an MCU chip according to claim 2, characterized in that: In step S1, the percentage of DMA in burst state within the active statistics window is calculated using the DMA channel burst state flag, and the average switching intensity per unit cycle within the active statistics window is calculated using the bus master device switching event count. The characteristics of burst window activity are calculated by combining the percentage of cycles in burst mode of the combined DMA and the average switching intensity per cycle.

4. The adaptive signal noise suppression method for an MCU chip according to claim 1, characterized in that: In step S2, the phase counter is reset by the nominal sampling clock edge and latched by the actual trigger edge arriving at the ADC sample-and-hold network. The latched value is converted by the counter time base to obtain the ADC sampling trigger edge phase offset of the current sampling cycle. The ADC channel analog front-end configuration word is a combination of the input impedance range field and the sample-and-hold time setting field; The Max-Min normalization method is used to normalize the ADC sampling trigger edge phase offset, input impedance level field and sampling hold time setting field respectively. The three normalized terms are then calculated by power-weighted product to obtain the channel jitter sensitive intermediate feature.

5. The adaptive signal noise suppression method for an MCU chip according to claim 4, characterized in that: In step S2, the channel jitter-sensitive intermediate features are combined with the burst window activity features. Assessment of pollution prediction values ​​at sampling points ,in, for The channel jitter-sensitive intermediate feature after Max-Min normalization, where λ is a preset tradeoff coefficient.

6. The adaptive signal noise suppression method for an MCU chip according to claim 1, characterized in that: In step S3, the ADC sampling data of the current sampling cycle is retrieved. The ADC sampling data is the first quantization output of the ADC on the input signal under test. The sampling point contamination prediction values ​​are mapped to differential suppression weights using a monotonically decreasing mapping function.

7. The adaptive signal noise suppression method for an MCU chip according to claim 6, characterized in that: In step S3, the jitter-compensated sampling sequence is output after the ADC sampling data is suppressed using differential suppression weights. ,in, The output of the jitter-compensated sampling sequence at the i-th sampling beat. For the ADC sampling data of the (i+j)th sampling cycle, The differential suppression weights for the corresponding beats are summed in the interval j from -M to M, where M is the weighted neighborhood radius. The weighted neighborhood radius is preset based on the jitter tolerance, ADC sampling rate, and the bandwidth of the signal under test.

8. The adaptive signal noise suppression method for an MCU chip according to claim 1, characterized in that: In step S4, a sliding window is set, and sampling beats with differential suppression weights less than the low weight judgment threshold within the sliding window are included in the low suppression weight sampling point set. The proportion of low-suppression weighted sampling points is the ratio of the number of elements in the low-suppression weighted sampling point set to the length of the sliding window; The jitter compensation sampling sequence is first-order differencing to obtain a difference sequence. The median of the difference sequence is calculated, and the absolute deviation sequence of the difference sequence relative to the median is calculated. The residual jitter indicator is calculated based on the median of the absolute deviation sequence. The residual jitter indicator is combined with the proportion of low-suppression weighted sampling points to calculate the sampling conflict feedback.

9. The adaptive signal noise suppression method for an MCU chip according to claim 8, characterized in that: In step S4, when the sampling conflict feedback amount is greater than the conflict trigger threshold, it is determined that there is a remaining conflict in this round of suppression. The subsequent burst transmission start phase of the DMA channel is offset relative to the ADC sampling trigger edge execution phase according to the sampling conflict feedback amount. The offset amount is obtained by the sampling conflict feedback amount through saturated linear mapping. Conversely, the current burst scheduling of the DMA channel is kept unchanged without phase adjustment.

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