Method, apparatus and device for high-speed peripheral component interconnect device-to-device data transmission

Abstract

The application discloses a high-speed peripheral component interconnect device data transmission method, device and equipment, relates to the processor microarchitecture design technical field, and includes: obtaining a transaction layer package from a high-speed peripheral component interconnect device; analyzing the header field of the transaction layer package to obtain a transaction type and a target address; when the transaction type is a memory read-write transaction, determining a traffic category according to the target address; when the traffic category is point-to-point traffic, forwarding the transaction layer package to a target high-speed peripheral component interconnect device corresponding to the target address according to a preset point-to-point pass-through switching matrix. Since the point-to-point traffic is guided to the preset point-to-point pass-through switching matrix for forwarding, the point-to-point traffic no longer passes through the main interconnection bus and does not need to experience arbitration and routing on the bus, thereby avoiding mutual interference caused by the point-to-point traffic and core compound chip access high-speed peripheral component interconnect device or double data rate memory traffic sharing the main interconnection bus.

Description

Technical Field

[0001] This application relates to the field of processor microarchitecture design technology, and in particular to a method, apparatus and device for data transmission between high-speed peripheral component interconnect devices. Background Technology

[0002] With the increasing prevalence of heterogeneous integrated architectures consisting of core complex dies (CCDs) and input / output dies (IODs) in high-performance processors, the types and number of devices mounted on the root complex ports of high-speed peripheral component interconnect (PCIe) RCs continue to increase, leading to a growing demand for peer-to-peer (P2P) data exchange between devices.

[0003] In the existing internal architecture of input / output chips, all high-speed peripheral component interconnect root complexes are connected to the point of coherence (PoC) and the double data rate memory controller (DDR controller) via a main interconnect bus. Point-to-point data transmission must sequentially pass through the root complex, the main interconnect bus, and the target root complex to reach its destination. This main interconnect bus simultaneously carries traffic from the core composite chip accessing high-speed peripheral component interconnect devices, traffic from the core composite chip reading and writing double data rate memory, and point-to-point traffic between devices. Point-to-point data on the main interconnect bus needs to undergo arbitration, routing, and buffering processes.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a method, apparatus, and device for data transmission between high-speed peripheral component interconnection devices, aiming to solve the technical problem of how to avoid mutual interference between different data during transmission.

[0006] To achieve the above objectives, this application proposes a method for data transmission between high-speed peripheral component interconnect devices, the method comprising: Obtain transaction layer packets from high-speed peripheral component interconnect devices; parse the header fields of the transaction layer packets to obtain the transaction type and target address; when the transaction type is a memory read / write transaction, determine the traffic category based on the target address; when the traffic category is point-to-point traffic, forward the transaction layer packets to the target high-speed peripheral component interconnect device corresponding to the target address according to a preset point-to-point pass-through switching matrix.

[0007] In one embodiment, when the transaction type is a memory read / write transaction, determining the traffic category based on the target address includes: When the transaction type is a memory read / write transaction, obtain the first spatial address range of the base address register of multiple high-speed peripheral component interconnection devices and the second spatial address range of double data rate memory; When the target address is within the range of the first spatial address, the traffic type is determined to be point-to-point traffic; When the target address is within the range of the second spatial address, the traffic category is determined to be either central processing unit traffic or double data rate memory traffic.

[0008] In one embodiment, when the traffic type is point-to-point traffic, forwarding the transaction layer packet to the target high-speed peripheral component interconnect device corresponding to the target address according to a preset point-to-point pass-through switching matrix includes: Based on the target address, the target high-speed peripheral component interconnect device is determined; When the traffic type is point-to-point traffic, the transmission path and target port load are determined from the preset point-to-point pass-through switching matrix based on the port address of the high-speed peripheral component interconnection device and the port address of the target high-speed peripheral component interconnection device. The transaction layer packet is forwarded to the target high-speed peripheral component interconnect device according to the transmission path and the target port load.

[0009] In one embodiment, forwarding the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path and the target port load includes: When the target port load is greater than or equal to a preset port load threshold, the transaction layer packet is cached in the buffer of the preset point-to-point pass-through switching matrix according to the transmission path; After caching is complete, the transaction layer packet is forwarded to the target high-speed peripheral component interconnect device according to the transmission path.

[0010] In one embodiment, forwarding the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path and the target port load includes: When the target port load is less than a preset port load threshold, the transaction layer packet is forwarded to the target high-speed peripheral component interconnect device according to the transmission path.

[0011] In one embodiment, before forwarding the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path and the target port load, the method further includes: Obtain the port bandwidth weights of each high-speed peripheral component interconnection device and the total available bandwidth of the preset point-to-point connection; Adjust the corresponding port bandwidth weights based on the port load of each high-speed peripheral component interconnect device. The available port bandwidth of each of the high-speed peripheral component interconnect devices is determined based on the total available bandwidth and the adjusted port bandwidth weights. Based on the available bandwidth of the port of the high-speed peripheral component interconnect device, perform the step of forwarding the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path and the target port load.

[0012] In one embodiment, after forwarding the transaction layer packet to the target high-speed peripheral component interconnect device corresponding to the target address according to a preset point-to-point pass-through switching matrix when the traffic type is point-to-point traffic, the method further includes: Obtain the current traffic load of the main interconnect bus and the preset point-to-point pass-through switching matrix, wherein the main interconnect bus is the transmission path corresponding to the central processing unit traffic, double data rate memory traffic, control traffic and configuration traffic; Based on the current traffic load, determine the amount of idle bandwidth of the preset point-to-point direct switching matrix; When the amount of idle bandwidth is greater than a preset bandwidth threshold, the amount of idle bandwidth is allocated to the main interconnect bus; When the current traffic load exceeds a preset matrix load threshold, the idle bandwidth allocated to the main interconnect bus is reclaimed, and the idle bandwidth is restored to the dedicated bandwidth of the preset point-to-point pass-through switching matrix.

[0013] Furthermore, to achieve the above objectives, this application also proposes a high-speed peripheral component interconnect device (PCI) data transmission apparatus, which includes: The input module is used to obtain transaction layer packets from high-speed peripheral component interconnect devices; The parsing module is used to parse the header fields of the transaction layer packet to obtain the transaction type and target address; The determination module is used to determine the traffic category based on the target address when the transaction type is a memory read / write transaction; The forwarding module is used to forward the transaction layer packet to the target high-speed peripheral component interconnect device corresponding to the target address according to a preset point-to-point pass-through switching matrix when the traffic type is point-to-point traffic.

[0014] In addition, to achieve the above objectives, this application also proposes a high-speed peripheral component interconnect device for data transmission, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the high-speed peripheral component interconnect device for data transmission method as described above.

[0015] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the high-speed peripheral component interconnection device data transmission method described above.

[0016] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the high-speed peripheral component interconnection device data transmission method described above.

[0017] One or more technical solutions proposed in this application have at least the following technical effects: The system acquires transaction layer packets from high-speed peripheral component interconnect devices; parses the header fields of the transaction layer packets to obtain the transaction type and destination address; when the transaction type is a memory read / write transaction, it determines the traffic category based on the destination address; when the traffic category is point-to-point traffic, it forwards the transaction layer packets to the target high-speed peripheral component interconnect device corresponding to the destination address according to a preset point-to-point pass-through switching matrix. Because a traffic classifier separates point-to-point traffic from memory access traffic based on the destination address and transaction type of the transaction layer packets, and guides the point-to-point traffic to the preset point-to-point pass-through switching matrix for forwarding, point-to-point traffic no longer passes through the main interconnect bus and does not need to undergo arbitration and routing on that bus. This avoids mutual interference caused by point-to-point traffic sharing the main interconnect bus with traffic from core composite chips accessing high-speed peripheral component interconnect devices or double-data-rate memory, solving the technical problem of how to avoid mutual interference between different data during transmission. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating an embodiment of the high-speed peripheral component interconnection device data transmission method of this application. Figure 2 This application provides a system structure diagram for a first embodiment of the high-speed peripheral component interconnection device data transmission method. Figure 3 This is a timing diagram illustrating a scenario provided in Embodiment 1 of the high-speed peripheral component interconnection device data transmission method of this application; Figure 4 This is a flowchart illustrating Embodiment 2 of the high-speed peripheral component interconnection device data transmission method of this application; Figure 5 A simplified flowchart is provided for Embodiment 2 of the high-speed peripheral component interconnection device data transmission method of this application; Figure 6 This is a schematic diagram of the module structure of the high-speed peripheral component interconnection device for data transmission between devices according to an embodiment of this application; Figure 7 This is a schematic diagram of the hardware operating environment involved in the data transmission method between high-speed peripheral component interconnection devices in this application embodiment.

[0021] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0023] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0024] The main solution of this application embodiment is: to obtain transaction layer packets from high-speed peripheral component interconnection devices; to parse the header fields of the transaction layer packets to obtain the transaction type and target address; when the transaction type is a memory read / write transaction, to determine the traffic category according to the target address; when the traffic category is point-to-point traffic, to forward the transaction layer packets to the target high-speed peripheral component interconnection device corresponding to the target address according to a preset point-to-point pass-through switching matrix.

[0025] In this embodiment, for ease of description, the following description will focus on a high-speed peripheral component interconnection device data transmission system.

[0026] In the existing internal architecture of input / output chips, all high-speed peripheral component interconnect root complexes are connected to the PoC and DDR via a main interconnect bus. Point-to-point data transmission must sequentially pass through the root complex, the main interconnect bus, and the target root complex to reach its destination. This main interconnect bus simultaneously carries traffic from the core composite chip accessing high-speed peripheral component interconnect devices, traffic from the core composite chip reading and writing double data rate memory, and point-to-point traffic between devices. Point-to-point data on the main interconnect bus needs to undergo arbitration, routing, and buffering processes.

[0027] This application provides a solution that employs a traffic classifier to separate point-to-point traffic from memory access traffic based on the target address and transaction type of the transaction layer packet, and to guide the point-to-point traffic to a preset point-to-point pass-through switching matrix for forwarding. This eliminates the need for point-to-point traffic to pass through the main interconnect bus and undergo arbitration and routing on that bus. As a result, it avoids mutual interference caused by point-to-point traffic sharing the main interconnect bus with traffic from core composite chips accessing high-speed peripheral component interconnect devices or double data rate memory. This solves the technical problem of how to avoid mutual interference between different data during transmission.

[0028] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device capable of performing the above functions, a high-speed peripheral component interconnection device data transmission system, etc. The following description uses a high-speed peripheral component interconnection device data transmission system as an example to illustrate this embodiment and the subsequent embodiments.

[0029] Based on this, embodiments of this application provide a method for data transmission between high-speed peripheral component interconnect devices, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the high-speed peripheral component interconnection device data transmission method of this application.

[0030] In this embodiment, the high-speed peripheral component interconnection device data transmission method includes steps S10~S40: Step S10: Obtain the transaction layer packet from the high-speed peripheral component interconnect device.

[0031] It should be noted that high-speed peripheral component interconnect (PSI) devices are external devices connected to input / output chips via PSI links. PSI devices include graphics processors, non-volatile memory, high-speed solid-state drives, or smart network interface cards (NICs). A transaction layer packet is a data transmission unit defined by the transaction layer in the PSI protocol. A transaction layer packet contains a header field and a payload field.

[0032] like Figure 2As shown, the input / output chip internally contains multiple root complexes, traffic classifiers located at the port entrances of each root complex, point-to-point pass-through switching matrices, a main interconnect bus, a consistency point, and a double data rate memory controller. The consistency point is a hardware module located within the input / output chip, responsible for maintaining cache consistency across multiple core complexes. It is the centralized arbitration node for all cache consistency transactions in the multi-core system. Root complex 0 is connected to graphics processor device 0 via a high-speed peripheral component interconnect link; root complex 1 is connected to the solid-state drive; root complex 2 is connected to graphics processor device 1; and root complex 3 is connected to the smart network interface card (NIC). Each root complex is connected to the point-to-point pass-through switching matrix and the main interconnect bus via the traffic classifier. The main interconnect bus is further connected to the consistency point and the double data rate memory controller.

[0033] Specifically, high-speed peripheral component interconnect (PSI) devices are connected to the corresponding root complex ports in input / output chips via PSI links. Each root complex port corresponds to one PSI device, and the root complex port is responsible for terminating the transaction layer protocol processing of the PSI link. When a PSI device needs to send data to a target PSI device, the source device encapsulates the data to be transmitted into a transaction layer packet according to the PSI protocol and sends the transaction layer packet to the connected root complex port via the PSI link. After receiving the transaction layer packet, the root complex port passes the transaction layer packet to the traffic classifier located at the inlet of the root complex port. The traffic classifier is the execution entity that obtains the transaction layer packet and performs subsequent classification processing on the transaction layer packet.

[0034] For example, with Figure 2 For example, when graphics processor device 0 needs to read video memory data from graphics processor device 1, graphics processor device 0 generates a transaction layer packet of the type memory read request and sends it to the root complex 0 port of the input / output chip via the high-speed peripheral component interconnect link. After receiving the transaction layer packet, the root complex 0 port passes it to the traffic classifier at the entrance of the root complex 0 port to parse the transaction layer packet. If the transaction layer packet is identified as point-to-point traffic, it will be routed to the point-to-point pass-through switching matrix and forwarded directly to the root complex 1 port by the switching matrix, and then reach graphics processor device 1 via the high-speed peripheral component interconnect link, thus bypassing the main interconnect bus. If the transaction layer packet is identified as non-point-to-point traffic, it will be routed to the main interconnect bus and processed by the main interconnect bus through the consistency point or double data rate memory controller.

[0035] It is understandable that since the traffic classifier acquires and processes the transaction layer packets before they arrive at the root complex port, step S10 enables the transaction layer packets to be intercepted and classified before entering the main interconnect bus, preventing all traffic from flooding into the main interconnect bus indiscriminately, thereby improving the timeliness of subsequent traffic classification and routing decisions.

[0036] Step S20: Parse the header fields of the transaction layer packet to obtain the transaction type and target address.

[0037] It should be noted that the header fields of the transaction layer packet include a format field, a type field, and an address field. The format field indicates the length of the transaction layer packet header, the type field indicates the transaction type of the transaction layer packet, and the address field indicates the location of the target of the transaction layer packet in the system address space.

[0038] Specifically, the traffic classifier starts from the beginning of the header of the acquired transaction layer packet and extracts each field sequentially according to the header format specified by the High-Speed ​​Peripheral Component Interconnection Protocol (HSIPP). The traffic classifier reads the value of the type field and compares it with the transaction type encoding table defined by the protocol to obtain the transaction type of the transaction layer packet. Transaction types include memory read / write transactions, configuration read / write transactions, and input / output read / write transactions. Simultaneously, the traffic classifier reads the target address from the address field, which is a 32-bit or 64-bit address value. For example, when the format field of a transaction layer packet indicates a four-double-word header and the type field value corresponds to a memory read request, the traffic classifier determines that the transaction type of the transaction layer packet is a memory read transaction and extracts the corresponding target address from the address field.

[0039] It is understandable that since the transaction type and target address can be obtained by parsing the header fields, step S20 can quickly extract the information required for traffic classification without parsing the payload of the transaction layer packet, thereby improving processing efficiency and reducing parsing overhead.

[0040] Step S30: When the transaction type is a memory read / write transaction, determine the traffic category based on the target address.

[0041] It should be noted that traffic categories are used to indicate which data path within the input / output chip a transaction layer packet should be transmitted through. Traffic categories include point-to-point traffic and memory access traffic.

[0042] Specifically, the traffic classifier compares the parsed transaction type with the type encoding of memory read / write transactions. When the transaction type matches a memory read / write transaction, the traffic classifier further compares the target address with a preset first address range and a second address range. Based on the comparison results, the traffic category of the transaction layer packet is determined. The first address range is the spatial address range corresponding to the base address registers of the interconnecting devices for each high-speed peripheral component, and the second address range is the address space range of the double data rate memory connected to the input / output chips.

[0043] It is understandable that since it is only necessary to distinguish which address space the target address falls into when the transaction type is a memory read / write transaction, step S30 can directly exclude non-memory access transactions such as configuration read / write transactions and input / output read / write transactions from address space comparison, thereby reducing unnecessary address comparison operations and improving classification speed.

[0044] In one feasible implementation, step S30 may include: when the transaction type is a memory read / write transaction, obtaining a first spatial address range of the base address register of multiple high-speed peripheral component interconnect devices and a second spatial address range of double data rate memory; when the target address is within the first spatial address range, determining the traffic type as point-to-point traffic; when the target address is within the second spatial address range, determining the traffic type as central processing unit traffic or double data rate memory traffic.

[0045] It should be noted that the base address register is a set of registers within the configuration space of a high-speed peripheral interconnect device (PEIT). The base address register stores the starting address and length of the address range allocated to the device in the system address space. The system software configures the value of the base address register when enumerating high-speed PIT devices. Double data rate (DMR) memory is an external storage device connected to the input / output chip via a DMR memory controller. The address space of DMR memory is uniformly addressed by the system memory management unit.

[0046] Specifically, the traffic classifier maintains an address mapping table. Each entry in the table contains an address range and its corresponding traffic category label. When determining the traffic category, the traffic classifier compares the target address sequentially with each address range in the address mapping table. When the target address falls within the first address space range corresponding to the base address register of a high-speed peripheral component interconnect device (PSBIT), it indicates that the transaction packet is accessing the internal resources of that PSBIT, and therefore the transaction packet is marked as point-to-point traffic. When the target address falls within the second address space range of a double data rate (DFR) memory, it indicates that the transaction packet is accessing memory space, and therefore the transaction packet is marked as memory access traffic. For example, when the target address is 0x0000_0000_8000_0000 and this address falls within the base address register range of a graphics processor (0x0000_0000_8000_0000 to 0x0000_0000_8FFF_FFFF), the traffic classifier marks the transaction packet as point-to-point traffic.

[0047] In this embodiment, by comparing the target address with the base address register address range and the memory address range respectively, the problem of how to accurately distinguish whether a transaction layer packet should take the point-to-point path or the memory access path is solved based on the target address.

[0048] The above are merely feasible implementations of step S30 provided in this embodiment. This embodiment does not specifically limit the specific implementation of step S30.

[0049] Step S40: When the traffic type is point-to-point traffic, the transaction layer packet is forwarded to the target high-speed peripheral component interconnect device corresponding to the target address according to the preset point-to-point pass-through switching matrix.

[0050] It should be noted that the preset point-to-point pass-through switching matrix is ​​a dedicated crossbar switch hardware module located inside the input / output chip. It is directly connected to all root composite ports within the input / output chip and is used to directly transmit transaction layer packets between the root composite ports without going through the main interconnect bus.

[0051] Understandably, since the preset point-to-point pass-through switching matrix provides a dedicated data path for point-to-point traffic that is independent of the main interconnect bus, step S40 enables point-to-point traffic to completely bypass the main interconnect bus, avoiding competition between point-to-point traffic and traffic accessing high-speed peripheral component interconnect devices or accessing double data rate memory on the main interconnect bus, thereby increasing the available bandwidth of point-to-point transmission to equal the physical bandwidth of the high-speed peripheral component interconnect link.

[0052] In one feasible implementation, step S40 may include: obtaining the current traffic load of the main interconnect bus and the preset point-to-point pass-through switching matrix, wherein the main interconnect bus is the transmission path corresponding to CPU traffic, double data rate memory traffic, control traffic, and configuration traffic; determining the amount of idle bandwidth of the preset point-to-point pass-through switching matrix based on the current traffic load; allocating the idle bandwidth to the main interconnect bus when the amount of idle bandwidth is greater than a preset bandwidth threshold; and reclaiming the idle bandwidth allocated to the main interconnect bus when the current traffic load is greater than a preset matrix load threshold, and restoring the idle bandwidth to the dedicated bandwidth of the preset point-to-point pass-through switching matrix.

[0053] It should be noted that the current traffic load represents the ratio of the actual amount of data transmitted by the preset point-to-point pass-through switching matrix per unit time to its total bandwidth capacity. The idle bandwidth is the bandwidth remaining after subtracting the used bandwidth corresponding to the current traffic load from the total bandwidth capacity of the preset point-to-point pass-through switching matrix. The preset bandwidth threshold is the minimum idle bandwidth required to trigger a bandwidth borrowing operation, and the preset matrix load threshold is the maximum traffic load value required to trigger a bandwidth reclamation operation.

[0054] Specifically, the bandwidth management unit built into the preset point-to-point pass-through switching matrix periodically monitors the traffic rate of each input port and accumulates it to obtain the total current traffic load of the preset point-to-point pass-through switching matrix; the bandwidth management unit subtracts the total current traffic load from the total bandwidth capacity to obtain the amount of idle bandwidth; when the amount of idle bandwidth is greater than the preset bandwidth threshold, the bandwidth management unit temporarily allocates all or part of the idle bandwidth to the arbitrator of the main interconnect bus through a switch control signal, so that the main interconnect bus obtains additional bandwidth for transmitting central processing unit traffic or double data rate memory traffic; the bandwidth management unit continues to monitor the current traffic load, and when the current traffic load rises and exceeds the preset matrix load threshold, the bandwidth management unit cancels the bandwidth allocation to the main interconnect bus through a switch control signal and reallocates the previously borrowed bandwidth to the preset point-to-point pass-through switching matrix for use.

[0055] In this embodiment, by temporarily lending the idle bandwidth of the preset point-to-point pass-through switching matrix to the main interconnect bus when it is idle, the problem of idle bandwidth resources of the preset point-to-point pass-through switching matrix while the main interconnect bus may still have bandwidth requirements under light load is solved, thereby improving the utilization rate of the total bandwidth inside the input / output chip.

[0056] The above are merely feasible implementations of step S40 provided in this embodiment. This embodiment does not specifically limit the specific implementation of step S40.

[0057] For example, such as Figure 3As shown, taking a typical point-to-point transmission scenario where graphics processor device 0 reads the video memory of graphics processor device 1 as an example, the timing of the data transmission process of this application is explained. Graphics processor device 0 sends a transaction layer packet of memory read transaction type to the root complex 0 port of the input / output chip through the high-speed peripheral component interconnect link. After the transaction layer packet arrives at the root complex 0 port, it is passed to the traffic classifier located at the port entrance. The traffic classifier parses the header of the transaction layer packet, identifies the transaction layer packet as a memory read transaction from the format field and type field, and extracts the target address from the address field. The traffic classifier compares the extracted target address with the base address register address space of each high-speed peripheral component interconnect device, and finds that the target address falls within the base address register space range of graphics processor device 1. Based on this, the traffic classifier determines the traffic type of the transaction layer packet as point-to-point traffic. The traffic classifier routes the transaction layer packet to the point-to-point pass-through switching matrix, rather than the main interconnect bus, according to the classification result.

[0058] Upon receiving the transaction layer packet, the point-to-point pass-through switching matrix determines the target device as graphics processor device 1 based on the destination address. It then forwards the packet directly from root complex 0 port to root complex 1 port via a crossbar switch, and finally sends it to graphics processor device 1 via the high-speed peripheral component interconnect link. This transaction layer packet completely bypasses the main interconnect bus during the entire transmission process, without passing through the consistency point or double data rate memory controller, thus not consuming any bandwidth of the main interconnect bus. Upon receiving the memory read transaction layer packet, graphics processor device 1 reads the requested data from its own video memory, encapsulates the data into a completion packet, and returns it to graphics processor device 0 via the same path—from root complex 1 port through the point-to-point pass-through switching matrix to root complex 0 port. Throughout the transmission process, because the point-to-point pass-through switching matrix provides a dedicated independent data path for point-to-point traffic, this point-to-point transmission will not compete with the traffic of the central processing unit accessing high-speed peripheral component interconnect devices, nor with the read and write traffic of double data rate memory, thereby avoiding arbitration and routing delays on the main interconnect bus, and the latency of point-to-point transmission is significantly reduced.

[0059] This embodiment provides a data transmission method based on a point-to-point pass-through switching matrix within an input / output chip. It acquires transaction layer packets from high-speed peripheral component interconnect devices; parses the header fields of the transaction layer packets to obtain the transaction type and destination address; when the transaction type is a memory read / write transaction, it determines the traffic category based on the destination address; when the traffic category is point-to-point traffic, it forwards the transaction layer packets to the target high-speed peripheral component interconnect device corresponding to the destination address according to a preset point-to-point pass-through switching matrix. Because a traffic classifier separates point-to-point traffic from memory access traffic based on the destination address and transaction type of the transaction layer packets, and guides the point-to-point traffic to the preset point-to-point pass-through switching matrix for forwarding, point-to-point traffic no longer passes through the main interconnect bus and does not need to undergo arbitration and routing on that bus. This avoids mutual interference caused by point-to-point traffic sharing the main interconnect bus with traffic from core composite chips accessing high-speed peripheral component interconnect devices or double-data-rate memory, solving the technical problem of how to avoid mutual interference between different data during transmission.

[0060] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in Embodiment 1 above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 4 Step S40 of the data transmission method based on the point-to-point pass-through switching matrix within the input / output chip further includes steps S41 to S43: Step S41: Determine the target high-speed peripheral component interconnect device based on the target address.

[0061] It should be noted that the target high-speed peripheral interconnect device is the destination device that the transaction layer packet wants to access, and the target high-speed peripheral interconnect device corresponds to the base address register address range into which the target address falls.

[0062] Specifically, in step S30, the traffic classifier has determined that the target address falls within the address range of a certain base address register. The high-speed peripheral component interconnect (HS-IP) device to which this base address register belongs is then identified as the target H-IP device. The traffic classifier queries an internally maintained device address mapping table. Each entry in this table records the association between a device identifier and its corresponding base address register address range. By matching the target address with this mapping table, the identifier of the target H-IP device can be obtained. For example, when the target address 0x0000_0000_8000_0000 falls within the base address register range of graphics processor one, the traffic classifier determines that the target H-IP device is graphics processor one.

[0063] It is understandable that, since the target address uniquely corresponds to the base address register space of a high-speed peripheral component interconnect device, step S41 can convert the address information into a specific device identifier, thereby providing accurate destination information for determining the transmission path in the preset point-to-point pass-through switching matrix.

[0064] Step S42: When the traffic type is point-to-point traffic, determine the transmission path and target port load from the preset point-to-point pass-through switching matrix based on the port address of the high-speed peripheral component interconnection device and the port address of the target high-speed peripheral component interconnection device.

[0065] It should be noted that the port address is the unique identifier of the root composite port to which the high-speed peripheral component interconnect device is connected within the preset point-to-point pass-through switching matrix. The transmission path is the physical connection route from the port to the target port within the preset point-to-point pass-through switching matrix. The target port load is the amount of data to be forwarded that the target port is currently carrying.

[0066] Specifically, the preset point-to-point pass-through switching matrix maintains a port connection configuration table, which records the crossbar connection status between each port. When the traffic classifier transmits transaction layer packets and their traffic category labels to the preset point-to-point pass-through switching matrix, the preset point-to-point pass-through switching matrix searches for or establishes a connection path from the port to the target port in the port connection configuration table based on the port address of the port in the switching matrix and the port address of the root complex port to which the target high-speed peripheral component interconnect device is connected. At the same time, the preset point-to-point pass-through switching matrix reads the output queue depth or current bandwidth value of the target port to obtain the target port load. For example, when the high-speed peripheral component interconnect device is connected to root complex port 0 and the target high-speed peripheral component interconnect device is connected to root complex port 3, the preset point-to-point pass-through switching matrix selects the crossbar connection from input port 0 to output port 3 as the transmission path.

[0067] Understandably, since the cross-connect architecture of the preset point-to-point pass-through switching matrix supports connections from any input port to any output port, step S42 can dynamically establish a dedicated transmission connection based on the port and the target port, while also knowing the congestion status of the target port to guide subsequent forwarding behavior.

[0068] Step S43: Forward the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path and the target port load.

[0069] It should be noted that the preset point-to-point pass-through switching matrix determines whether transaction layer packets are forwarded in pass-through mode or store-and-forward mode based on the load of the target port.

[0070] Specifically, the preset point-to-point pass-through switching matrix compares the target port load with the preset port load threshold; selects different forwarding modes based on the comparison results; in the selected forwarding mode, the transaction layer packet is passed from the port along the transmission path to the target port, and then the target port sends the transaction layer packet to the target high-speed peripheral component interconnect device through the high-speed peripheral component interconnect link.

[0071] Understandably, since different forwarding modes are selected based on the target port load, step S43 enables the forwarding of transaction layer packets with the lowest latency when the target port is idle, and avoids data loss when the target port is busy, thereby improving the reliability and efficiency of transmission.

[0072] In one feasible implementation, step S43 may include: when the target port load is less than a preset port load threshold, forwarding the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path.

[0073] It should be noted that the preset port load threshold is a threshold value used to determine whether the target port is in a busy state. When the target port load is less than this threshold, it means that the target port has idle capacity to receive and immediately forward data.

[0074] Specifically, the preset point-to-point pass-through switching matrix compares the target port load with the preset port load threshold. When the target port load is less than the preset port load threshold, the preset point-to-point pass-through switching matrix starts forwarding the arrived partial data to the target port through the transmission path before the transaction layer packet is fully written into the port's input buffer, without waiting for the complete transaction layer packet to arrive.

[0075] In this embodiment, by using a pass-through mode for forwarding when the target port is idle, the problem of minimizing the dwell time of transaction layer packets within the preset point-to-point pass-through switching matrix when the target port load is low is solved.

[0076] In another feasible implementation, step S43 may include: when the target port load is greater than or equal to a preset port load threshold, caching the transaction layer packet into the buffer of the preset point-to-point pass-through switching matrix according to the transmission path; after caching is completed, forwarding the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path.

[0077] It should be noted that the buffer is a static random access memory (SRAM) equipped on each port of the pre-defined point-to-point pass-through switching matrix. The buffer is used to temporarily store transaction layer packets waiting to be forwarded. Buffer completion means that all bytes of a complete transaction layer packet have been written to the buffer.

[0078] Specifically, the preset point-to-point pass-through switching matrix compares the target port load with a preset port load threshold. When the target port load is greater than or equal to the preset port load threshold, the preset point-to-point pass-through switching matrix writes each part of the transaction layer packet into the port's buffer in sequence. After the complete transaction layer packet is written into the buffer, the preset point-to-point pass-through switching matrix reads the transaction layer packet from the buffer and forwards it to the target port through the transmission path.

[0079] In this embodiment, by adopting a store-and-forward mode when the target port is busy, the problem of how to avoid transmission errors or retransmissions of transaction layer packets during transmission due to the target port's inability to receive them in time is solved.

[0080] In another feasible implementation, step S43 may include: obtaining the port bandwidth weights of each high-speed peripheral component interconnect device and the total available bandwidth of the preset point-to-point pass-through switching matrix; adjusting the corresponding port bandwidth weights according to the port load of each high-speed peripheral component interconnect device; determining the available port bandwidth of each high-speed peripheral component interconnect device according to the total available bandwidth and the adjusted port bandwidth weights; and performing the step of forwarding the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path and the target port load, based on the available port bandwidth of the high-speed peripheral component interconnect device.

[0081] It should be noted that port bandwidth weight is a proportional coefficient assigned to each port within the total available bandwidth of the preset point-to-point pass-through switching matrix. Port load is the amount of data actually transmitted by the port per unit time. Port available bandwidth is the maximum transmission rate that the port can use, calculated based on the port bandwidth weight and the total available bandwidth.

[0082] Specifically, the scheduler of the pre-defined point-to-point pass-through switching matrix reads the port load value of each port from the traffic counter of each port; the scheduler sorts the port load values ​​of each port in descending order; the scheduler increases the bandwidth weight of ports with loads above the average value and decreases the bandwidth weight of ports with loads below the average value according to the sorting result; the scheduler multiplies the total available bandwidth by the adjusted bandwidth weight of each port to obtain the available bandwidth of each port; the scheduler controls the actual forwarding rate of each port according to the available bandwidth of each port, so that the actual forwarding rate of each port does not exceed its available bandwidth.

[0083] In this embodiment, by dynamically adjusting the port bandwidth weights according to the actual load of each port, the problem of how to fairly allocate the total available bandwidth of the preset point-to-point pass-through switching matrix among multiple concurrent point-to-point transmissions is solved.

[0084] The above are merely feasible implementations of step S43 provided in this embodiment. This embodiment does not specifically limit the specific implementation of step S43.

[0085] This embodiment provides a data transmission method based on a point-to-point pass-through switching matrix within an input / output chip. The method determines the target high-speed peripheral component interconnect (PSI) device based on the target address. When the traffic type is point-to-point traffic, the method determines the transmission path and target port load from a preset point-to-point pass-through switching matrix based on the port addresses of the PSI device and the target PSI device. The method then forwards the transaction layer packet to the target PSI device based on the transmission path and the target port load. By employing a technique that selects either pass-through or store-and-forward mode based on the target port load, the method avoids data loss that might occur when the target port is busy. It solves the problem of selecting an appropriate forwarding method based on the real-time status of the target port during point-to-point transmission to ensure transmission reliability, thus achieving adaptive forwarding of point-to-point transmission under different port load conditions.

[0086] For example, to help understand the implementation flow of the high-speed peripheral component interconnection device data transmission method obtained by combining this embodiment with the above embodiment one, please refer to Figure 5 , Figure 5 A simplified flowchart of a high-speed peripheral component interconnection method for data transmission between devices is provided, specifically: After a transaction layer packet arrives at the root composite port of an I / O chip from the source high-speed peripheral component interconnect (PSI) device via the PSI link, it is first passed to the traffic classifier located at the port's ingress. The traffic classifier receives the packet, parses its header fields, identifies the header length from the format field, the transaction type from the type field, and extracts the destination address from the address field. The traffic classifier then branches based on the transaction type: when the transaction type is a configuration read / write transaction or an I / O control transaction, the traffic classifier classifies the packet as control traffic and routes it directly to the main interconnect bus, which then forwards it to the consistency point for processing.

[0087] When the transaction type is a memory read / write transaction, the traffic classifier further compares the extracted target address with the address range of the base address register space of each high-speed peripheral component interconnect device and the address range of the double data rate memory space. If the target address falls within the address range of the double data rate memory space, the traffic classifier identifies the transaction packet as memory access traffic and routes it to the main interconnect bus, where it is processed by the main interconnect bus through a consistency point or the double data rate memory controller. If the target address falls within the address range of the base address register space of other high-speed peripheral component interconnect devices, the traffic classifier identifies the transaction packet as point-to-point traffic and routes it to a preset point-to-point pass-through switching matrix. Through the above-mentioned traffic separation mechanism based on transaction type and target address, this method achieves the separation of different types of traffic at the input / output chip entry point, allowing point-to-point traffic, memory access traffic, and control traffic to enter independent transmission paths.

[0088] After the traffic classifier marks the transaction layer packet as point-to-point traffic and routes it to the preset point-to-point pass-through switching matrix, the preset point-to-point pass-through switching matrix determines the target high-speed peripheral component interconnect device corresponding to the transaction layer packet based on the destination address, and determines the transmission path from the source port to the destination port from the crossbar switch architecture based on the source port address and the destination port address, while reading the current load of the destination port as the destination port load; the preset point-to-point pass-through switching matrix selects the forwarding mode based on the comparison result of the destination port load and the preset port load threshold—when the destination port load is less than the preset port load threshold, the transaction layer packet is forwarded directly from the source port to the destination port in pass-through mode via the transmission path, and then reaches the target high-speed peripheral component interconnect device via the root complex and high-speed peripheral component interconnect link corresponding to the destination port; when the destination port load is greater than or equal to the preset port load threshold, the transaction layer packet is first buffered in the port buffer of the preset point-to-point pass-through switching matrix, and after the complete transaction layer packet has been buffered, it is forwarded to the destination port via the transmission path. The pre-defined point-to-point pass-through switching matrix obtains the current load of each port through the traffic counters on each port. Based on the current load, it dynamically adjusts the bandwidth weight of each port and determines the available bandwidth of each port according to the total available bandwidth of the pre-defined point-to-point pass-through switching matrix and the adjusted bandwidth weights. The actual forwarding rate of each port is then controlled according to its available bandwidth. After this forwarding process, point-to-point traffic completely bypasses the main interconnect bus during the entire transmission process. It does not require arbitration or routing on the main interconnect bus, nor does it compete with traffic from the CPU accessing high-speed peripheral interconnect devices or read / write traffic from Double Data Rate (DDR) memory. This achieves path separation between point-to-point traffic and CPU / DDR traffic.

[0089] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the data transmission method between high-speed peripheral component interconnection devices of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0090] This application also provides a high-speed peripheral component interconnection device for data transmission between devices. Please refer to [link / reference]. Figure 6 The high-speed peripheral component interconnection device for data transmission includes: Input module 10 is used to obtain transaction layer packets from high-speed peripheral component interconnect devices; Parsing module 20 is used to parse the header fields of the transaction layer packet to obtain the transaction type and target address; The determination module 30 is used to determine the traffic category based on the target address when the transaction type is a memory read / write transaction; Forwarding module 40 is used to forward the transaction layer packet to the target high-speed peripheral component interconnect device corresponding to the target address according to a preset point-to-point pass-through switching matrix when the traffic type is point-to-point traffic.

[0091] The high-speed peripheral component interconnect (PCI) data transmission device provided in this application, employing the high-speed PCI data transmission method described in the above embodiments, can solve the technical problem of how to avoid mutual interference between different data during transmission. Compared with the prior art, the beneficial effects of the high-speed PCI data transmission device provided in this application are the same as those of the high-speed PCI data transmission method described in the above embodiments, and other technical features in the high-speed PCI data transmission device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0092] The determining module 30 is further configured to, when the transaction type is a memory read / write transaction, obtain the first spatial address range of the base address register of the multiple high-speed peripheral component interconnection devices and the second spatial address range of the double data rate memory; When the target address is within the range of the first spatial address, the traffic type is determined to be point-to-point traffic; When the target address is within the range of the second spatial address, the traffic category is determined to be either central processing unit traffic or double data rate memory traffic.

[0093] The forwarding module 40 is further configured to determine the target high-speed peripheral component interconnect device based on the target address; When the traffic type is point-to-point traffic, the transmission path and target port load are determined from the preset point-to-point pass-through switching matrix based on the port address of the high-speed peripheral component interconnection device and the port address of the target high-speed peripheral component interconnection device. The transaction layer packet is forwarded to the target high-speed peripheral component interconnect device according to the transmission path and the target port load.

[0094] The forwarding module 40 is further configured to cache the transaction layer packet in the buffer of the preset point-to-point pass-through switching matrix according to the transmission path when the target port load is greater than or equal to a preset port load threshold. After caching is complete, the transaction layer packet is forwarded to the target high-speed peripheral component interconnect device according to the transmission path.

[0095] The forwarding module 40 is further configured to forward the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path when the target port load is less than a preset port load threshold.

[0096] The forwarding module 40 is also used to obtain the port bandwidth weights of each high-speed peripheral component interconnection device and the total available bandwidth of the preset point-to-point connection. Adjust the corresponding port bandwidth weights based on the port load of each high-speed peripheral component interconnect device. The available port bandwidth of each of the high-speed peripheral component interconnect devices is determined based on the total available bandwidth and the adjusted port bandwidth weights. Based on the available bandwidth of the port of the high-speed peripheral component interconnect device, perform the step of forwarding the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path and the target port load.

[0097] The forwarding module 40 is also used to obtain the current traffic load of the main interconnect bus and the preset point-to-point pass-through switching matrix, wherein the main interconnect bus is the transmission path corresponding to the central processing unit traffic, double data rate memory traffic, control traffic and configuration traffic; Based on the current traffic load, determine the amount of idle bandwidth of the preset point-to-point direct switching matrix; When the amount of idle bandwidth is greater than a preset bandwidth threshold, the amount of idle bandwidth is allocated to the main interconnect bus; When the current traffic load exceeds a preset matrix load threshold, the idle bandwidth allocated to the main interconnect bus is reclaimed, and the idle bandwidth is restored to the dedicated bandwidth of the preset point-to-point pass-through switching matrix.

[0098] This application provides a high-speed peripheral component interconnect device for data transmission, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform the high-speed peripheral component interconnect device for data transmission method described in Embodiment 1 above.

[0099] The following is for reference. Figure 7 This document illustrates a structural schematic diagram of a high-speed peripheral component interconnect (PCI) data transmission device suitable for implementing embodiments of this application. The high-speed PCI data transmission device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), tablets, PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 7 The high-speed peripheral component interconnection device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0100] like Figure 7As shown, the high-speed peripheral component interconnect (PCI) data transfer device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the PCI data transfer device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows high-speed peripheral component interconnect (PCI) data transmission devices to wirelessly or wiredly communicate with other devices to exchange data. While the figures show high-speed PCI data transmission devices with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0101] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0102] The high-speed peripheral component interconnect (PCI) data transmission device provided in this application, employing the high-speed PCI data transmission method described in the above embodiments, can solve the technical problem of how to avoid mutual interference between different data during transmission. Compared with the prior art, the beneficial effects of the high-speed PCI data transmission device provided in this application are the same as those of the high-speed PCI data transmission method described in the above embodiments, and other technical features of this high-speed PCI data transmission device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0103] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0104] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0105] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the high-speed peripheral component interconnection device data transmission method in the above embodiments.

[0106] Specific examples of computer-readable storage media provided in this application may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium can be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0107] The aforementioned computer-readable storage medium may be included in a high-speed peripheral component interconnect (PIC) data transmission device; or it may exist independently and not be assembled into a high-speed PIC data transmission device.

[0108] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by the high-speed peripheral component interconnect (PIC) data transmission device, the high-speed PIC data transmission device performs the following actions: acquires a transaction layer packet from the high-speed PIC device; parses the header field of the transaction layer packet to obtain the transaction type and destination address; when the transaction type is a memory read / write transaction, determines the traffic category based on the destination address; and when the traffic category is point-to-point traffic, forwards the transaction layer packet to the target high-speed PIC device corresponding to the destination address according to a preset point-to-point pass-through switching matrix.

[0109] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as C++, and conventional procedural programming languages ​​such as "C" or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0110] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0111] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0112] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described high-speed peripheral component interconnection device data transmission method, thereby solving the technical problem of how to avoid mutual interference between different data during transmission. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the high-speed peripheral component interconnection device data transmission method provided in the above embodiments, and will not be repeated here.

[0113] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the high-speed peripheral component interconnection device data transmission method described above.

[0114] The computer program product provided in this application solves the technical problem of how to avoid mutual interference between different data during transmission. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the high-speed peripheral component interconnection device data transmission method provided in the above embodiments, and will not be repeated here.

[0115] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A method for data transmission between high-speed peripheral component interconnect devices, characterized in that, The method includes: Obtain transaction layer packets from high-speed peripheral component interconnect devices; Parse the header fields of the transaction layer packet to obtain the transaction type and target address; When the transaction type is a memory read / write transaction, the traffic category is determined based on the target address; When the traffic type is point-to-point traffic, the transaction layer packet is forwarded to the target high-speed peripheral component interconnect device corresponding to the target address according to the preset point-to-point pass-through switching matrix.

2. The method as described in claim 1, characterized in that, When the transaction type is a memory read / write transaction, determining the traffic category based on the target address includes: When the transaction type is a memory read / write transaction, obtain the first spatial address range of the base address register of multiple high-speed peripheral component interconnection devices and the second spatial address range of double data rate memory; When the target address is within the range of the first spatial address, the traffic type is determined to be point-to-point traffic; When the target address is within the range of the second spatial address, the traffic category is determined to be either central processing unit traffic or double data rate memory traffic.

3. The method as described in claim 1, characterized in that, When the traffic type is point-to-point traffic, forwarding the transaction layer packet to the target high-speed peripheral component interconnect device corresponding to the target address according to a preset point-to-point pass-through switching matrix includes: Based on the target address, the target high-speed peripheral component interconnect device is determined; When the traffic type is point-to-point traffic, the transmission path and target port load are determined from the preset point-to-point pass-through switching matrix based on the port address of the high-speed peripheral component interconnection device and the port address of the target high-speed peripheral component interconnection device. The transaction layer packet is forwarded to the target high-speed peripheral component interconnect device according to the transmission path and the target port load.

4. The method as described in claim 3, characterized in that, The step of forwarding the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path and the target port load includes: When the target port load is greater than or equal to a preset port load threshold, the transaction layer packet is cached in the buffer of the preset point-to-point pass-through switching matrix according to the transmission path; After caching is complete, the transaction layer packet is forwarded to the target high-speed peripheral component interconnect device according to the transmission path.

5. The method as described in claim 3, characterized in that, The step of forwarding the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path and the target port load includes: When the target port load is less than a preset port load threshold, the transaction layer packet is forwarded to the target high-speed peripheral component interconnect device according to the transmission path.

6. The method as described in claim 3, characterized in that, Before forwarding the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path and the target port load, the method further includes: Obtain the port bandwidth weights of each high-speed peripheral component interconnection device and the total available bandwidth of the preset point-to-point connection; Adjust the corresponding port bandwidth weights based on the port load of each high-speed peripheral component interconnect device. The available port bandwidth of each of the high-speed peripheral component interconnect devices is determined based on the total available bandwidth and the adjusted port bandwidth weights. Based on the available bandwidth of the port of the high-speed peripheral component interconnect device, perform the step of forwarding the transaction layer packet to the target high-speed peripheral component interconnect device according to the transmission path and the target port load.

7. The method as described in claim 1, characterized in that, When the traffic type is point-to-point traffic, after forwarding the transaction layer packet to the target high-speed peripheral component interconnect device corresponding to the target address according to the preset point-to-point pass-through switching matrix, the method further includes: Obtain the current traffic load of the main interconnect bus and the preset point-to-point pass-through switching matrix, wherein the main interconnect bus is the transmission path corresponding to the central processing unit traffic, double data rate memory traffic, control traffic and configuration traffic; Based on the current traffic load, determine the amount of idle bandwidth of the preset point-to-point direct switching matrix; When the amount of idle bandwidth is greater than a preset bandwidth threshold, the amount of idle bandwidth is allocated to the main interconnect bus; When the current traffic load exceeds a preset matrix load threshold, the idle bandwidth allocated to the main interconnect bus is reclaimed, and the idle bandwidth is restored to the dedicated bandwidth of the preset point-to-point pass-through switching matrix.

8. A high-speed peripheral component interconnection device for data transmission, characterized in that, The device includes: The input module is used to obtain transaction layer packets from high-speed peripheral component interconnect devices; The parsing module is used to parse the header fields of the transaction layer packet to obtain the transaction type and target address; The determination module is used to determine the traffic category based on the target address when the transaction type is a memory read / write transaction; The forwarding module is used to forward the transaction layer packet to the target high-speed peripheral component interconnect device corresponding to the target address according to a preset point-to-point pass-through switching matrix when the traffic type is point-to-point traffic.

9. A high-speed peripheral component interconnection device for data transmission, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the high-speed peripheral component interconnect device data transmission method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the high-speed peripheral component interconnection device data transmission method as described in any one of claims 1 to 7.

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