Electronic device, electronic device control method, computer program product, and medium

Abstract

The application discloses an electronic device, an electronic device control method, a computer program product and a medium, relates to the technical field of electronic devices, and the electronic device comprises a first processor, provides at least one group of first signal ports for signal transmission at a first transmission rate; at least one second processor, provides at least one group of second signal ports for signal transmission at a second transmission rate; a connection component comprising a first link and a second link, both of which are connected between the first signal port and the second signal port, and a rate converter is arranged on the second link; a controller connected with the first processor and the second processor respectively, used for acquiring a comparison result of the first transmission rate and the second transmission rate, and controlling signal transmission through the first link or the second link according to the comparison result. The technical problem that the application scene of the electronic device is limited in the related art, and performance and cost cannot be considered, the scene adaptation capability of the electronic device is improved, and performance and cost are balanced.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and in particular to an electronic device, an electronic device control method, a computer program product, and a medium. Background Technology

[0002] In related technologies, electronic devices typically employ a single signal transmission architecture. A first signal port provided by a first processor is connected to a rate converter on a switching board via a cable. After rate conversion by the rate converter, the signal is then connected to a second signal port provided by a second processor via another cable. However, this architecture only has one signal transmission path via the rate converter between the first and second signal ports. It cannot control the signal transmission via different links based on the comparison between the first and second transmission rates of the first and second signal ports. This means that even when the first and second transmission rates match, the signal still needs to be converted by the rate converter, preventing the second processor from achieving its maximum bandwidth performance. Furthermore, it increases material costs, signal loss, and forwarding delay, limiting the application scenarios of electronic devices and making it impossible to balance performance and cost. Summary of the Invention

[0003] This application provides an electronic device, an electronic device control method, a computer program product, and a medium to solve the technical problem in the related art where the application scenarios of electronic devices are limited and performance and cost cannot be balanced.

[0004] This application provides an electronic device, comprising: a first processor providing at least one set of first signal ports for signal transmission at a first transmission rate; at least one second processor providing at least one set of second signal ports for signal transmission at a second transmission rate; a connection component including a first link and a second link, both the first link and the second link being connected between the first signal port and the second signal port, the second link being provided with a rate converter; and a controller connected to the first processor and the second processor respectively, for acquiring a comparison result between the first transmission rate and the second transmission rate, and controlling the signal between the first signal port and the second signal port to be transmitted via the first link or the second link according to the comparison result.

[0005] This application also provides an electronic device control method. Based on any of the above-mentioned electronic devices, the electronic device control method includes: obtaining a comparison result of a first transmission rate and a second transmission rate; and controlling the signal between a first signal port and a second signal port to be transmitted via a first link or a second link according to the comparison result; wherein the first transmission rate is the signal transmission rate of the first signal port provided by the first processor, and the second transmission rate is the signal transmission rate of the second signal port provided by the second processor.

[0006] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the electronic device control method described in the following embodiments.

[0007] Obtain the comparison result between the first transmission rate and the second transmission rate; based on the comparison result, control the signal between the first signal port and the second signal port to be transmitted via the first link or the second link; wherein, the first transmission rate is the signal transmission rate of the first signal port provided by the first processor, and the second transmission rate is the signal transmission rate of the second signal port provided by the second processor.

[0008] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the electronic device control method described in the following embodiments.

[0009] Obtain the comparison result between the first transmission rate and the second transmission rate; based on the comparison result, control the signal between the first signal port and the second signal port to be transmitted via the first link or the second link; wherein, the first transmission rate is the signal transmission rate of the first signal port provided by the first processor, and the second transmission rate is the signal transmission rate of the second signal port provided by the second processor.

[0010] This application sets up a connection component including a first link and a second link, and sets up a rate converter on the second link. Simultaneously, a controller acquires the comparison result between the first transmission rate and the second transmission rate, and controls the signal between the first signal port and the second signal port to be transmitted via the first link or the second link based on the comparison result. This allows the electronic device to flexibly select the signal transmission path according to the relationship between the first and second transmission rates: when the first transmission rate is less than or equal to the second transmission rate, the signal is transmitted directly via the first link without passing through the rate converter, reducing material costs, signal loss, and forwarding delay; when the first transmission rate is greater than the second transmission rate, the signal is transmitted after rate conversion by the rate converter on the second link, ensuring that the second processor obtains full bandwidth performance, thereby expanding the application scenarios of the electronic device and achieving a balance between performance and cost. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of an electronic device in related technologies; Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application; Figure 3 A schematic diagram of the structure of an electronic device provided in another embodiment of this application; Figure 4 This is a schematic diagram of the structure of an electronic device provided in yet another embodiment of this application; Figure 5 A schematic diagram of a processor connector provided according to an embodiment of this application; Figure 6 A schematic flowchart of an electronic device control method provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device control device provided in an embodiment of this application; Figure 8 This is an internal structural diagram of a computer device provided in an embodiment of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0014] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] Accelerated electronic devices are high-performance computing devices specifically designed for computationally intensive tasks such as machine learning and deep learning. Unlike general-purpose electronic devices, accelerated electronic devices are equipped with acceleration chips such as graphics processors and neural network processors, along with high-bandwidth memory, high-speed interconnects, and high-speed storage architectures. They are specifically designed to handle tasks such as model training, fine-tuning, inference, and data processing. They are the core hardware infrastructure for the application of computing power in the industry and are widely used in scenarios such as data centers, enterprise server rooms, and edge terminals.

[0017] Compared to general-purpose electronic devices, accelerated electronic devices possess four core advantages: ultra-high parallel computing capabilities, ultra-large memory bandwidth, low-latency data throughput, and multi-card collaborative computing. These advantages enable them to efficiently address core needs such as massive data processing, model iteration optimization, and real-time business response. PCIe GPU servers are accelerated electronic devices that utilize PCIe (High-Speed ​​Peripheral Component Interconnect) slot-mounted graphics processors. This is a mainstream hardware architecture common in the industry, distinct from NVLink (a high-speed interconnect bus) direct-connection and SXM (a graphics processor onboard interface standard) onboard electronic devices. The graphics processor interconnects with the central processing unit, memory, and storage system of electronic devices via the PCIe 4.0 / 5.0 / 6.0 bus. Here, 4.0 / 5.0 / 6.0 refers to specific versions, demonstrating strong versatility, scalability, and compatibility, making them suitable for the vast majority of enterprise deployment scenarios. PCIe GPU server core technical features: Adopts a modular design with standard PCIe slots, supporting free plugging, replacement, and expansion of graphics processors; mainstream PCIe 5.0 bus, with a single-channel bandwidth of up to 128GB / s, meeting typical computing power transmission needs; single-card power consumption is generally 300-600W, with controllable energy consumption and lower hardware maintenance costs; no dedicated interconnect backplane required, compatible with standardized server chassis, and supports multiple types of consumer and industrial-grade graphics processors. The core advantages of PCIe GPU servers are: strong hardware compatibility, flexible iteration and upgrades, low procurement and maintenance costs, high model versatility, support for single-card to 8-card expansion, and compatibility with standardized data center deployments without customized hardware modifications. PCIe GPU server applicable scenarios: small to medium-scale model training, lightweight fine-tuning of large models, high-frequency inference services, computer vision analysis, intelligent office, data preprocessing, virtualized computing rendering, etc. Not suitable for scenarios with extreme bandwidth requirements such as distributed high-intensity training of trillions of ultra-large models and high-frequency collaborative computing with multiple cards.

[0018] like Figure 1 As shown, a solution for an electronic device with 8 PCIe form factor GPUs is provided in the related technology. This solution is suitable for scenarios with low computational performance requirements, such as 8-card high-density inference, virtual workstations, cloud rendering, and offline large models.

[0019] In this design, the CPU of the motherboard outputs eight PCIe 6.0 x8 ports (eight-channel ports of the 6th generation High Speed ​​Peripheral Component Interconnect standard), which are connected to the switch board via high-speed cables. The switch board is equipped with four GearBox chips (rate converters), each converting the two PCIe 6.0 x8 input signals from the motherboard into two PCIe 5.0 x16 output signals (sixteen-channel signals of the 5th generation High Speed ​​Peripheral Component Interconnect standard), thus enabling an electronic device architecture where eight GPU cards operate with PCIe 5.0 x16 bandwidth. Simultaneously, the power board supplies power to the motherboard and the switch board, and is responsible for auxiliary power supply to the PCIe form factor GPU cards.

[0020] However, in scenarios with PCIe 5.0 or PCIe 4.0 GPU cards, the above solution requires the uplink CPU to have a PCIe speed of PCIe 6.0 or PCIe 5.0 to fully utilize the GPU card's performance. For scenarios with an uplink CPU of PCIe 5.0 or PCIe 4.0, the GearBox chip forces a conversion from high-speed to low-speed signals, resulting in only half the performance of the PCIe 5.0 or PCIe 4.0 GPU card. Furthermore, current physical devices are still at most PCIe 6.0, but for PCIe 6.0 GPU card configurations, the GearBox chip forces a conversion from PCIe 6.0 to PCIe 5.0 signals, further reducing the GPU card's performance and increasing hardware costs by adding a switch board and four GearBox chips. From a signal path loss perspective, high-speed PCIe signals pass through the switch board traces and GearBox chips, resulting in greater signal loss and lower link stability. Meanwhile, the GearBox chip adds tens of nanoseconds of physical layer latency. In related technologies, every two GPU cards are bonded to a single GearBox chip, meaning that a failure in one GPU card will affect the other GPU card under the same GearBox chip, resulting in poor fault isolation capabilities.

[0021] To address the aforementioned technical issues, such as Figure 2 As shown, one embodiment of this application provides an electronic device, which includes a first processor, a second processor, a controller, and a connection component, specifically: A first processor provides at least one set of first signal ports for signal transmission at a first transmission rate.

[0022] The first processor can be the central processing unit (CPU). As the core of the computer system for computation and control, the first processor is the final execution unit for information processing and program execution.

[0023] The first signal port is integrated inside the first processor and can be provided by the PCIe controller inside the first processor, and brought out through the pins or solder balls of the first processor. Specifically, the first signal port can refer to a high-speed differential signal port provided by the first processor, such as a PCIe port. Of course, the first signal port can also be an NVLink port (High-Speed ​​Interconnect Bus port), a CXL port (Compute Fast Link port), a SATA port (Serial Advanced Technology Accessory port), a USB port (Universal Serial Bus port), or other high-speed serial differential signal ports.

[0024] The first transmission rate refers to the rate at which the first signal port transmits signals. Specifically, it can be 16GT / s for PCIe 4.0, 32GT / s for PCIe 5.0, or 64GT / s for PCIe 6.0. Here, 4.0, 5.0, and 6.0 refer to the version numbers of the Fast Peripheral Component Interconnect standard, with the rate doubling with each generation.

[0025] For example, the number of first signal ports can be 8 sets of PCIe x8 ports, all of which are integrated inside the first processor and provided by the PCIe controller inside the first processor.

[0026] At least one second processor provides at least one set of second signal ports for signal transmission at a second transmission rate.

[0027] The second processor can be a graphics processing unit (GPU), a processor specifically designed for graphics processing and parallel computing. Alternatively, it can be a neural network processor, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a tensor processor, or other processing chips with high-speed signal port output capabilities.

[0028] The second signal port is integrated inside the second processor and can be provided by the PCIe controller inside the second processor, and brought out through the pins or solder balls of the second processor. The second signal port refers to the high-speed differential signal port provided by the second processor, such as a PCIe port. Of course, the second signal port can also be an NVLink port (High-Speed ​​Interconnect Bus port), a CXL port (Compute Fast Link port), a SATA port (Serial Advanced Technology Accessory port), a USB port (Universal Serial Bus port), or other high-speed serial differential signal ports.

[0029] The second transmission rate refers to the rate at which the second signal port transmits signals. Specifically, it can be 16GT / s for PCIe 4.0, 32GT / s for PCIe 5.0, or 64GT / s for PCIe 6.0.

[0030] The number of second signal ports can be 8 sets of PCIe x16 ports. All 8 sets of PCIe x16 ports are integrated inside the second processor and are provided by the PCIe controller inside the second processor.

[0031] A connection component refers to a signal transmission path connecting a first signal port and a second signal port, including a first link and a second link. Both the first and second links are connected between the first and second signal ports, and both exist structurally, forming two selectable signal transmission paths. The first link is a signal transmission path that does not pass through a rate converter, used to directly connect the first and second signal ports. The second link is a signal transmission path that passes through a rate converter, and a rate converter is installed on it.

[0032] A rate converter is used to perform rate conversion and / or channel number conversion on high-speed differential signals. Specifically, a rate converter can be a GearBox chip, a retimer, an adapter chip, or other devices with rate conversion capabilities. For example, a rate converter can be a GearBox chip used to convert an input PCIe x8 signal to a PCIe x16 signal output.

[0033] The controller, connected to both the first and second processors, is used to acquire a comparison result between the first and second transmission rates, and based on the comparison result, control the transmission of signals between the first and second signal ports via the first or second link. Specifically, the controller can be a baseboard management controller, a complex programmable logic device, a microcontroller, a programmable logic device, or other devices with rate acquisition and link configuration functions.

[0034] In this embodiment, by setting up two link cables, the first signal port and the second signal port can simultaneously have two signal transmission paths: a direct connection path and a path via a rate converter. The electronic device can flexibly select the signal transmission path according to the relationship between the first transmission rate and the second transmission rate, which expands the application scenarios of the electronic device and achieves a balance between performance and cost.

[0035] like Figure 3 As shown, one embodiment of this application provides an electronic device, which includes a first processor, a second processor, a controller, a connection component, a first board, a third board, and a processor connector. Specifically: The first board refers to the board that carries the first processor and the first connector. Specifically, the first board can be a motherboard, a computing board, a baseboard, or other board that carries the processor. In this embodiment, the first board is a motherboard.

[0036] The first connector is disposed on the first board, and its first end is connected to the first signal port. Specifically, the first connector can be an MCIO connector (multi-channel input / output connector), a SlimSAS connector (small serial connection small computer system interface connector), an OCuLink connector (miniature high-speed optical copper interconnect connector), or other high-speed signal connectors.

[0037] This embodiment shows a specific example of a first link as the connecting component. The first link includes a first connector and a first cable. The first end of the first connector is connected to a first signal port, and the second end of the first connector is connected to a second signal port through the first cable.

[0038] In this application, the first cable can be a first direct-connect accessory cable; the first end of the first direct-connect accessory cable is connected to the first connector, and the second end of the first direct-connect accessory cable is connected to the processor connector; the first direct-connect accessory cable integrates signal lines, sideband signal lines, and slot power supply lines. The signal lines are used to transmit signals between the first signal port and the second signal port, the sideband signal lines are used to transmit sideband signals, and the slot power supply lines are used to transmit slot power. Thus, the three types of signals or power supplies share the same direct-connect accessory cable, eliminating the need for separate wiring.

[0039] The processor connector has a first end connected to the second end of at least one set of first connectors. Specifically, the processor connector can be a graphics processor direct connection accessory connector, which is fixed to the wall of the electronic device housing through a fixing hole, or fixed to the electronic device housing through an auxiliary component. Compared with the related technology where the processor connector is set on the board, in this application the processor is set independently of the board, which can reduce the board size.

[0040] The third board contains a power connector and a power interface. The power connector is used to connect to an external power source. The power interface connects to the processor connector via a power cable, supplying power to the second processor via the processor connector. The second processor also has an auxiliary power interface. This auxiliary power interface connects to the second processor via a separate power cable, supplying power to the second processor. The auxiliary power interface is located on the second processor and does not pass through the processor connector; it is used to meet the high power consumption requirements of the second processor.

[0041] In this embodiment, the third board is a power supply board. The power connector is used to connect to an external power source, and the power supply interface connects to the processor connector via a power cable, providing slot power to the second processor through the processor connector. Slot power supply includes P3V3 and PCIe_12V_SLOT, where P3V3 refers to 3.3V slot power supply and PCIe_12V_SLOT refers to 12V slot power supply; both are standard power supplies provided to the second processor through the processor connector. The power of the slot power supply is limited by the Fast Peripheral Component Interconnect (FPCI) standard, typically up to 75 watts. When the power consumption of the second processor exceeds the slot power supply capacity, auxiliary power is also required to the second processor via a separate power cable.

[0042] The third board is also equipped with a sideband signal connector. The first end of the sideband signal connector is used to receive the sideband signal, and the second end of the sideband signal connector is connected to the processor connector through the sideband signal cable. The sideband signal is transmitted to the second processor through the processor connector. The sideband signal includes at least one of the following: reset signal, management bus signal, and reference clock signal.

[0043] The first board also includes a first controller and a second controller. The first controller is connected to both the first and second processors and is used to collect the signal port rates of the first and second processors and compare their values. The second controller is connected to both the first controller and the first processor and is used to control the transmission of signals between the first and second signal ports via either the first or second link, based on the comparison result from the first controller. In this embodiment, the first controller is a baseboard management controller, and the second controller is a complex programmable logic device (CPL).

[0044] The third board also has a third controller, which is connected to the first controller and the rate converter. It is used to receive control signals from the first controller and to forward or convert the sideband signals.

[0045] In this embodiment, the third controller is a complex programmable logic device.

[0046] In this application, the first signal port has a first number of channels, the second signal port has a second number of channels, and the rate converter is used to convert the signal with the first number of channels into the signal with the second number of channels, wherein the second number of channels is greater than the first number of channels.

[0047] The relationship between the first transmission rate of the first signal port and the second transmission rate of the second signal port determines whether a rate converter is needed between the first signal port and the second signal port.

[0048] When the first transmission rate is less than or equal to the second transmission rate, the first signal port can be directly connected to the second signal port point-to-point without going through a rate converter. In this case, the signal transmission path between the first signal port and the second signal port is the shortest, the material cost is the lowest, and the signal loss and forwarding delay are minimal.

[0049] When the first transmission rate is greater than the second transmission rate, the rate of the first signal port is higher than that of the second signal port. If directly connected, the second signal port cannot operate at the first transmission rate, thus failing to utilize the high-speed advantage of the first signal port. In this case, a rate converter is needed to convert the signal output from the first signal port with the first number of channels into a signal with the second number of channels, where the second number of channels is greater than the first number of channels, so that the second signal port can achieve full bandwidth performance.

[0050] This embodiment establishes a first link, enabling a direct signal transmission path between the first and second signal ports without a rate converter. When the first transmission rate is less than or equal to the second transmission rate, the first signal port can directly connect to the second signal port point-to-point without a rate converter, minimizing the signal transmission path and reducing material costs, signal loss, and forwarding delay. Furthermore, the first direct-connect accessory cable integrates signal lines, sideband signal lines, and slot power supply lines, allowing all three types of signals or power supplies to share the same cable, reducing the number of cables inside the electronic device and improving maintainability. The processor connector is fixed to the chassis wall or auxiliary components via mounting holes, relieving the tensile stress of the cable on the connector and protecting the reliability of the connection between the connector and the cable.

[0051] In this embodiment, the remaining signal ports on the first board can be connected to a storage device or a network interface card (NIC). Specifically, the storage device can be an NVMe drive, and the NIC can be a smart NIC or a management NIC. Specifically, the first signal port consists of eight PCIe x8 ports (Rapid Peripheral Component Interconnect Standard 8-Channel Port), and the second signal port consists of eight PCIe x8 ports, corresponding to a configuration of eight PCIe x8 graphics processor cards. In another embodiment, the first signal port consists of eight PCIe x16 ports (Rapid Peripheral Component Interconnect Standard 16-Channel Port), and the second signal port consists of eight PCIe x16 ports, corresponding to a configuration of eight PCIe x16 graphics processor cards. In yet another embodiment, the first signal port consists of eight PCIe x8 ports, and two of these eight PCIe x8 ports are combined to form one PCIe x16 port, resulting in four PCIe x16 ports, corresponding to a configuration of four PCIe x16 graphics processor cards.

[0052] In a specific example, the electronic device provided in this embodiment can be applied to scenarios where the first transmission rate is less than or equal to the second transmission rate. For instance, the eight first differential signal ports of the first processor can be connected to eight second differential signal ports via a first link cable, eliminating the need for forwarding through a switching board and a rate converter. The eight second differential signal ports are fixed inside the chassis by structural components. The PCIe performance comparison between the electronic device provided in this application and electronic devices provided in related technologies is as follows: Table 1

[0053] Table 2

[0054] As shown in Table 1, the electronic device provided in this application has the same bandwidth performance as the electronic device provided in related technologies. Specifically, in scenarios where the first transmission rate is less than or equal to the second transmission rate, the first differential signal port is connected to the second differential signal port through the first link cable, and the second processor operates at its own rate, with the same bandwidth performance as the solution via the rate converter. As shown in Table 2, the cost of this application is superior to that of related technologies, with lower signal path loss and forwarding delay, and better fault isolation. Specifically: In terms of cost, this application eliminates the need for a second board and rate converters, resulting in a lower bill of materials cost; while related technologies require an additional second board and four rate converters, leading to higher costs. In terms of signal path loss, this application eliminates rate converter insertion loss, resulting in lower signal path loss; while related technologies incur additional rate converter loss. In terms of forwarding delay, this application uses pure direct cable transmission, resulting in the lowest forwarding delay; while related technologies add tens of nanoseconds of physical layer delay to the rate converter. Regarding fault isolation, the eight second processors in this application are decoupled and independent, and a fault in a single second processor does not affect the remaining second processors; while in related technologies, every two second processors are bound and coupled to a rate converter, and a fault in a single second processor will affect the other second processor under the same rate converter.

[0055] like Figure 4 As shown, one embodiment of this application provides an electronic device, which includes a first processor, a second processor, a controller, a connection component, a first board, a second board, a third board, and a processor connector. Specifically: The first board refers to the board that carries the first processor and the first connector. Specifically, the first board can be a motherboard, a computing board, a baseboard, or other board that carries the processor. In this embodiment, the first board is a motherboard.

[0056] The first connector is mounted on the first board, and its first end is connected to the first signal port. Specifically, the first connector can be an MCIO connector, a SlimSAS connector, an OCuLink connector, or other high-speed signal connectors.

[0057] This embodiment shows a specific example of a second link as the connecting component. The second link includes a first connector, a second cable, a second connector, a rate converter, a third connector, and a third cable. The first end of the first connector is connected to a first signal port. The second end of the first connector is connected to the first end of the second connector via the second cable. The second end of the second connector is connected to the first end of the rate converter. The second end of the rate converter is connected to the first end of the third connector. The second end of the third connector is connected to the second signal port via the third cable.

[0058] The second cable can be a high-speed cable, a direct-connect accessory cable, or other high-speed differential signal cable.

[0059] The third cable can be a second direct-connect accessory cable. The first end of the second direct-connect accessory cable connects to the third connector, and the second end connects to the processor connector. The second direct-connect accessory cable integrates signal lines, sideband signal lines, and slot power lines. The signal lines transmit signals output by the rate converter, the sideband signal lines transmit sideband signals forwarded or level-converted by the third controller, and the slot power lines transmit slot power. Therefore, the signals output by the rate converter, the sideband signals processed by the third controller, and the slot power supply all share the same direct-connect accessory cable, eliminating the need for separate wiring.

[0060] The electronic device also includes a second board, on which a rate converter, at least one set of second connectors, and at least one set of third connectors are disposed.

[0061] The second board refers to the board containing the data rate converter, the second connector, and the third connector. Specifically, the second board can be a switching board, an adapter board, a matching board, or another data rate converter board. In this embodiment, the second board is a switching board.

[0062] The rate converter can specifically be a GearBox chip, a retimer, an adapter chip, or other devices with rate conversion and / or channel number conversion functions. In this embodiment, the rate converter is a GearBox chip, used to convert the input PCIe x8 signal into a PCIe x16 signal for output.

[0063] The second connector is located on the second board, with its first end connected to the second cable and its second end connected to the first end of the rate converter. Specifically, the second connector can be an MCIO connector, a SlimSAS connector, an OCuLink connector, or other high-speed differential signal connectors.

[0064] The third connector is located on the second board. Its first end connects to the second end of the rate converter, and its second end connects to the third cable. Specifically, the third connector can be an MCIO connector, a SlimSAS connector, an OCuLink connector, or other high-speed signal connectors.

[0065] In this embodiment, the second board can be 350mm × 205mm in size, which is 30.51% smaller in area compared to the 350mm × 295mm switching board in related technologies, thus reducing PCB costs. In this embodiment, the second board reuses the fixing method of the power board and processor connector of the first board.

[0066] The first end of the processor connector is connected to the second end of at least one set of third connectors, and the second end of the processor connector is connected to at least one set of second signal ports.

[0067] The processor connector is located on the second processor side, with its first end connected to the second end of the third connector, and its second end connected to the second signal port. Specifically, the processor connector can be a graphics processor direct-connect accessory connector, an MCIO connector, a SlimSAS connector, or other high-speed signal connectors.

[0068] The processor connector may include a connector body, with a first end for connecting to a first cable or a third cable, and a second end for connecting to a second signal port. Specifically, the connector body may be an MCIO connector body, a SlimSAS connector body, or other high-speed signal connector bodies. In this embodiment, the connector body is a GPU DA CONN connector body. For example, the processor connector may specifically be as follows: Figure 5 As shown, it can be fixed to the chassis wall or the mechanism fixing auxiliary parts through the fixing holes.

[0069] The connector body also integrates sideband signal terminals, which are used to transmit at least one of reset signals, management bus signals, and reference clock signals. Specifically, the sideband signal terminals can be I2C terminals, reset signal terminals, clock signal terminals, or other sideband signal terminals.

[0070] In this application, a fourth controller is also provided on the second motherboard. The fourth controller is connected to the second controller and the rate converter respectively, and is used to receive the control signal of the second controller and monitor the status of the rate converter. Specifically, the fourth controller can be a CPLD.

[0071] It is understood that this application may also include other cables, such as power cables, sideband signal cables, etc., and this application does not limit them.

[0072] An electronic device chassis refers to the enclosure that houses the various boards and connectors of an electronic device. In this embodiment, the processor connector can specifically be a graphics processor direct-connect accessory connector, which is fixed to the wall of the electronic device's housing through mounting holes, or fixed to the electronic device's housing through auxiliary parts. This can release the tensile stress of the cable on the connector and protect the reliability of the connection between the connector and the cable.

[0073] This embodiment establishes a second link to create a signal transmission path between the first and second signal ports via a rate converter. When the first transmission rate is greater than the second transmission rate, the speed of the first signal port is higher than that of the second signal port. If directly connected, the second signal port cannot operate at the first transmission rate, thus negating the high-speed advantage of the first signal port. In this case, the signal is transmitted via the second link, where the rate converter transforms the signal with the first number of channels into a signal with the second number of channels, which is greater than the first number of channels. This allows the second signal port to achieve full bandwidth performance. In this embodiment, the first transmission rate can be PCIe 6.0 and the second transmission rate can be PCIe 5.0; or, the first transmission rate can be PCIe 5.0 and the second transmission rate can be PCIe 4.0.

[0074] Furthermore, the second direct-connect accessory cable integrates signal lines, sideband signal lines, and slot power supply lines. The signal output from the rate converter, the sideband signal processed by the third controller, and the slot power supply share the same cable, reducing the number of cables inside the electronic device and improving maintainability. The processor connector body integrates sideband signal terminals, and the sideband signal is integrated with the main signal in the same connector, reducing the number of connectors. The processor connector is fixed to the chassis wall or mechanical auxiliary parts through mounting holes, releasing the tensile stress of the cable on the connector and protecting the reliability of the connection between the connector and the cable.

[0075] In the PCIe bus, the total bandwidth equals the product of the single-channel transfer rate and the number of channels. The same total bandwidth can be achieved through different combinations; for example, PCIe 5.0 x8 and PCIe 4.0 x16 have the same total bandwidth, as do PCIe 6.0 x8 and PCIe 5.0 x16.

[0076] When the first transmission rate is less than or equal to the second transmission rate, the first signal port can be directly connected to the second signal port point-to-point without going through a rate converter. In this case, the second signal port operates at the first transmission rate, resulting in the shortest signal transmission path, the lowest material cost, and minimal signal loss and forwarding delay.

[0077] When the first transmission rate is greater than the second transmission rate, the speed of the first signal port is higher than that of the second signal port. If directly connected, the second signal port can only operate at its own speed, and the high-speed advantage of the first signal port cannot be utilized. In this case, a rate converter is needed to convert the signal output from the first signal port with the first number of channels into a signal with the second number of channels, where the second number of channels is greater than the first number of channels, so that the second signal port can achieve full bandwidth performance.

[0078] For example, when the first signal port is PCIe 6.0 x8 and the second signal port is PCIe 5.0 x16, the first transmission rate is greater than the second transmission rate. If directly connected, the second signal port can only operate as PCIe 5.0 x8, with a bandwidth only half that of PCIe 5.0 x16. After converting PCIe 6.0 x8 to PCIe 5.0 x16 using a rate converter, the second signal port operates as PCIe 5.0 x16, doubling the bandwidth and achieving full bandwidth performance.

[0079] Therefore, this application enables electronic devices to adapt to GPU card scenarios with different speed combinations by setting two scenarios. Regardless of the relationship between the CPU port speed and the GPU card speed, the GPU card can obtain full bandwidth performance, which expands the application scenarios of electronic devices and achieves a balance between performance and cost.

[0080] In a specific example, the electronic device provided in this embodiment can be applied to scenarios where the first transmission rate is greater than the second transmission rate, such as when the first transmission rate is the transmission rate corresponding to the sixth generation Fast Peripheral Component Interconnect standard and the second transmission rate is the transmission rate corresponding to the fifth generation Fast Peripheral Component Interconnect standard, or when the first transmission rate is the transmission rate corresponding to the fifth generation Fast Peripheral Component Interconnect standard and the second transmission rate is the transmission rate corresponding to the fourth generation Fast Peripheral Component Interconnect standard.

[0081] In this scenario, the eight sixth-generation or fifth-generation eight-channel differential signal ports of the first processor are transmitted to the rate converter on the second board via the first connector. The rate converter converts these signals into eight fifth-generation or fourth-generation sixteen-channel differential signals, which are then connected to the eight second differential signal ports via eight third connectors and a second direct-connect accessory cable. The PCIe performance of the electronic device provided in this application is compared with that of electronic devices provided in related technologies as follows: Table 3

[0082] Table 4

[0083] As shown in Table 3, the electronic device provided in this application has the same bandwidth performance as the electronic device provided in related technologies. Specifically, in scenarios where the first transmission rate is greater than the second transmission rate, this application converts the high-speed eight-channel signal into a low-speed sixteen-channel signal through a rate converter, and the second processor operates at its own full bandwidth, with the same bandwidth performance as the solution in related technologies. As shown in Table 4, the performance of this application is on par with related technologies, but the cost is better, the signal path loss is lower, and the difference in forwarding delay and fault isolation is not significant. Specifically: In terms of cost, the size of the second board in this application is 350 mm × 205 mm, which is 30.51% smaller than the 350 mm × 295 mm of related technologies, resulting in a reduction in printed circuit board cost; while the second board size of related technologies is larger. In terms of signal path loss, the traces on the second board of this application are shorter, resulting in lower signal path loss; while the printed circuit board traces of related technologies are longer, resulting in greater insertion loss. In terms of forwarding delay, both this application and related technologies increase the physical layer delay of the rate converter by tens of nanoseconds, with little difference. In terms of fault isolation, this application and related technologies both use a binding coupling of every two second processors, with little difference.

[0084] In one feasible implementation, the first link and the second link are arranged in layers within the electronic device chassis, with the first link located on the first layer and the second link located on the second layer. A shielding partition is provided between the first and second layers. Specifically, the interior of the electronic device chassis is divided into a first layer and a second layer along the height direction. The first link is arranged on the first layer, and the second link is arranged on the second layer. The first link and the second link are spatially separated, avoiding the two link cables being physically adjacent. The shielding partition is provided between the first and second layers, separating them. The shielding partition can specifically be a metal partition, a conductive foam partition, a metallized film partition, or other partitions with electromagnetic shielding functions. In this embodiment, the shielding partition is a metal partition.

[0085] Since the first link transmits a high-speed signal without rate conversion, and the second link transmits a high-speed differential signal after rate conversion, both being high-speed differential signals, signal crosstalk can easily occur if they are placed close together. This embodiment effectively reduces signal crosstalk between the two links by arranging the first and second links in layers and placing a shielding partition between the two layers, thereby improving the quality of high-speed signal transmission.

[0086] like Figure 6 As shown, one embodiment of this application provides an electronic device control method, which specifically includes: S1: Obtain the comparison result between the first transmission rate and the second transmission rate.

[0087] Specifically, the controller acquires the first transmission rate of the first signal port and the second transmission rate of the second signal port, compares their magnitudes, and obtains a comparison result. The first transmission rate is the signal transmission rate of the first signal port provided by the first processor, and the second transmission rate is the signal transmission rate of the second signal port provided by the second processor. In this embodiment, the first transmission rate can be 16GT / s for PCIe 4.0, 32GT / s for PCIe 5.0, or 64GT / s for PCIe 6.0; the second transmission rate can be 16GT / s for PCIe 4.0, 32GT / s for PCIe 5.0, or 64GT / s for PCIe 6.0. The controller can specifically be a baseboard management controller, a complex programmable logic device, a microcontroller, or other devices with rate acquisition and comparison functions. In this embodiment, the controller includes a first controller and a second controller. The first controller is a baseboard management controller used to acquire and compare rates, and the second controller is a complex programmable logic device used to configure the link.

[0088] S2: Based on the comparison result, control the signal between the first signal port and the second signal port to be transmitted via the first link or the second link, wherein the first transmission rate is the signal transmission rate of the first signal port provided by the first processor, and the second transmission rate is the signal transmission rate of the second signal port provided by the second processor.

[0089] Specifically, based on the comparison result, the controller controls the signal between the first signal port and the second signal port to be transmitted via either the first link or the second link. The first link is a signal transmission path that does not pass through a rate converter, while the second link is a signal transmission path that does pass through a rate converter.

[0090] When the first transmission rate is less than or equal to the second transmission rate, the first signal port can be directly connected point-to-point to the second signal port without going through a rate converter. In this case, the controller control signal is transmitted via the first link. The signal output from the first signal port is transmitted sequentially through the first connector, the first cable, and the processor connector to the second signal port. Because the signal does not pass through a rate converter, the signal transmission path is the shortest, reducing material costs, signal loss, and forwarding delay.

[0091] When the first transmission rate is greater than the second transmission rate, the rate of the first signal port is higher than that of the second signal port. If directly connected, the second signal port cannot operate at the first transmission rate, thus negating the high-speed advantage of the first signal port. In this case, the controller control signal is transmitted via the second link. The signal output from the first signal port is transmitted sequentially through the first connector, the second cable, and the second connector to the first end of the rate converter. After rate conversion, it is output from the second end of the rate converter to the third connector, then transmitted through the third connector and the third cable to the processor connector, and finally transmitted through the processor connector to the second signal port. Because the signal undergoes rate conversion through the rate converter, the second signal port achieves full bandwidth performance.

[0092] This embodiment obtains the comparison result between the first transmission rate and the second transmission rate, and controls the signal between the first signal port and the second signal port to be transmitted via the first link or the second link according to the comparison result. This enables the electronic device to automatically adapt to the optimal link according to the rate relationship: when the first transmission rate is less than or equal to the second transmission rate, the signal is transmitted via the first link without passing through the rate converter, resulting in the shortest signal transmission path and reducing material costs, signal loss, and forwarding delay; when the first transmission rate is greater than the second transmission rate, the signal is transmitted via the second link, and the rate converter converts the signal with the first number of channels into the signal with the second number of channels, which is greater than the first number of channels, so that the second signal port obtains full bandwidth performance. Thus, the same electronic device hardware structure can adapt to different rate scenarios without replacing the board, expanding the application scenarios of the electronic device and achieving a balance between performance and cost. Moreover, the controller automatically obtains the comparison result and configures the signal transmission path without manual intervention, improving deployment efficiency.

[0093] Embodiments of this application provide an electronic device control apparatus, which specifically includes, as follows: Figure 7 As shown, the fault handling device includes: an acquisition module 20 and a control module 21.

[0094] The acquisition module 20 is used to acquire the comparison result between the first transmission rate and the second transmission rate.

[0095] Control module 21 is used to control the transmission of signals between the first signal port and the second signal port via the first link or the second link according to the comparison result; wherein, the first transmission rate is the signal transmission rate of the first signal port provided by the first processor, and the second transmission rate is the signal transmission rate of the second signal port provided by the second processor.

[0096] For specific limitations regarding the control device of the electronic device, please refer to the limitations on the control method of the electronic device mentioned above, which will not be repeated here. Each module in the above-mentioned electronic device control can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the electronic device in hardware form or independent of it, or they can be stored in the memory of the electronic device in software form, so that the processor can call and execute the operations corresponding to each module.

[0097] like Figure 8 As shown, embodiments of this application also provide a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above embodiments of the electronic device control method.

[0098] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the electronic device control method when it is run.

[0099] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0100] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the electronic device control method.

[0101] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above embodiments of the electronic device control method.

[0102] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "electronic device," or "apparatus" used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0103] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0104] The above provides a detailed description of an electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. An electronic device, characterized in that, The electronic device includes: A first processor provides at least one set of first signal ports for signal transmission at a first transmission rate; At least one second processor provides at least one set of second signal ports for signal transmission at a second transmission rate; A connection component, comprising a first link and a second link, wherein the first link and the second link are both connected between the first signal port and the second signal port, and a rate converter is provided on the second link; The controller, connected to the first processor and the second processor respectively, is used to obtain the comparison result of the first transmission rate and the second transmission rate, and control the signal between the first signal port and the second signal port to be transmitted through the first link or the second link according to the comparison result.

2. The electronic device according to claim 1, characterized in that, The first link includes a first connector and a first cable. A first end of the first connector is connected to the first signal port, and a second end of the first connector is connected to the second signal port via the first cable.

3. The electronic device according to claim 1, characterized in that, The second link includes a first connector, a second cable, a second connector, the rate converter, a third connector, and a third cable. The first end of the first connector is connected to the first signal port. The second end of the first connector is connected to the first end of the second connector via the second cable. The second end of the second connector is connected to the first end of the rate converter. The second end of the rate converter is connected to the first end of the third connector. The second end of the third connector is connected to the second signal port via the third cable.

4. The electronic device according to claim 2 or 3, characterized in that, The electronic device further includes a first board, on which a first processor and at least one set of first connectors are disposed.

5. The electronic device according to claim 3, characterized in that, The electronic device also includes a second board, on which a rate converter, at least one set of second connectors, and at least one set of third connectors are disposed.

6. The electronic device according to claim 1, characterized in that, The electronic device further includes a processor connector, a first end of which is connected to the second end of at least one set of first connectors, and / or the first end of which is connected to the second end of at least one set of third connectors, and the second end of which is connected to at least one set of second signal ports.

7. The electronic device according to claim 6, characterized in that, The electronic device also includes a housing, and the processor connector is fixed to the wall of the housing through a fixing hole, or fixed to the housing through an auxiliary component of the housing.

8. The electronic device according to claim 7, characterized in that, The electronic device also includes a third board, which is provided with a power connector and a power supply interface; The power connector is used to connect to an external power source; The power supply interface is connected to the processor connector via a power supply cable, and provides slot power to the second processor through the processor connector.

9. The electronic device according to claim 8, characterized in that, The second processor is also provided with an auxiliary power supply interface; The power supply interface is connected to the auxiliary power supply interface of the second processor via an independent power cable to supply power to the second processor. The auxiliary power supply interface is located on the second processor.

10. The electronic device according to claim 8, characterized in that, The third board is also provided with a sideband signal connector. The first end of the sideband signal connector is used to receive a sideband signal, and the second end of the sideband signal connector is connected to the processor connector through a sideband signal cable. The sideband signal is transmitted to the second processor through the processor connector. The sideband signal includes at least one of a reset signal, a management bus signal, and a reference clock signal.

11. The electronic device according to claim 4, characterized in that, The first board also includes a first controller and a second controller. The first controller is connected to the first processor and the second processor respectively, and is used to collect the signal port rate of the first processor and the signal port rate of the second processor, and compare their magnitudes; The second controller is connected to the first controller and the first processor respectively, and is used to control the signal between the first signal port and the second signal port to be transmitted through the first link or the second link according to the comparison result of the first controller.

12. The electronic device according to claim 11, characterized in that, The third board is also equipped with a third controller, which is connected to the first controller and the rate converter respectively. It is used to receive the control signals of the first controller and to forward or convert the sideband signals.

13. The electronic device according to claim 2, characterized in that, The first cable is the first direct-connect accessory cable; The first end of the first direct-connect accessory cable is connected to the first connector, and the second end of the first direct-connect accessory cable is connected to the processor connector. The first direct-connect accessory cable integrates a signal line, a sideband signal line, and a slot power supply line. The signal line is used to transmit signals between the first signal port and the second signal port, the sideband signal line is used to transmit sideband signals, and the slot power supply line is used to transmit slot power.

14. The electronic device according to claim 3, characterized in that, The third cable is the second direct-connect accessory cable; The first end of the second direct-connect accessory cable is connected to the third connector, and the second end of the second direct-connect accessory cable is connected to the processor connector. The second direct-connect accessory cable integrates a signal line, a sideband signal line, and a slot power supply line. The signal line is used to transmit the signal output by the rate converter, the sideband signal line is used to transmit the sideband signal after being forwarded or level-converted by the third controller, and the slot power supply line is used to transmit slot power supply.

15. The electronic device according to claim 6, characterized in that, The processor connector includes: The connector body has a first end for connecting to a first cable or a third cable, and a second end for connecting to a second signal port. The connector body also integrates a sideband signal terminal, which is used to transmit at least one of a reset signal, a management bus signal, and a reference clock signal.

16. The electronic device according to claim 1, characterized in that, The first signal port has a first number of channels, the second signal port has a second number of channels, and the rate converter is used to convert a signal with the first number of channels into a signal with the second number of channels, wherein the second number of channels is greater than the first number of channels.

17. A method for controlling an electronic device, based on the electronic device as described in any one of claims 1-16, characterized in that, The electronic device control method includes: Obtain the comparison result between the first transmission rate and the second transmission rate; Based on the comparison result, the signal between the first signal port and the second signal port is controlled to be transmitted via the first link or the second link; Wherein, the first transmission rate is the signal transmission rate of the first signal port provided by the first processor, and the second transmission rate is the signal transmission rate of the second signal port provided by the second processor.

18. The electronic device control method according to claim 17, characterized in that, The step of controlling the transmission of the signal between the first signal port and the second signal port via the first link or the second link based on the comparison result includes: In response to the first transmission rate being less than or equal to the second transmission rate, the signal between the first signal port and the second signal port is controlled to be transmitted via the first link; In response to the first transmission rate being greater than the second transmission rate, the signal between the first signal port and the second signal port is controlled to be transmitted via the second link.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the electronic device control method as described in any one of claims 17 to 18.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the electronic device control method as described in any one of claims 17 to 18.

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