Fully autonomous pxi e measurement and control device and method based on loongson 2k3000

Abstract

The application discloses a full-autonomous PXIe measurement and control device and method based on a Loongson 2K3000, and relates to the technical field of electronic measurement and automatic control. The device adopts a three-layer stacking architecture of a core board, a carrier board, an interface board and a backboard, and the backboard is provided with a system slot, a power supply slot and a plurality of peripheral slots. The core board is loaded with a Loongson processor, and each slot is connected through the multi-Bank architecture of a domestic PCIe exchange chip. The carrier board FPGA receives processor instructions, generates PXIe_SYNC100 and PXI_CLK10 signal broadcast distribution, and the backboard is provided with a same-source clock Buffer chip based on a 10MHz temperature compensation crystal oscillator to provide a reference clock. The application avoids supply chain risks through full-stack domestic substitution, realizes nanosecond-level synchronization through FPGA and same-source clock design, guarantees the stability of multi-module parallel interaction in combination with multi-Bank shunting and time-sharing reset logic, and is suitable for wide-temperature working conditions and mainstream PXIe boards.

Description

Technical Field

[0001] This invention relates to the field of electronic measurement and automatic control technology, specifically to a fully autonomous PXIe measurement and control device and method based on Loongson 2K3000. Background Technology

[0002] With the development of defense technology and industrial automation, the requirements for data processing capabilities, transmission bandwidth, and system reliability of measurement and control systems are increasing. As the core carrier for equipment information testing, military simulation, and data acquisition, measurement and control platforms are widely used in military, power, energy, and industrial automation fields. The PXIe bus, with its advantages of high bandwidth, low latency, modular expansion, and high-precision synchronous collaboration among multiple devices, has become the mainstream bus in the military testing field. However, most current PXIe measurement and control equipment is based on x86 architecture processors such as Intel / AMD, and the underlying hardware and software ecosystem is dependent on foreign manufacturers. Existing systems often rely on complex external independent clock modules when handling multi-channel synchronous acquisition, increasing system complexity and cost.

[0003] Currently, high-end measurement and control platforms mainly purchase NI or B&K products, using foreign main control chips and bus switching chips. Core components and underlying ecosystems are monopolized by foreign countries, posing security risks and supply risks, and failing to meet the requirements for localization and security applications in key fields such as military industry.

[0004] Existing domestically produced measurement and control equipment is mostly a single-function modular design. Its bus bandwidth, interface configuration, and clock synchronization accuracy cannot meet the needs of military lightweight, multi-device collaboration, and high-speed measurement and control scenarios. In addition, it lacks complete software and hardware solutions adapted to domestic operating systems. The upper computer measurement and control software has poor adaptability and cannot be compatible with mainstream PXIe functional modules on the market, and its scalability is limited. In other words, the system adaptability and scenario compatibility are insufficient. Summary of the Invention

[0005] This invention provides a fully independent PXIe measurement and control device based on Loongson 2K3000, which solves the technical problems of poor consistency of multi-channel data acquisition and low system reliability caused by the core components of existing PXIe measurement and control devices being subject to foreign control and insufficient clock synchronization accuracy.

[0006] This invention is achieved through the following technical solution:

[0007] In the first aspect, this application provides a fully autonomous PXIe measurement and control device based on Loongson 2K3000, including a core board, a carrier board, an interface board and a PXIe backplane, wherein the PXIe backplane is provided with one system slot, one power supply slot and multiple peripheral function slots.

[0008] The core board is inserted into the system slot and is equipped with a processor based on the LoongArch architecture. The processor is connected to a domestic PCIe switching chip through a PCIe interface. The PCIe switching chip is connected to each peripheral function slot through the multi-bank splitting architecture of the PXIe backplane.

[0009] The carrier board is equipped with an FPGA, which is connected to the processor through a PCIe interface and a low-speed control interface, and is connected to each peripheral function slot through backplane wiring; the FPGA is configured to receive processor instructions, generate a PXIe_SYNC100 synchronization signal and a PXI_CLK10 clock, and broadcast them to each peripheral function slot.

[0010] The PXIe backplane is equipped with a common clock buffer chip. The input terminal of the common clock buffer chip receives a reference clock signal, and the output terminal provides a reference clock to the PCIe controller of the processor and each peripheral function slot, so that the reference clocks of the processor and each peripheral function slot are from the same source.

[0011] The interface board provides the external physical interfaces for the core board and the carrier board.

[0012] Further optimizations include: the processor is a Loongson LS2K3000 octa-core processor with a maximum clock speed of 2.2GHz; the core board also integrates 16GB of DDR4 memory and a 1TB solid-state drive; the device is compatible with Loongnix or Kylin operating systems and can operate stably within a wide temperature range of -40℃ to +70℃.

[0013] A further optimization scheme is as follows: the FPGA is directly connected to the processor through a PCIe 3.0 x1 interface and performs low-speed control communication through an LPC interface; after the FPGA is configured to receive instructions from the processor, it broadcasts the PXIe_SYNC100 synchronization signal and the PXI_CLK10 clock to all peripheral function slots through backplane wiring, thereby realizing nanosecond-level synchronous triggering of each peripheral function slot.

[0014] A further optimization scheme is as follows: the PCIe switching chip is an SM8748EIP chip; the multi-bank splitting architecture connects the PCIe 3.0 x4 uplink to the PCIe switching chip, and the PCIe switching chip splits multiple downlink ports to connect to each peripheral function slot, forming a star topology; the PCIe switching chip is configured to support parallel high-speed data interaction and plug-and-play expansion of multi-slot PXIe function modules.

[0015] A further optimization scheme is that the same-source clock buffer chip outputs multiple clock signals, one of which is directly connected to the processor's PCIe controller as a reference clock, and the other clock signals are distributed to each peripheral function slot to ensure that the reference clock of all peripheral function slots is the same as the processor's reference clock.

[0016] It also includes a power supply module, which is configured to convert the external 24V power supply into an internal operating voltage of 12V, 5V and 3.3V; the FPGA is configured to receive a reset release signal sent by the processor through the GPIO or LPC interface after the processor has started and stabilized, and then control the reset and configuration timing of each peripheral function slot in a time-division multiplexing manner.

[0017] A further optimization solution is that the interface board integrates an HDMI video interface, a gigabit Ethernet interface, a USB interface, a CAN bus interface, and an RS series serial port to cover the communication and display needs of military and industrial measurement and control.

[0018] Secondly, this application provides a fully autonomous PXIe measurement and control method based on Loongson 2K3000, including the following steps:

[0019] The reference clock signal is received through the same-source clock buffer chip on the PXIe backplane, and a reference clock is provided to the processor's PCIe controller and each peripheral function slot, so that the reference clock of the processor and each peripheral function slot are from the same source.

[0020] The processor interacts with various peripheral function slots at high speed through the multi-bank routing architecture of the PCIe switching chip.

[0021] The FPGA receives instructions from the processor, generates a PXIe_SYNC100 synchronization signal and a PXI_CLK10 clock, and broadcasts them to each peripheral function slot through backplane wiring to achieve nanosecond-level synchronous triggering of multiple peripheral function slots.

[0022] The measurement and control data is collected through the various peripheral function slots, transmitted to the processor via the PCIe switching chip for processing, and the measurement and control results are output to the outside world through the interface board.

[0023] A further optimized solution involves the following steps for the processor to perform high-speed data interaction with each peripheral function slot via the multi-bank distribution architecture of the PCIe switching chip:

[0024] The processor is connected to the PCIe switch chip via a PCIe 3.0 x4 uplink;

[0025] The PCIe switching chip generates multiple downlink ports that are connected to various peripheral function slots, forming a star topology.

[0026] The PCIe switching chip supports parallel high-speed data interaction and plug-and-play expansion of multi-slot PXIe functional modules.

[0027] A further optimization involves the following step: In the process where the same-source clock buffer chip provides a reference clock to the processor's PCIe controller and various peripheral function slots:

[0028] The same-source clock buffer chip outputs multiple clock signals, one of which goes directly to the processor's PCIe controller, while the other clock signals are distributed to the respective peripheral function slots.

[0029] By using a shared clock buffer chip, the reference clock of each peripheral function slot is ensured to be from the same source and at the same frequency as the processor's reference clock, thereby reducing clock deviation in multi-channel data acquisition.

[0030] A further optimization scheme includes power timing control steps:

[0031] Converts the external 24V power supply input to 12V, 5V and 3.3V internal operating voltage;

[0032] After power-on, the processor starts up first via its internal clock. Once the processor system is stable, it sends a reset release signal to the FPGA via GPIO or LPC interface.

[0033] After receiving the reset release signal, the FPGA controls the reset and configuration timing of each peripheral function slot in a time-division manner to avoid power-on shock and bus preemption.

[0034] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0035] By replacing imported core components with domestically produced ones across the entire stack, the system eliminates supply chain disruptions and information security risks at their source. It utilizes a shared clock buffer chip to ensure that the processor and all peripheral functional slots share the same reference clock. Combined with the PXIe_SYNC100 synchronization signal generated by the FPGA and the PXI_CLK10 clock broadcast distribution, nanosecond-level synchronous triggering is achieved, significantly improving the consistency of multi-channel data acquisition. A PCIe switching link based on a multi-bank split architecture ensures the stability and low latency of parallel high-speed data interaction between multi-slot functional modules. The processor-controlled time-division reset logic of the FPGA ensures system startup reliability. Simultaneously, it is compatible with domestic operating systems and mainstream domestic and imported PXIe functional boards, adapting to the needs of military and industrial measurement and control scenarios under wide-temperature and complex operating conditions. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0037] In the attached diagram:

[0038] Figure 1 A schematic diagram of the front panel interface of the fully autonomous PXIe measurement and control device based on Loongson 2K3000 provided for the embodiments of this application;

[0039] Figure 2 This is a schematic diagram of the CPU core board and interface board provided in an embodiment of this application;

[0040] Figure 3 Clock distribution diagram of CPU core board, carrier board, and backplane provided for embodiments of this application;

[0041] Figure 4 This is a schematic diagram of the CPU carrier board circuit connection provided in an embodiment of this application;

[0042] Figure 5 This is a schematic diagram of the system business function flow provided in the embodiments of this application;

[0043] Figure 6 This is a schematic diagram of the overall power supply of the power module provided in the embodiments of this application;

[0044] Figure 7 This is a schematic diagram of the backplane power supply circuit provided in an embodiment of this application;

[0045] Figure 8 This is a schematic diagram of the carrier board power supply circuit provided in an embodiment of this application;

[0046] Figure 9 A flowchart of a fully autonomous PXIe measurement and control method based on Loongson 2K3000 provided for embodiments of this application. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0048] First, some of the technical terms used in this application will be explained to help those skilled in the art understand this application.

[0049] PXIe: PCI eXtensions for Instrumentation, PCI extensions for instrumentation systems;

[0050] LoongArch: Loongson Architecture;

[0051] PCIe: Peripheral Component Interconnect Express, a high-speed peripheral component interconnect extension;

[0052] FPGA: Field Programmable Gate Array;

[0053] LPC: Low Pin Count;

[0054] DDR4: Double Data Rate 4, fourth-generation double data rate synchronous dynamic random access memory;

[0055] GPIO: General Purpose Input / Output;

[0056] ESD: Electro-Static Discharge;

[0057] USB: Universal Serial Bus;

[0058] HDMI: High Definition Multimedia Interface;

[0059] CAN: Controller Area Network;

[0060] SM8748EIP is a PCIe switching chip model;

[0061] SMQ7K325T: SMQ7K325T Field Programmable Gate Array;

[0062] Loongnix: Loongnix Operating System, the Loongson open-source operating system;

[0063] PXI_CLK10: PXIe 10 MHz Clock, PXIe 10MHz clock signal;

[0064] PXIe_SYNC100: PXIe 100 MHz Synchronization Signal.

[0065] In one embodiment, the fully autonomous PXIe measurement and control device based on Loongson 2K3000 adopts a three-layer stacked modular architecture of core board, carrier board, interface board and PXIe backplane. This ensures high integration, small size and lightweight design of the entire device while achieving clear functional partitioning and independent modular operation and maintenance, adapting to the needs of military miniaturized equipment and rapid repair and maintenance. For example... Figure 1 As shown, the interface board integrates various external physical interfaces on the front panel of the device, facilitating on-site wiring and maintenance. The PXIe backplane is planned with one system slot, one power slot, and multiple peripheral function slots, specifically five peripheral function slots. The maximum power supported by the whole machine is 720W, and the core board is vertically inserted into the system slot.

[0066] Figure 2 (a) is a schematic diagram of the CPU core board provided in an embodiment of this application;

[0067] Figure 2 (b) is a schematic diagram of the interface board provided in an embodiment of this application;

[0068] like Figure 2 As shown, the core board is equipped with a processor based on the LoongArch proprietary instruction set architecture. This processor connects to a domestically produced PCIe switching chip (such as the SM8748EIP) via a PCIe interface, and utilizes a multi-bank distribution architecture deployed in the backplane to achieve communication connections with various peripheral function slots. Figure 4 As shown, the carrier board integrates a domestic FPGA (model SMQ7K325T). This FPGA not only establishes a high-speed data channel with the processor through the PCIe 3.0 x1 interface, but also receives control commands from the processor through low-speed control interfaces such as LPC, and uses dedicated wiring resources on the backplane to connect to each peripheral function slot.

[0069] Specifically, during operation, after receiving instructions from the processor, the FPGA generates a PXIe_SYNC100 synchronization signal and a PXI_CLK10 clock conforming to the PXIe specification. For example... Figure 3 As shown, the synchronous clock buffer chip on the backplane receives the reference clock signal from an external 10MHz temperature-compensated crystal oscillator. After processing, it provides reference clocks to the processor's PCIe controller and each peripheral function slot, ensuring that the reference clocks of the entire system are from the same source. The interface board is responsible for bringing out the physical interface between the core board and the carrier board to the device panel. In addition, through electromagnetic compatibility optimization design and wide-temperature component selection, the device is guaranteed to operate stably in complex electromagnetic environments and within a wide temperature range of -40℃ to +70℃.

[0070] This embodiment eliminates the security risks of relying on foreign core chips by replacing all domestically produced components in the entire stack. Relying on the same clock distribution and FPGA broadcast mechanism, a highly consistent system clock reference is constructed, providing underlying hardware support for high-precision measurement and control applications and effectively improving the level of independent control of equipment in classified and critical fields.

[0071] In one embodiment, the device uses a Loongson LS2K3000 octa-core processor as the core computing unit, with a maximum clock speed of 2.2GHz, capable of handling complex measurement and control algorithm calculations. For example... Figure 2 As shown, the core board integrates 16GB of DDR4 memory and a 1TB solid-state drive, used for high-speed data caching and large-capacity historical data storage, respectively. On the software side, the device is deeply adapted to the Loongnix or Kylin operating system, achieving full-link adaptation of the underlying drivers and hardware firmware. A PCIe device driver has been developed, supporting Plug and Play (PnP) functionality, and can automatically identify and configure PXIe functional cards from different manufacturers (such as NI or domestic brands), ensuring compatibility with mainstream NI series and domestic standardized PXIe functional cards. Furthermore, the system integrates domestic professional test and control software platforms such as Kaiyun Etest, enabling automated testing of the board's functional performance.

[0072] Taking into account the complexity of military and industrial environments, the overall design meets a wide operating temperature range of -40 degrees Celsius to 70 degrees Celsius. By selecting industrial-grade wide-temperature components and special heat dissipation design, the equipment can be stably started and operated in extremely cold or high-temperature chambers.

[0073] This integrated hardware and software design with a wide temperature range enhances the device's environmental adaptability in field deployments or enclosed cabinet environments, solves the problem that existing domestic platforms cannot operate stably in extreme temperature environments, and meets the stringent requirements of military field operations and industrial high-temperature workshops.

[0074] In one embodiment, communication between the FPGA and the processor uses a PCIe 3.0 x1 interface for high-speed data exchange, while low-speed control signaling such as reset and status queries is transmitted through an LPC interface, achieving physical separation between the data plane and the control plane. Figure 4 As shown, the FPGA's internal logic is configured to precisely generate the PXIe_SYNC100 synchronization signal and the PXI_CLK10 clock after receiving the processor's synchronization trigger instruction.

[0075] Furthermore, these two signals are broadcast to all peripheral function slots via a specially laid differential clock line on the backplane. Since the signals originate from the same FPGA and the traces are of equal length, the phase difference of the trigger signals received by each peripheral function slot is extremely small, enabling nanosecond-level synchronous triggering accuracy.

[0076] This design abandons the traditional solution of external independent clock module and uses the flexibility of FPGA to achieve high-precision intra-system synchronization, effectively ensuring the consistency and real-time performance of multi-channel data acquisition, and greatly reducing the synchronization error when multiple devices work together. It is particularly suitable for phased array radar and multi-sensor fusion scenarios with strict time consistency requirements.

[0077] In one embodiment, the device uses the SM8748EIP chip as a domestically produced PCIe switching chip. For example... Figure 2 As shown, the chip manages backplane bus resources through a multi-bank split architecture. In practice, the processor's PCIe 3.0 x4 uplink is connected to the switching chip, and then the chip splits multiple downlink ports to connect to various peripheral function slots, forming a star topology.

[0078] Preferably, the device enumeration logic built into the switching chip supports hot-plug detection. When an operator inserts a PXIe functional module, the system can automatically recognize and load the driver, enabling plug-and-play functionality. The multi-bank design also allows for the isolation and reservation of bandwidth for different slots, effectively solving the contention problem caused by shared bandwidth in traditional buses. This ensures that high-priority modules can obtain stable bandwidth resources, avoids bus contention, and guarantees the stability of data transmission.

[0079] This enables the device to support parallel high-speed data interaction of multi-slot functional modules, solving the technical problems of insufficient bandwidth of traditional buses and data packet loss when multiple modules work together, improving the system's scalability and real-time response capability, and meeting the stringent requirements of complex measurement and control systems for real-time transmission of large amounts of data.

[0080] In one embodiment, the output of the same-source clock buffer chip is split into multiple low-jitter clock signals. One of these signals is directly connected to the processor's PCIe controller, while the others are distributed to various peripheral function slots via backplane traces. This ensures that the reference clock for all PCIe links originates from the same crystal oscillator, fundamentally eliminating clock drift. Figure 6 As shown, the device also integrates a power module, responsible for converting the external 24V power supply into internal operating voltages of 12V, 5V, and 3.3V. For example... Figure 7 As shown, the power module provides stable operating voltages for each component on the backplane and carrier board.

[0081] Specifically, to address the inrush current and bus contention issues arising from simultaneous power-up of multiple modules, the device employs a time-sharing reset mechanism led by the FPGA. Upon power-up, the processor starts first and enters a stable state, then sends a reset release signal to the FPGA via GPIO or LPC interface. Upon receiving this signal, the FPGA releases the reset signals of each peripheral function slot sequentially at preset time intervals.

[0082] This staggered startup strategy effectively suppresses inrush current, prevents the simultaneous startup of multiple high-power modules from impacting the power bus, ensures a smooth and orderly system startup process, significantly improves the system's startup reliability in complex power supply environments, and reduces the risk of failure caused by concurrent startup of multiple modules.

[0083] In one embodiment, the interface board, acting as a hub for internal and external connections, integrates a rich set of communication and display interfaces. For example... Figure 1 As shown, the panel layout includes an HDMI video interface (supporting 4K@60fps) for connecting to a local monitor for status display; a Gigabit Ethernet interface for connecting to a local area network for remote data transmission; two USB 2.0 ports, two USB 3.0 ports, and two USB 3.1 ports for connecting keyboards and mice, external storage, and high-speed data transmission; as well as a CAN bus interface and RS series serial port commonly used in industrial settings.

[0084] Furthermore, ESD protection and signal isolation measures have been incorporated into the interface circuit design, enhancing the port's survivability in environments with strong electromagnetic interference.

[0085] This diversified interface design aims to cover various application scenarios in military and industrial measurement and control. Whether connecting to modern networked equipment or traditional serial communication sensors, no additional adapters are required. This effectively solves the technical shortcomings of existing domestic measurement and control platforms, such as poor interface compatibility and difficulty in adapting to complex field environments, and improves the device's scenario adaptability and deployment flexibility.

[0086] Secondly, based on the aforementioned device architecture, this application also provides a fully autonomous PXIe measurement and control method based on Loongson 2K3000, such as... Figure 9 As shown, this method is executed according to a predetermined process, specifically including the following steps:

[0087] Step S1: Receive the reference clock signal from the external 10MHz temperature-compensated crystal oscillator through the same-source clock buffer chip on the PXIe backplane, and provide reference clocks to the processor's PCIe controller and each peripheral function slot, so that the reference clocks of the processor and each peripheral function slot are from the same source, and establish a unified clock reference for the entire system.

[0088] Specifically, during the initial power-up phase, the same-source clock buffer chip first locks the reference clock signal. After internal phase-locked loop frequency multiplication and buffering, it outputs multiple low-jitter clock copies with consistent phase. One of these copies goes directly to the processor's PCIe controller, while the others are distributed to the peripheral function slots through strictly equal-length differential traces on the backplane, ensuring that the reference clocks of each node are from the same source and at the same frequency, thus eliminating clock drift.

[0089] Step S2: The processor uses the multi-bank distribution architecture of the PCIe switching chip to perform high-speed data interaction with each peripheral function slot, and completes the initial configuration of system bus resources.

[0090] Specifically, the processor starts and initializes the domestically produced PCIe switching chip (such as SM8748EIP), establishing communication links with each peripheral function slot. The switching chip isolates and reserves bus bandwidth through a multi-bank architecture, supports parallel data interaction and plug-and-play expansion of multi-slot PXIe function modules, and ensures that high-priority modules obtain stable bandwidth resources.

[0091] Step S3: The FPGA receives the instruction from the processor and generates a PXIe_SYNC100 synchronization signal and a PXI_CLK10 clock in response to the instruction. These signals are then broadcast and distributed to each peripheral function slot via backplane wiring to achieve nanosecond-level synchronous triggering of multiple peripheral function slots.

[0092] Specifically, before the measurement and control task begins, the processor sends a synchronization trigger command to the carrier FPGA via the PCIe 3.0 x1 interface and the LPC low-speed control interface. The FPGA's internal logic responds to this command, accurately generating a synchronization signal conforming to the PXIe specification and a 100MHz differential clock, and broadcasting it to all peripheral function slots via dedicated backplane wiring resources, triggering each slot to perform phase-aligned data acquisition.

[0093] Step S4: Collect measurement and control data through each peripheral function slot, transmit it to the processor for processing via the PCIe switching chip, and output the measurement and control results to the outside world through the interface board.

[0094] Specifically, after receiving the synchronization trigger signal, each peripheral function slot performs multi-channel data acquisition. The acquired raw data is aggregated to the processor via the PCIe switching chip. After the processor completes data parsing, filtering algorithm calculation, and protocol encapsulation, the processed measurement and control results are output to the display terminal, host computer, or lower-level control system through physical interfaces such as Gigabit Ethernet, HDMI, or serial port integrated on the interface board, thus completing the full-link closed-loop measurement and control process.

[0095] This method achieves closed-loop management of the entire link from clock synchronization to data output through standardized process control, effectively ensuring the timeliness of measurement and control data and the consistency of multi-channel data, improving the system response speed in complex measurement and control scenarios, and providing reliable process assurance for high-precision measurement and control tasks.

[0096] In one embodiment, the process of high-speed data interaction by the processor through the multi-bank off-grid architecture of the PCIe switching chip is as follows. Figure 2As shown, at the physical layer, the processor is connected to the uplink port of the SM8748EIP switching chip via a PCIe 3.0 x4 link, and the downlink port of the switching chip is connected to each peripheral function slot via backplane wiring, forming a star topology.

[0097] The switching chip is responsible for maintaining the communication status of each port and supports parallel data interaction between multi-slot PXIe functional modules. When a new functional module is inserted, the switching chip detects that the link training is complete, triggers an interrupt notification processor, and the system automatically enumerates the device and allocates resources, achieving plug-and-play functionality. For scenarios with concurrent transmission of multiple modules, the arbitration mechanism inside the switching chip ensures that high-priority data is passed first.

[0098] This method breaks through the limitations of traditional bus shared bandwidth, realizes high-speed data interaction in parallel by multiple modules, meets the stringent requirements of high-precision measurement and control for real-time transmission of large amounts of data, and at the same time, the plug-and-play feature simplifies the system deployment and function expansion process and improves operation and maintenance efficiency.

[0099] In one embodiment, the operation of the same-source clock buffer chip to provide a reference clock is crucial to ensuring system synchronization accuracy. For example... Figure 3 As shown, the chip's input receives a highly stable 10MHz temperature-compensated crystal oscillator reference clock signal. After internal phase-locked loop frequency multiplication and buffering, it outputs multiple clock replicas with consistent phase. One low-jitter clock signal is directly supplied to the processor's PCIe controller, while the other signals are sent to their respective peripheral function slots via strictly equal-length differential traces on the backplane.

[0100] Specifically, since all clock signals originate from the same source and have the same transmission delay, the reference clocks of the processor and each peripheral function slot are from the same source and at the same frequency.

[0101] This design significantly reduces clock skew during multi-channel data acquisition, avoiding data splicing errors or phase ambiguity caused by clock asynchrony. It is particularly suitable for multi-sensor fusion applications that require strict time alignment, improving the reliability of measurement and control data and the accuracy of fusion analysis, and providing accurate data support for scientific decision-making.

[0102] In one embodiment, power timing control steps are implemented throughout the entire system power-on startup process. For example... Figure 6 As shown, firstly, the power module converts the incoming 24V DC power supply into the 12V, 5V, and 3.3V voltage rails required by the system. Upon power-up, the processor starts up first using its internal clock source, performing self-tests and loading the operating system.

[0103] Furthermore, after the processor system is fully stable and the measurement and control program is running, a reset release signal is sent to the FPGA via the GPIO or LPC interface. Figure 7 and Figure 8 As shown, after receiving the signal, the timing control logic embedded inside the FPGA starts to perform a time-division reset operation, sequentially raising the reset pin level of each peripheral function slot according to the preset time window.

[0104] This staggered startup strategy effectively suppresses surge current, prevents the impact on the power bus caused by the simultaneous startup of multiple high-power modules, and avoids deadlock caused by multiple modules competing for bus control at the same time. It ensures the robustness of system startup, solves the problem of high startup failure rate of existing equipment in complex power supply environments, and improves the survivability of equipment when deployed in the field.

[0105] Thirdly, embodiments of this application also provide a readable storage medium.

[0106] The present application has a PXIe bus measurement and control program stored on a readable storage medium, wherein when the PXIe bus measurement and control program is executed by a processor, it implements the steps of the PXIe bus measurement and control method described above.

[0107] The method implemented when the PXIe bus measurement and control program is executed can be referred to in the various embodiments of the PXIe bus measurement and control method of this application, and will not be repeated here.

[0108] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0109] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fully autonomous PXIe measurement and control device based on Loongson 2K3000, characterized in that, It includes a core board, a carrier board, an interface board, and a PXIe backplane. The PXIe backplane has one system slot, one power slot, and multiple peripheral function slots. The core board is inserted into the system slot and is equipped with a processor based on the LoongArch architecture. The processor is connected to a domestic PCIe switching chip through a PCIe interface. The PCIe switching chip is connected to each peripheral function slot through the multi-bank splitting architecture of the PXIe backplane. The carrier board is equipped with an FPGA, which is connected to the processor through a PCIe interface and a low-speed control interface, and is connected to each peripheral function slot through backplane wiring; the FPGA is configured to receive processor instructions, generate a PXIe_SYNC100 synchronization signal and a PXI_CLK10 clock, and broadcast them to each peripheral function slot. The PXIe backplane is equipped with a common clock buffer chip. The input terminal of the common clock buffer chip receives a reference clock signal, and the output terminal provides a reference clock to the PCIe controller of the processor and each peripheral function slot, so that the reference clocks of the processor and each peripheral function slot are from the same source. The interface board provides the external physical interfaces for the core board and the carrier board.

2. The fully autonomous PXIe measurement and control device based on Loongson 2K3000 according to claim 1, characterized in that, The processor is a Loongson LS2K3000 octa-core processor; the core board also integrates memory and a solid-state drive; The device is compatible with Loongnix or Kylin operating systems.

3. The fully autonomous PXIe measurement and control device based on Loongson 2K3000 according to claim 1, characterized in that, The FPGA is directly connected to the processor via a PCIe 3.0 x1 interface and performs low-speed control communication via an LPC interface. After the FPGA is configured to receive instructions from the processor, it broadcasts the PXIe_SYNC100 synchronization signal and the PXI_CLK10 clock to all peripheral function slots through backplane wiring, thereby achieving nanosecond-level synchronous triggering of each peripheral function slot.

4. The fully autonomous PXIe measurement and control device based on Loongson 2K3000 according to claim 1, characterized in that, The PCIe switching chip is an SM8748EIP chip; the multi-bank splitting architecture connects the PCIe 3.0 x4 uplink to the PCIe switching chip, and the PCIe switching chip splits multiple downlink ports to connect to each peripheral function slot, forming a star topology; the PCIe switching chip is configured to support parallel high-speed data interaction and plug-and-play expansion of multi-slot PXIe function modules.

5. The fully autonomous PXIe measurement and control device based on Loongson 2K3000 according to claim 1, characterized in that, The same-source clock buffer chip outputs multiple clock signals, one of which is directly connected to the processor's PCIe controller as a reference clock, while the other clock signals are distributed to each peripheral function slot to ensure that the reference clock of all peripheral function slots is of the same source and frequency as the processor's reference clock. It also includes a power supply module, which is configured to convert the external 24V power supply into an internal operating voltage of 12V, 5V and 3.3V; the FPGA is configured to receive a reset release signal sent by the processor through the GPIO or LPC interface after the processor has started and stabilized, and then control the reset and configuration timing of each peripheral function slot in a time-division multiplexing manner.

6. The fully autonomous PXIe measurement and control device based on Loongson 2K3000 according to claim 1, characterized in that, The interface board integrates an HDMI video interface, a gigabit Ethernet interface, a USB interface, a CAN bus interface, and an RS series serial port to cover the communication and display needs of military and industrial measurement and control.

7. A fully autonomous PXIe measurement and control method based on Loongson 2K3000, characterized in that, Includes the following steps: The reference clock signal is received through the same-source clock buffer chip on the PXIe backplane, and a reference clock is provided to the processor's PCIe controller and each peripheral function slot, so that the reference clock of the processor and each peripheral function slot are from the same source. The processor interacts with various peripheral function slots at high speed through the multi-bank routing architecture of the PCIe switching chip. The FPGA receives instructions from the processor, generates a PXIe_SYNC100 synchronization signal and a PXI_CLK10 clock, and broadcasts them to each peripheral function slot through backplane wiring to achieve nanosecond-level synchronous triggering of multiple peripheral function slots. The measurement and control data is collected through the various peripheral function slots, transmitted to the processor via the PCIe switching chip for processing, and the measurement and control results are output to the outside world through the interface board.

8. The fully autonomous PXIe measurement and control method based on Loongson 2K3000 according to claim 7, characterized in that, The steps for the processor to perform high-speed data interaction with each peripheral function slot through the multi-bank architecture of the PCIe switching chip specifically include: The processor is connected to the PCIe switch chip via a PCIe 3.0 x4 uplink; The PCIe switching chip generates multiple downlink ports that are connected to various peripheral function slots, forming a star topology. The PCIe switching chip supports parallel high-speed data interaction and plug-and-play expansion of multi-slot PXIe functional modules.

9. The fully autonomous PXIe measurement and control method based on Loongson 2K3000 according to claim 7, characterized in that, In the step where the same-source clock buffer chip provides a reference clock to the processor's PCIe controller and various peripheral function slots: The same-source clock buffer chip outputs multiple clock signals, one of which goes directly to the processor's PCIe controller, while the other clock signals are distributed to the respective peripheral function slots. By using a shared clock buffer chip, the reference clock of each peripheral function slot is ensured to be from the same source and at the same frequency as the processor's reference clock, thereby reducing clock deviation in multi-channel data acquisition.

10. The fully autonomous PXIe measurement and control method based on Loongson 2K3000 according to claim 7, characterized in that, It also includes power supply timing control steps: Converts the external 24V power supply input to 12V, 5V and 3.3V internal operating voltage; After power-on, the processor starts up first via its internal clock. Once the processor system is stable, it sends a reset release signal to the FPGA via GPIO or LPC interface. After receiving the reset release signal, the FPGA controls the reset and configuration timing of each peripheral function slot in a time-division manner to avoid power-on shock and bus preemption.

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