A hot plug card control method, device and system of a PCIe device

Abstract

The embodiment of the present application relates to a PCIe device hot plug card control method, device and system, wherein the method comprises: receiving card insertion information or card removal information sent by a hot plug card; when receiving the card insertion information, performing power-on operation on a first target slot according to the card insertion information; receiving a power supply signal of the first target slot, and when the power supply signal is valid, performing logical AND operation on a platform reset signal, a soft reset signal and the power supply signal to generate a card reset signal and send the card reset signal to the PCIe device; when receiving the card removal information, performing power-off operation on a second target slot according to the card removal information; detecting slot in-place state information of the PCIe device; judging whether the card in the second target slot is removed according to the slot in-place state information; if yes, generating a first interrupt signal to an operating system to make the operating system update the in-place state information of the second target slot. The present application can realize the safety, flexibility and low power consumption of the hot plug process.

Description

Technical Field

[0001] This invention relates to the field of equipment control, and more particularly to a method for controlling hot-swappable cards in a PCIe device, a device for controlling hot-swappable cards in a PCIe device, and a control system for hot-swappable cards in a PCIe device. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard widely used for connecting devices such as GPU cards, memory controllers, and network cards. Hot-swapping technology, a core function of PCIe devices, allows devices to be inserted and removed without shutting down the system, greatly improving system maintenance efficiency and availability.

[0003] However, existing PCIe hot-plug control schemes all use unified hardware implementation and software interface to ensure consistent and reliable PCIe hot-plug behavior across servers from different vendors. However, this method suffers from complex hardware design, requiring additional external buttons, indicator lights, and other components, leading to high development difficulty. Summary of the Invention

[0004] Therefore, in order to overcome at least some of the defects and deficiencies of the prior art, this invention proposes a hot-swappable card control method for PCIe devices to improve the flexibility of the hot-swappable process and reduce development complexity.

[0005] On one hand, an embodiment of the present invention proposes a hot-swappable card control method for a PCIe device, comprising: receiving card insertion information or card removal information sent by a hot-swappable card; when the card insertion information is received, powering on a first target slot according to the card insertion information; receiving a power signal from the first target slot, and when the power signal is valid, performing a logical AND operation between a platform reset signal, a soft reset signal, and the power signal to generate a card reset signal and sending it to the PCIe device, so that the PCIe device resets the first target slot according to the card reset signal; when the card removal information is received, powering off a second target slot according to the card removal information; detecting the slot presence status information of the PCIe device; determining whether the card in the second target slot has been removed according to the slot presence status information; if so, generating a first interrupt signal to the operating system, so that the operating system updates the presence status information of the second target slot.

[0006] In one embodiment of the present invention, the step of powering on the first target slot according to the card insertion information when the card insertion information is received includes: generating a second interrupt signal to the operating system according to the card insertion information when the card insertion information is received, so that the operating system performs an interrupt according to the second interrupt signal; determining the first target slot in the PCIe device according to the card insertion information; increasing the power enable signal of the first target slot to power on the first target slot; wherein, the first target slot is the slot in the PCIe device where a card needs to be inserted.

[0007] In one embodiment of the present invention, the step of powering off the second target slot according to the card removal information when the card removal information is received includes: generating a third interrupt signal to the operating system according to the card removal information when the card removal information is received, so that the operating system is interrupted according to the third interrupt signal; determining the second target slot of the PCIe device according to the card removal information; and lowering the power enable signal of the second target slot to power off the second target slot; wherein the second target slot is the slot of the PCIe device where the card needs to be removed.

[0008] In one embodiment of the present invention, before receiving the card insertion information sent by the hot-swappable card, the method further includes: reading the slot presence status information of all slots of the PCIe device; and lowering and powering off the power enable signal of the uninserted slot according to the slot presence status information.

[0009] In one embodiment of the present invention, the method further includes: real-time monitoring and reading the slot presence status information of the uninserted card slot; determining whether the slot presence status information has changed; if so, generating a fourth interrupt signal to the operating system.

[0010] On the other hand, the hot-swappable card control device for a PCIe device proposed in this embodiment of the invention is applicable to the hot-swappable card control method for a PCIe device as described above. The device includes: a platform controller hub, a control chip, and an auxiliary chip; the control chip is electrically connected to the platform controller hub; the control chip is electrically connected to the auxiliary chip, and the auxiliary chip is electrically connected to the slot of the PCIe device; wherein, the auxiliary chip is used to detect the slot presence status information of the PCIe device slot in real time and transmit it to the control chip; the platform controller hub is used to read the hot-swappable card insertion information when it receives the card insertion information. The control chip displays the slot's in-slot status information and triggers it to send a second interrupt signal to the operating system, while also sending power-on information for the first target slot. It monitors the power-good reset signal of the first target slot output by the auxiliary chip. When the power signal is detected as valid, it performs a logical AND operation on the platform reset signal, the soft reset signal output by the control chip, and the power-good reset signal to generate a card reset signal and reset the first target slot. It also detects the enumeration status of the PCIe device; when a newly inserted PCIe card is detected, it automatically loads the appropriate device driver to complete the card insertion process. The control chip is used to receive power-on information from the first target slot, and according to the power-on information, increase the power enable signal of the first target slot, and control the auxiliary chip to power on the first target slot; the platform controller hub is also used to receive card removal information of hot-swappable cards, and according to the card removal information, trigger the control chip to send a third interrupt signal to the operating system, so that the operating system stops data transmission to the target PCIe card corresponding to the card removal information of the PCIe device through the third interrupt signal, and uninstalls the device driver corresponding to the target PCIe card; at the same time, it sends a command to the control chip. The control chip receives power-off information from the second target slot and monitors the slot presence status information of the second target slot. When the slot presence status information of the second target slot is determined, the control chip is triggered to send a first interrupt signal to the operating system, so that the operating system updates the presence status of the second target slot according to the first interrupt signal and completes the card removal process. The control chip is also used to receive power-off information from the second target slot, and lower the power enable signal of the second target slot according to the power-off information, and control the auxiliary chip to power off the second target slot, so that the auxiliary chip stops outputting the power good reset signal of the second target slot.

[0011] In one embodiment of the present invention, the platform controller hub is further configured to, after the PCIe device is powered on, read the slot presence status information of all slots of the PCIe device, and obtain the slots without cards and slots with cards inserted based on the slot presence status information, lower the power enable signal of the slots without cards inserted and power off the power; monitor the slot presence status information received by the control chip in real time, and when the detected slot presence status information changes from low to high, confirm that a PCIe card is inserted in the slot, and trigger the control chip to send a fourth interrupt signal to the operating system.

[0012] In one embodiment of the present invention, the auxiliary chip includes a signal debouncing chip, a power monitoring chip, a slot protection chip, and a platform controller hub bus protection chip; wherein, the signal debouncing chip is used to debounc and stabilize the card removal information, card insertion information, slot presence status information, and slot presence status information received by the platform controller hub; the power monitoring chip is used to monitor the power information of the PCIe device slot and output power good reset information; the slot protection chip is used to protect the power supply of the PCIe device slot; and the platform controller hub bus protection chip is used to prevent the platform controller hub bus from locking up during hot-plugging.

[0013] Furthermore, the present invention provides a hot-swappable card control device for a PCIe device, applicable to the hot-swappable card control method for a PCIe device as described above. The device includes: a first receiving module for receiving card insertion information or card removal information sent by the hot-swappable card; a power-on module for powering on a first target slot according to the card insertion information when the card insertion information is received; and a card reset signal generation module for receiving a power signal from the first target slot, and when the power signal is valid, performing a logical AND operation between a platform reset signal, a soft reset signal, and the power signal to generate a card reset signal, which is then sent to the PCIe device to enable the hot-swappable card control method for the PCIe device. The PCIe device resets the first target slot according to the card reset signal; the power-off module is used to power off the second target slot according to the card removal information when the card removal information is received; the information detection module is used to detect the slot presence status information of the PCIe device; the first judgment module is used to determine whether the card in the second target slot has been removed according to the slot presence status information; the signal generation module is used to generate a first interrupt signal to the operating system when the first judgment module determines that the card in the second target slot has been removed according to the slot presence status information, so that the operating system updates the presence status information of the second target slot.

[0014] In another aspect, the present invention provides a hot-swappable card control system for a PCIe device, comprising: a memory and a processor connected to the memory, wherein the memory stores a computer program, and the processor executes a hot-swappable card control method for a PCIe device as described above when running the computer program.

[0015] As can be seen from the above, the above-mentioned technical features of the present invention can have the following beneficial effects: This application realizes safe hot-swapping of PCIe cards on PCIe devices by performing signal monitoring, interrupt response, power control, reset loading, and status update on different steps for card removal information and card insertion information, thereby improving the safety and reliability of hot-swapping. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating a hot-swappable card control method for a PCIe device according to the present invention.

[0018] Figure 2 for Figure 1 A flowchart illustrating the specific steps of step S12.

[0019] Figure 3 for Figure 1 A flowchart illustrating the specific steps of step S14.

[0020] Figure 4 for Figure 1 A flowchart illustrating the additional steps preceding step S11.

[0021] Figure 5 for Figure 4 A flowchart illustrating the steps following step S102.

[0022] Figure 6a This is a schematic diagram of the hot-swappable card insertion process according to a specific embodiment of the present invention.

[0023] Figure 6b This is a schematic diagram of the hot-swappable card removal process according to a specific embodiment of the present invention.

[0024] Figure 7a This is a schematic diagram of the hardware module of a hot-swappable card control device for a PCIe device according to the present invention.

[0025] Figure 7b This is a hardware architecture diagram related to a specific embodiment of the present invention.

[0026] Figure 8 This is a schematic diagram of a hot-swappable card control device for a PCIe device according to the present invention.

[0027] Figure 9 This is a schematic diagram of a hot-swappable card control system for a PCIe device according to the present invention.

[0028] Figure 10 This is a schematic diagram of a storage medium module according to the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] As the current mainstream high-speed expansion bus standard, the PCIe bus's hot-swappable function is one of the key technologies to ensure uninterrupted system operation. It allows users to insert and remove PCIe cards (such as network cards, GPU cards, storage controllers, etc.) without shutting down the system, greatly reducing downtime caused by equipment maintenance.

[0031] This application proposes a hot-swappable card control method for PCIe devices. The hot-swappable card control method for PCIe devices can be applied to electronic devices or PCIe devices that support the PCIe standard, such as servers and embedded devices. It can realize safe and efficient hot-swapping of PCIe cards during system operation, and is especially suitable for data centers and industrial control scenarios with high requirements for device availability and maintenance efficiency.

[0032] like Figure 1 As shown, this embodiment of the invention provides a method for controlling the hot-swappable cards of a PCIe device. The specific hardware architecture of this embodiment can be as follows: Figure 8 As shown, the following embodiments will be combined with Figures 7a-7b The architecture is explained in detail below. Specifically, an embodiment of the present invention provides a method for controlling the hot-swappable card of a PCIe device, which includes, for example, the following steps: S11. Receive card insertion information or card removal information sent by the hot-swappable card; S12. When card insertion information is received, power on the first target slot according to the card insertion information. S13. Receive the power signal of the first target slot. When the power signal is valid, perform a logical AND operation between the platform reset signal, the soft reset signal and the power signal to generate a card reset signal and send it to the PCIe device so that the PCIe device resets the first target slot according to the card reset signal. S14. When card removal information is received, power off the second target slot according to the card removal information. S15. Detect the slot presence status information of the PCIe device; S16. Determine whether the card in the second target slot has been removed based on the slot in-slot status information; S17. If so, a first interrupt signal is generated to the operating system so that the operating system updates the in-situ status information of the second target slot.

[0033] In step S11, the card insertion information and card removal information are determined by, for example... Figure 7a The auxiliary chip shown generates information in real time: Card insertion information is generated when the user inserts a PCIe card into the PCIe device slot, as the slot's presence status signal (e.g., PRSNT#) changes from low to high, and card insertion information is generated, which can be transmitted to the control chip, for example, via the I2C bus. Card removal information is generated when the user presses the hot-swap button (ATTN#) to remove the card, and is also transmitted to the control chip via the ATTN# signal. The card removal and card insertion information may include key parameters such as slot number and signal change timing to ensure the control chip can accurately locate the target slot.

[0034] In step S12, after receiving the card insertion information, the control chip can first verify the validity of the signal. For example, it can confirm that the PRSNT# signal has been continuously high for more than 10 milliseconds to avoid false triggering. Then, it can verify the signal validity through an interface (e.g., ...). Figure 7b The PCH SMBus interface shown sends a slot location request to the Platform Controller Hub (PCH). The PCH can, for example, use the system slot mapping table to determine the physical address of the first target slot; then the control chip outputs a high-level power enable signal (PWR_EN) to trigger the slot protection chip (such as... Figure 7b The TPS2321 chip shown closes its internal switch to provide dual 12V / 3.3V power to the first target slot. During the power supply process, it automatically performs current limiting (initial current ≤ 500mA) to prevent power-on surges from damaging the electronic components of the PCIe card.

[0035] In step S13, the power supply to the first target slot can be stabilized before proceeding with the subsequent reset operation. A power monitoring chip (such as...) Figure 7bThe DS1818 chip shown acquires the power supply voltage of the first target slot in real time. When it detects that the 12V voltage is stable within the range of 11.8V-12.2V and the 3.3V voltage is stable within the range of 3.2V-3.4V, and the duration is greater than, for example, 10 milliseconds, it outputs a high-level power good reset signal (e.g., ...). Figure 7b The PowerGD signal shown. After receiving the PowerGD signal from the power monitoring chip, the PCH retrieves the platform reset signal (such as...). Figure 7b The PLATFORM_RESET signal (high and active during system initialization) and the soft reset signal (Soft_RSTn, active low) output by the control chip are subjected to a three-signal AND operation via hardware logic gates. A low-level card reset signal is generated only when the PLATFORM_RESET signal, Soft_RSTn signal, and PowerGD signal are all active. The card reset signal is transmitted to the first target slot via the PCIe reset pin, triggering the PCIe card to execute the reset procedure, clearing residual device configurations, and preparing for subsequent enumeration.

[0036] In step S14, the second target slot is the PCIe slot where the user needs to remove the card. Before powering off the second target slot, it needs to be safely unloaded. Specifically, after the control chip receives the card removal information, it first sends an interrupt request to the PCH. The PCH triggers an operating system interrupt, and the operating system stops data transmission with the PCIe card in the second target slot (e.g., disabling disk read / write and disconnecting the network connection). Next, the operating system calls the driver unloading interface to safely remove the device driver corresponding to the PCIe card (e.g., closing the driver process and releasing memory mapping space). After ensuring no resource occupation, it sends an unloading completion signal back to the PCH. Finally, the PCH sends a power-off command to the control chip through the SMBus interface. The control chip sets the PWR_EN signal of the second target slot low, and the slot protection chip disconnects the power supply circuit, realizing the safety logic of unloading first and then powering off.

[0037] In step S15, the slot presence status information may be, for example, a PRSNT# signal or something similar. Figure 7b The PRSNT signal is shown. The control chip continuously collects the PRSNT# signal of all slots through the auxiliary chip to generate slot presence status information. The slot presence status information may include, for example, the current slot number, signal level, and duration. The control chip focuses on monitoring the PRSNT# signal change after power failure for the second target slot: if the user has removed the PCIe card, the PRSNT# signal may change from high level to low level; if it has not been removed, the signal remains high, and the control chip will send a "card not removed reminder" to the operating system through the PCH.

[0038] In step S16, it is determined whether the card in the second target slot has been removed. This can be done, for example, by judging the level change of the PRSNT# signal: if the PRSNT# signal of the second target slot changes from high level to low level, it is determined that the card has been removed; if the PRSNT# signal of the second target slot does not change, it is determined that the card has not been removed. The control chip can perform multiple re-monitoring, for example, re-detecting at 1 second intervals, until the results of 3 consecutive detections are consistent, to avoid misjudgment.

[0039] In step S17, the first interrupt signal may be, for example, a state update trigger signal. The control chip generates the first interrupt signal (e.g., Figure 7b The PCA9555 chip shown outputs a low level on its INT pin, which is transmitted to the operating system via the interrupt controller. After the operating system responds to the interrupt, it accesses the SMBus register of the PCH, reads the latest second target slot presence status information table, updates the status of the second target slot from inserted card to not inserted card, and synchronously updates the device list in the system device manager, thus completing the card removal process loop.

[0040] In embodiments of the present invention, the order of steps S12 and S14 can be determined by whether the received information is card insertion information or card removal information.

[0041] This invention receives card insertion or removal information for hot-swapping, then initiates a card insertion process based on the insertion information and a card removal process based on the removal information. This makes the card insertion and removal processes in hot-swapping logically clear and seamlessly connected. The entire process, from card insertion detection to driver loading and card removal detection to unloading, is fully automated without manual intervention, improving the user experience. It also implements a complete process logic for signal monitoring, interrupt response, power control, reset loading, and status updates for slots on PCIe devices, enabling safe hot-swapping of PCIe cards and improving the safety and reliability of hot-swapping.

[0042] Furthermore, such as Figure 2 and Figures 7a-7b As shown, step S12 specifically includes: S121. When the card insertion information is received, a second interrupt signal is generated to the operating system based on the card insertion information, so that the operating system performs an interrupt according to the second interrupt signal; S122. Determine the first target slot in the PCIe device based on the card insertion information; S123. Increase the power enable signal of the first target slot to power on the first target slot; wherein, the first target slot is the slot where the PCIe device needs to insert a card.

[0043] Specifically, in step S121, the second interrupt signal can, for example, be used to notify the operating system to prepare for card insertion. (Control chip, such as...) Figure 7b The PCA9555 chip shown generates a second interrupt signal (edge-triggered, high-level transition) via a GPIO pin after confirming the card insertion information is valid. This second interrupt signal is routed to the operating system kernel via the interrupt controller. Upon receiving the second interrupt signal, the operating system suspends non-critical processes (such as background services), calls the hot-plug handling thread, and prepares to receive subsequent slot positioning and driver loading instructions to ensure real-time performance.

[0044] In step S122, the card insertion information may include, for example, the physical slot number (e.g., "Slot_3") acquired by the auxiliary chip. The control chip sends this number to the PCH via the SMBus interface. The PCH determines the system address of the first target slot by querying a pre-stored mapping table of slot physical numbers and system addresses (e.g., querying to find that Slot_3 corresponds to PCIe Root Port 00:1C.0). Then, the PCH sends a test signal (e.g., reading the device ID register) to the system address of the first target slot via the PCIe bus. If no response is returned (because the first target slot is in an uninserted state, and the first target slot is not powered on, so no response is normal), the positioning is confirmed to be correct; if an abnormal response is returned, a repositioning request is sent to the control chip to avoid positioning errors.

[0045] In step S123, the first target slot is currently powered off, so its power enable signal is low. The output pin of the control chip (PCA9555 chip) defaults to a low level (PWR_EN low level indicates power off). Upon receiving the power-on command from the PCH, it pulls the corresponding pin level high to 3.3V (high level indicates power on). This high-level signal is transmitted to the enable pin of the slot protection chip (TPS2321 chip), closing the internal switch of the TPS2321 chip and starting to supply power to the first target slot. During power supply, the TPS2321 chip monitors the output current in real time. If the current exceeds the current corresponding to the maximum power consumption of the PCIe card (e.g., 2A), it automatically shuts off the switch and sends an overcurrent alarm signal to the control chip to protect the device.

[0046] Furthermore, such as Figure 3 As shown, step S14 specifically includes: S141. When the card removal information is received, a third interrupt signal is generated to the operating system based on the card removal information, so that the operating system can be interrupted according to the third interrupt signal; S142. Determine the second target slot of the PCIe device based on the card removal information; S143. Lower the power enable signal of the second target slot to power off the second target slot; wherein, the second target slot is the slot where the PCIe device needs to remove the card.

[0047] Steps S141-S143 are a detailed expansion of the card removal and power-off operation, wherein the third interrupt signal can be used to notify the operating system to prepare for card removal.

[0048] Specifically, in step S141, after the control chip confirms the validity of the ATTN# signal (the signal triggered after the user presses the hot-plug button), for example, after maintaining a high level for more than 50 milliseconds, it generates a third interrupt signal (level triggered, active low). The third interrupt signal has a higher priority than the first interrupt signal, ensuring that the operating system prioritizes the card removal process. Upon receiving the third interrupt signal, the operating system immediately suspends all data transmissions related to the PCIe card in the second target slot (such as terminating file copying and disconnecting the network connection) to prevent data loss, and simultaneously closes applications that depend on the PCIe card (such as GPU acceleration software, storage array management tools, etc.).

[0049] In step S142, the card removal information may include, for example, the number of the hot-swap button, such as Button_5. The control chip determines the physical number of the second target slot by querying a pre-configured button-slot mapping table or binding table, for example, binding Button_5 to Slot_5 in the binding table. The control chip sends this physical number to the PCH via the SMBus interface. The PCH, in conjunction with the system address mapping table, determines the PCIe bus address of the second target slot and verifies whether the device corresponding to that address exists (e.g., by reading the device ID in the PCIe configuration space). If it exists, the second target slot is confirmed to be correct; if it does not exist, the message "No card in slot" is displayed.

[0050] In step S143, the power-off operation requires unloading to be performed before the power-off can be carried out. The specific logic is as follows: After the operating system completes driver unloading (e.g., by calling the pci_remove_driver() interface) and sends a signal indicating completion to the PCH, the PCH sends a power-off command to the control chip. The control chip pulls the PWR_EN signal corresponding to the second target slot from high to 0V (or low), de-energizes the enable pin of the TPS2321 chip, opens its internal switch, and stops supplying power to the second target slot. After power-off, the DS1818 chip detects that the voltage of the second target slot has dropped to 0V and stops outputting the PowerGD signal. The control chip records the power-off time and status for subsequent troubleshooting.

[0051] Furthermore, such as Figure 4 As shown, before step S11, the step further includes: S101. Read the slot availability information of all slots of the PCIe device; S102. Based on the slot presence information, lower the power enable signal of the uninserted card slot and turn off the power.

[0052] In this embodiment, steps S101-S102 are the initialization of the entire system or server during the power-on process.

[0053] Specifically, in step S101, the read operation is performed after the system power-on phase, which can be, for example, the BIOS initialization phase. The PCH sends a "full slot status query" command to the control chip via the SMBus interface. The control chip collects the PRSNT# signal of all PCIe slots through an auxiliary chip. The control chip organizes the PRSNT# signal level (high level slot = slot with card inserted, low level slot = slot without card inserted) and signal stability (such as whether there is jitter) of each slot into a slot presence status information table, summarizes it into slot presence status information, and feeds it back to the PCH via the SMBus interface. The PCH stores this table in a fixed address in the system memory (such as 0x000E0000) for subsequent access by the operating system.

[0054] In step S142, the PCH filters out slots with a low PRSNT# signal from the status information table and marks them as slots without cards, generating a list of slots without cards. Then, the PCH sends a power-off command for the slots without cards and the list of slots without cards to the control chip via the SMBus interface. The control chip sets the PWR_EN signal low for all slots in the list of slots without cards, and the slot protection chip disconnects the power supply. This reduces idle power consumption. At the same time, no operation is performed on slots with cards already inserted, allowing them to continue to maintain a high-level state. After power-off, the control chip monitors the PRSNT# signal of the slots without cards in real time. If a card is subsequently inserted, the signal changes from low to high, immediately triggering the subsequent card insertion process.

[0055] Furthermore, such as Figure 5 As shown, after step S102, the method further includes: S103. Monitor and read the slot presence status information of the uninserted card slot in real time; S104. Determine whether the slot's in-place status information has changed; S105. If so, a fourth interrupt signal is generated for the operating system.

[0056] Specifically, in step S103, after the aforementioned power-off of the uninserted card slot, the slot's position status information is monitored and read in real time. This monitoring operation can, for example, employ a periodic sampling + abnormal triggering mechanism: the control chip sets a sampling period of 500 milliseconds, periodically acquiring the PRSNT# signal of the uninserted card slot to avoid wasting resources with high-frequency sampling; if the PRSNT# signal of the uninserted card slot changes from low to high, the control chip triggers abnormal sampling (sampling period shortened to 10 milliseconds), continuously sampling 5 times to confirm the authenticity of the signal change and avoid false triggering.

[0057] In step S104, it is determined whether the slot presence status information has changed. This determination can be based, for example, on the signal level change plus its duration: if, during abnormal sampling, all five sampling results are high-level and the duration is ≥50ms, then the slot presence status information is determined to have changed (i.e., a card is inserted into the slot). If the sampling results show alternating high and low levels, it is determined to be signal jitter, and this change is ignored; monitoring continues according to the monitoring operation in step S104.

[0058] In step S105, the fourth interrupt signal is used to notify the operating system in advance to prepare for card insertion.

[0059] The control chip generates a fourth interrupt signal (such as a high-level transition on the INT pin of the PCA9555 chip), which is transmitted to the operating system through the interrupt controller. After the operating system responds to the interrupt, it preloads the PCIe enumeration driver (such as pci_enum_driver), clears the historical configuration information of the target slot, prepares for the rapid enumeration of subsequent card insertions, and shortens the card insertion process time.

[0060] like Figure 6a As shown, the card insertion process in this embodiment is as follows: S211 Power-on Initialization: After the system powers on, the PCH reads the PRSNT# status of all slots on the PCIe device through the SMBus interface. For slots without cards, the PCH uses the PCA9555 chip to set their power enable (PWR_EN) low to power off, while slots with cards remain in the default power-on state.

[0061] S212, Insertion Detection: Real-time monitoring of the slot presence status information of uninserted slots, determining whether the PRSNT# signal of that slot changes from low to high. If so, a fourth interrupt signal is generated and sent to the operating system, indicating that a PCIe card may be inserted. When the user inserts a PCIe card into the first target slot, the PRSNT# signal of that slot changes from low to high. After debouncing by the MAX6816 chip, a fourth interrupt signal is generated by the PCA9555 signal and sent to the operating system. Simultaneously, the auxiliary chip generates card insertion information and transmits it to the control chip.

[0062] S213, Button Confirmation: When the user presses the hot-swap button (ATTN#), the signal is also debounced by the MAX6816 signal. The control chip generates the first interrupt signal to the operating system based on the card insertion information. The operating system responds to the interrupt and triggers the PCA9555 chip interrupt at the same time.

[0063] S214 Power-on Enable: After receiving the card insertion intention, the operating system sends a command to the PCA9555 chip through the PCH SMBus interface to set the PWR_EN of the corresponding first target slot from low to high. The internal switch of the TPS2321 chip closes, providing 12V / 3.3V power-on to the first target slot with current limiting to prevent damage to the device.

[0064] S215, Reset Timing: After the power supply stabilizes, the DS1818 chip detects that the voltage of the first target slot has reached the specified value and outputs the PowerGD signal. At this time, the PCH performs a logical AND operation on the platform reset signal (PLATFORM_RESET), the Soft_RSTn output by the PCA9555 chip, and the PowerGD signal to generate the final PCIe card reset signal, which is sent to the PCIe device to perform a reset operation on the first target slot, ensuring that the device initialization environment is stable.

[0065] S216, Driver Loading: The operating system detects the device enumeration status of the PCIe bus. When a newly inserted PCIe card is detected, it automatically searches for and loads the compatible driver. If no compatible driver is found, the user is prompted to install it manually. After the driver is loaded, the indicator light corresponding to the slot lights up normally, and the card insertion process ends.

[0066] like Figure 6b As shown, the card removal process in this embodiment is as follows: S221, Card Removal Intent: When the user is ready to remove the card, press the hot-swap button (ATTN#). After the signal is stabilized by the signal de-jitter chip, card removal information is generated and transmitted to the control chip. S222, Safe Uninstallation: The control chip generates a second interrupt signal to the operating system based on the card removal information. After the operating system responds to the interrupt, it stops data transmission with the target PCIe card, closes the application process that depends on the device, releases system resources, safely uninstalls the device driver, and proceeds to step S223. S223 Power-off Control: Based on the card removal information, the second target slot for removing the card is determined. The control chip lowers the power enable signal (PWR_EN) of the second target slot, triggering the slot protection chip to disconnect the power supply. The DS1818 power monitoring chip stops outputting the PowerGD signal. Then, the slot power indicator light goes out. The PCIe card can only be physically removed after the user confirms that there is no power. S224, Status Recovery: Real-time detection of the slot presence status information of the PCIe device. Based on whether the PRSNT# signal returns to its initial low level, it determines whether the card in the second target slot has been removed. If it is confirmed that the card has been removed, the control chip generates a third interrupt signal and sends it to the operating system. The operating system updates the presence status information of the second target slot, the card removal process ends, and the user can perform the next hot-plug operation.

[0067] In this embodiment, the entire hot-plugging process is controlled directly by the operating system through the PCH SMBus interface, controlling the output signals of the PCA9555 chip to manage power and reset. Simultaneously, the MAX6816 chip is used for debouncing to ensure stable mechanical signals. The LTC4313 chip maintains the reliability of the SMBus bus; the TPS2321 chip ensures power supply safety; and the DS1818 chip provides a good power-on reset timing sequence. This process is applicable to all standard PCIe cards, and is simple and logically clear.

[0068] like Figure 7a As shown, the present invention also provides a hot-swap card control device 30 for PCIe devices. (As illustrated...) Figure 7a As shown, the hot-swappable card control device 30 of the PCIe device includes, for example, a platform controller hub 31, a control chip 32, and an auxiliary chip 33; the control chip 32 is electrically connected to the platform controller hub 31; the control chip 32 is electrically connected to the auxiliary chip 33, and the auxiliary chip 33 is electrically connected to the slot of the PCIe device.

[0069] Specifically, the platform controller hub 31 (PCH) is electrically connected to the control chip to coordinate the operation of each component. The control chip 32, for example, is a PCA9555 I / O expander, electrically connected to both the PCH and the auxiliary chip, responsible for signal transmission and instruction execution. The auxiliary chip 33 is electrically connected to the PCIe device slot; all components communicate via the SMBus interface, eliminating the need for complex wiring and reducing hardware development complexity. The auxiliary chip 33 is used to detect the slot availability information of the PCIe device in real time and transmit it to the control chip 32.

[0070] When the platform controller hub 31 receives card insertion information of a hot-swappable card, it reads the slot presence status information in the control chip and triggers the control chip 32 to send a second interrupt signal to the operating system and sends power-on information of the first target slot to the control chip; it monitors the power-on reset signal of the first target slot output by the auxiliary chip, and when the power-on reset signal is detected to be valid, it performs a logical AND operation on the platform reset signal, the soft reset signal output by the control chip, and the power-on reset signal to generate a card reset signal and perform a reset operation on the first target slot; it detects the enumeration status of the PCIe device, and when a newly inserted PCIe card is identified, it automatically loads the adapted device driver to complete the card insertion process.

[0071] The control chip 32 is used to receive the power-on information of the first target slot, increase the power enable signal of the first target slot according to the power-on information, and control the auxiliary chip 33 to perform a power-on operation on the first target slot.

[0072] The platform controller hub 31 is also used to receive card removal information of hot-swappable cards, and trigger the control chip to send a third interrupt signal to the operating system based on the card removal information, so that the operating system stops data transmission to the target PCIe card corresponding to the card removal information of the PCIe device through the second interrupt signal, and uninstalls the device driver corresponding to the target PCIe card; at the same time, it sends power-off information of the second target slot to the control chip; monitors the slot presence status information of the second target slot, and when it determines the slot presence status information of the second target slot, it triggers the control chip to send a first interrupt signal to the operating system, so that the operating system updates the presence status of the second target slot according to the first interrupt signal and completes the card removal process.

[0073] The control chip is also used to receive power-off information of the second target slot, and adjust the power enable signal of the second target slot according to the power-off information, and control the auxiliary chip to power off the second target slot so that the auxiliary chip stops outputting the power good reset signal of the second target slot.

[0074] Furthermore, the platform controller hub 31 is also used to read the slot presence status information of all slots of the PCIe device after the PCIe device is powered on, and to obtain the slots without cards and the slots with cards inserted based on the slot presence status information, and to lower and power off the power enable signal of the slots without cards inserted; to monitor the slot presence status information received by the control chip 32 in real time, and when the detected slot presence status information changes from low to high, to confirm that a PCIe card is inserted in the slot, and to trigger the control chip to send a fourth interrupt signal to the operating system.

[0075] After the system powers on, the PCH first performs a slot status scan, reading the PRSNT# signal of all slots and generating a status table. For slots without cards inserted, the PCH uses the control chip to set the PWR_EN signal low to achieve power-off energy saving. For slots with cards inserted, the PCH controls the control chip to keep the PWR_EN signal high to ensure normal power supply to the device. The PCH configures the interrupt triggering mode (e.g., edge triggering) and sampling period (e.g., 500ms) of the control chip to prepare for subsequent monitoring. The PCH function for slot status change monitoring: The PCH reads the slot presence status information collected by the control chip in real time through the SMBus interface, focusing on monitoring the PRSNT# signal of slots without cards inserted. When the PRSNT# signal of a slot without cards inserted changes from low to high, the PCH triggers the control chip to send a fourth interrupt signal to the operating system, while simultaneously preloading the enumeration driver. If the PRSNT# signal of a slot with cards inserted changes from high to low (card not removed according to procedure), the PCH immediately cuts off the power supply to that slot through the control chip and sends an abnormal card removal alarm to the operating system.

[0076] Furthermore, the auxiliary chip 33 includes a signal de-jitter chip 331, a power monitoring chip 332, a slot protection chip 333, and a platform controller hub bus protection chip 334; Among them, the signal de-shaking chip 331 (e.g. Figure 7b The MAX6816 chip shown is used to de-jitter and stabilize the card removal information, card insertion information, slot presence status information and slot presence status information received by the platform controller hub 31. The power monitoring chip 332 (e.g.) Figure 7b The DS1818 chip shown is used to monitor the power information of the PCIe device slot and output a power-good reset message. The slot protection chip 333 (such as Figure 7b The TPS2321 chip shown is used to protect the power supply to the slot of the PCIe device; The platform controller hub bus protection chip 334 (such as...) Figure 7b The LTC4313 chip shown is used to prevent the bus of the platform controller hub from locking up during hot-plugging.

[0077] Specifically, the signal de-jitter chip 331 is used to receive mechanical contact signals such as PRSNT# and ATTN#, filter jitter through an RC filter circuit and a Schmitt trigger, and output a stable signal to the control chip; The power monitoring chip 332 is connected in parallel on the slot power supply circuit to collect the 12V / 3.3V voltage of the slot, output the PowerGD signal to the PCH, and record voltage fluctuation data for fault tracing. The slot protection chip 333 is connected in series in the power supply circuit to receive the PWR_EN signal from the control chip 32, realize power supply on / off control, and also has current limiting and overcurrent protection functions. The platform controller hub bus protection chip 334 is connected in parallel on the SMBus bus to automatically disconnect the bus connection when a bus conflict or overvoltage occurs during hot-plugging, preventing the PCH bus from being locked.

[0078] like Figures 7a-7b As shown, during the card insertion process, the auxiliary chip 33 detects the card insertion, then sends the signal to the control chip 32 after debouncing, then the control chip 32 generates a second interrupt signal, then the PCH responds and locates the first target slot, then the control chip 32 increases the PWR_EN of the first target slot, then the slot protection chip 333 supplies power, then the power monitoring chip 332 outputs the PowerGD signal, then the PCH generates a reset signal, then the PCIe card is reset, then the PCH detects the enumeration status, and then the operating system loads the driver.

[0079] During the card removal process, the auxiliary chip 33 detects the ATTN# signal, then sends the signal to the control chip 32 after debouncing. The control chip 32 then generates a third interrupt signal, followed by a response from the PCH. The operating system then stops transmission and uninstalls the driver. The PCH then issues a power-off command, the control chip lowers the PWR_EN of the second target slot, the slot protection chip 333 is powered off, the auxiliary chip 33 detects the PRSNT# signal, the control chip 32 generates a fourth interrupt signal, and the operating system updates the status.

[0080] In one embodiment, the entire hot-plugging process can be controlled directly by the operating system via the PCH SMBus interface, controlling the output signals of the PCA9555 chip to manage power and reset. Simultaneously, the MAX6816 chip is used for debouncing to ensure stable mechanical signals. The LTC4313 chip maintains SMBus bus reliability; the TPS2321 chip ensures power supply safety; and the DS1818 chip provides good power-on and reset timing. This process is applicable to all standard PCIe cards and is simple and logically clear.

[0081] The specific card insertion and removal procedures of the hot-swappable card control device for the PCIe device can be referred to the parts described in the above embodiments, and will not be repeated here.

[0082] In one specific embodiment, when performing a hot-swapping scenario for a server PCIe network card, after the server powers on, the PCH reads the PRSNT# signal of the eight PCIe slots through the SMBus interface. Finding that three slots are not occupied, the PCA9555 chip lowers the PWR_EN signal to disable power in these slots. When the user inserts a PCIe network card, the PRSNT# signal changes from low to high. After debouncing by the MAX6816 chip, the PCA9555 chip sends a second interrupt signal to the operating system. The operating system identifies the first target slot (slot 2 (the second PCIe slot out of the eight)). The PCA9555 chip raises its PWR_EN signal, and the TPS2321 chip limits the current to power on slot 2. After the DS1818 chip detects stable voltage, it outputs the PowerGD signal. The PCH logically ANDs the PLATFORM_RESET, Soft_RSTn, and PowerGD signals to generate a reset signal, resetting slot 2. The operating system detects the new device, automatically loads the network card driver, the network card indicator light illuminates, and the card insertion is complete. Next, the card removal operation: The user presses the ATTN# button, and the signal is debounced to trigger the third interrupt signal. The operating system stops the network card data transmission and uninstalls the driver; the PCA9555 chip lowers the PWR_EN signal of slot 2, and the TPS2321 chip powers off slot 2; after the PRSNT# signal is detected to return to a low level, the PCA9555 chip sends the first interrupt signal, the operating system updates the status of slot 2 to no card inserted, and the card removal is completed.

[0083] In one specific embodiment, during hot-swapping of the embedded device storage controller, after power-on initialization, slots 4, 5, and 6 (i.e., the 4th, 5th, and 6th PCIe slots out of 8) without inserted cards are powered off, and their presence status is monitored in real time. After the storage controller is inserted, the device is successfully recognized and put into use after a debouncing, power-on, reset, and driver loading process. When the card is removed, the operating system safely uninstalls the driver and then powers off. After confirming the card is removed, the status is updated. The entire process involves no data loss and the device remains undamaged.

[0084] like Figure 8 As shown, one embodiment of the present invention provides a hot-swap card control device 400 for a PCIe device. For example... Figure 8 As shown, the hot-swappable card control device 400 of the PCIe device includes, for example, a first receiving module 401, a power-on module 402, a card reset signal generation module 403, a power-off module 404, an information detection module 405, a first judgment module 406, and a signal generation module 407.

[0085] Specifically, the first receiving module 401 is used to receive card insertion information or card removal information sent by the hot-swappable card.

[0086] The power-on module 402 is used to power on the first target slot according to the card insertion information when the card insertion information is received.

[0087] The card reset signal generation module 403 is used to receive the power signal of the first target slot. When the power signal is valid, it performs a logical AND operation between the platform reset signal, the soft reset signal and the power signal to generate a card reset signal and sends it to the PCIe device so that the PCIe device resets the first target slot according to the card reset signal.

[0088] The power-off module 404 is used to perform a power-off operation on the second target slot according to the card removal information when the card removal information is received.

[0089] The information detection module 405 is used to detect the slot presence status information of the PCIe device.

[0090] The first judgment module 406 is used to determine whether the card in the second target slot has been removed based on the slot in-slot status information.

[0091] The signal generation module 407 is used to generate a third interrupt signal to the operating system when the first judgment module determines that the card in the second target slot has been removed from the slot's in-slot status information, so that the operating system updates the in-slot status information of the second target slot.

[0092] It should be noted that the hot-swappable card control method for PCIe devices implemented by the PCIe device hot-swappable card control device 40 provided in this embodiment is as described in the first embodiment above, and therefore will not be described in detail here. Optionally, the various modules and other operations or functions in the third embodiment are respectively for implementing the method of the first embodiment of the present invention, and the beneficial effects are the same as those in the first embodiment. For the sake of brevity, they will not be described in detail here.

[0093] like Figure 9 As shown, a first embodiment of the present invention provides a hot-swappable card control system 500 for a PCIe device. The hot-swappable card control system 500 includes, for example, a memory 510 and a processor 520 connected to the memory 510. The memory 510 may be, for example, a non-volatile memory, on which a computer program 511 is stored. The processor 520 may be, for example, an embedded processor. When the processor 520 executes the computer program 511, it performs a hot-swappable card control method for a PCIe device according to the aforementioned first embodiment.

[0094] For the specific working process and technical effects of the hot-swappable card control system 500 for PCIe devices in this embodiment, please refer to the description of the first embodiment above.

[0095] like Figure 10 As shown, one embodiment of the present invention provides a storage medium, such as a computer-readable storage medium 600. The computer-readable storage medium 600 is, for example, a non-volatile memory, such as a magnetic medium (e.g., hard disk, floppy disk, and magnetic tape), an optical medium (e.g., CD-ROM and DVD), a magneto-optical medium (e.g., optical disc), and hardware devices specifically configured for storing and executing computer-executable instructions (e.g., read-only memory (ROM), random access memory (RAM), flash memory, etc.). Computer-executable instructions 610 are stored on the computer-readable storage medium 600. The computer-readable storage medium 600 can be executed by one or more processors or processing devices to implement a hot-swap card control method for a PCIe device according to the first embodiment described above.

[0096] Furthermore, it is understood that the foregoing embodiments are merely illustrative examples of the present invention. Provided that the technical features do not conflict, the structure is not contradictory, and the purpose of the invention is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for controlling the hot-swappable cards of a PCIe device, characterized in that, include: Receive card insertion or card removal information sent by hot-swappable cards; When the card insertion information is received, the first target slot is powered on according to the card insertion information; The system receives the power signal from the first target slot. When the power signal is valid, it performs a logical AND operation between the platform reset signal, the soft reset signal, and the power signal to generate a card reset signal, which is then sent to the PCIe device so that the PCIe device can reset the first target slot according to the card reset signal. When the card removal information is received, the power is cut off to the second target slot according to the card removal information; Detect the slot presence status information of the PCIe device; Determine whether the card in the second target slot has been removed based on the slot's in-slot status information; If so, a first interrupt signal is generated to the operating system, so that the operating system updates the in-situ status information of the second target slot.

2. The hot-swappable card control method for PCIe devices according to claim 1, characterized in that, When the card insertion information is received, the step of powering on the first target slot according to the card insertion information includes: When the card insertion information is received, a second interrupt signal is generated to the operating system based on the card insertion information, so that the operating system performs an interrupt according to the second interrupt signal; The first target slot in the PCIe device is determined based on the card insertion information; Increase the power enable signal of the first target slot to power on the first target slot; wherein, the first target slot is the slot where the PCIe device needs to insert a card.

3. The hot-swappable card control method for PCIe devices according to claim 1, characterized in that, When the card removal information is received, the step of powering off the second target slot according to the card removal information includes: When the card removal information is received, a third interrupt signal is generated to the operating system based on the card removal information, so that the operating system can be interrupted according to the third interrupt signal; The second target slot of the PCIe device is determined based on the card removal information; The power enable signal of the second target slot is lowered to power off the second target slot; wherein, the second target slot is the slot where the PCIe device needs to remove the card.

4. The method for controlling the hot-swappable cards of a PCIe device according to any one of claims 1-3, characterized in that, Before receiving the card insertion information sent by the hot-swappable card, the method further includes: Read the slot availability information of all slots in the PCIe device; Based on the slot presence information, the power enable signal of the uninserted card slot is lowered and power is turned off.

5. The hot-swappable card control method for PCIe devices according to claim 4, characterized in that, After lowering and powering off the power enable signal of the uninserted card slot based on the slot presence status information, the method further includes: Real-time monitoring and reading of the slot presence status information of the uninserted card slot; Determine whether the slot's in-situ status information has changed; If so, a fourth interrupt signal is generated for the operating system.

6. A hot-swappable card control device for a PCIe device, applicable to the hot-swappable card control method for a PCIe device as described in any one of claims 1 to 5, characterized in that, The device includes: a platform controller hub, a control chip, and an auxiliary chip; the control chip is electrically connected to the platform controller hub; the control chip is electrically connected to the auxiliary chip, and the auxiliary chip is electrically connected to the slot of the PCIe device.

7. The hot-swappable card control device for PCIe equipment according to claim 6, characterized in that, The platform controller hub is also used to read the slot presence status information of all slots of the PCIe device after the PCIe device is powered on, and to determine the slots without cards and the slots with cards inserted based on the slot presence status information. It then lowers the power enable signal of the slots without cards inserted and cuts off the power. It also monitors the slot presence status information received by the control chip in real time. When the slot presence status information changes from low to high, it confirms that a PCIe card is inserted into the slot and triggers the control chip to send a fourth interrupt signal to the operating system.

8. The hot-swappable card control device for PCIe equipment according to claim 6, characterized in that, The auxiliary chips include a signal de-jitter chip, a power monitoring chip, a slot protection chip, and a platform controller hub bus protection chip. The signal de-jitter chip is used to de-jitter and stabilize the card removal information, card insertion information, slot presence status information of all slots of the PCIe device, and slot presence status information received by the platform controller hub. The power monitoring chip is used to monitor the power information of the PCIe device slot and output a power good reset message; The slot protection chip is used to protect the power supply to the slot of the PCIe device; The platform controller hub bus protection chip is used to prevent the platform controller hub bus from locking up during hot-plugging.

9. A hot-swappable card control device for a PCIe device, applicable to the hot-swappable card control method for a PCIe device as described in any one of claims 1 to 5, characterized in that, The device includes: The first receiving module is used to receive card insertion information or card removal information sent by the hot-swappable card; The power-on module is used to power on the first target slot according to the card insertion information when the card insertion information is received; The card reset signal generation module is used to receive the power signal of the first target slot. When the power signal is valid, it performs a logical AND operation between the platform reset signal, the soft reset signal and the power signal to generate a card reset signal and sends it to the PCIe device so that the PCIe device resets the first target slot according to the card reset signal. A power-off module is used to perform a power-off operation on the second target slot according to the card removal information when the card removal information is received; The information detection module is used to detect the slot presence status information of the PCIe device; The first judgment module is used to determine whether the card in the second target slot has been removed based on the slot in-slot status information. The signal generation module is used to generate a first interrupt signal to the operating system when the first judgment module determines that the card in the second target slot has been removed from the slot, so that the operating system updates the slot's status information.

10. A hot-swappable card control system for a PCIe device, characterized in that, include: A memory and a processor connected to the memory, the memory storing a computer program, the processor executing the computer program to perform a hot-swap card control method for a PCIe device as described in any one of claims 1 to 5.

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