A serial data transmission system and method

Abstract

The application provides a serial port data transmission system and method, and relates to the technical field of data transmission. The system comprises at least one server mainboard, each server mainboard comprising a server CPU and a multiplexing management module; the server CPU is internally provided with multiple independent UART serial ports, which are used for encapsulating multiple independent UART serial port data into a group of time division multiplexing bus signals according to a preset frame format; the multiplexing management module is used for analyzing the time division multiplexing bus signals and separating and restoring independent serial port signals of each channel; a USB-to-serial port module is used for converting the independent serial port signals of each channel into USB signals, connecting a client through a USB interface, and realizing local direct connection debugging; a serial port server is used for receiving the time division multiplexing bus signals and connecting the client through an Ethernet interface, and realizing multi-server remote network debugging. The application effectively solves the problems of insufficient pin resources, great difficulty in controlling the impedance of the wiring, and low efficiency in operation and maintenance troubleshooting.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and more specifically, to a serial port data transmission system and method. Background Technology

[0002] As server system integration continues to increase, server CPUs typically need to provide multiple independent UART debugging serial ports for monitoring and debugging server operation during the R&D and maintenance phases. In practical applications, server debugging serial ports need to support two debugging methods simultaneously: one is local USB direct connection debugging, where engineers connect the host computer directly to the server motherboard via USB cable for close-range debugging; the other is remote Ethernet debugging, where a serial port server converts Ethernet signals into serial signals, allowing engineers to debug the server remotely over a network. Especially in data center and server room applications, multiple servers often need to be connected to the same serial port server simultaneously for centralized debugging and management, which places higher demands on the signal transmission architecture of the server debugging serial port.

[0003] In existing technologies, multiple independent UART serial port signals output by the server CPU are typically all connected to the onboard CPLD / FPGA, where the CPLD / FPGA internally implements signal buffering and splitting output functions. After being split by the CPLD / FPGA, one of the multiple UART signals retains all independent TX / RX traces and is led out to the motherboard connector, then connected via cable to an ETH-to-serial server. The controller inside the serial server converts each independent serial port signal into an Ethernet data stream for remote network debugging. The other path directly connects to a USB-to-serial module via the motherboard's internal PCB traces, converting the multiple serial ports into USB signals for direct connection to the host computer, enabling local direct debugging. In this solution, after being split by the CPLD / FPGA, both debugging links retain all independent serial port traces, with each serial port occupying independent transmit and receive signal lines.

[0004] However, on the one hand, the CPU's multiple debug serial ports occupy a large number of CPLD / FPGA I / O pins. Server peripherals are numerous, and CPLD / FPGA pin resources are already scarce. When the number of debug serial ports is large, insufficient pin resources can easily occur, even requiring the addition of new CPLD / FPGA devices, increasing hardware costs and server logic design complexity. On the other hand, each CPU UART has independent transmit and receive signal lines. After being split by the CPLD / FPGA, both debug links still retain all independent serial port traces. Taking an 8-channel debug serial port as an example, a single link requires 16 connector pins. The increased number of pins forces the use of larger connectors, encroaching on board component layout space and resulting in denser PCB wiring, increasing the difficulty of controlling trace impedance. Furthermore, in application scenarios where multiple servers are simultaneously connected to a serial server network, a large number of cables need to be laid between the servers. Since each serial port is independent, when a connection failure occurs in one serial port, it is difficult to quickly locate the corresponding channel and cable in the complex wiring environment, leading to low equipment maintenance and troubleshooting efficiency. Summary of the Invention

[0005] The purpose of this application is to provide a serial port data transmission system and method to solve the problems of insufficient pin resources, difficulty in controlling trace impedance, and low efficiency in equipment operation and maintenance in the prior art.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: On one hand, embodiments of this application provide a serial port data transmission system, the system comprising: At least one server motherboard, each of the server motherboards including a server CPU and a multiplexing management module; The server CPU has multiple independent UART serial ports built-in, which are used to encapsulate the data from the multiple independent UART serial ports into a set of time-division multiplexed bus signals according to a preset frame format. The time-division multiplexed bus signals are transmitted through the downlink bus and the uplink bus. The multiplexing management module is connected to the server CPU through the downlink bus and the uplink bus. The multiplexing management module is used to parse the received time-division multiplexing bus signal and separate and recover the independent serial port signal of each channel. The USB to serial port module is connected to the multiplexing management module and is used to convert the independent serial port signals of each channel separated and recovered by the multiplexing management module into USB signals, and connect them to the client through the USB interface to realize local direct connection debugging. The motherboard connector is connected to the input terminal of the multiplexing management module and is used to lead the time-division multiplexing bus signal to the outside of the motherboard. A serial port server, connected to the motherboard connector, is used to receive the time-division multiplexed bus signals and connect to the client via an Ethernet interface to enable remote network debugging of multiple servers.

[0007] Optionally, the multiplexing management module is implemented by any one of CPLD, FPGA, ASIC, MCU or SOC; The multiplexing management module is equipped with a TDM UART decoding unit. The TDM UART decoding unit is used to perform frame synchronization, channel identification, data extraction and verification on the time-division multiplexed bus signal according to the preset frame format, so as to separate and recover the independent serial port signal of each channel.

[0008] Optionally, the motherboard connector is provided with downlink bus signal pins, uplink bus signal pins, and GND ground pin; The external cable connecting the motherboard connector to the serial server includes three signal lines corresponding to three pins.

[0009] Optionally, the preset frame format includes, in sequence: frame header, serial port channel number, serial port data, CRC checksum, and frame trailer; The frame header, the serial port channel number, the CRC checksum, and the frame tail occupy a total of 32 bits, and the serial port data field is 8N bits in length, where N is the number of bytes.

[0010] Optionally, in the preset frame format, a status code field is also provided between the frame header and the serial port channel number; The status code field is used to characterize the current real-time load status or rate demand indication of the corresponding serial port channel.

[0011] Optionally, the server CPU is equipped with a load monitoring and rate decision module, which is used to generate the corresponding status code according to the transmit buffer level of each serial port channel, and encapsulate the status code into the preset frame format; The status code includes at least one or a combination of the following encoded states: The idle state code indicates that there is currently no data to be sent on the corresponding channel; Light load status coding indicates that the transmit buffer occupancy rate of the corresponding channel is lower than the first threshold; The intermediate load status code indicates that the transmit buffer occupancy rate of the corresponding channel is between the first threshold and the second threshold; The full-load status code indicates that the occupancy rate of the corresponding channel's transmit buffer is higher than the second threshold; The burst warning status code indicates that the corresponding channel is about to generate burst data, requesting the receiving end to increase the bus rate in advance.

[0012] Optionally, the multiplexing management module and / or the serial port server are equipped with an arbitration decision module. The arbitration decision module is used to parse the received status code and, in combination with its own link quality monitoring results, comprehensively determine whether to perform the adjustment of the time-division multiplexing bus operating rate. When it is determined that speed needs to be increased or decreased, the arbitration decision module sends a rate negotiation frame to the server CPU through the uplink bus. After receiving the rate negotiation frame, the server CPU confirms and executes the rate switch. The bus operating speed after the speed switch is not lower than the theoretical minimum speed requirement corresponding to the current number of active serial ports, and the theoretical minimum speed requirement satisfies: Rate_min = N_active × (Baud_UART ÷ 8) × L_frame Where N_active is the number of currently active serial port channels, Baud_UART is the original serial port baud rate, and L_frame is the total number of bits per frame.

[0013] Optionally, the serial port server is simultaneously connected to multiple motherboard connectors of the server motherboards, and the serial port server is internally configured with a controller and a channel mapping table. The channel mapping table is used to record the correspondence between the identification information of each server motherboard and the serial port channel number inside each server motherboard; The controller associates the decoded serial port data of each channel with the corresponding server motherboard and serial port channel according to the channel mapping table, and when converting it into an Ethernet packet, it carries both the server motherboard identifier field and the serial port channel number field in the Ethernet packet.

[0014] Optionally, the serial port server is further provided with a port status indicator module and a data cache module; The port status indication module includes status indicator lights that correspond one-to-one with each motherboard connector access port, used to indicate the link connection status and data transmission activity status of the corresponding port; The data caching module is used to cache and queue the data of each channel according to a preset priority strategy when multiple server motherboards send data to the serial port server at the same time, and then upload the data to the client sequentially through the Ethernet interface.

[0015] On the other hand, this application also provides a serial port data transmission method applied to the above-mentioned system, the method comprising: Each server motherboard's CPU encapsulates its internal multi-channel independent UART serial port data into a set of time-division multiplexed bus signals according to a preset frame format, and transmits them to the corresponding multiplexing management module through its respective downlink bus. Each of the multiplexing management modules parses the received time-division multiplexed bus signal, separates and recovers the independent serial port signal of each channel, and outputs the separated and recovered independent serial port signal of each channel to the USB to serial port module. After being converted into a USB signal, it is connected to the client through the USB interface to realize local direct connection debugging of each server motherboard. Each of the multiplexing management modules leads out the time-division multiplexed bus signal through its respective motherboard connector and transmits it to the same serial port server via an external cable; The serial port server receives and decodes the time-division multiplexed bus signals from each of the server motherboards, recovers the serial port data of each channel of each server motherboard, and associates and identifies each channel data with the corresponding server motherboard and serial port channel according to the internally preset channel mapping table. The serial port server converts all channel data from all server motherboards after association into Ethernet packets and uploads them to the client via the Ethernet interface, enabling remote network debugging of multiple servers.

[0016] Compared with the prior art, this application has the following advantages: This application provides a serial port data transmission system that encapsulates multiple independent UART serial port data from the server CPU into a set of time-division multiplexed bus signals according to a preset frame format. After being parsed by the multiplexing management module, the independent serial port signals of each channel are separated and recovered. These signals are then used for local direct connection debugging via a USB-to-serial module and for remote network debugging via a motherboard connector to a serial port server. This system replaces the traditional multi-channel independent serial port traces with a set of time-division multiplexed bus signals, solving the problems of insufficient pin resources, difficulty in controlling trace impedance, and low efficiency in equipment maintenance and troubleshooting.

[0017] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the architecture of the serial port data transmission system provided in the embodiments of this application.

[0020] Figure 2 This is a schematic diagram of a preset frame format provided in an embodiment of this application.

[0021] Figure 3 An exemplary flowchart of a serial port data transmission method provided in an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0024] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0026] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0027] To address the problems of insufficient pin resources, difficulty in controlling trace impedance, and low efficiency in equipment maintenance and troubleshooting mentioned in the background art, this application provides a serial port data transmission system, such as... Figure 1 As shown, the serial data transmission system includes: At least one server motherboard, each including a server CPU and a multiplexing management module; the server CPU has multiple independent UART serial ports built-in, used to encapsulate the data from these multiple independent UART serial ports into a set of time-division multiplexed bus signals according to a preset frame format, the time-division multiplexed bus signals including a downlink bus and an uplink bus; the multiplexing management module is connected to the server CPU via the downlink and uplink buses, and is used to parse the received time-division multiplexed bus signals and separate and recover the independent serial port signals of each channel; a USB to serial port module, connected to the multiplexing management module, is used to convert the independent serial port signals of each channel separated and recovered by the multiplexing management module into USB signals, and connect to the client via a USB interface to achieve local direct connection debugging; a motherboard connector, connected to the input terminal of the multiplexing management module, is used to lead the time-division multiplexed bus signals to the outside of the motherboard; a serial port server, connected to the motherboard connector, is used to receive the time-division multiplexed bus signals and connect to the client via an Ethernet interface to achieve multi-server remote network debugging.

[0028] The server motherboard is the circuit board assembly in the server that carries the core computing and logic control functions. In this embodiment, there can be one or multiple server motherboards. When there are multiple server motherboards, each server motherboard is connected to the same serial port server through its own motherboard connector, thereby enabling centralized remote debugging of multiple servers. For example, in a data center rack, 10 servers can be placed side by side. Each server motherboard has a motherboard connector, and the motherboard connectors of the 10 servers are connected to the same serial port server through 10 three-core cables. In this way, maintenance personnel only need to access the IP address of one serial port server to simultaneously monitor and manage the debugging serial ports of 10 servers.

[0029] Optionally, the server CPU is the central processing unit on the server motherboard, which integrates multiple independent UART serial ports. UART (Universal Asynchronous Receiver / Transmitter) is an asynchronous serial communication interface. Each UART serial port includes independent transmit signal lines UART_TX_x and receive signal lines UART_RX_x, where x represents the serial port channel number. In this embodiment, the server CPU can have 8, 10, or more independent UART serial ports. Each UART serial port can operate independently, with independent baud rate configuration and data transmission / reception capabilities.

[0030] In existing technology, server CPUs support both local USB direct-connect debugging and remote Ethernet debugging via multi-channel debug serial ports. The system is divided into two main areas: the left side is the server motherboard, and the right side houses the ETH serial server and the user PC. The server CPU typically has multiple independent UART channels, each containing independent transmit signal lines (UART_TX_x) and receive signal lines (UART_RX_x). All serial ports are connected to the onboard CPLD / FPGA, which internally implements signal buffering and branching output functions. The first branch of the CPLD / FPGA serial port is the network remote debugging link: the multiple UART signals after branching by the CPLD / FPGA retain the independent TX / RX traces of each channel and are all led out to the motherboard connector. The serial signals are then connected to the ETH to UART serial server connector via cables. The internal controller of the serial server converts each independent serial signal into an Ethernet data stream, which is then connected to the host PC via a network cable to achieve remote network debugging. The second branch of the CPLD / FPGA serial port is a local USB direct-connect debugging link: the multiple UARTs after being branched by the CPLD / FPGA are directly connected to the USB to UART conversion module through the internal PCB traces of the motherboard. The conversion module converts the multiple serial ports into USB signals, which are then directly connected to the host PC via USB cables to achieve local direct-connect debugging. The host computer interaction logic is as follows: the local USB and remote Ethernet links establish independent communication with the user PC.

[0031] In this application, the server CPU no longer directly outputs multiple independent UART serial port signals to the multiplexing management module for simple signal buffering and splitting. Instead, the server CPU first encapsulates the multiple independent UART serial port data into a set of time-division multiplexed bus signals according to a preset frame format. Time-division multiplexing (TDM) refers to the technique of dividing multiple signals into several time slots on the same transmission medium for transmission. In this application, multiple UART serial port data are allocated in different time slots and transmitted through the same set of buses.

[0032] Optionally, the time-division multiplexed bus signal is transmitted via a downlink bus and an uplink bus. The downlink bus is used to transmit multi-channel serial port data encapsulated by the server CPU to the multiplexing management module, and the uplink bus is used to transmit debugging commands issued by the client via a USB-to-serial module or a serial server back to the server CPU. The downlink bus and the uplink bus constitute a bidirectional transmission bus. In this embodiment, the downlink bus is named TDM_UART_TX, and the uplink bus is named TDM_UART_RX.

[0033] As one implementation method, the preset frame format is a unified data frame structure used by the server CPU when encapsulating multiple serial port data. Figure 2 This is a schematic diagram of the serial port frame format provided in the embodiments of this application, such as... Figure 2 As shown, in this embodiment, the preset frame format sequentially includes: a frame header, a serial port channel number, serial port data, a CRC checksum, and a frame trailer. The frame header identifies the start position of a data frame, facilitating frame synchronization at the receiving end; the serial port channel number identifies the serial port channel to which the data frame belongs, enabling the receiving end to distribute data to the corresponding channel; the serial port data is the payload carried by the frame, i.e., the original UART serial port data; the CRC checksum performs cyclic redundancy checks on the data frame to detect whether errors occur during transmission; and the frame trailer identifies the end position of a data frame.

[0034] In this embodiment, the frame header, the serial port channel number, the CRC checksum, and the frame trailer together occupy 32 bits, and the serial port data field is 8N bits long, where N is the number of bytes. Taking the transmission of only 1 byte of serial port data at a time as an example, the minimum total length of a single frame is 40 bits. When only 1 byte of serial port data is transmitted at a time, the single frame length accounts for the largest proportion, which is the most demanding operating condition for the bus speed.

[0035] Assuming the original serial port bit rate is 115200 bit / s, and a single UART byte needs to be encapsulated into a frame requiring 40 bits of transmission, the minimum bus speed requirement for a single serial port is: Rate_single = 115200 ÷ 8 × 40 = 576000 bit / s. When the CPU has 10 independent serial ports operating simultaneously, the minimum operating speed of the TDM_UART_TX bus is no less than 5.76 Mbit / s. This calculation provides a clear basis for quantitative evaluation of the bus speed, enabling bandwidth assessment to be completed during the solution design phase, facilitating standardized hardware porting. For example, if a bus transceiver supporting speeds of 10 Mbit / s or higher is selected, the requirement for 10 serial ports to operate at full load simultaneously can be met; if only 4 serial ports need to be supported, the bus speed can be reduced to 2.304 Mbit / s, allowing for the selection of a lower-cost, lower-power bus transceiver.

[0036] As an example, the specific field composition of the frame format can be shown in Table 1 below: Table 1

[0037] Optionally, the multiplexing management module is connected to the server CPU via a downlink bus and an uplink bus. The multiplexing management module is a core logic module on the server motherboard used for parsing and demultiplexing time-division multiplexed bus signals. In this embodiment, the multiplexing management module is implemented using any one of a CPLD, FPGA, ASIC, MCU, or SOC. CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array) are both programmable logic devices with flexible programming capabilities and abundant I / O resources; ASIC (Application Specific Integrated Circuit) is an integrated circuit customized for a specific application; MCU (Microcontroller Unit) and SOC (System on Chip) are highly integrated and feature-rich processing chips. This application does not limit the specific device used to implement the multiplexing management module, as long as it can perform the parsing and demultiplexing of time-division multiplexed bus signals.

[0038] Optionally, the multiplexing management module internally includes a TDM UART decoding unit. This unit performs frame synchronization, channel identification, data extraction, and verification on the time-division multiplexed bus signals according to a preset frame format, thereby separating and recovering the independent serial port signals for each channel. The specific working process is as follows: First, the TDM UART decoding unit searches for frame headers in the received data stream. When a frame header is detected, the start position of a data frame is determined, achieving frame synchronization. Then, the serial port channel number following the frame header is read to determine the serial port channel to which the data frame belongs. Next, the payload in the serial port data field is extracted, and the data is verified using a CRC checksum field. Finally, the verified data is distributed to the serial port output port of the corresponding channel, recovering the independent serial port signal for that channel. Through the above process, the multiplexing management module completely separates and recovers the time-division multiplexed serial port data on the downlink bus into multiple independent serial port signals.

[0039] In this embodiment, the multiplexing management module also includes a TDM UART encoding unit, which encapsulates uplink data into time-division multiplexed bus signals according to a preset frame format. In the reverse channel, debugging commands sent by the client are converted into corresponding time-division multiplexed bus signals via a USB-to-serial module or serial server, and then transmitted to the multiplexing management module via the uplink bus TDM_UART_RX. The TDM UART decoding unit of the multiplexing management module parses the time-division multiplexed bus signals on the uplink bus, separates and recovers the independent serial port signals for each channel, and transmits them to the server CPU. The working principles of the uplink and downlink channels are completely symmetrical.

[0040] Optionally, the USB-to-serial module is connected to the multiplexing management module. The USB-to-serial module is a conversion module used to convert serial signals to USB signals. In this embodiment, the multiplexing management module directly connects the separated and recovered independent serial signals of each channel to the USB-to-serial module via internal PCB traces on the motherboard. The USB-to-serial module converts multiple serial signals into USB signals, which are then directly connected to the host client (user PC) via a USB cable to achieve local direct-connection debugging functionality. The USB-to-serial module can be implemented using existing USB-to-serial chips, such as the FTDI series chips, CH340 series chips, and CP2102 series chips. Taking the FTDI FT4232H chip as an example, this chip supports the conversion of four independent UART channels to USB signals. Engineers only need one USB cable to simultaneously open four serial terminal windows on their local computer, each corresponding to one of the four debugging serial ports.

[0041] In one implementation, the motherboard connector is connected to the input of the multiplexing management module. The motherboard connector, located at the edge of the server motherboard, is used to route signals from inside the motherboard to the outside. In this embodiment, the multiplexing management module routes the TDM_UART_TX and TDM_UART_RX signals externally to the motherboard connector. The motherboard connector has only three pins: a downlink bus signal pin, an uplink bus signal pin, and a GND ground pin. The external cable connecting the motherboard connector to the serial server contains only three signal lines corresponding to these three pins. For example, the motherboard connector can be a 3-pin wafer connector or a header connector, and the external cable can be a 3-core ribbon cable or a 3-core shielded cable.

[0042] It should be noted that in existing technologies, taking an 8-channel debug serial port as an example, a single link requires 16 connector pins, resulting in large connectors and congested wiring. In this application, however, the motherboard connector only requires 3 pins, allowing for the use of smaller connectors and freeing up PCB layout space. The number of long traces is significantly reduced, lowering wiring difficulty and reducing the pressure on signal crosstalk and impedance control. External connection cables require only three signal lines, significantly reducing the number of cables compared to traditional multi-channel independent serial port wiring solutions, thus reducing the difficulty of PCB wiring and data center wiring.

[0043] The serial port server is connected to the motherboard connector. The serial port server is a device used to convert serial port signals into Ethernet signals. In this embodiment, an external cable connects the motherboard connector to the serial port server. The serial port server has an internal controller that receives bus frames, decodes them, recovers the serial port data, converts it into Ethernet packets, and uploads them to the host client for remote network debugging. The serial port server is connected to the motherboard connectors of multiple server motherboards. The serial port server has an internal controller and a channel mapping table. The channel mapping table records the correspondence between the identification information of each server motherboard and the serial port channel numbers within each server motherboard. Based on the channel mapping table, the controller associates the decoded serial port data with the corresponding server motherboard and serial port channel, and when converting it into Ethernet packets, it simultaneously carries the server motherboard identification field and the serial port channel number field in the Ethernet packets.

[0044] As an example, the channel mapping table can be shown in Table 2 below: Table 2

[0045] In this embodiment, the serial port server is also equipped with a cascading interface, which is used to connect to the next-level serial port server to achieve multi-level cascading expansion. When multiple levels are cascaded, the controller of each level of the serial port server adds its own server identifier to the Ethernet packet level by level, forming a packet containing complete cascading path information. For example, in a large data center, the first-level serial port server is connected to server motherboards S1 to S10, and the second-level serial port server is connected to server motherboards S11 to S20. The first-level and second-level serial port servers are connected through the cascading interface. When server motherboard S15 on the second-level serial port server generates data, the second-level serial port server adds the S15 identifier to the Ethernet packet and then uploads it to the first-level serial port server through the cascading interface. The first-level serial port server then adds its own identifier and uploads it to the client. The client can determine that the data comes from server motherboard S15 on the second-level serial port server based on the complete cascading path information in the packet.

[0046] The serial server also includes a port status indicator module and a data buffer module. The port status indicator module includes status indicator lights corresponding one-to-one with each motherboard connector port, used to indicate the link connectivity and data transmission activity of the corresponding port. For example, when a port is normally connected and there is no data transmission, the status indicator light is solid green; when a port is transmitting data, the status indicator light flashes green; when a port's link is interrupted, the status indicator light is solid red. The data buffer module is used to buffer and queue data from each channel according to a preset priority strategy when multiple server motherboards simultaneously send data to the serial server, and then upload it sequentially to the client via the Ethernet interface. The priority strategy includes any of the following or a combination thereof: based on server motherboard priority, based on serial channel priority, based on first-come-first-served, and based on data urgency. For example, server motherboard S1 can be set to high priority; when S1 and S2 send data simultaneously, the serial server will prioritize uploading data from S1.

[0047] In this embodiment, the data transmission directions of the uplink and downlink buses are opposite. The uplink bus is used to encapsulate debugging commands issued by the client via a USB-to-serial module or a serial server according to a preset frame format and transmit them back to the server CPU. The downlink and uplink buses adopt either single-ended or differential signal transmission methods. Differential signal transmission provides stronger anti-interference capabilities and is suitable for longer-distance transmission scenarios; single-ended signal transmission simplifies the circuit structure and is suitable for shorter-distance transmission scenarios.

[0048] Optionally, when using differential signal transmission, the downlink bus TDM_UART_TX uses a pair of differential signal lines TDM_UART_TX_P and TDM_UART_TX_N for transmission, and the uplink bus TDM_UART_RX uses a pair of differential signal lines TDM_UART_RX_P and TDM_UART_RX_N for transmission. Correspondingly, the motherboard connector needs to be allocated five pins: TDM_UART_TX_P, TDM_UART_TX_N, TDM_UART_RX_P, TDM_UART_RX_N, and GND (ground). The external cable needs to contain five signal lines. When using single-ended signal transmission, the motherboard connector only needs to be allocated three pins, and the external cable only needs to contain three signal lines, resulting in a simpler circuit structure. Those skilled in the art can flexibly choose between single-ended and differential signal transmission methods based on the actual transmission distance and anti-interference requirements.

[0049] In this embodiment, a status code field is also provided between the frame header and the serial port channel number in the preset frame format. The status code field is used to characterize the current real-time load status or rate demand indication of the corresponding serial port channel. The server CPU has a load monitoring and rate decision module, which is used to generate the corresponding status code according to the transmit buffer level of each serial port channel and encapsulate the status code into the preset frame format.

[0050] Optionally, the status code includes at least one or a combination of the following encoded states: idle state code, indicating that there is currently no data to be transmitted on the corresponding channel; lightly loaded state code, indicating that the transmit buffer occupancy rate of the corresponding channel is lower than a first threshold; medium loaded state code, indicating that the transmit buffer occupancy rate of the corresponding channel is between the first threshold and the second threshold; fully loaded state code, indicating that the transmit buffer occupancy rate of the corresponding channel is higher than the second threshold; burst warning state code, indicating that the corresponding channel is about to generate burst data and requests the receiver to increase the bus rate in advance.

[0051] In this embodiment, a 4-bit status code is used as an example. The specific definition of the status code is shown in Table 3 below: Table 3

[0052] It should be noted that the status code field can be set independently between the frame header and the serial port channel number, or it can be implemented as part of the frame header. When the status code is part of the frame header, the frame header field can be designed as 12 bits, where the high 8 bits are fixed frame header flags and the low 4 bits are the status code. Both implementation methods can achieve the function of carrying status codes, and this application does not impose any restrictions on this.

[0053] As an example, the frame format after adding the status code can be shown in Table 4 below: Table 4

[0054] In this embodiment, the multiplexing management module and / or the serial port server are equipped with an arbitration decision module. The arbitration decision module parses the received status code and, combined with its own link quality monitoring results, comprehensively determines whether to adjust the time-division multiplexing bus operating rate. When it is determined that a speed increase or decrease is needed, the arbitration decision module sends a rate negotiation frame to the server CPU via the uplink bus. Upon receiving the rate negotiation frame, the server CPU confirms and executes the rate switch. The bus operating rate after the rate switch is not lower than the theoretical minimum rate requirement corresponding to the current number of active serial ports. The theoretical minimum rate requirement satisfies: Rate_min = N_active × (Baud_UART ÷ 8) × L_frame, where N_active is the number of currently active serial port channels, Baud_UART is the original serial port baud rate, and L_frame is the total number of bits per frame.

[0055] Optionally, the arbitration decision module's arbitration logic is as follows: The acceleration condition is receiving full-load status codes for three consecutive frames or more, or receiving burst warning status codes, or multiple channels simultaneously reporting medium-load or higher-level status codes; the deceleration condition is all channels reporting idle or light-load status codes for ten consecutive frames or more, and the receiver itself not detecting data loss or abnormal bit error rate; the maintenance condition is that the status codes of each channel are mixed, with no clear consistent trend, or the receiver's own link quality monitoring shows that the bit error rate at the current rate is close to the threshold. When arbitrating, the arbitration decision module must also consider the receiver's own link quality monitoring results: during acceleration, the current bit error rate must be below the threshold (e.g., less than 10^-6) to ensure signal integrity is maintained after acceleration; during deceleration, even if the CPU suggests deceleration, if the bit error rate is high, deceleration can be temporarily suspended or reduced only to a medium rate to ensure transmission reliability is prioritized.

[0056] As an example, assume there are currently 10 serial ports, with an original serial port bit rate of 115200 bits / s and a total frame size of 40 bits. When all 10 serial ports are operating at full capacity, the theoretical minimum speed requirement is 10 × (115200 ÷ 8) × 40 = 5.76 Mbit / s. When only 3 serial ports are detected as active, the theoretical minimum speed requirement is 3 × (115200 ÷ 8) × 40 = 1.728 Mbit / s. At this point, the arbitration decision module can reduce the bus speed from 5.76 Mbit / s to 1.728 Mbit / s, reducing power consumption by approximately 70%. When the number of active serial ports increases to 6, the theoretical minimum speed requirement is 6 × (115200 ÷ 8) × 40 = 3.456 Mbit / s, and the arbitration decision module will increase the bus speed to above 3.456 Mbit / s.

[0057] In this embodiment, the rate switching process is as follows: After the receiving end generates a rate switching request, it sends the target rate encoding to the server CPU through a dedicated rate negotiation frame in the uplink channel of the next frame; after receiving the rate negotiation frame, the server CPU verifies the feasibility of the target rate, and performs clock switching at the beginning boundary of the next frame period after confirmation; during rate switching, the sending end and the receiving end synchronously adjust the clock, and retain several transition redundant frames before and after the switch to avoid data loss at the moment of switching; the server CPU carries an acknowledgment flag in the first data frame after the switch, and the receiving end confirms the successful rate switching after receiving it.

[0058] In this embodiment, the bus speed can be divided into several discrete levels: L0 corresponds to a sleep rate of tens of kbps, maintaining only link keep-alive, suitable for scenarios where all channels are idle for more than 1 second; L1 corresponds to a low speed of 0.3 times the base rate, suitable for scenarios where most channels are lightly loaded; L2 corresponds to a medium speed of 0.6 times the base rate, suitable for scenarios with mixed light and medium loads; L3 corresponds to full speed of 1.0 times the base rate, suitable for scenarios where most channels are fully loaded or when a sudden warning is received. The switching strategy adopts a step-by-step approach to avoid the impact of sudden speed changes on signal integrity; only when a sudden warning status code is received can a speed jump be performed, directly increasing from L1 to L3 to quickly respond to sudden demands.

[0059] In this embodiment, the order of data frame fields in the preset frame format can be adjusted according to actual needs. For example, the CRC check field can be placed before the serial data field, or the frame trailer can be placed before the CRC check field. Adjusting the field order does not affect the basic logic of frame parsing, as long as the sending and receiving ends use the same frame format convention. Other fields can also be added to the preset frame format. For example, a frame sequence number field can be added to detect frame loss; a priority field can be added to identify the priority of the data frame; and an encryption flag can be added to indicate whether the data frame is encrypted. After adding fields, the total length of a single frame increases accordingly, and the minimum bus speed requirement also increases accordingly, but the core technical solution remains unchanged.

[0060] In this embodiment, the time slot occupied by each serial port on the bus is not specified; the content of different serial ports is mainly distinguished by the serial port channel number. Optionally, when the server CPU encapsulates data frames, it allocates a serial port channel number to each frame of data. The receiving end distributes the data to the corresponding serial port channel based on the serial port channel number. The time slot occupied by each serial port on the bus can be fixed or dynamically allocated. For example, a polling method can be used to allocate time slots to each serial port sequentially, or a priority method can be used to allocate more time slots to higher-priority serial ports. Distinguishing the content of different serial ports by the serial port channel number makes the bus time slot allocation more flexible and can adapt to scenarios with uneven load on different serial ports.

[0061] In this embodiment, the external cables between the serial port server and each server motherboard are connected in a star topology. That is, each server motherboard connects to the same serial port server via its own independent external cable. The star topology is simple and facilitates fault isolation. When a cable on one server motherboard fails, it only affects the debugging communication of that motherboard and does not affect the normal operation of other server motherboards. Correspondingly, the serial port server has multiple ports, each connected to a server motherboard. The controller of the serial port server assigns a unique port number to each port and associates the port number with a server motherboard identifier. When a port receives data, the controller determines the corresponding server motherboard identifier based on the port number and carries that identifier in the Ethernet packet.

[0062] In this embodiment, the serial port server also includes an encryption and security authentication module. This module encrypts serial port data from the server motherboard and authenticates incoming clients. Optionally, the encryption and security authentication module performs lightweight symmetric encryption on the serial port data field in the time-division multiplexed bus signal; the key is pre-negotiated between the server CPU and the serial port server via a secure channel. When a client connects, it needs to complete two-way authentication with the serial port server; if authentication fails, the communication link is refused. Through the encryption and security authentication module, this embodiment meets the compliance requirements for confidential or high-security scenarios, preventing the leakage of debugging data and unauthorized device access.

[0063] In this embodiment, the local USB debugging link and the remote Ethernet debugging link establish communication with the client independently. In the local USB debugging link, the multiplexing management module outputs the separated and recovered independent serial port signals of each channel to the USB-to-serial module. The USB-to-serial module converts the serial port signals into USB signals and connects to the client via the USB interface. In the remote Ethernet debugging link, the multiplexing management module leads the time-division multiplexed bus signal out through the motherboard connector and transmits it to the serial port server via an external cable. The serial port server decodes the time-division multiplexed bus signal and converts it into Ethernet packets, which are then connected to the client via the Ethernet interface. The two debugging links can work simultaneously without interference. Engineers can perform local debugging via the USB interface and remote debugging via the Ethernet interface. Each link establishes a communication connection with the client independently, and the client can open two terminal windows simultaneously for local and remote debugging.

[0064] Based on the above implementation, this application also provides a serial port data transmission method, applied to the aforementioned serial port data transmission system. Please refer to [link to relevant documentation]. Figure 3 The method includes: S102, the server CPU of each server motherboard encapsulates the multi-channel independent UART serial port data in its own internal multiplex serial port into a set of time-division multiplexed bus signals according to a preset frame format, and transmits them to the corresponding multiplexing management module through its own downlink bus.

[0065] The server CPU's internal multiple independent UART serial ports each generate serial data. The server CPU's encapsulation module encapsulates the data from each serial port into independent data frames according to a preset frame format. Each data frame sequentially includes a frame header, status code, serial port channel number, serial data, CRC checksum, and frame trailer. After encapsulation, the server CPU sends the data frames from the multiple serial ports sequentially to the multiplexing management module via the downlink bus TDM_UART_TX in a time-division multiplexing manner. For example, assuming the server CPU has 10 UART serial ports, each generating 14,400 bytes of data per second, the server CPU encapsulates the data from these 10 serial ports into 10 data frames, each containing an 8-bit frame header, a 4-bit status code, an 8-bit channel number, 8 bits of data, an 8-bit CRC checksum, and an 8-bit frame trailer, totaling 44 bits. The server CPU then sends these 10 data frames sequentially to the downlink bus using a polling method.

[0066] S104: Each multiplexing management module parses the received time-division multiplexed bus signal, separates and recovers the independent serial port signal of each channel, and outputs the separated and recovered independent serial port signal of each channel to the USB to serial port module. After being converted into a USB signal, it is connected to the client through the USB interface to realize local direct connection debugging of each server motherboard.

[0067] The TDM UART decoding unit within the multiplexing management module receives the time-division multiplexing bus signal from the downlink bus. It first searches the frame header to achieve frame synchronization, then reads the status code and serial port channel number, extracts the serial port data, and performs CRC verification. After successful verification, the data is distributed to the corresponding channel's serial port output port, recovering the independent serial port signal for each channel. The recovered serial port signal is then output to the USB-to-serial module via the motherboard's internal PCB traces. The USB-to-serial module converts the signal into a USB signal, which is then connected to the client via a USB interface for local direct connection debugging.

[0068] Meanwhile, the multiplexing management module directly routes the time-division multiplexed bus signals on the downlink and uplink buses to the motherboard connector. The motherboard connector is assigned only three pins, corresponding to the downlink bus signal, uplink bus signal, and GND ground, respectively. The external cable contains only three signal lines, connecting the motherboard connector to the serial server. For example, assuming there are 10 servers in the rack, each server's motherboard connector is connected to the corresponding port of the serial server via a three-core cable. A total of 10 three-core cables are needed for 10 servers, significantly reducing the number of cables compared to the traditional solution requiring 16 cables (8 serial ports) or 20 cables (10 serial ports) per server.

[0069] S106, each multiplexing management module leads out the time-division multiplexed bus signal through its own motherboard connector and transmits it to the same serial port server via external cables.

[0070] The serial server's internal controller receives time-division multiplexed bus signals from each server motherboard, decodes them according to a preset frame format, and recovers the serial data from each channel of each server motherboard. Based on an internally pre-set channel mapping table, the controller determines the server motherboard and serial channel to which each data frame belongs, and adds a server motherboard identifier and a serial channel number identifier to the data so that the data source can be distinguished when subsequently converted into an Ethernet packet. For example, when the serial server receives a data frame from Port3 with channel number CH5, the controller determines from the channel mapping table that the data frame comes from serial channel CH5 of server motherboard S3, and adds the identifier "S3-CH5" to the Ethernet packet.

[0071] S108, the serial port server receives and decodes the time-division multiplexed bus signals from each server motherboard, recovers the serial port data of each channel of each server motherboard, and associates and identifies each channel data with the corresponding server motherboard and serial port channel according to the internally preset channel mapping table.

[0072] The S110 serial server converts all channel data from all server motherboards after association into Ethernet packets and uploads them to the client via the Ethernet interface, enabling remote network debugging of multiple servers.

[0073] Optionally, the serial server encapsulates all channel data after association into Ethernet packets according to the Ethernet protocol and uploads them to the client via the Ethernet interface. Upon receiving the Ethernet packets, the client distributes the data to the corresponding terminal windows for display based on the server motherboard identifier field and the serial port channel number field in the packets, thereby enabling remote network debugging across multiple servers. For example, an operations and maintenance personnel can open management software on a client computer, displaying 10 servers, each with 10 serial ports, for a total of 100 terminal windows. The personnel can switch to view any serial port data from any server at any time.

[0074] In the reverse channel, debugging commands sent by the client are converted into corresponding time-division multiplexed bus signals by the serial port server and then transmitted back to the respective server CPUs via external cables and the uplink bus TDM_UART_RX. Optionally, the debugging commands sent by the client are first transmitted to the serial port server via the Ethernet interface. The controller inside the serial port server encapsulates the debugging commands into time-division multiplexed bus signals according to a preset frame format, transmits them to the motherboard connector via an external cable, and then transmits them to the multiplexing management module via the uplink bus. The multiplexing management module parses the time-division multiplexed bus signals on the uplink bus, separates and recovers the independent serial port signals for each channel, and transmits them to the server CPU. After receiving the debugging commands, the server CPU executes the corresponding operations to complete the debugging process.

[0075] In this embodiment, multiple server motherboards are simultaneously connected to the same serial port server, forming a multi-server centralized debugging network architecture. Each server motherboard is connected to the same serial port server via its own motherboard connector and external cables. Only one set of three-wire transmission cables is laid between each server motherboard and the serial port server: a downlink bus signal line, an uplink bus signal line, and a GND ground wire. Compared to traditional solutions that require dozens of independent serial port cables per server, this embodiment significantly reduces the number of cables and simplifies data center cabling.

[0076] In a network scenario where multiple servers simultaneously connect to a serial port server, only one set of three-wire transmission cables is deployed between each server and the serial port server. When a serial communication failure occurs, the corresponding server cable link can be quickly located, narrowing down the troubleshooting scope and significantly reducing the time spent on fault location during maintenance. Combined with the serial port channel number carried within the frame, the specific faulty serial port channel can be accurately located, greatly improving maintenance troubleshooting efficiency. For example, when maintenance personnel discover abnormal debugging data on server S5, they only need to check the three-core cable corresponding to S5 and the Port5 port of the serial port server, without having to check dozens of cables one by one.

[0077] In summary, this application encapsulates multiple independent UART serial port data from the server CPU into a set of time-division multiplexed bus signals according to a preset frame format. After parsing by the multiplexing management module, the independent serial port signals of each channel are separated and recovered. These signals are then used for local direct connection debugging via a USB-to-serial module and for remote network debugging via a motherboard connector to a serial port server. This replaces the traditional multi-channel independent serial port routing with a set of time-division multiplexed bus signals, solving the problems of insufficient pin resources, difficulty in controlling trace impedance, and low efficiency in equipment maintenance and troubleshooting. Furthermore, by introducing a status code field and a dynamic bandwidth allocation mechanism, power consumption optimization and electromagnetic interference suppression are achieved under normal operating conditions while ensuring communication reliability under the most demanding operating conditions. Through a network architecture where multiple servers connect to the same serial port server, centralized remote debugging and rapid fault location of multiple servers are realized.

[0078] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0079] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A serial port data transmission system, characterized in that, The system includes: At least one server motherboard, each of the server motherboards including a server CPU and a multiplexing management module; The server CPU has multiple independent UART serial ports built-in, which are used to encapsulate the data from the multiple independent UART serial ports into a set of time-division multiplexed bus signals according to a preset frame format. The time-division multiplexed bus signals are transmitted through the downlink bus and the uplink bus. The multiplexing management module is connected to the server CPU through the downlink bus and the uplink bus. The multiplexing management module is used to parse the received time-division multiplexing bus signal and separate and recover the independent serial port signal of each channel. The USB to serial port module is connected to the multiplexing management module and is used to convert the independent serial port signals of each channel separated and recovered by the multiplexing management module into USB signals, and connect them to the client through the USB interface to realize local direct connection debugging. The motherboard connector is connected to the input terminal of the multiplexing management module and is used to lead the time-division multiplexing bus signal to the outside of the motherboard. A serial port server, connected to the motherboard connector, is used to receive the time-division multiplexed bus signals and connect to the client via an Ethernet interface to enable remote network debugging of the server.

2. The serial port data transmission system according to claim 1, characterized in that, The multiplexing management module is implemented using any one of CPLD, FPGA, ASIC, MCU or SOC; The multiplexing management module is equipped with a TDM UART decoding unit. The TDM UART decoding unit is used to perform frame synchronization, channel identification, data extraction and verification on the time-division multiplexed bus signal according to the preset frame format, so as to separate and recover the independent serial port signal of each channel.

3. The serial port data transmission system according to claim 1, characterized in that, The motherboard connector is equipped with downlink bus signal pins, uplink bus signal pins, and GND ground pin; The external cable connecting the motherboard connector to the serial server includes three signal lines corresponding to three pins.

4. The serial port data transmission system according to claim 1, characterized in that, The preset frame format includes, in sequence: frame header, serial port channel number, serial port data, CRC checksum, and frame trailer; The frame header, the serial port channel number, the CRC checksum, and the frame tail occupy a total of 32 bits. The fields of the serial port data are 8N bits in length, where N is the number of bytes.

5. The serial port data transmission system according to claim 4, characterized in that, In the preset frame format, a status code field is also set between the frame header and the serial port channel number; The status code field is used to characterize the current real-time load status or rate demand indication of the corresponding serial port channel.

6. The serial port data transmission system according to claim 5, characterized in that, The server CPU is equipped with a load monitoring and rate decision module, which is used to generate the corresponding status code based on the transmit buffer level of each serial port channel, and encapsulate the status code into the preset frame format. The status code includes at least one or a combination of the following encoded states: The idle state code indicates that there is currently no data to be sent on the corresponding channel; Light load status coding indicates that the transmit buffer occupancy rate of the corresponding channel is lower than the first threshold; The intermediate load status code indicates that the transmit buffer occupancy rate of the corresponding channel is between the first threshold and the second threshold; The full-load status code indicates that the occupancy rate of the corresponding channel's transmit buffer is higher than the second threshold; The burst warning status code indicates that the corresponding channel is about to generate burst data, requesting the receiving end to increase the bus rate in advance.

7. The serial port data transmission system according to claim 6, characterized in that, The multiplexing management module and / or the serial port server are equipped with an arbitration decision module. The arbitration decision module is used to parse the received status code and, in combination with its own link quality monitoring results, comprehensively determine whether to perform the adjustment of the time-division multiplexing bus operating rate. When it is determined that speed needs to be increased or decreased, the arbitration decision module sends a rate negotiation frame to the server CPU through the uplink bus. After receiving the rate negotiation frame, the server CPU confirms and executes the rate switch. The bus operating speed after the speed switch is not lower than the theoretical minimum speed requirement corresponding to the current number of active serial ports, and the theoretical minimum speed requirement satisfies: Rate_min = N_active × (Baud_UART ÷ 8) × L_frame Where N_active is the number of currently active serial port channels, Baud_UART is the original serial port baud rate, and L_frame is the total number of bits per frame.

8. The serial port data transmission system according to claim 1, characterized in that, The serial port server is connected to multiple motherboard connectors of the server motherboards at the same time, and the serial port server is equipped with a controller and a channel mapping table. The channel mapping table is used to record the correspondence between the identification information of each server motherboard and the serial port channel number inside each server motherboard; The controller associates the decoded serial port data of each channel with the corresponding server motherboard and serial port channel according to the channel mapping table, and when converting it into an Ethernet packet, it carries both the server motherboard identifier field and the serial port channel number field in the Ethernet packet.

9. The serial port data transmission system according to claim 8, characterized in that, The serial port server is also equipped with a port status indicator module and a data cache module; The port status indication module includes status indicator lights that correspond one-to-one with each motherboard connector access port, used to indicate the link connection status and data transmission activity status of the corresponding port; The data caching module is used to cache and queue the data of each channel according to a preset priority strategy when multiple server motherboards send data to the serial port server at the same time, and then upload the data to the client sequentially through the Ethernet interface.

10. A serial port data transmission method, applied to the system as described in any one of claims 1 to 9, characterized in that, The method includes: Each server motherboard's CPU encapsulates its internal multi-channel independent UART serial port data into a set of time-division multiplexed bus signals according to a preset frame format, and transmits them to the corresponding multiplexing management module through its respective downlink bus. Each of the multiplexing management modules parses the received time-division multiplexed bus signal, separates and recovers the independent serial port signal of each channel, and outputs the separated and recovered independent serial port signal of each channel to the USB to serial port module. After being converted into a USB signal, it is connected to the client through the USB interface to realize local direct connection debugging of each server motherboard. Each of the multiplexing management modules leads out the time-division multiplexed bus signal through its respective motherboard connector and transmits it to the same serial port server via an external cable; The serial port server receives and decodes the time-division multiplexed bus signals from each of the server motherboards, recovers the serial port data of each channel of each server motherboard, and associates and identifies each channel data with the corresponding server motherboard and serial port channel according to the internally preset channel mapping table. The serial port server converts all channel data from all server motherboards after association into Ethernet packets and uploads them to the client via the Ethernet interface, enabling remote network debugging of multiple servers.

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