An axi-to-axi-stream data conversion module and method based on effective byte dynamic aggregation

Abstract

The application discloses an AXI-to-AXI-Stream data conversion module and method based on effective byte dynamic aggregation, an input interface is used for receiving a data stream AXI_in, that is, an AXI data stream to be converted; a byte effective detection unit detects and counts effective bytes wstrb according to an AXI interface protocol; a data effective detection unit detects and counts effective data wdata according to the AXI interface protocol; a dynamic aggregation unit is used for dynamically aggregating and splicing the effective bytes wstrb and the effective data wdata, and generating AXI-Stream data meeting a single output bit width; and an output interface is used for outputting the AXI-Stream data.

Description

Technical Field

[0001] This invention belongs to the field of signal processing technology and relates to an AXI to AXI-Stream data conversion technology. Background Technology

[0002] In modern digital systems, especially high-performance computing and data processing systems based on FPGAs or ASICs, data bus protocols are the core of connecting various functional modules. The AXI protocol, as an industry-standard high-performance, high-bandwidth bus interface, is widely used for data exchange between processors, DMA controllers, and high-speed peripheral controllers.

[0003] The AXI protocol defines independent read / write data channels, address channels, and control channels, supporting burst transfers. In the write data channel, in addition to the WDATA write data and WLAST last data flag signals, there is a crucial WSTRB write strobe signal. Each bit of the WSTRB signal corresponds to one byte on the WDATA bus, indicating which bytes on the WDATA bus are valid within the current clock cycle. This mechanism allows AXI master devices to perform unaligned or partial byte writes, such as DMA controllers communicating with the host via a PCIe interface, greatly improving data transfer flexibility.

[0004] However, in many dedicated data processing pipelines, such as video processing, AI inference, and network packet processing, a simpler, continuous data streaming protocol, namely AXI-Stream, is often used. The AXI-Stream protocol does not have an address channel; it transmits data as a continuous stream in a unidirectional manner through the TDATA, TVALID, TREADY, and TLAST signals, making it well-suited for processing continuous data streams without address information.

[0005] In practical applications, a common problem is how to efficiently and losslessly convert data from the AXI bus into AXI-Stream format for use by back-end processing units, such as PCIe DMA write operations. Traditional conversion methods usually have the following drawbacks.

[0006] Invalid data transmission: Simple conversions may ignore the WSTRB signal and directly pack all data on the WDATA bus, including invalid bytes, into TDATA. This not only wastes AXI-Stream's bandwidth but also places an additional burden on the back-end processing unit, requiring it to identify and discard invalid data itself.

[0007] Discontinuous data flow: When an AXI write operation contains invalid bytes, if the conversion process simply discards the entire data word, it will cause "holes" in the AXI-Stream data stream. This disrupts the continuity of the data stream and contradicts the original design intent.

[0008] Therefore, existing technologies lack an efficient conversion mechanism that can intelligently identify valid bytes in AXI write data and dynamically aggregate them into a continuous, compact AXI-Stream data stream. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the prior art and provide an AXI to AXI-Stream data conversion module based on dynamic aggregation of effective bytes, achieving the following objectives.

[0010] Eliminating invalid data transmission: The WSTRB signal in the AXI write data channel is precisely parsed, and only valid bytes are packaged into the AXI-Stream data stream, thereby completely eliminating the transmission of invalid data and improving data bandwidth utilization.

[0011] Ensuring data stream continuity: Even if the input AXI data word contains invalid bytes, the output AXI-Stream is a continuous, gapless, and valid data stream, meeting the backend processing module's requirement for a continuous data stream.

[0012] Dynamic byte aggregation: It can dynamically "stitch" together valid bytes from multiple consecutive, partially valid AXI data words to form one or more complete AXI-Stream data packets without waiting for a complete AXI data word to be fully valid.

[0013] The module includes an input interface, a byte validity detection unit, a data validity detection unit, a dynamic aggregation unit, and an output interface. The input interface is used to receive the data stream AXI_in, i.e., the AXI data stream to be converted. The byte validity detection unit detects and counts valid bytes wstrb according to the AXI interface protocol. The data validity detection unit detects and counts valid data wdata according to the AXI interface protocol. The dynamic aggregation unit is used to dynamically aggregate and concatenate valid bytes wstrb and valid data wdata to generate AXI-Stream data that meets the single output bit width. The output interface is used to output AXI-Stream data.

[0014] The method includes the following steps: Step 1, receiving the data stream AXI_in; Step 2, detecting and counting the valid bytes wstrb and valid data wdata of the AXI data stream to be converted according to the AXI interface protocol; Step 3, dynamically aggregating and concatenating the valid bytes wstrb and valid data wdata; Step 4, if the count of valid bytes meets the AXI-Stream data bit width for a single output, then output the aggregated data; otherwise, repeat steps 1 to 3.

[0015] This invention maximizes bandwidth utilization: by accurately identifying and transmitting only valid bytes, it eliminates the transmission of invalid data on the AXI-Stream channel, ensuring that 100% of the data bandwidth is used for the payload. In scenarios involving the writing of large amounts of unaligned or partially written data, bandwidth efficiency can be improved several times. It also improves backend processing efficiency: the backend processing module receives a "clean" and continuous data stream, eliminating the need to expend logical resources to parse and remove invalid bytes, simplifying the design and improving the overall system processing performance. Furthermore, it ensures the integrity of the data stream: the dynamic aggregation mechanism ensures that all valid bytes in the original AXI transaction, no matter how scattered, can be completely and orderly converted into the AXI-Stream data stream, and the boundaries of data packets are correctly identified by the TLAST signal, ensuring the semantic integrity of the data. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the module's principle structure.

[0017] Figure 2 It is a flowchart of the method and steps.

[0018] Figure 3 It is an input / output timing diagram.

[0019] Figure labeling: Input interface 1, Byte validity detection unit 2, Data validity detection unit 3, Dynamic aggregation unit 4, Output interface 5. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to the embodiments and the accompanying drawings.

[0021] Module principle structure as follows Figure 1 As shown, input interface 1 receives the data stream AXI_in, which is the AXI data stream to be converted; byte validity detection unit 2 detects and counts valid bytes wstrb according to the AXI interface protocol; data validity detection unit 3 detects and counts valid data wdata according to the AXI interface protocol; dynamic aggregation unit 4 dynamically aggregates and splices valid bytes wstrb and valid data wdata to generate AXI-Stream data that meets the single output bit width, and outputs it from output interface 5.

[0022] The method and steps are as follows Figure 2 As shown, Step 1: Receive the data stream AXI_in; Step 2: Detect and count the valid bytes wstrb and valid data wdata of the AXI data stream to be converted according to the AXI interface protocol; Step 3: Dynamically aggregate and concatenate the valid bytes wstrb and valid data wdata; Step 4: If the counted number of valid bytes meets the AXI-Stream data bit width for a single output, output the aggregated data; otherwise, repeat Steps 1 to 3.

[0023] Taking an input AXI data stream with a bit width of 64 bits, an output AXI-Stream data stream with a bit width of 64 bits, and four output data points forming a single last output as an example, the input / output timing diagram is as follows: Figure 3 As shown: The input AXI data streams are 64'h0123456789abcdef, 64'h3456789abcdef012, 64'h789abcdef0123456, and 64'h89abcdef01234567.

[0024] For the first input AXI data, during T3~T5, the valid bytes wstrb are detected as 8'h10, 8'h0f, and 8'he0, and the valid data are detected as 8'h67, 32'h89abcdef, and 24'h012345. At this time, the number of valid bytes counted meets the requirement of 8 bytes, or 64 bits, for the output AXI-Stream data. Therefore, the first AXI-Stream data 64'h0123456789abcdef is output in T6.

[0025] For the second input AXI data, during T6~T9, the valid bytes wstrb are detected as 8'h30, 8'h03, 8'hb0, and 8'h0b, and the valid data are detected as 16'h789a, 16'hf012, 16'h3456, and 16'h3456. At this time, the number of valid bytes counted meets the requirement of 8 bytes, or 64 bits, for the output AXI-Stream data. Therefore, the second AXI-Stream data 64'h3456789abcdef012 is output at T10.

[0026] For the third input AXI data, the valid byte wstrb is detected as 8'hff at T10, and the valid data is 64'h789abcdef0123456. At this time, the number of valid bytes counted meets the requirement of 8 bytes, or 64 bits, for the output AXI-Stream data. Therefore, the third AXI-Stream data 64'h0123456789abcdef is output at T11.

[0027] For the fourth input AXI data, during T11-T12, the valid bytes wstrb are detected as 8'h1f and 8'he0, and the valid data are detected as 40'hef01234567 and 24'h89abcd. At this time, the number of valid bytes counted meets the requirement of 8 bytes, or 64 bits, for the output AXI-Stream data. Therefore, the fourth AXI-Stream data 64'h89abcdef01234567 is output in T13, and the last signal of the AXI-Stream output is generated at the same time.

[0028] The above embodiments do not limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention are included within the scope of protection.

Claims

1. An AXI to AXI-Stream data conversion module based on dynamic aggregation of effective bytes, characterized in that, include: Input interface, byte validity detection unit, data validity detection unit, dynamic aggregation unit, output interface; The input interface is used to receive the data stream AXI_in, i.e., the AXI data stream to be converted; the byte validity detection unit detects and counts valid bytes wstrb according to the AXI interface protocol; the data validity detection unit detects and counts valid data wdata according to the AXI interface protocol; the dynamic aggregation unit is used to dynamically aggregate and concatenate valid bytes wstrb and valid data wdata to generate AXI-Stream data that meets the single output bit width; the output interface is used to output AXI-Stream data.

2. A method for converting AXI to AXI-Stream data based on dynamic aggregation of effective bytes, characterized in that, include: Step 1: Receive the data stream AXI_in; Step 2: Detect and count the valid bytes wstrb and valid data wdata of the AXI data stream to be converted according to the AXI interface protocol; Step 3: Dynamically aggregate and concatenate the valid bytes wstrb and valid data wdata; Step 4: If the count of valid bytes meets the AXI-Stream data bit width for a single output, output the aggregated data; otherwise, repeat steps 1 to 3.

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